From: Adrian Weber Date: Wed, 23 Sep 2020 15:16:44 +0000 (+0200) Subject: different way of calculation for ram addressing due to modelsim issue X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f2b17057fead419216e81ce39e9700897263a4c9;p=dirich.git different way of calculation for ram addressing due to modelsim issue --- diff --git a/combiner_cts/code_EBR/Calibration.vhd b/combiner_cts/code_EBR/Calibration.vhd index 923ff83..012a4db 100644 --- a/combiner_cts/code_EBR/Calibration.vhd +++ b/combiner_cts/code_EBR/Calibration.vhd @@ -189,6 +189,7 @@ begin --BUS Handler proc_reg : process + variable tmp_chnl_addr : std_logic_vector(6 downto 0); begin wait until rising_edge(CLK); BUS_TX.ack <= '0'; @@ -278,7 +279,8 @@ begin Monitor_RAM_RE <= '1'; elsif (BUS_RX.addr(11 downto 4) > x"03") and (BUS_RX.addr(11 downto 4) < x"20") then BUS_TX.ack <= '0'; - Monitor_RAM_AddChnl <= std_logic_vector(unsigned("00" & BUS_RX.addr(4 downto 0))+1); + tmp_chnl_addr := "00" & BUS_RX.addr(4 downto 0); + Monitor_RAM_AddChnl <= std_logic_vector(unsigned(tmp_chnl_addr)+1); Monitor_RAM_AddFPGA <= std_logic_vector(unsigned(BUS_RX.addr(8 downto 5)) - 2); Monitor_RAM_RE <= '1'; else