From: Cahit Date: Wed, 26 Feb 2014 12:01:03 +0000 (+0100) Subject: tdc_v1.6: first working version X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f36f39981b0226c4288321bac60c1df798f534d5;p=trb3.git tdc_v1.6: first working version --- diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd index 0a0d9c2..9ba2d10 100644 --- a/32PinAddOn/config.vhd +++ b/32PinAddOn/config.vhd @@ -12,11 +12,11 @@ package config is --Include GbE logic constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; - constant NUM_TDC_CHANNELS_POWER2: integer range 0 to 6 := 3; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS_POWER2: integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons constant USE_DOUBLE_EDGE : integer := c_YES; --Include SPI on AddOn connector - constant INCLUDE_SPI : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; --Add logic to generate configurable trigger signal from input signals. constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj index aa1d81c..af9b4a2 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.prj +++ b/32PinAddOn/trb3_periph_32PinAddOn.prj @@ -152,21 +152,21 @@ add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd" add_file -vhdl -lib "work" "currentRelease/Channel.vhd" add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd" add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd" -add_file -vhdl -lib "work" "currentRelease/FIFO_36x128_OutReg_Counter.vhd" +#add_file -vhdl -lib "work" "currentRelease/FIFO_36x128_OutReg_Counter.vhd" add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd" add_file -vhdl -lib "work" "currentRelease/Readout.vhd" add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd" add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd" add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd" add_file -vhdl -lib "work" "currentRelease/TDC.vhd" -#add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd" +add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd" add_file -vhdl -lib "work" "currentRelease/up_counter.vhd" add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd" add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" -add_file -vhdl -lib "work" "currentRelease/Reference_Channel_200.vhd" -add_file -vhdl -lib "work" "currentRelease/Reference_Channel.vhd" +#add_file -vhdl -lib "work" "currentRelease/Reference_Channel_200.vhd" +#add_file -vhdl -lib "work" "currentRelease/Reference_Channel.vhd" add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd" diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd index 755d20d..ad6f643 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.vhd +++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd @@ -101,7 +101,7 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL signal clk_125_i : std_logic; -- 125 MHz, via Clock Manager and bypassed PLL signal clk_20_i : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL - signal osc_int : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL + signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -310,6 +310,8 @@ begin port map ( OSC => osc_int); + + --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) @@ -728,13 +730,13 @@ begin gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate THE_TRIG_LOGIC : input_to_trigger_logic generic map( - INPUTS => 24, + INPUTS => 32, OUTPUTS => 4 ) port map( CLK => clk_100_i, - INPUT => INP(24 downto 1), + INPUT => INP(32 downto 1), OUTPUT => trig_out, DATA_IN => trig_din, @@ -745,6 +747,7 @@ begin NACK_OUT => trig_nack, ADDR_IN => trig_addr ); + FPGA5_COMM(10 downto 7) <= trig_out; end generate; --------------------------------------------------------------------------- @@ -869,7 +872,5 @@ begin end generate Gen_Hit_In_Signals; end generate; - -- Trigger on a TDC Channel - FPGA5_COMM(10) <= hit_in_i(to_integer(unsigned(tdc_ctrl_reg(5*32+7 downto 5*32)))); end architecture; diff --git a/tdc_releases/tdc_v1.6/Channel.vhd b/tdc_releases/tdc_v1.6/Channel.vhd index 236da4c..661f5c3 100644 --- a/tdc_releases/tdc_v1.6/Channel.vhd +++ b/tdc_releases/tdc_v1.6/Channel.vhd @@ -116,14 +116,20 @@ architecture Channel of Channel is attribute syn_keep of hit_buf : signal is true; attribute syn_keep of trig_win_end_tdc_i : signal is true; attribute syn_keep of trig_win_end_rdo_i : signal is true; + attribute syn_keep of epoch_cntr_reg : signal is true; +-- attribute syn_keep of epoch_cntr_2reg : signal is true; attribute syn_preserve : boolean; attribute syn_preserve of coarse_cntr_reg : signal is true; attribute syn_preserve of hit_buf : signal is true; attribute syn_preserve of trig_win_end_tdc_i : signal is true; + attribute syn_preserve of epoch_cntr_reg : signal is true; +-- attribute syn_preserve of epoch_cntr_2reg : signal is true; attribute nomerge : string; attribute nomerge of hit_buf : signal is "true"; attribute nomerge of trig_win_end_tdc_i : signal is "true"; attribute nomerge of trig_win_end_rdo_i : signal is "true"; + attribute nomerge of epoch_cntr_reg : signal is "true"; +-- attribute nomerge of epoch_cntr_2reg : signal is "true"; ------------------------------------------------------------------------------- @@ -148,7 +154,7 @@ begin HIT_IN => hit_buf, TRIGGER_WIN_END_TDC => trig_win_end_tdc_i, TRIGGER_WIN_END_RDO => trig_win_end_rdo_i, - EPOCH_COUNTER_IN => epoch_cntr_2reg, --EPOCH_COUNTER_IN, + EPOCH_COUNTER_IN => epoch_cntr_reg, --epoch_cntr_2reg, COARSE_COUNTER_IN => coarse_cntr_reg, READ_EN_IN => READ_EN_IN, FIFO_DATA_OUT => ch_data_i, @@ -224,7 +230,7 @@ begin D_OUT => coarse_cntr_reg); epoch_cntr_reg <= EPOCH_COUNTER_IN when rising_edge(CLK_200); - epoch_cntr_2reg <= epoch_cntr_reg when rising_edge(CLK_200); +-- epoch_cntr_2reg <= epoch_cntr_reg when rising_edge(CLK_200); ------------------------------------------------------------------------------- -- DEBUG Counters diff --git a/tdc_releases/tdc_v1.6/Channel_200.vhd b/tdc_releases/tdc_v1.6/Channel_200.vhd index d66775a..0fd2bdc 100644 --- a/tdc_releases/tdc_v1.6/Channel_200.vhd +++ b/tdc_releases/tdc_v1.6/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2014-01-28 +-- Last update: 2014-02-25 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- diff --git a/tdc_releases/tdc_v1.6/TDC.vhd b/tdc_releases/tdc_v1.6/TDC.vhd index 29392b3..0275363 100644 --- a/tdc_releases/tdc_v1.6/TDC.vhd +++ b/tdc_releases/tdc_v1.6/TDC.vhd @@ -122,6 +122,10 @@ architecture TDC of TDC is signal hit_latch : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0'); signal hit_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 1); signal hit_2reg : std_logic_vector(CHANNEL_NUMBER-1 downto 1); +-- Calibration + signal hit_calibration_cntr : unsigned(15 downto 0) := (others => '0'); + signal hit_calibration_i : std_logic; + signal calibration_freq_select : unsigned(3 downto 0) := (others => '0'); -- To the channels signal rd_en_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal trg_win_end_i : std_logic; @@ -182,9 +186,10 @@ begin reset_coarse_cntr_i <= CONTROL_REG_IN(13); reset_coarse_cntr_200 <= reset_coarse_cntr_i when rising_edge(CLK_TDC); -- Reset coarse counter control register synchronised to the coarse counter clk - trig_win_en_i <= CONTROL_REG_IN(1*32+31); - ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); - data_limit_i <= unsigned(CONTROL_REG_IN(4*32+7 downto 4*32+0)); + trig_win_en_i <= CONTROL_REG_IN(1*32+31); + ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); + data_limit_i <= unsigned(CONTROL_REG_IN(4*32+7 downto 4*32+0)); + calibration_freq_select <= unsigned(CONTROL_REG_IN(31 downto 28)); -- Reset signals reset_tdc_i <= RESET when rising_edge(CLK_TDC); @@ -192,6 +197,15 @@ begin reset_rdo_i <= RESET when rising_edge(CLK_READOUT); reset_rdo <= reset_rdo_i when rising_edge(CLK_READOUT); + -- Hit for calibration generation + Calibration_Pulses : process (HIT_CALIBRATION) + begin + if rising_edge(HIT_CALIBRATION) then + hit_calibration_cntr <= hit_calibration_cntr + to_unsigned(1, 16); + end if; + end process Calibration_Pulses; + + hit_calibration_i <= hit_calibration_cntr(to_integer(calibration_freq_select)); -- Blocks the input after the rising edge against short pulses GEN_HitBlock : for i in 1 to CHANNEL_NUMBER-1 generate @@ -209,11 +223,11 @@ begin -- Channel and calibration enable signals GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate - process (ch_en_i, calibration_on, HIT_CALIBRATION, hit_latch) + process (ch_en_i, calibration_on, hit_calibration_i, hit_latch) begin if ch_en_i(i) = '1' then if calibration_on = '1' then - hit_in_i(i) <= HIT_CALIBRATION; + hit_in_i(i) <= hit_calibration_i; else hit_in_i(i) <= hit_latch(i); end if; @@ -224,10 +238,10 @@ begin end generate GEN_Channel_Enable; -- purpose: Calibration trigger for the reference channel - process (calibration_on, HIT_CALIBRATION, REFERENCE_TIME) is + process (calibration_on, hit_calibration_i, REFERENCE_TIME) is begin -- process if calibration_on = '1' then - hit_in_i(0) <= HIT_CALIBRATION; + hit_in_i(0) <= hit_calibration_i; else hit_in_i(0) <= REFERENCE_TIME; end if; diff --git a/tdc_releases/tdc_v1.6/tdc_constraints.lpf b/tdc_releases/tdc_v1.6/tdc_constraints.lpf index 1914698..4c59ca0 100644 --- a/tdc_releases/tdc_v1.6/tdc_constraints.lpf +++ b/tdc_releases/tdc_v1.6/tdc_constraints.lpf @@ -4,10 +4,10 @@ ############################################################################## ## REGION DECLERATION ## ############################################################################## -REGION "REGION_UR_CC" "R51C106D" 4 3 DEVSIZE; -REGION "REGION_LR_CC" "R85C106D" 3 3 DEVSIZE; -REGION "REGION_UL_CC" "R48C53D" 3 3 DEVSIZE; -REGION "REGION_LL_CC" "R90C53D" 3 3 DEVSIZE; +#REGION "REGION_UR_CC" "R51C106D" 4 3 DEVSIZE; +#REGION "REGION_LR_CC" "R85C106D" 3 3 DEVSIZE; +#REGION "REGION_UL_CC" "R48C53D" 3 3 DEVSIZE; +#REGION "REGION_LL_CC" "R89C53D" 3 3 DEVSIZE; ############################################################################## @@ -672,199 +672,199 @@ LOCATE UGROUP "ff_en_64" SITE "R113C27D" ; ############################################################################## UGROUP "E&F_ref" BBOX 6 27 BLKNAME THE_TDC/ReferenceChannel/Channel200; -LOCATE UGROUP "E&F_ref" SITE "R11C129D" ; +LOCATE UGROUP "E&F_ref" SITE "R11C128D" ; UGROUP "E&F_1" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200; LOCATE UGROUP "E&F_1" SITE "R11C155D" ; UGROUP "E&F_2" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200; -LOCATE UGROUP "E&F_2" SITE "R15C129D" ; +LOCATE UGROUP "E&F_2" SITE "R15C128D" ; UGROUP "E&F_3" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200; LOCATE UGROUP "E&F_3" SITE "R15C155D" ; UGROUP "E&F_4" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200; -LOCATE UGROUP "E&F_4" SITE "R24C129D" ; +LOCATE UGROUP "E&F_4" SITE "R24C128D" ; UGROUP "E&F_5" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200; LOCATE UGROUP "E&F_5" SITE "R24C155D" ; UGROUP "E&F_6" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200; -LOCATE UGROUP "E&F_6" SITE "R38C129D" ; -UGROUP "E&F_7" BBOX 6 25 +LOCATE UGROUP "E&F_6" SITE "R38C128D" ; +UGROUP "E&F_7" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200; -LOCATE UGROUP "E&F_7" SITE "R38C156D" ; -UGROUP "E&F_8" BBOX 6 25 +LOCATE UGROUP "E&F_7" SITE "R38C155D" ; +UGROUP "E&F_8" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200; -LOCATE UGROUP "E&F_8" SITE "R42C131D" ; -UGROUP "E&F_9" BBOX 6 25 +LOCATE UGROUP "E&F_8" SITE "R42C128D" ; +UGROUP "E&F_9" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200; -LOCATE UGROUP "E&F_9" SITE "R42C156D" ; -UGROUP "E&F_10" BBOX 6 24 +LOCATE UGROUP "E&F_9" SITE "R42C155D" ; +UGROUP "E&F_10" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200; -LOCATE UGROUP "E&F_10" SITE "R56C131D" ; -UGROUP "E&F_11" BBOX 6 25 +LOCATE UGROUP "E&F_10" SITE "R56C128D" ; +UGROUP "E&F_11" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200; LOCATE UGROUP "E&F_11" SITE "R56C155D" ; -UGROUP "E&F_12" BBOX 6 25 +UGROUP "E&F_12" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200; -LOCATE UGROUP "E&F_12" SITE "R11C84D" ; -UGROUP "E&F_13" BBOX 6 25 +LOCATE UGROUP "E&F_12" SITE "R11C83D" ; +UGROUP "E&F_13" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200; -LOCATE UGROUP "E&F_13" SITE "R15C84D" ; -UGROUP "E&F_14" BBOX 6 25 +LOCATE UGROUP "E&F_13" SITE "R15C83D" ; +UGROUP "E&F_14" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200; -LOCATE UGROUP "E&F_14" SITE "R24C84D" ; -UGROUP "E&F_15" BBOX 6 25 +LOCATE UGROUP "E&F_14" SITE "R24C83D" ; +UGROUP "E&F_15" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200; -LOCATE UGROUP "E&F_15" SITE "R38C84D" ; -UGROUP "E&F_16" BBOX 6 25 +LOCATE UGROUP "E&F_15" SITE "R38C83D" ; +UGROUP "E&F_16" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200; -LOCATE UGROUP "E&F_16" SITE "R42C84D" ; -UGROUP "E&F_17" BBOX 6 24 +LOCATE UGROUP "E&F_16" SITE "R42C83D" ; +UGROUP "E&F_17" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200; -LOCATE UGROUP "E&F_17" SITE "R60C131D" ; -UGROUP "E&F_18" BBOX 6 25 +LOCATE UGROUP "E&F_17" SITE "R60C128D" ; +UGROUP "E&F_18" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200; LOCATE UGROUP "E&F_18" SITE "R60C155D" ; -UGROUP "E&F_19" BBOX 6 25 +UGROUP "E&F_19" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200; -LOCATE UGROUP "E&F_19" SITE "R74C131D" ; -UGROUP "E&F_20" BBOX 6 25 +LOCATE UGROUP "E&F_19" SITE "R74C128D" ; +UGROUP "E&F_20" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200; -LOCATE UGROUP "E&F_20" SITE "R74C156D" ; -UGROUP "E&F_21" BBOX 6 25 +LOCATE UGROUP "E&F_20" SITE "R74C155D" ; +UGROUP "E&F_21" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200; -LOCATE UGROUP "E&F_21" SITE "R78C131D" ; -UGROUP "E&F_22" BBOX 6 25 +LOCATE UGROUP "E&F_21" SITE "R78C128D" ; +UGROUP "E&F_22" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200; -LOCATE UGROUP "E&F_22" SITE "R78C156D" ; -UGROUP "E&F_23" BBOX 6 25 +LOCATE UGROUP "E&F_22" SITE "R78C155D" ; +UGROUP "E&F_23" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200; -LOCATE UGROUP "E&F_23" SITE "R92C131D" ; -UGROUP "E&F_24" BBOX 6 25 +LOCATE UGROUP "E&F_23" SITE "R92C128D" ; +UGROUP "E&F_24" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200; -LOCATE UGROUP "E&F_24" SITE "R92C156D" ; -UGROUP "E&F_25" BBOX 6 25 +LOCATE UGROUP "E&F_24" SITE "R92C155D" ; +UGROUP "E&F_25" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200; -LOCATE UGROUP "E&F_25" SITE "R96C131D" ; -UGROUP "E&F_26" BBOX 6 25 +LOCATE UGROUP "E&F_25" SITE "R96C128D" ; +UGROUP "E&F_26" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200; -LOCATE UGROUP "E&F_26" SITE "R96C156D" ; -UGROUP "E&F_27" BBOX 6 25 +LOCATE UGROUP "E&F_26" SITE "R96C155D" ; +UGROUP "E&F_27" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200; -LOCATE UGROUP "E&F_27" SITE "R105C131D" ; -UGROUP "E&F_28" BBOX 6 25 +LOCATE UGROUP "E&F_27" SITE "R105C128D" ; +UGROUP "E&F_28" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200; -LOCATE UGROUP "E&F_28" SITE "R105C156D" ; -UGROUP "E&F_29" BBOX 6 25 +LOCATE UGROUP "E&F_28" SITE "R105C155D" ; +UGROUP "E&F_29" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200; -LOCATE UGROUP "E&F_29" SITE "R92C84D" ; -UGROUP "E&F_30" BBOX 6 25 +LOCATE UGROUP "E&F_29" SITE "R92C83D" ; +UGROUP "E&F_30" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200; -LOCATE UGROUP "E&F_30" SITE "R96C84D" ; -UGROUP "E&F_31" BBOX 6 25 +LOCATE UGROUP "E&F_30" SITE "R96C83D" ; +UGROUP "E&F_31" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200; -LOCATE UGROUP "E&F_31" SITE "R105C84D" ; -UGROUP "E&F_32" BBOX 6 25 +LOCATE UGROUP "E&F_31" SITE "R105C83D" ; +UGROUP "E&F_32" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200; LOCATE UGROUP "E&F_32" SITE "R78C72D" ; -UGROUP "E&F_33" BBOX 6 25 +UGROUP "E&F_33" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200; -LOCATE UGROUP "E&F_33" SITE "R11C59D" ; -UGROUP "E&F_34" BBOX 6 25 +LOCATE UGROUP "E&F_33" SITE "R11C56D" ; +UGROUP "E&F_34" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200; -LOCATE UGROUP "E&F_34" SITE "R15C59D" ; -UGROUP "E&F_35" BBOX 6 25 +LOCATE UGROUP "E&F_34" SITE "R15C56D" ; +UGROUP "E&F_35" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200; -LOCATE UGROUP "E&F_35" SITE "R24C59D" ; -UGROUP "E&F_36" BBOX 6 25 +LOCATE UGROUP "E&F_35" SITE "R24C56D" ; +UGROUP "E&F_36" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200; -LOCATE UGROUP "E&F_36" SITE "R38C59D" ; -UGROUP "E&F_37" BBOX 6 25 +LOCATE UGROUP "E&F_36" SITE "R38C56D" ; +UGROUP "E&F_37" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200; -LOCATE UGROUP "E&F_37" SITE "R42C59D" ; -UGROUP "E&F_38" BBOX 6 25 +LOCATE UGROUP "E&F_37" SITE "R42C56D" ; +UGROUP "E&F_38" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200; -LOCATE UGROUP "E&F_38" SITE "R11C3D" ; -UGROUP "E&F_39" BBOX 6 25 +LOCATE UGROUP "E&F_38" SITE "R11C2D" ; +UGROUP "E&F_39" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200; -LOCATE UGROUP "E&F_39" SITE "R11C28D" ; -UGROUP "E&F_40" BBOX 6 25 +LOCATE UGROUP "E&F_39" SITE "R11C29D" ; +UGROUP "E&F_40" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200; -LOCATE UGROUP "E&F_40" SITE "R15C3D" ; -UGROUP "E&F_41" BBOX 6 25 +LOCATE UGROUP "E&F_40" SITE "R15C2D" ; +UGROUP "E&F_41" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200; -LOCATE UGROUP "E&F_41" SITE "R15C28D" ; -UGROUP "E&F_42" BBOX 6 25 +LOCATE UGROUP "E&F_41" SITE "R15C29D" ; +UGROUP "E&F_42" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200; -LOCATE UGROUP "E&F_42" SITE "R24C3D" ; -UGROUP "E&F_43" BBOX 6 25 +LOCATE UGROUP "E&F_42" SITE "R24C2D" ; +UGROUP "E&F_43" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200; -LOCATE UGROUP "E&F_43" SITE "R24C28D" ; -UGROUP "E&F_44" BBOX 6 25 +LOCATE UGROUP "E&F_43" SITE "R24C29D" ; +UGROUP "E&F_44" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200; -LOCATE UGROUP "E&F_44" SITE "R38C3D" ; -UGROUP "E&F_45" BBOX 6 25 +LOCATE UGROUP "E&F_44" SITE "R38C2D" ; +UGROUP "E&F_45" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200; -LOCATE UGROUP "E&F_45" SITE "R38C28D" ; -UGROUP "E&F_46" BBOX 6 25 +LOCATE UGROUP "E&F_45" SITE "R38C29D" ; +UGROUP "E&F_46" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200; -LOCATE UGROUP "E&F_46" SITE "R42C3D" ; -UGROUP "E&F_47" BBOX 6 25 +LOCATE UGROUP "E&F_46" SITE "R42C2D" ; +UGROUP "E&F_47" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200; -LOCATE UGROUP "E&F_47" SITE "R42C28D" ; -UGROUP "E&F_48" BBOX 6 25 +LOCATE UGROUP "E&F_47" SITE "R42C29D" ; +UGROUP "E&F_48" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200; -LOCATE UGROUP "E&F_48" SITE "R56C3D" ; -UGROUP "E&F_49" BBOX 6 25 +LOCATE UGROUP "E&F_48" SITE "R56C2D" ; +UGROUP "E&F_49" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200; -LOCATE UGROUP "E&F_49" SITE "R56C28D" ; -UGROUP "E&F_50" BBOX 6 25 +LOCATE UGROUP "E&F_49" SITE "R56C29D" ; +UGROUP "E&F_50" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200; -LOCATE UGROUP "E&F_50" SITE "R92C59D" ; -UGROUP "E&F_51" BBOX 6 25 +LOCATE UGROUP "E&F_50" SITE "R92C56D" ; +UGROUP "E&F_51" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200; -LOCATE UGROUP "E&F_51" SITE "R96C59D" ; -UGROUP "E&F_52" BBOX 6 25 +LOCATE UGROUP "E&F_51" SITE "R96C56D" ; +UGROUP "E&F_52" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200; -LOCATE UGROUP "E&F_52" SITE "R105C59D" ; -UGROUP "E&F_53" BBOX 6 25 +LOCATE UGROUP "E&F_52" SITE "R105C56D" ; +UGROUP "E&F_53" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200; -LOCATE UGROUP "E&F_53" SITE "R60C3D" ; -UGROUP "E&F_54" BBOX 6 25 +LOCATE UGROUP "E&F_53" SITE "R60C2D" ; +UGROUP "E&F_54" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200; -LOCATE UGROUP "E&F_54" SITE "R60C28D" ; -UGROUP "E&F_55" BBOX 6 25 +LOCATE UGROUP "E&F_54" SITE "R60C29D" ; +UGROUP "E&F_55" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200; -LOCATE UGROUP "E&F_55" SITE "R74C3D" ; -UGROUP "E&F_56" BBOX 6 25 +LOCATE UGROUP "E&F_55" SITE "R74C2D" ; +UGROUP "E&F_56" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200; -LOCATE UGROUP "E&F_56" SITE "R74C28D" ; -UGROUP "E&F_57" BBOX 6 25 +LOCATE UGROUP "E&F_56" SITE "R74C29D" ; +UGROUP "E&F_57" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200; -LOCATE UGROUP "E&F_57" SITE "R78C3D" ; -UGROUP "E&F_58" BBOX 6 25 +LOCATE UGROUP "E&F_57" SITE "R78C2D" ; +UGROUP "E&F_58" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200; -LOCATE UGROUP "E&F_58" SITE "R78C28D" ; -UGROUP "E&F_59" BBOX 6 25 +LOCATE UGROUP "E&F_58" SITE "R78C29D" ; +UGROUP "E&F_59" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200; -LOCATE UGROUP "E&F_59" SITE "R92C3D" ; -UGROUP "E&F_60" BBOX 6 25 +LOCATE UGROUP "E&F_59" SITE "R92C2D" ; +UGROUP "E&F_60" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200; -LOCATE UGROUP "E&F_60" SITE "R92C28D" ; -UGROUP "E&F_61" BBOX 6 25 +LOCATE UGROUP "E&F_60" SITE "R92C29D" ; +UGROUP "E&F_61" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200; -LOCATE UGROUP "E&F_61" SITE "R96C3D" ; -UGROUP "E&F_62" BBOX 6 25 +LOCATE UGROUP "E&F_61" SITE "R96C2D" ; +UGROUP "E&F_62" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200; -LOCATE UGROUP "E&F_62" SITE "R96C28D" ; -UGROUP "E&F_63" BBOX 6 25 +LOCATE UGROUP "E&F_62" SITE "R96C29D" ; +UGROUP "E&F_63" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200; -LOCATE UGROUP "E&F_63" SITE "R105C3D" ; -UGROUP "E&F_64" BBOX 6 25 +LOCATE UGROUP "E&F_63" SITE "R105C2D" ; +UGROUP "E&F_64" BBOX 6 27 BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200; -LOCATE UGROUP "E&F_64" SITE "R105C28D" ; +LOCATE UGROUP "E&F_64" SITE "R105C29D" ; ############################################################################# ## Coarse counter register placement @@ -890,10 +890,10 @@ LOCATE UGROUP "Epoch_Counter" SITE R36C138D; UGROUP "BusHandlers" BLKNAME THE_TDC/TheHitCounterBus - BLKNAME THE_TDC/TheStatusRegistersBus - BLKNAME THE_TDC/TheLostHitBus - BLKNAME THE_TDC/TheEncoderStartBus - BLKNAME THE_TDC/TheEncoderFinishedBus; + BLKNAME THE_TDC/TheStatusRegistersBus; +# BLKNAME THE_TDC/TheLostHitBus +# BLKNAME THE_TDC/TheEncoderStartBus +# BLKNAME THE_TDC/TheEncoderFinishedBus; #LOCATE UGROUP "BusHandlers" REGION BUS @@ -904,9 +904,11 @@ UGROUP "BusHandlers" ############################################################################# BLOCK NET "THE_TDC/reset_tdc*" ; +BLOCK NET "THE_TDC/reset_rdo*" ; BLOCK NET "THE_TDC/hit_in_i_*" ; +BLOCK NET "THE_TDC/reset_counters_i*" ; #BLOCK PATH TO CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/SimAdderNo_FC/FF_*" ; -#BLOCK NET "THE_TDC/reset_counters_200*" ; + BLOCK PATH TO CELL "THE_TDC/GEN_Channels_*_Channels/sync_q_2*"; PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; @@ -916,10 +918,10 @@ MAXDELAY NET "THE_TDC/ReferenceChannel/hit_buf" 0.600000 nS DATAPATH_ONLY ; MAXDELAY NET "THE_TDC/GEN_Channels_*_Channels/hit_buf" 0.600000 nS DATAPATH_ONLY ; MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; -MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/epoch_cntr_*" 5.000000 X; -MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/ReferenceChannel/Channel200/epoch_cntr_*" 5.000000 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/GEN_Channels_*_Channels/epoch_cntr_reg*" 5.000000 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5.000000 X; + #MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X; MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg_*" 2.000000 X; MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/FIFO_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X; #MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/FIFO_ALMOST_FULL_OUT" TO CELL "THE_TDC/TheReadout/data_out_reg*" 2.000000 X; -