From: Adrian Weber Date: Tue, 12 Jan 2021 16:17:59 +0000 (+0100) Subject: new PLL for 240MHz -> 50MHz. Used for calibration Clock on combiner board of CBM... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f37a7a69a36dc0ad2addbab0c806a8f947edbcd3;p=tdc.git new PLL for 240MHz -> 50MHz. Used for calibration Clock on combiner board of CBM RICH (recovered 240MHz clock) --- diff --git a/base/cores/ecp3/PLL/pll_in240_out50.ipx b/base/cores/ecp3/PLL/pll_in240_out50.ipx new file mode 100644 index 0000000..39a30d0 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in240_out50.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/ecp3/PLL/pll_in240_out50.lpc b/base/cores/ecp3/PLL/pll_in240_out50.lpc new file mode 100644 index 0000000..10ae46f --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in240_out50.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_in240_out50 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/12/2021 +Time=14:19:24 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=240 +Div=24 +ClkOPBp=0 +Post=16 +U_OFrq=50 +OP_Tol=0.0 +OFrq=50.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=5 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=100 +OK_Tol=0.0 +KFrq=100.000000 +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=1.369727 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_in240_out50 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 50 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw diff --git a/base/cores/ecp3/PLL/pll_in240_out50.vhd b/base/cores/ecp3/PLL/pll_in240_out50.vhd new file mode 100644 index 0000000..c932f9f --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in240_out50.vhd @@ -0,0 +1,95 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- Module Version: 5.7 +--/usr/local/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_in240_out50 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 50 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Tue Jan 12 14:19:24 2021 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in240_out50 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); +end pll_in240_out50; + +architecture Structure of pll_in240_out50 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "240.000000"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 5, CLKI_DIV=> 24, + FIN=> "240.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in240_out50 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on