From: Jan Michel <j.michel@gsi.de>
Date: Fri, 5 Jun 2015 12:41:03 +0000 (+0200)
Subject: added few syn_hier constraints
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f45a7370d8e656817a764cb51e289d9c2f5dcf8c;p=trbnet.git

added few syn_hier constraints
---

diff --git a/.gitignore b/.gitignore
index 7ac4178..e458796 100644
--- a/.gitignore
+++ b/.gitignore
@@ -16,3 +16,6 @@ workdir
 *.tcl
 *.bak
 *.edn
+*.pp
+*.readme
+*.tft
diff --git a/media_interfaces/med_ecp3_sfp_sync.vhd b/media_interfaces/med_ecp3_sfp_sync.vhd
index 9e7e77d..d067773 100644
--- a/media_interfaces/med_ecp3_sfp_sync.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync.vhd
@@ -74,7 +74,8 @@ architecture med_ecp3_sfp_sync_arch of med_ecp3_sfp_sync is
   attribute HGROUP of med_ecp3_sfp_sync_arch : architecture  is "media_interface_group";
   attribute syn_sharing : string;
   attribute syn_sharing of med_ecp3_sfp_sync_arch : architecture is "off";
-
+  attribute syn_hier : string;
+  attribute syn_hier of med_ecp3_sfp_sync_arch : architecture is "hard";
 
 component DCS
 -- synthesis translate_off
diff --git a/special/trb_net_reset_handler.vhd b/special/trb_net_reset_handler.vhd
index 8a9b59a..4794b5e 100644
--- a/special/trb_net_reset_handler.vhd
+++ b/special/trb_net_reset_handler.vhd
@@ -55,6 +55,9 @@ attribute syn_preserve of reset : signal  is true;
 attribute syn_preserve of reset_cnt : signal  is true;
 attribute syn_preserve of comb_async_rst_n : signal  is true;
 
+attribute syn_hier : string;
+attribute syn_hier of behavioral : architecture is "firm";
+
 begin
 
 ----------------------------------------------------------------
diff --git a/trb_net16_regio_bus_handler_record.vhd b/trb_net16_regio_bus_handler_record.vhd
index 1fe2f04..9bc65ed 100644
--- a/trb_net16_regio_bus_handler_record.vhd
+++ b/trb_net16_regio_bus_handler_record.vhd
@@ -45,6 +45,9 @@ end entity;
 
 architecture regio_bus_handler_arch of trb_net16_regio_bus_handler_record is
 
+  attribute syn_hier : string;
+  attribute syn_hier of regio_bus_handler_arch : architecture is "hard";
+
   signal port_select_int      : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS;
   signal next_port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS;