From: Ingo Froehlich Date: Wed, 22 Aug 2018 20:43:28 +0000 (+0200) Subject: merged resub registers with sci_reader X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f49d2b3992df8b9cb8868419acb5fabe53c69322;p=trbnet.git merged resub registers with sci_reader --- diff --git a/media_interfaces/med_ecp3_sfp_sync.vhd b/media_interfaces/med_ecp3_sfp_sync.vhd index 308f518..c4433c4 100644 --- a/media_interfaces/med_ecp3_sfp_sync.vhd +++ b/media_interfaces/med_ecp3_sfp_sync.vhd @@ -290,10 +290,10 @@ THE_SCI_READER : entity work.sci_reader BUS_RX => BUS_RX, BUS_TX => BUS_TX, - MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i, - MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i, - MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i, - MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'), + --MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i, + --MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i, + --MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i, + --MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'), DEBUG_OUT => open ); diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd index 64578f0..66cc76e 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd @@ -43,8 +43,6 @@ entity med_ecp3_sfp_sync_4 is --Control Interface BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; - MII_RX : in CTRLBUS_RX; - MII_TX : out CTRLBUS_TX; -- Status and control port STAT_DEBUG : out std_logic_vector (63 downto 0); @@ -111,6 +109,9 @@ attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; signal mii_tx_i : CTRLBUS_TX_array_t(0 to 3); signal mii_rx_i : CTRLBUS_RX_array_t(0 to 3); + +signal loc_bus_rx : CTRLBUS_RX; +signal loc_bus_tx : CTRLBUS_TX; type u8_arr is array (0 to 3) of unsigned(7 downto 0); signal cv_cnt, cv_cnt_sys : u8_arr; @@ -271,57 +272,6 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave on tx_sync_qd_c => '0' ); -BUS_MULTIPLEXER : process - begin - wait until rising_edge(SYSCLK); - mii_rx_i(0).data <= mii_rx.data; - mii_rx_i(1).data <= mii_rx.data; - mii_rx_i(2).data <= mii_rx.data; - mii_rx_i(3).data <= mii_rx.data; - mii_rx_i(0).addr <= mii_rx.addr; - mii_rx_i(1).addr <= mii_rx.addr; - mii_rx_i(2).addr <= mii_rx.addr; - mii_rx_i(3).addr <= mii_rx.addr; - - mii_tx.data <= mii_tx_i(0).data or mii_tx_i(1).data or mii_tx_i(2).data or mii_tx_i(3).data; - mii_tx.ack <= mii_tx_i(0).ack or mii_tx_i(1).ack or mii_tx_i(2).ack or mii_tx_i(3).ack; - mii_tx.unknown <= mii_tx_i(0).unknown and mii_tx_i(1).unknown and mii_tx_i(2).unknown and mii_tx_i(3).unknown; - - mii_rx_i(0).read <= '0'; - mii_rx_i(1).read <= '0'; - mii_rx_i(2).read <= '0'; - mii_rx_i(3).read <= '0'; - mii_rx_i(0).write <= '0'; - mii_rx_i(1).write <= '0'; - mii_rx_i(2).write <= '0'; - mii_rx_i(3).write <= '0'; - -- connect debug registers, mii0 should be at 0x00+offset, mii1 at - -- 0x10+offset, etc - if (mii_rx.read = '1') then - if (mii_rx.addr(7 downto 4) = (REG_OFFSET(7 downto 4))) then - mii_rx_i(0).read <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 1)) then - mii_rx_i(1).read <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 2)) then - mii_rx_i(2).read <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 3)) then - mii_rx_i(3).read <= '1'; - end if; - end if; - - if (mii_rx.write = '1') then - if (mii_rx.addr(7 downto 4) = (REG_OFFSET(7 downto 4))) then - mii_rx_i(0).write <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 1)) then - mii_rx_i(1).write <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 2)) then - mii_rx_i(2).write <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 3)) then - mii_rx_i(3).write <= '1'; - end if; - end if; -end process; - gen_control : for i in 0 to 3 generate gen_used_control : if IS_USED(i) = c_YES generate @@ -407,25 +357,103 @@ THE_SCI_READER : entity work.sci_reader --Slowcontrol BUS_RX => BUS_RX, BUS_TX => BUS_TX, + + LOC_BUS_RX => loc_BUS_RX, + LOC_BUS_TX => loc_BUS_TX, + - MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0), - MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0), - - MEDIA_STATUS_REG_IN(191 downto 64) => stat_fsm_reset_i(127 downto 0), - MEDIA_STATUS_REG_IN(199 downto 192) => cv_cnt_sys(0), - MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1), - MEDIA_STATUS_REG_IN(215 downto 208) => cv_cnt_sys(2), - MEDIA_STATUS_REG_IN(223 downto 216) => cv_cnt_sys(3), + --MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0), + --MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0), + + --MEDIA_STATUS_REG_IN(191 downto 64) => stat_fsm_reset_i(127 downto 0), + --MEDIA_STATUS_REG_IN(199 downto 192) => cv_cnt_sys(0), + --MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1), + --MEDIA_STATUS_REG_IN(215 downto 208) => cv_cnt_sys(2), + --MEDIA_STATUS_REG_IN(223 downto 216) => cv_cnt_sys(3), - MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'), + --MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'), --MEDIA_STATUS_REG_IN(383 downto 256) => debug_retrans_i, --MEDIA_STATUS_REG_IN(511 downto 384) => (others => '0'), - DEBUG_OUT => open ); +BUS_WRITER : process + begin + wait until rising_edge(SYSCLK); + loc_BUS_TX.unknown <= '0'; + loc_BUS_TX.rack <= '0'; + loc_BUS_TX.wack <= '0'; + loc_BUS_TX.data <= x"00000000"; + loc_BUS_TX.ack <= '0'; + mii_rx_i(0).data <= loc_BUS_RX.data; + mii_rx_i(1).data <= loc_BUS_RX.data; + mii_rx_i(2).data <= loc_BUS_RX.data; + mii_rx_i(3).data <= loc_BUS_RX.data; + mii_rx_i(0).addr <= loc_BUS_RX.addr; + mii_rx_i(1).addr <= loc_BUS_RX.addr; + mii_rx_i(2).addr <= loc_BUS_RX.addr; + mii_rx_i(3).addr <= loc_BUS_RX.addr; + mii_rx_i(0).read <= '0'; + mii_rx_i(1).read <= '0'; + mii_rx_i(2).read <= '0'; + mii_rx_i(3).read <= '0'; + mii_rx_i(0).write <= '0'; + mii_rx_i(1).write <= '0'; + mii_rx_i(2).write <= '0'; + mii_rx_i(3).write <= '0'; + + --000 stat + --001 + --010 + --011 + --100 med_ctrl + -- ... + --111 + + if loc_BUS_RX.addr(2) = '0' then + if loc_BUS_RX.read = '1' then + loc_BUS_TX.ack <= '1'; + case loc_BUS_RX.addr(4 downto 0) is + when "00000" => loc_BUS_TX.data <= stat_rx_control_i(31 downto 0); + when "00001" => loc_BUS_TX.data <= stat_tx_control_i(31 downto 0); + when "00010" => loc_BUS_TX.data <= stat_fsm_reset_i(31 downto 0); + when "00011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(0)); + when "01011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(1)); + when "10011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(2)); + when "11011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(3)); + end case; + end if; + else + loc_BUS_TX.data <= mii_tx_i(0).data or mii_tx_i(1).data or mii_tx_i(2).data or mii_tx_i(3).data; + loc_BUS_TX.ack <= mii_tx_i(0).ack or mii_tx_i(1).ack or mii_tx_i(2).ack or mii_tx_i(3).ack; + loc_BUS_TX.unknown <= mii_tx_i(0).unknown and mii_tx_i(1).unknown and mii_tx_i(2).unknown and mii_tx_i(3).unknown; + if loc_BUS_RX.read = '1' then + if loc_BUS_RX.addr(4 downto 3) = "00" then + mii_rx_i(0).read <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "01" then + mii_rx_i(1).read <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "10" then + mii_rx_i(2).read <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "11" then + mii_rx_i(3).read <= '1'; + end if; + elsif loc_BUS_RX.write = '1' then + if loc_BUS_RX.addr(4 downto 3) = "00" then + mii_rx_i(0).write <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "01" then + mii_rx_i(1).write <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "10" then + mii_rx_i(2).write <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "11" then + mii_rx_i(3).write <= '1'; + end if; + end if; + end if; +end process; + + cv_cnt_sys <= cv_cnt when rising_edge(SYSCLK); wa_position <= (others => '0'); diff --git a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd index 42e7389..dda7a55 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd @@ -43,8 +43,6 @@ entity med_ecp3_sfp_sync_4_slave3 is --Control Interface BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; - MII_RX : in CTRLBUS_RX; - MII_TX : out CTRLBUS_TX; -- Status and control port STAT_DEBUG : out std_logic_vector (63 downto 0); @@ -110,6 +108,10 @@ attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; signal mii_tx_i : CTRLBUS_TX_array_t(0 to 3); signal mii_rx_i : CTRLBUS_RX_array_t(0 to 3); + +signal loc_bus_rx : CTRLBUS_RX; +signal loc_bus_tx : CTRLBUS_TX; + begin @@ -267,59 +269,6 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave on ); -- clk_rxi <= (0 => CLK_REF_FULL,1 => CLK_REF_FULL,2 => CLK_REF_FULL,3 => clk_rx_full(3)); - - -BUS_MULTIPLEXER : process - begin - wait until rising_edge(SYSCLK); - - mii_rx_i(0).data <= mii_rx.data; - mii_rx_i(1).data <= mii_rx.data; - mii_rx_i(2).data <= mii_rx.data; - mii_rx_i(3).data <= mii_rx.data; - mii_rx_i(0).addr <= mii_rx.addr; - mii_rx_i(1).addr <= mii_rx.addr; - mii_rx_i(2).addr <= mii_rx.addr; - mii_rx_i(3).addr <= mii_rx.addr; - - mii_tx.data <= mii_tx_i(0).data or mii_tx_i(1).data or mii_tx_i(2).data or mii_tx_i(3).data; - mii_tx.ack <= mii_tx_i(0).ack or mii_tx_i(1).ack or mii_tx_i(2).ack or mii_tx_i(3).ack; - - mii_rx_i(0).read <= '0'; - mii_rx_i(1).read <= '0'; - mii_rx_i(2).read <= '0'; - mii_rx_i(3).read <= '0'; - mii_rx_i(0).write <= '0'; - mii_rx_i(1).write <= '0'; - mii_rx_i(2).write <= '0'; - mii_rx_i(3).write <= '0'; - -- connect debug registers, mii0 should be at 0x00+offset, mii1 at - -- 0x10+offset, etc - if (mii_rx.read = '1') then - if (mii_rx.addr(7 downto 4) = (REG_OFFSET(7 downto 4))) then - mii_rx_i(0).read <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 1)) then - mii_rx_i(1).read <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 2)) then - mii_rx_i(2).read <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 3)) then - mii_rx_i(3).read <= '1'; - end if; - end if; - - if (mii_rx.write = '1') then - if (mii_rx.addr(7 downto 4) = (REG_OFFSET(7 downto 4))) then - mii_rx_i(0).write <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 1)) then - mii_rx_i(1).write <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 2)) then - mii_rx_i(2).write <= '1'; - elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 3)) then - mii_rx_i(3).write <= '1'; - end if; - end if; -end process; - gen_control : for i in 0 to 3 generate gen_used_control : if IS_USED(i) = c_YES generate @@ -401,11 +350,15 @@ THE_SCI_READER : entity work.sci_reader --Slowcontrol BUS_RX => BUS_RX, BUS_TX => BUS_TX, + + LOC_BUS_RX => loc_BUS_RX, + LOC_BUS_TX => loc_BUS_TX, + - MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0), - MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0), - MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i(31 downto 0), - MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'), + --MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0), + --MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0), + --MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i(31 downto 0), + --MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'), --MEDIA_STATUS_REG_IN(383 downto 256) => debug_retrans_i, --MEDIA_STATUS_REG_IN(511 downto 384) => (others => '0'), @@ -413,6 +366,70 @@ THE_SCI_READER : entity work.sci_reader DEBUG_OUT => open ); +BUS_WRITER : process + begin + wait until rising_edge(SYSCLK); + loc_BUS_TX.unknown <= '0'; + loc_BUS_TX.rack <= '0'; + loc_BUS_TX.wack <= '0'; + loc_BUS_TX.data <= x"00000000"; + loc_BUS_TX.ack <= '0'; + mii_rx_i(0).data <= loc_BUS_RX.data; + mii_rx_i(1).data <= loc_BUS_RX.data; + mii_rx_i(2).data <= loc_BUS_RX.data; + mii_rx_i(3).data <= loc_BUS_RX.data; + mii_rx_i(0).addr <= loc_BUS_RX.addr; + mii_rx_i(1).addr <= loc_BUS_RX.addr; + mii_rx_i(2).addr <= loc_BUS_RX.addr; + mii_rx_i(3).addr <= loc_BUS_RX.addr; + mii_rx_i(0).read <= '0'; + mii_rx_i(1).read <= '0'; + mii_rx_i(2).read <= '0'; + mii_rx_i(3).read <= '0'; + mii_rx_i(0).write <= '0'; + mii_rx_i(1).write <= '0'; + mii_rx_i(2).write <= '0'; + mii_rx_i(3).write <= '0'; + + if loc_BUS_RX.addr(2) = '0' then + if loc_BUS_RX.read = '1' then + loc_BUS_TX.ack <= '1'; + case loc_BUS_RX.addr(4 downto 0) is + when "00000" => loc_BUS_TX.data <= stat_rx_control_i(31 downto 0); + when "00001" => loc_BUS_TX.data <= stat_tx_control_i(31 downto 0); + when "00010" => loc_BUS_TX.data <= stat_fsm_reset_i(31 downto 0); + end case; + end if; + else + loc_BUS_TX.data <= mii_tx_i(0).data or mii_tx_i(1).data or mii_tx_i(2).data or mii_tx_i(3).data; + loc_BUS_TX.ack <= mii_tx_i(0).ack or mii_tx_i(1).ack or mii_tx_i(2).ack or mii_tx_i(3).ack; + loc_BUS_TX.unknown <= mii_tx_i(0).unknown and mii_tx_i(1).unknown and mii_tx_i(2).unknown and mii_tx_i(3).unknown; + if loc_BUS_RX.read = '1' then + if loc_BUS_RX.addr(4 downto 3) = "00" then + mii_rx_i(0).read <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "01" then + mii_rx_i(1).read <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "10" then + mii_rx_i(2).read <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "11" then + mii_rx_i(3).read <= '1'; + end if; + elsif loc_BUS_RX.write = '1' then + if loc_BUS_RX.addr(4 downto 3) = "00" then + mii_rx_i(0).write <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "01" then + mii_rx_i(1).write <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "10" then + mii_rx_i(2).write <= '1'; + elsif loc_BUS_RX.addr(4 downto 3) = "11" then + mii_rx_i(3).write <= '1'; + end if; + end if; + end if; + + +end process; + wa_position <= (others => '0'); STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0); diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index 78766cd..8cba59b 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -117,7 +117,10 @@ signal DEBUG_OUT_i : std_logic_vector(31 downto 0); signal last_FORCE_CRC_ERROR_IN : std_logic; signal crc_error_delay : std_logic_vector(3 downto 0) := "0000"; - +signal tx_got_force_error : std_logic := '0'; +signal tx_force_crc_error : std_logic := '0'; +signal tx_force_pak_error : std_logic := '0'; + begin @@ -240,20 +243,19 @@ PROC_REG : process begin BUS_TX.ack <= '0'; if BUS_RX.write = '1' then BUS_TX.ack <= '1'; - case BUS_RX.addr(3 downto 0) is - when x"0" => force_crc_error <= '1'; - when x"1" => crc_error_delay <= BUS_RX.data(3 downto 0); + case BUS_RX.addr(1 downto 0) is + when "00" => force_crc_error <= BUS_RX.data(0); + crc_error_delay <= BUS_RX.data(7 downto 4); + tx_force_crc_error <= BUS_RX.data(8); + tx_force_pak_error <= BUS_RX.data(9); + when "01" => force_crc_error <= '0'; tx_force_crc_error <= '0'; tx_force_pak_error <= '0'; when others => BUS_TX.unknown <= '1'; end case; elsif BUS_RX.read = '1' then BUS_TX.ack <= '1'; - case BUS_RX.addr(3 downto 0) is - when x"0" => BUS_TX.data <= x"000" & "000" & force_crc_error & request_retr_counter; - when x"1" => BUS_TX.data <= x"0000" & start_retr_counter; - when x"2" => BUS_TX.data <= STAT_TX_CONTROL_i; - when x"3" => BUS_TX.data <= DEBUG_TX_CONTROL_i; - when x"4" => BUS_TX.data <= STAT_RX_CONTROL_i; - when x"5" => BUS_TX.data <= DEBUG_RX_CONTROL_i; + case BUS_RX.addr(1 downto 0) is + when "00" => BUS_TX.data <= x"00000" & "00" & tx_force_pak_error & tx_force_crc_error & crc_error_delay & "000" & force_crc_error; + when "01" => BUS_TX.data <= request_retr_counter & start_retr_counter; when others => BUS_TX.unknown <= '1'; end case; end if; @@ -263,6 +265,12 @@ PROC_REG : process begin elsif request_retr_i = '1' then force_crc_error <= '0'; end if; + + if tx_got_force_error = '1' then + tx_force_crc_error <= '0'; + tx_force_pak_error <= '0'; + end if; + end process; ------------------------------------------------- @@ -289,6 +297,10 @@ THE_TX : tx_control START_RETRANSMIT_IN => start_retr_i, START_POSITION_IN => start_retr_position_i, + FORCE_CRC_ERROR => tx_force_crc_error, + FORCE_PAK_ERROR => tx_force_pak_error, + GOT_FORCE_ERROR => tx_got_force_error, + SEND_DLM => TX_DLM, SEND_DLM_WORD => TX_DLM_WORD, diff --git a/media_interfaces/sync/med_sync_define.vhd b/media_interfaces/sync/med_sync_define.vhd index 5d2afda..e832191 100644 --- a/media_interfaces/sync/med_sync_define.vhd +++ b/media_interfaces/sync/med_sync_define.vhd @@ -77,6 +77,10 @@ component tx_control is START_RETRANSMIT_IN : in std_logic := '0'; START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); + FORCE_CRC_ERROR : in std_logic; + FORCE_PAK_ERROR : in std_logic; + GOT_FORCE_ERROR : out std_logic := '0'; + SEND_DLM : in std_logic := '0'; SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0'); diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index 3724128..3416fed 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -111,6 +111,7 @@ signal resub_mode : std_logic := '0'; --signal last_good_pos_counter : std_logic_vector(7 downto 0) := (others => '0'); --signal last_send_link_reset_i : std_logic; signal reset_retrans : std_logic; +signal force_crc_error_int : std_logic := '0'; --signal num_count : unsigned(7 downto 0) := (others => '0'); --signal max_count : unsigned(7 downto 0) := (others => '0'); @@ -244,7 +245,7 @@ PROC_RX_FSM : process begin make_reset_i <= '0'; rx_data(7 downto 0) <= reg_rx_data_in; if reg_rx_k_in = '1' and reg_rx_data_in = x"BC" then - rx_state <= wAIT_1; + rx_state <= WAIT_1; end if; when WAIT_1 => @@ -288,6 +289,11 @@ PROC_RX_FSM : process begin elsif reg_rx_k_in = '1' then rx_state <= FIRST; -- SLEEP; end if; + if use_crc = '1' and num_pakets /= 0 and force_crc_error_int = '0' then + -- IDLE only allowed after CRC + rx_state <= GET_CRC; + force_crc_error_int <= '1'; + end if; when GET_DATA => rx_state_bits <= x"4"; @@ -306,13 +312,14 @@ PROC_RX_FSM : process begin end if; when GET_CRC => - if (use_crc = '0') then + if use_crc = '0' then -- first time - load_use_crc <= '1'; - disable_crc <= '0'; + load_use_crc <= '1'; + disable_crc <= '0'; + force_crc_error_int <= '0'; else if (crc_q /= reg_rx_data_in or waiting_for_retr = '1' or --- or num_pakets /= 5) - (force_crc_error = '1' and CRC_ERROR_DELAY_cnt = "0000") ) and disable_crc = '0' then + (force_crc_error = '1' and CRC_ERROR_DELAY_cnt = "0000") or force_crc_error_int = '1') and disable_crc = '0' then -- bad pulse_bad <= '1'; if waiting_for_retr = '0' then @@ -326,7 +333,8 @@ PROC_RX_FSM : process begin end if; else -- good - pulse_good <= '1'; + pulse_good <= '1'; + force_crc_error_int <= '0'; if force_crc_error = '0' then CRC_ERROR_DELAY_cnt <= CRC_ERROR_DELAY; disable_crc <= '0'; diff --git a/media_interfaces/sync/sci_reader.vhd b/media_interfaces/sync/sci_reader.vhd index 765db6a..61310f8 100644 --- a/media_interfaces/sync/sci_reader.vhd +++ b/media_interfaces/sync/sci_reader.vhd @@ -27,8 +27,11 @@ entity sci_reader is --Slowcontrol BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; - - MEDIA_STATUS_REG_IN : in std_logic_vector(511 downto 0) := (others => '0'); + + LOC_BUS_RX : out CTRLBUS_RX; + LOC_BUS_TX : in CTRLBUS_TX; + + --MEDIA_STATUS_REG_IN : in std_logic_vector(511 downto 0) := (others => '0'); DEBUG_OUT : out std_logic_vector(31 downto 0) ); @@ -67,6 +70,8 @@ WA_POS_OUT <= wa_position; BUS_TX.unknown <= '0'; BUS_TX.rack <= '0'; BUS_TX.wack <= '0'; + LOC_BUS_RX.addr <= BUS_RX.addr; + LOC_BUS_RX.data <= BUS_RX.data; PROC_SCI_CTRL: process variable cnt : integer range 0 to 4 := 0; @@ -74,6 +79,13 @@ begin wait until rising_edge(CLK); BUS_TX.ack <= '0'; BUS_TX.nack <= '0'; + --BUS_TX.unknown <= '0'; + --BUS_TX.rack <= '0'; + --BUS_TX.wack <= '0'; + LOC_BUS_RX.read <= '0'; + LOC_BUS_RX.write <= '0'; + BUS_TX.data <= x"ffffffff"; + case sci_state is when IDLE => SCI_SEL <= (others => '0'); @@ -92,6 +104,8 @@ begin SCI_WRDATA <= BUS_RX.data(7 downto 0); SCI_RD <= BUS_RX.read and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8)); SCI_WR <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8)); + LOC_BUS_RX.read <= BUS_RX.read and BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8); + LOC_BUS_RX.write <= BUS_RX.write and BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8); sci_state <= SCTRL; elsif sci_timer(sci_timer'left) = '1' then sci_timer <= (others => '0'); @@ -99,11 +113,18 @@ begin end if; when SCTRL => if sci_reg_i = '1' then - BUS_TX.data <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))); - BUS_TX.ack <= '1'; + --BUS_TX.data <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(4 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(4 downto 0))))); + --BUS_TX.ack <= '1'; + BUS_TX.data <= x"12341234"; + LOC_BUS_RX.read <= BUS_RX.read; + LOC_BUS_RX.write <= BUS_RX.write; SCI_WR <= '0'; SCI_RD <= '0'; - sci_state <= IDLE; + if (LOC_BUS_TX.ack = '1') then + sci_state <= IDLE; + BUS_TX.data <= LOC_BUS_TX.data; + BUS_TX.ack <= '1'; + end if; else sci_state <= SCTRL_WAIT; end if; @@ -113,6 +134,7 @@ begin sci_state <= SCTRL_FINISH; when SCTRL_FINISH => BUS_TX.data(7 downto 0) <= SCI_RDDATA; + BUS_TX.data(31 downto 8) <= x"000000"; BUS_TX.ack <= '1'; SCI_WR <= '0'; SCI_RD <= '0'; @@ -139,9 +161,9 @@ begin cnt := cnt + 1; end case; - if (BUS_RX.read = '1' or BUS_RX.write = '1') and sci_state /= IDLE then - BUS_TX.nack <= '1'; BUS_TX.ack <= '0'; - end if; +-- if (BUS_RX.read = '1' or BUS_RX.write = '1') and sci_state /= IDLE and sci_reg_i = '0' then +-- BUS_TX.nack <= '1'; BUS_TX.ack <= '0'; +-- end if; end process; diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index a52fcee..6e19ec8 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -27,6 +27,11 @@ entity tx_control is START_RETRANSMIT_IN : in std_logic := '0'; START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); + + FORCE_CRC_ERROR : in std_logic; + FORCE_PAK_ERROR : in std_logic; + GOT_FORCE_ERROR : out std_logic := '0'; + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM SEND_DLM : in std_logic := '0'; SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0'); @@ -261,7 +266,12 @@ begin when SEND_IDLE_L => TX_DATA_OUT <= K_IDLE; TX_K_OUT <= '1'; - current_state <= SEND_IDLE_H; + if FORCE_PAK_ERROR = '1' then + GOT_FORCE_ERROR <= '1'; + current_state <= SEND_DATA_H; + else + current_state <= SEND_IDLE_H; + end if; first_idle <= first_idle; load_eop <= '0'; resub_mode <= '0'; @@ -298,8 +308,13 @@ begin current_state <= SEND_CHKSUM_H; when SEND_CHKSUM_H => - TX_DATA_OUT <= crc_q; - + if FORCE_CRC_ERROR = '1' then + GOT_FORCE_ERROR <= '1'; + TX_DATA_OUT <= std_logic_vector(unsigned(crc_q) + 1); + else + TX_DATA_OUT <= crc_q; + end if; + when SEND_START_L => TX_DATA_OUT <= K_BGN; TX_K_OUT <= '1'; @@ -332,7 +347,8 @@ begin when SEND_RESET => TX_DATA_OUT <= K_RST; TX_K_OUT <= '1'; - resub_mode <= '0'; + resub_mode <= '0'; + if send_link_reset_qtx = '0' then current_state <= SEND_IDLE_L; end if; @@ -382,7 +398,9 @@ begin if reset_retrans = '1' then resub_mode <= '0'; end if; - + if FORCE_PAK_ERROR = '0' and FORCE_CRC_ERROR = '0' then + GOT_FORCE_ERROR <= '0'; + end if; end process;