From: hadeshyp <hadeshyp>
Date: Wed, 3 Jun 2009 12:48:11 +0000 (+0000)
Subject: attilio:. 1 long calibration , new default thresholds
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f4f26ac38773ad8c7ae95637105e78c22cce2a34;p=mdcoep.git

attilio:. 1 long calibration , new default thresholds
---

diff --git a/design/initialization_RAM.vhd b/design/initialization_RAM.vhd
index bd6c8bd..f24bbc0 100644
--- a/design/initialization_RAM.vhd
+++ b/design/initialization_RAM.vhd
@@ -274,8 +274,8 @@ architecture Structure of initialization_RAM is
 -------------------------------------------------------------------------------
 -- 
 -------------------------------------------------------------------------------
-    attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x000000000000000000000000000000000100011400061000340006100030000610001C0006100018";
-    attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00061000140006100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 35 31 1D 19 15 11 
+    attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x000000000000000000000000000000000100011400011000340001100030000110001C0001100018";
+    attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00011000140001100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 35 31 1D 19 15 11 
 
     attribute INITVAL_0B of initialization_RAM_0_0_0 : label is "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC";--REGISTER_3
                                                            --<REGISTER_3
@@ -381,8 +381,8 @@ begin
 -- FEE INIT: 1 LONG MB
 -------------------------------------------------------------------------------
 
-       INITVAL_0D=> "0x000000000000000000000000000000000100011400061000340006100030000610001C0006100018", -- GLOBAL DISABLE in CPLD
-       INITVAL_0C=> "0x00061000140006100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 35 31 1D 19 15 11 
+       INITVAL_0D=> "0x000000000000000000000000000000000100011400011000340001100030000110001C0001100018", -- GLOBAL DISABLE in CPLD
+       INITVAL_0C=> "0x00011000140001100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 35 31 1D 19 15 11 
      
        INITVAL_0B=> "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC",
                                                             --<REGISTER_3
diff --git a/design/load_ROC1_tdc_setup.vhd b/design/load_ROC1_tdc_setup.vhd
index 701bca9..420e1a8 100644
--- a/design/load_ROC1_tdc_setup.vhd
+++ b/design/load_ROC1_tdc_setup.vhd
@@ -21,7 +21,6 @@ library ecp2m;
 use ecp2m.components.all;
 -- synopsys translate_on
 
-
 entity load_ROC1_tdc_setup is
   generic (
     width                         : integer := 6);  -- number of bit of the counter if 4 and clk 100MHz
diff --git a/design/trigger_distributor.vhd b/design/trigger_distributor.vhd
index 2042798..df9e02b 100644
--- a/design/trigger_distributor.vhd
+++ b/design/trigger_distributor.vhd
@@ -73,10 +73,10 @@ architecture behavioral of trigger_distributor is
   signal debug_normal_trigger_number, debug_calibration_trigger_number : std_logic_vector(7 downto 0);
   signal debug_token_back_number                                       : std_logic_vector(7 downto 0);
   signal pulse_a_rdo_in                                                : std_logic;
-  signal pulse_begin_run_trigger                                       : std_logic;
+ -- signal pulse_begin_run_trigger                                       : std_logic;
   signal not_reset                                                     : std_logic;
   signal counter_wait_after_roc1                                       : std_logic_vector(12 downto 0);
-
+  signal pulse_internal_reset_in                                       : std_logic;
 -------------------------------------------------------------------------------
 -- I use this exeption for naming signal(they should be lower case in general). In this case
 -- capital letters with "reg" or "next" at the beginning.
@@ -85,7 +85,7 @@ architecture behavioral of trigger_distributor is
   signal reg_LED_ERROR_OUT, reg_LED_GOOD_OUT    : std_logic;
   signal next_LED_CNT_1_OUT, next_LED_CNT_2_OUT : std_logic;
   signal next_LED_ERROR_OUT, next_LED_GOOD_OUT  : std_logic;
-
+  signal reg_internal_reset_in  : std_logic;
 
   component edge_to_pulse
     port (
@@ -114,14 +114,14 @@ begin  -- behavioral
 -- After the the firmware is loaded in the FPGA, the begin run trigger is
 -- generated automatically and the FEE is initialized.
 -------------------------------------------------------------------------------
-  BEGIN_RUN_TRIGGER_FROM_RESET : edge_to_pulse
-    port map (
-      CLOCK            => CLK,
-      ENABLE_CLK_IN    => '1',
-      SIGNAL_IN        => not_reset,
-      PULSE_OUT        => pulse_begin_run_trigger);
+--   BEGIN_RUN_TRIGGER_FROM_RESET : edge_to_pulse
+--     port map (
+--       CLOCK            => CLK,
+--       ENABLE_CLK_IN    => '1',
+--       SIGNAL_IN        => not_reset,
+--       PULSE_OUT        => pulse_begin_run_trigger);
 
-  not_reset <= not(RESET);
+--   not_reset <= not(RESET);
 
 -------------------------------------------------------------------------------
 -- Register and reset for the FSM
@@ -172,11 +172,9 @@ begin  -- behavioral
 -- Check the .srr report! Also here signals in the sensitivity list are
 -- important for simulation 
 -------------------------------------------------------------------------------
-  process (current_state,
-           internal_calibration_trigger,
-           reg_trigger_type_in, reg_trigger_in,
-           ROC1_WRITTEN_IN, A_RDO_IN, pulse_begin_run_trigger,
-           counter_wait_after_roc1)
+  process (current_state, reg_trigger_in,
+           ROC1_WRITTEN_IN, A_RDO_IN, 
+           counter_wait_after_roc1, reg_internal_reset_in)
   begin
     
     next_debug_register       <= (others => '0');
@@ -202,11 +200,11 @@ begin  -- behavioral
         next_token_to_trb         <= '0';
         up_number_of_trigger      <= '0';
         reset_calibration_counter <= '0';
-        if (pulse_begin_run_trigger = '1') then
+        if (reg_internal_reset_in  = '1') then
           next_state              <= begrun_trigger_state;
         elsif (reg_trigger_in = '1') then
           if (register_trigger_condition(3 downto 0) = x"C") then
-            next_state            <= calibration_state;
+           next_state            <= calibration_state;
           else
             next_state            <= normal_trigger_state;
           end if;
@@ -393,9 +391,11 @@ begin  -- behavioral
       if RESET = '1' then
         reg_trigger_type_in          <= (others => '0');
         reg_trigger_in               <= '0';
+        reg_internal_reset_in <= '0';
       else
         reg_trigger_type_in          <= TRIGGER_TYPE_IN;
         reg_trigger_in               <= TRIGGER_IN;
+        reg_internal_reset_in        <= INTERNAL_RESET_IN; 
       end if;
     end if;
   end process;
@@ -405,27 +405,27 @@ begin  -- behavioral
 -- The calibration trigger is generated every
 -- x"register_trigger_condition(15 downto 4)" number of normal trigger
 -------------------------------------------------------------------------------
-  process (CLK, RESET, register_trigger_condition)
-  begin
-    if (rising_edge(CLK)) then
-      if (RESET = '1') then
-        internal_calibration_trigger <= '0';
+--   process (CLK, RESET, register_trigger_condition)
+--   begin
+--     if (rising_edge(CLK)) then
+--       if (RESET = '1') then
+--         internal_calibration_trigger <= '0';
 
---       elsif ( (register_trigger_condition(3 downto 0) = x"E") and
---               (counter_number_of_trigger(11 downto 0) = register_trigger_condition(15 downto 4)) ) then  --enable cal trigger
---         internal_calibration_trigger <= '1';
+-- --       elsif ( (register_trigger_condition(3 downto 0) = x"E") and
+-- --               (counter_number_of_trigger(11 downto 0) = register_trigger_condition(15 downto 4)) ) then  --enable cal trigger
+-- --         internal_calibration_trigger <= '1';
 
-      elsif (register_trigger_condition(3 downto 0) = x"C") then  --only cal trigger
-        internal_calibration_trigger <= '1';
+--       elsif (register_trigger_condition(3 downto 0) = x"C") then  --only cal trigger
+--         internal_calibration_trigger <= '1';
 
-      elsif (register_trigger_condition(3 downto 0) = x"D") then  --disable cal trigger
-        internal_calibration_trigger <= '0';
+--       elsif (register_trigger_condition(3 downto 0) = x"D") then  --disable cal trigger
+--         internal_calibration_trigger <= '0';
 
-      else
-        internal_calibration_trigger <= '0';
-      end if;
-    end if;
-  end process;
+--       else
+--         internal_calibration_trigger <= '0';
+--       end if;
+--     end if;
+--   end process;
 
   
 -------------------------------------------------------------------------------