From: Cahit Date: Mon, 21 Oct 2013 10:43:02 +0000 (+0200) Subject: corrections, remarks X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f51de5e82d25fb24d5e53a12eb15c1dab984b713;p=publication.git corrections, remarks --- diff --git a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf index 384e003..89d6408 100644 Binary files a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf and b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf differ diff --git a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex index b6f0e2a..61b972c 100644 --- a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex +++ b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex @@ -2,6 +2,11 @@ \pdfoutput=1 % only if pdf/png/jpg images are used \documentclass{JINST} + +\usepackage{changes} +\definechangesauthor[name={Cahit Ugur}, color=orange]{CU} + + \title{TRB3: A 264 Channel High Precision TDC Platform and Its Applications} \author{J.~Adamczewski-Musch$^a$, @@ -52,6 +57,7 @@ Digital electronic circuits; Data acquisition circuits} \usepackage[poorman]{cleveref} + \begin{document} \section{Introduction} @@ -59,8 +65,8 @@ Digital electronic circuits; Data acquisition circuits} The $4+1$ FPGA board ``TRB3'' (\cref{fig:trb3}a) can serve various applications in experimental particle physics and beyond due to its general-purpose design. It uses Lattice ECP3-150EA FPGAs as complex -commercial electronic components while realizing the remaining -auxiliary parts with simple standard components. Consequently, the +commercial electronic components while realising the remaining +auxiliary parts with simple standard components. Moreover, the board provides flexible connectivity by eight SFP ports and mezzanine extensions for every FPGA including a high pin-out for the peripheral FPGAs. We call this concept COME\&KISS: COMplex COMmercial Elements \& @@ -83,8 +89,8 @@ the platform. \includegraphics[width=\textwidth]{gfx/trb3/cts-web}\\ (b) \end{minipage} - \caption{(a) The TRB3 without any mezzazine cards. (b) Screenshot - showing the Central Trigger System webinterface.} + \caption{(a) The TRB3 without any mezzanine cards. (b) Screenshot + showing the Central Trigger System web interface.} \label{fig:trb3} \end{figure} @@ -103,26 +109,26 @@ The project provides a comfortable, robust and modular software environment, ranging from low-level register access to the FPGA firmwares on the command line to high-level control via web2.0 technologies, see \cref{sec:software}. This is complemented by -comprehensive specifications and documentation \cite{trb-web} +comprehensive specifications and documentations \cite{trb-web} provided by the large user base from the experiments HADES and PANDA at GSI in Darmstadt, Germany. -In \cref{sec:frontends}, existing front-ends and applications are -presented. In \cref{sec:juelich,sec:mainz}, results of two test -beamtimes are summarized in which the TRB3 platform has been +In \cref{sec:frontends} existing front-ends and applications are +presented. In \cref{sec:juelich,sec:mainz} results of two test +beamtimes are summarised in which the TRB3 platform has been successfully deployed. \section{Precise Time Digitisation in FPGA}\label{sec:tdc} -One key component of the TRB3 is the $64+1$ channel time-to-digital -converter (TDC) implemented in the peripheral FPGAs of the TRB3 with a -time precision down to $7.2$\,ps. It ``misuses'' FPGA resources (LUTs -as full-adders) as delay elements and can cope with burst hit rates of -up to $50$\,MHz. Owing to its flexible design, an application-specific -trade-off between number of channels, time precision and dead-time can -be achieved for each front-end design. Implementation details can be -found in \cite{ugur-twepp2011} and first applications are described in -\cite{ugur-twepp2012}. +One key component of the TRB3 is the $64+1$ channel time-to-digital converter +(TDC) implemented in the peripheral FPGAs of the TRB3 with a time precision +down to $7.2$\,ps on a single channel. It ``misuses'' FPGA resources (LUTs as +full-adders) as delay elements and can cope with burst hit rates of up to +$66$\,MHz. Owing to its flexible design, an application-specific trade-off +between number of channels, time precision and dead-time can be achieved for +each front-end design. Implementation details can be found in +\cite{ugur-twepp2011} and first applications are described in +\cite{ugur-twepp2012}. \section{Software Environment}\label{sec:software} @@ -144,31 +150,33 @@ trigger event numbers are available. Additionally, the platform enables every user group to profit from common software developments, such as a ``standalone'' ROOT unpacker -\cite{unpacker-web} for the TDC datastream including methods for the +\cite{unpacker-web} for the TDC data-stream including methods for the calibration of the delay lines. In this case, the data is usually acquired with the HADES DAQ software system in HLD files and -subsequently analyzed offline. There are also interfaces to DABC +subsequently analysed offline. There are also interfaces to DABC \cite{dabc-web} which enables online monitoring and calibration of the TRB3 read-out. -Since the length of each delay line of the TDC depends highly on the -specific placing and thus routing of the elements inside the FPGA, a -proper calibration of this fine-time is necessary. This can be done -simply by assuming that each element has the same propagation delay, -but this limits the time resolution to about $1$\,ns. If one assumes -that the read-out clock is uncorrelated to the measured signals, a -\emph{flat} fine-time histogram of all detected signals is expected. -Any deviation must be due to different propagation delays and thus -each element can be calibrated appropiately (details see -\cite{ugur-twepp2011}). However, if the detector signal rate is not -sufficient (leading to insufficient statistics in the fine-time -histogram), artifical hits stemming from an uncorrelated signal source -must be additionally generated and read-out. This technique is already -available on the TRB3 and is currently under test. +Since the length of the total propagation delay on each delay line of the TDC +depends highly on the specific placing and routing of the elements inside the +FPGA, a proper calibration of this fine-time is necessary. This can be done +simply by assuming that each element has the same propagation delay, but this +limits the time precision to about $1$\,ns. \added[id=CU]{(where did you get + this information from? From my measurements I get up to 40 ps precision. But + sometimes there is the risk of getting double or more peaks. So this method + is only for test purposes. I don't think this should be in the paper.)} If +one assumes that the read-out clock is uncorrelated to the measured signals, a +\emph{flat} fine-time histogram of all detected signals is expected. Any +deviation must be due to different propagation delays, thus each element +can be calibrated appropriately (details see \cite{ugur-twepp2011}). However, +if the detector signal rate is not sufficient (leading to insufficient +statistics in the fine-time histogram), artificial hits stemming from an +uncorrelated signal source must be additionally generated and read-out. This +technique is already available on the TRB3 and is currently under test. \section{Front-end Electronics}\label{sec:frontends} -% To convert the analog signals from the detector to digital pulses +% To convert the analogue signals from the detector to digital pulses % suitable for the TDC, the front-end electronics board PaDiWa was % designed using the differential input buffers of an FPGA as % discriminators with a PWM generated voltage as a variable threshold. @@ -187,7 +195,7 @@ available on the TRB3 and is currently under test. \centering \begin{minipage}{0.4\linewidth} \centering - \includegraphics[width=\textwidth]{gfx/frontends/padiwa}\\ + \includegraphics[width=\textwidth]{gfx/frontends/padiwa_transparent.png}\\ (a) \end{minipage} \quad @@ -197,19 +205,21 @@ available on the TRB3 and is currently under test. (b) \end{minipage} \caption{(a) The PaDiWa leading edge discriminator front-end. Other - versions with different analog connectors are available. (b) The - schematic for one channel showing the KISS part (FPGA excluded).} + versions with different analogue connectors are available. (b) The + schematic of one channel showing the KISS part (FPGA excluded).} \label{fig:padiwa} \end{figure} The PaDiWa\footnote{Acronym for PANDA, DIRC, WASA.} is the first front-end board following the COME\&KISS principle (\cref{fig:padiwa}). It uses the LVDS input buffers of a Lattice -MachXO2 FPGA to realize a leading edge discriminator for $16$ analog -input signals. Besides that, only standard components like an $10$x -MMIC wideband amplifier and and RC low-passes to generate the -threshold voltages via PWM are used. Using test pulses with an -amplitude of $500$\,$\mu$V and a length of $6$\,ns, a time resolution +MachXO2 FPGA to realise a leading edge discriminator for $16$ analogue +input signals. \replaced[id=CU]{Besides that, few standard components like $10$x +MMIC wideband amplifiers and RC low-passes are used to generate the +threshold voltages via PWM.}{Besides that, only standard components like an $10$x +MMIC wideband amplifier and RC low-passes to generate the +threshold voltages via PWM are used.} Using test pulses with an +amplitude of $500$\,$\mu$V and a length of $6$\,ns, a time precision of the full system including the TRB3 of $23$\,ps was measured \cite{ugur-twepp2012}. This front-end has been successfully used in the test beamtimes, see \cref{sec:juelich,sec:mainz}. @@ -234,31 +244,30 @@ the test beamtimes, see \cref{sec:juelich,sec:mainz}. \end{minipage} \caption{The Charge-to-Width front-end for HADES ECAL. (a) The layout again illustrating the COME\&KISS principle. (b) The - corresponding schematic for one channel (excluding the FPGA)} + corresponding schematic of one channel (excluding the FPGA)} \label{fig:qdc} \end{figure} -The charge information of the pulse extracted from time over threshold -is usually not precise enough for calorimeters. Thus, the leading edge -measurement can be complemented by a modified Wilkinson ADC circuit, -which encodes the charge in the width of the digital pulse delivered -to the TDC. A proof-of-concept board was already successfully tested -and a version with an improved dynamic range is currently designed for -the HADES ECAL detector (\cref{fig:qdc}). It is based on the -experience with the PaDiWa board and provides $8$ input channels -(using in total $32$ FPGA TDC channels for two leading edges and two -trailing edges for each input channel) with a charge resolution of -$0.2$\,\% and a high dynamic range of $250$. +The charge information of a pulse extracted from the time over threshold +measurement is usually not precise enough for calorimeters. Thus, the leading +edge measurement can be complemented by a modified Wilkinson ADC circuit, +which encodes the charge in the width of the digital pulse delivered to the +TDC. A proof-of-concept board was already successfully tested and a version +with an improved dynamic range is currently designed for the HADES ECAL +detector (\cref{fig:qdc}). It is based on the experience with the PaDiWa board +and provides $8$ input channels (using in total $32$ FPGA TDC channels for two +leading edges and two trailing edges for each input channel) with a charge +precision of $0.2$\,\% and a high dynamic range of $250$. \subsection{n-XYTER ASIC for HADES Pion Tracker} -The TRB3 can also be used as an infrastructure to read out specialized +The TRB3 can also be used as an infrastructure to read out specialised integrated solutions using the peripheral FPGAs, for example to provide a timing reference, transport the acquired data to the eventbuilder and slow control configuration of the chip. This was -realized for the n-XYTER ASIC, which provides the timestamp and the +realised for the n-XYTER ASIC, which provides the timestamp and the pulse height of self-triggered $128$ channels. In this case, the -integration of read-out and slow control (e.\,g. trigger windows) on +integration of the read-out and slow control (e.\,g. trigger windows) on the peripheral FPGA was easily achieved due to the well-documented VHDL interfaces of the TRB3 platform. @@ -289,8 +298,8 @@ The test beamtime took place in J\"{u}lich behind the TOF experiment (\cref{fig:juelich}) in October 2012. Here, protons with a momentum of $2.95$\,GeV and a rate of $10^7$\,Hz were scattered at a target and detected in two different DIRC detectors. Additionally, different -multi-anodes PMTs were tested. In total, 10 TRB3s with PaDiWa -front-ends were used providing $2400$ channels in total. It was the +multi-anode PMTs were tested. In total, 10 TRB3s with PaDiWa +front-ends were used providing $2400$ channels. It was the largest system of TRB3s used in a test beamtime so far and has worked successfully. @@ -324,7 +333,7 @@ MAMI-B microtron in Mainz (electron accelerator) with a beam energy of $855$\,MeV. A Cherenkov counter prototype using the DIRC principle was placed in the beam line. The prototype comprises a highly-polished fused silica bar with a lens attached, an oil-filled expansion volume -and a photon detector matrix of up to $6$ $64$-channel MCP-PMTs which +and a photon detector matrix of $6$ $64$-channel MCP-PMTs, which were read out by the TRB3 system. In total, 4 TRB3s with TDC implementations were used with two different discriminator front-ends: the PaDiWa and the NINO ASIC. The beam current was set to achieve a @@ -341,14 +350,14 @@ Finally, we present some planned or ongoing extensions of the platform. The detection of leading and trailing edge in a single TDC channel, which doubles the number of channels per board for timestamp and width measurements. This feature is highly desired for the -described charge-to-width front-end. The temperature stability of the -PaDiWa thresholds and of the TDC calibration is currently -investigated. There are also two further front-end developments: -Integration of the MuPix ASIC for the PANDA luminosity detector and -the SPADIC ASIC for a TPC in Mainz. Since both ASICs use the CBMnet -protocol, an implementation of CBMnet on the TRB3 was started. -Furthermore, an extension of TrbNet with defined propagation delays of -trigger signals for PANDA is being developed and tested. +described charge-to-width front-end. The temperature +\replaced[id=CU]{independence}{stability} of the PaDiWa thresholds and of the +TDC calibration is currently investigated. There are also two further +front-end developments: Integration of the MuPix ASIC for the PANDA luminosity +detector and the SPADIC ASIC for a TPC in Mainz. Since both ASICs use the +CBMnet protocol, an implementation of CBMnet on the TRB3 was +started. Furthermore, an extension of TrbNet with defined propagation delays +of trigger signals for PANDA is being developed and tested.