From: hadeshyp Date: Fri, 21 Jan 2011 15:58:29 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~130 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f577b2201fc8138df96c4f6dfcccf0ee41bb45e6;p=trbnet.git *** empty log message *** --- diff --git a/lattice/ecp2m/trb_net16_fifo_arch.vhd b/lattice/ecp2m/trb_net16_fifo_arch.vhd index b7d2e6c..b933069 100644 --- a/lattice/ecp2m/trb_net16_fifo_arch.vhd +++ b/lattice/ecp2m/trb_net16_fifo_arch.vhd @@ -19,6 +19,7 @@ entity trb_net16_fifo is WRITE_ENABLE_IN : in std_logic; DATA_OUT : out std_logic_vector(15 downto 0); -- Output data PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data + DATA_COUNT_OUT : out std_logic_vector(10 downto 0); READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag EMPTY_OUT : out std_logic @@ -89,6 +90,7 @@ begin din(c_DATA_WIDTH + 1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 1 downto c_DATA_WIDTH); + DATA_COUNT_OUT <= (others => '0'); -- gen_FIFO6 : if DEPTH = 6 generate fifo:lattice_ecp2m_fifo_18x1k diff --git a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd index 3bce0be..faef295 100755 --- a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd +++ b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd @@ -110,8 +110,8 @@ generic( port( refclkp : in std_logic; refclkn : in std_logic; - rxrefclk : in std_logic; - refclk : in std_logic; +-- rxrefclk : in std_logic; +-- refclk : in std_logic; rxa_pclk : out std_logic; rxb_pclk : out std_logic; hdinp_0 : in std_logic; @@ -559,8 +559,8 @@ gen_serdes_0_100_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = port map( refclkp => SD_REFCLK_P_IN, refclkn => SD_REFCLK_N_IN, - rxrefclk => '0', -- raw 100MHz clock - refclk => '0', -- raw 100MHz clock +-- rxrefclk => '0', -- raw 100MHz clock +-- refclk => '0', -- raw 100MHz clock rxa_pclk => rx_halfclk, -- clock multiplier set by data bus width rxb_pclk => open, hdinp_0 => SD_RXD_P_IN, -- SerDes I/O diff --git a/special/trb_net_bridge_pcie_apl.vhd b/special/trb_net_bridge_pcie_apl.vhd index 8902010..67f34f9 100644 --- a/special/trb_net_bridge_pcie_apl.vhd +++ b/special/trb_net_bridge_pcie_apl.vhd @@ -8,6 +8,9 @@ use work.trb_net_components.all; entity trb_net_bridge_pcie_apl is + generic( + USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES) + ); port( CLK : in std_logic; RESET : in std_logic; @@ -30,12 +33,13 @@ entity trb_net_bridge_pcie_apl is APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + APL_FIFO_COUNT_IN : in std_logic_vector (11*2**(c_MUX_WIDTH)-1 downto 0); --Internal Data Bus BUS_ADDR_IN : in std_logic_vector(31 downto 0); - BUS_WDAT_IN : in std_logic_vector(63 downto 0); - BUS_RDAT_OUT : out std_logic_vector(63 downto 0); - BUS_SEL_IN : in std_logic_vector(7 downto 0); + BUS_WDAT_IN : in std_logic_vector(31 downto 0); + BUS_RDAT_OUT : out std_logic_vector(31 downto 0); + BUS_SEL_IN : in std_logic_vector(3 downto 0); BUS_WE_IN : in std_logic; BUS_CYC_IN : in std_logic; BUS_STB_IN : in std_logic; @@ -79,22 +83,18 @@ end entity; architecture trb_net_bridge_pcie_apl_arch of trb_net_bridge_pcie_apl is signal fifo_net_to_pci_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); - signal fifo_net_to_pci_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); +-- signal fifo_net_to_pci_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); signal fifo_net_to_pci_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); - signal fifo_net_to_pci_din : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0); +-- signal fifo_net_to_pci_din : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0); signal fifo_net_to_pci_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); - signal fifo_net_to_pci_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal fifo_net_to_pci_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); - signal fifo_pci_to_net_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); - signal fifo_pci_to_net_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); - signal fifo_pci_to_net_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); - signal fifo_pci_to_net_dout : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0); - signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); - signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); +-- signal fifo_pci_to_net_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); +-- signal fifo_pci_to_net_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); +-- signal fifo_pci_to_net_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); +-- signal fifo_pci_to_net_dout : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0); +-- signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); +-- signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); - type data_count_t is array(0 to 2**c_MUX_WIDTH-1) of std_logic_vector(10 downto 0); - signal fifo_pci_to_net_data_count : data_count_t; - signal fifo_net_to_pci_data_count : data_count_t; signal sender_control : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); signal sender_target : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); signal sender_error : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); @@ -105,16 +105,16 @@ architecture trb_net_bridge_pcie_apl_arch of trb_net_bridge_pcie_apl is -- signal comb_channel_address : integer range 0 to 7; -- signal last_CPU_ADDRESS : std_logic_vector(15 downto 0); - signal next_CPU_DATA_OUT: std_logic_vector(31 downto 0); - signal buf_CPU_DATA_OUT : std_logic_vector(31 downto 0); - signal last_fifo_read : std_logic; - signal buf_CPU_DATAREADY_OUT : std_logic; - signal b_CPU_DATAREADY_OUT : std_logic; +-- signal next_CPU_DATA_OUT: std_logic_vector(31 downto 0); +-- signal buf_CPU_DATA_OUT : std_logic_vector(31 downto 0); +-- signal last_fifo_read : std_logic; +-- signal buf_CPU_DATAREADY_OUT : std_logic; +-- signal b_CPU_DATAREADY_OUT : std_logic; signal bus_ack_i : std_logic; - signal bus_data_i : std_logic_vector(63 downto 0); - signal bus_rdat_i : std_logic_vector(63 downto 0); + signal bus_data_i : std_logic_vector(31 downto 0); + signal bus_rdat_i : std_logic_vector(31 downto 0); signal bus_read_i : std_logic; signal bus_write_i : std_logic; signal bus_stb_rising : std_logic; @@ -133,17 +133,17 @@ begin STAT(12) <= bus_ack_i; STAT(13) <= fifo_net_to_pci_read(1); STAT(15 downto 14) <= BUS_WDAT_IN(1 downto 0); - STAT(16) <= fifo_pci_to_net_read(1); - STAT(17) <= fifo_pci_to_net_valid_read(1); - STAT(18) <= fifo_pci_to_net_empty(1); - STAT(19) <= fifo_pci_to_net_write(1); + STAT(16) <= '0'; --fifo_pci_to_net_read(1); + STAT(17) <= '0'; --fifo_pci_to_net_valid_read(1); + STAT(18) <= '0'; --fifo_pci_to_net_empty(1); + STAT(19) <= '0'; --fifo_pci_to_net_write(1); STAT(20) <= APL_READ_IN(1); - STAT(21) <= fifo_pci_to_net_full(1); + STAT(21) <= '0'; --fifo_pci_to_net_full(1); STAT(22) <= RESET; STAT(23) <= '0'; STAT(24) <= fifo_net_to_pci_empty(1); STAT(25) <= fifo_net_to_pci_read(1); - STAT(26) <= fifo_net_to_pci_write(1); + STAT(26) <= '0'; --fifo_net_to_pci_write(1); STAT(31 downto 27) <= (others => '0'); -------------------------------- @@ -164,12 +164,9 @@ begin bus_write_i <= BUS_WE_IN and bus_stb_rising; channel_address <= to_integer(unsigned(BUS_ADDR_IN(6 downto 4))); --- comb_channel_address <= conv_integer(CPU_ADDRESS(6 downto 4)); - read_regs : process(sender_control, sender_target, sender_error, sender_status, fifo_net_to_pci_data_count, - fifo_pci_to_net_data_count, BUS_ADDR_IN, bus_read_i, bus_write_i, api_status, - fifo_net_to_pci_full, fifo_net_to_pci_empty, fifo_pci_to_net_full, fifo_pci_to_net_empty, - bus_data_i, BUS_WDAT_IN, channel_address, CTRL) + read_regs : process(sender_control, sender_target, sender_error, sender_status, APL_FIFO_COUNT_IN, + BUS_ADDR_IN, api_status, fifo_net_to_pci_empty, bus_data_i, channel_address, fifo_net_to_pci_dout) variable tmp : std_logic_vector(7 downto 0); begin bus_data_i <= (others => '0'); @@ -177,23 +174,26 @@ begin case tmp is --middle nibble is dont care when x"10" => - bus_data_i <= x"00000000" & sender_control(channel_address*32+31 downto channel_address*32); + bus_data_i <= sender_control(channel_address*32+31 downto channel_address*32); when x"11" => - bus_data_i <= x"00000000" & sender_target(channel_address*32+31 downto channel_address*32); + bus_data_i <= sender_target(channel_address*32+31 downto channel_address*32); when x"12" => - bus_data_i <= x"00000000" & sender_error(channel_address*32+31 downto channel_address*32); - when x"14" => - bus_data_i <= x"00000000" & x"000" & "00" & fifo_pci_to_net_empty(channel_address) & fifo_pci_to_net_full(channel_address) - & "000000" & fifo_pci_to_net_data_count(channel_address)(9 downto 0); + bus_data_i <= sender_error(channel_address*32+31 downto channel_address*32); +-- when x"14" => +-- bus_data_i <= x"000" & "00" & fifo_pci_to_net_empty(channel_address) & fifo_pci_to_net_full(channel_address) +-- & "000000" & fifo_pci_to_net_data_count(channel_address)(9 downto 0); when x"1F" => - bus_data_i <= x"00000000" & sender_status(channel_address*32+31 downto channel_address*32); + bus_data_i <= sender_status(channel_address*32+31 downto channel_address*32); + when x"23" => + bus_data_i <= fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32); when x"24" => - bus_data_i <= x"00000000" & x"000" & "00" & fifo_net_to_pci_empty(channel_address) & fifo_net_to_pci_full(channel_address) - & "00000" & fifo_net_to_pci_data_count(channel_address)(10 downto 0); - when x"30" => - bus_data_i <= x"00000000" & api_status(channel_address*32+31 downto channel_address*32); + bus_data_i <= x"000" & "00" & fifo_net_to_pci_empty(channel_address) & '0' + & "00000" & APL_FIFO_COUNT_IN(11*channel_address+10 downto 11*channel_address); + when x"30" =>-- fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost, but transfer size is limited anyhow + + bus_data_i <= api_status(channel_address*32+31 downto channel_address*32); when others => - bus_data_i <= x"00000000" & x"10000000"; --"1000000000000000000" & CTRL(31 downto 19); + bus_data_i <= x"10000000"; --"1000000000000000000" & CTRL(31 downto 19); end case; end process; @@ -255,108 +255,64 @@ begin --connection to API - next_APL_SEND_OUT(i) <= '1' when BUS_ADDR_IN(11 downto 8) = "0001" + next_APL_SEND_OUT(i) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1" and BUS_ADDR_IN(7 downto 4) = std_logic_vector(to_unsigned(i,4)) - and BUS_ADDR_IN(3 downto 0) = "0000" + and BUS_ADDR_IN(3 downto 0) = x"0" and bus_write_last = '1' else '0'; - APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i); - APL_DATA_OUT((i+1)*16-1 downto i*16) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH-1 downto i*18); - APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH+1 downto i*18+c_DATA_WIDTH); - APL_PACKET_NUM_OUT(i*3+2) <= '0'; + APL_DATAREADY_OUT(i) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1" + and BUS_ADDR_IN(7 downto 4) = std_logic_vector(to_unsigned(i,4)) + and BUS_ADDR_IN(3 downto 0) = x"3" + and bus_write_i = '1' else '0'; + + APL_DATA_OUT((i+1)*16-1 downto i*16) <= BUS_WDAT_IN(15 downto 0); + APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= BUS_WDAT_IN(17 downto 16); + APL_PACKET_NUM_OUT(i*3+2) <= '0'; APL_SHORT_TRANSFER_OUT(i) <= sender_control(i*32+8); APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32); APL_TARGET_ADDRESS_OUT(i*16+15 downto i*16) <= sender_target(i*32+15 downto i*32); APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32); - fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost, but transfer size is limited anyhow --connection from API - fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= fifo_net_to_pci_data_count(i)(6 downto 0); - fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0'); - fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i); - - fifo_net_to_pci_din(18*i+c_DATA_WIDTH-1 downto 18*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); - fifo_net_to_pci_din(18*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i); - fifo_net_to_pci_din(18*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2); - fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i) and not fifo_net_to_pci_full(i); - APL_READ_OUT(i) <= not fifo_net_to_pci_full(i); + fifo_net_to_pci_empty(i) <= not APL_DATAREADY_IN(i); --or_all(APL_FIFO_COUNT_IN(11*i+10 downto 11*i)); + + fifo_net_to_pci_dout(32*i+c_DATA_WIDTH-1 downto 32*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); + fifo_net_to_pci_dout(32*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i); + fifo_net_to_pci_dout(32*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2); + fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= (others => '0'); + fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i); + fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0'); + APL_READ_OUT(i) <= fifo_net_to_pci_read(i); + +-- fifo_net_to_pci_din(18*i+c_DATA_WIDTH-1 downto 18*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); +-- fifo_net_to_pci_din(18*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i); +-- fifo_net_to_pci_din(18*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2); +-- fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i) and not fifo_net_to_pci_full(i); +-- APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i); +-- APL_DATA_OUT((i+1)*16-1 downto i*16) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH-1 downto i*18); +-- APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH+1 downto i*18+c_DATA_WIDTH); +-- APL_PACKET_NUM_OUT(i*3+2) <= '0'; +-- fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost, but transfer size is limited anyhow end generate; --------------------------------- --- fifo as bridge to pci --------------------------------- - - - gen_incoming_fifos : for i in 0 to 2**(c_MUX_WIDTH)-1 generate - - FIFO_NET_TO_PCI: trb_net16_fifo - generic map( - USE_VENDOR_CORES => c_YES, - USE_DATA_COUNT => c_YES, - DEPTH => 6 - ) - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => '1', - READ_ENABLE_IN => fifo_net_to_pci_read(i), - WRITE_ENABLE_IN => fifo_net_to_pci_write(i), - DATA_IN => fifo_net_to_pci_din(18*i+15 downto 18*i), - PACKET_NUM_IN => fifo_net_to_pci_din(18*i+17 downto 18*i+16), - DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i), - PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16), - DATA_COUNT_OUT => fifo_net_to_pci_data_count(i)(10 downto 0), - full_out => fifo_net_to_pci_full(i), - empty_out => fifo_net_to_pci_empty(i) - ); - - FIFO_PCI_TO_NET: trb_net16_fifo - generic map( - USE_VENDOR_CORES => c_YES, - USE_DATA_COUNT => c_YES, - DEPTH => 6 - ) - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => '1', - READ_ENABLE_IN => fifo_pci_to_net_read(i), - WRITE_ENABLE_IN => fifo_pci_to_net_write(i), - DATA_IN => BUS_WDAT_IN(15 downto 0), - PACKET_NUM_IN => BUS_WDAT_IN(17 downto 16), - DATA_OUT => fifo_pci_to_net_dout(18*i+15 downto 18*i), - PACKET_NUM_OUT => fifo_pci_to_net_dout(18*i+17 downto 18*i+16), - DATA_COUNT_OUT => fifo_pci_to_net_data_count(i)(10 downto 0), - full_out => fifo_pci_to_net_full(i), - empty_out => fifo_pci_to_net_empty(i) - ); - - end generate; - - proc_valid_read : process(CLK) - begin - if rising_edge(CLK) then - fifo_pci_to_net_valid_read <= fifo_pci_to_net_read and not fifo_pci_to_net_empty; - fifo_net_to_pci_valid_read <= fifo_net_to_pci_read and not fifo_net_to_pci_empty; - end if; - end process; - proc_fifo_readwrite : process(BUS_ADDR_IN, bus_read_i, bus_write_i, channel_address) + proc_fifo_readwrite : process(BUS_ADDR_IN, bus_read_i, channel_address, APL_DATAREADY_IN, fifo_net_to_pci_read) begin + fifo_net_to_pci_valid_read <= fifo_net_to_pci_read and APL_DATAREADY_IN; fifo_net_to_pci_read <= (others => '0'); - fifo_pci_to_net_write <= (others => '0'); if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then fifo_net_to_pci_read(channel_address) <= bus_read_i; end if; - if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"13" then - fifo_pci_to_net_write(channel_address) <= bus_write_i; - end if; end process; + + bus_rdat_i <= bus_data_i(31 downto 0); + bus_ack_i <= (bus_read_i or bus_write_i); + proc_register_cpu_output : process(CLK) begin if rising_edge(CLK) then @@ -365,16 +321,73 @@ begin end if; end process; - process(BUS_ADDR_IN, bus_data_i, fifo_net_to_pci_dout, bus_read_i, bus_write_i, channel_address) - begin - if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then - bus_rdat_i <= fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32) & fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32); - bus_ack_i <= (bus_read_last or bus_write_i); - else - bus_rdat_i <= bus_data_i(31 downto 0) & bus_data_i(31 downto 0); - bus_ack_i <= (bus_read_i or bus_write_i); - end if; - end process; +-- process(BUS_ADDR_IN, bus_data_i, fifo_net_to_pci_dout, bus_read_i, bus_write_i, channel_address) +-- begin +-- if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then +-- bus_rdat_i <= fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32); +-- bus_ack_i <= (bus_read_i or bus_write_i); +-- else + +-- end if; +-- end process; + + +-------------------------------- +-- fifo as bridge to pci +-------------------------------- + + +-- gen_incoming_fifos : for i in 0 to 2**(c_MUX_WIDTH)-1 generate +-- gen_used_fifos : if USE_CHANNELS(i/2) = c_YES generate +-- -- FIFO_NET_TO_PCI: trb_net16_fifo +-- -- generic map( +-- -- USE_VENDOR_CORES => c_YES, +-- -- USE_DATA_COUNT => c_YES, +-- -- DEPTH => 6 +-- -- ) +-- -- port map( +-- -- CLK => CLK, +-- -- RESET => RESET, +-- -- CLK_EN => '1', +-- -- READ_ENABLE_IN => fifo_net_to_pci_read(i), +-- -- WRITE_ENABLE_IN => fifo_net_to_pci_write(i), +-- -- DATA_IN => fifo_net_to_pci_din(18*i+15 downto 18*i), +-- -- PACKET_NUM_IN => fifo_net_to_pci_din(18*i+17 downto 18*i+16), +-- -- DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i), +-- -- PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16), +-- -- DATA_COUNT_OUT => fifo_net_to_pci_data_count(i)(10 downto 0), +-- -- full_out => fifo_net_to_pci_full(i), +-- -- empty_out => fifo_net_to_pci_empty(i) +-- -- ); +-- +-- -- FIFO_PCI_TO_NET: trb_net16_fifo +-- -- generic map( +-- -- USE_VENDOR_CORES => c_YES, +-- -- USE_DATA_COUNT => c_YES, +-- -- DEPTH => 6 +-- -- ) +-- -- port map( +-- -- CLK => CLK, +-- -- RESET => RESET, +-- -- CLK_EN => '1', +-- -- READ_ENABLE_IN => fifo_pci_to_net_read(i), +-- -- WRITE_ENABLE_IN => fifo_pci_to_net_write(i), +-- -- DATA_IN => BUS_WDAT_IN(15 downto 0), +-- -- PACKET_NUM_IN => BUS_WDAT_IN(17 downto 16), +-- -- DATA_OUT => fifo_pci_to_net_dout(18*i+15 downto 18*i), +-- -- PACKET_NUM_OUT => fifo_pci_to_net_dout(18*i+17 downto 18*i+16), +-- -- DATA_COUNT_OUT => fifo_pci_to_net_data_count(i)(10 downto 0), +-- -- full_out => fifo_pci_to_net_full(i), +-- -- empty_out => fifo_pci_to_net_empty(i) +-- -- ); +-- end generate; +-- end generate; + +-- proc_valid_read : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- end if; +-- end process; -------------------------------- diff --git a/special/trb_net_bridge_pcie_endpoint.vhd b/special/trb_net_bridge_pcie_endpoint.vhd index e873b49..71fda63 100644 --- a/special/trb_net_bridge_pcie_endpoint.vhd +++ b/special/trb_net_bridge_pcie_endpoint.vhd @@ -10,16 +10,16 @@ use work.trb_net_components.all; entity trb_net_bridge_pcie_endpoint is generic( USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES); - AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_NO,c_NO,c_NO,c_NO) + AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_YES,c_YES,c_YES,c_YES) ); port( RESET : in std_logic; CLK: in std_logic; BUS_ADDR_IN : in std_logic_vector(31 downto 0); - BUS_WDAT_IN : in std_logic_vector(63 downto 0); - BUS_RDAT_OUT : out std_logic_vector(63 downto 0); - BUS_SEL_IN : in std_logic_vector(7 downto 0); + BUS_WDAT_IN : in std_logic_vector(31 downto 0); + BUS_RDAT_OUT : out std_logic_vector(31 downto 0); + BUS_SEL_IN : in std_logic_vector(3 downto 0); BUS_WE_IN : in std_logic; BUS_CYC_IN : in std_logic; BUS_STB_IN : in std_logic; @@ -68,6 +68,7 @@ architecture trb_net_bridge_pcie_endpoint_arch of trb_net_bridge_pcie_endpoint i signal APL_TARGET_ADDRESS_OUT : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0); signal APL_ERROR_PATTERN_IN : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); signal APL_TARGET_ADDRESS_IN : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0); + signal APL_FIFO_COUNT_OUT : std_logic_vector(2**(c_MUX_WIDTH)*11-1 downto 0); signal APL_MY_ADDRESS_IN : std_logic_vector(15 downto 0); signal buf_api_stat_fifo_to_int : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); @@ -411,24 +412,25 @@ begin APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, APL_LENGTH_IN => x"FFFF", APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8), + APL_FIFO_COUNT_OUT => APL_FIFO_COUNT_OUT((2*i+1)*11+10 downto (2*i+1)*11), -- Internal direction port INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), - INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), - INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), - INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i), + INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i), INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i), - INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), - INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), - CTRL_SEQNR_RESET => '0', + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), + CTRL_SEQNR_RESET => '0', -- Status and control port STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32), STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) @@ -439,18 +441,35 @@ begin + APL_READ_OUT(2*i) <= '0'; + APL_DATAREADY_OUT(2*i) <= '0'; + APL_RUN_OUT(2*i) <= '0'; + APL_SEQNR_OUT(2*i*8+7 downto 2*i*8) <= (others => '0'); + APL_DATA_OUT(2*i*c_DATA_WIDTH+15 downto 2*i*c_DATA_WIDTH) <= (others => '0'); + APL_PACKET_NUM_OUT(2*i*c_NUM_WIDTH+2 downto 2*i*c_NUM_WIDTH) <= (others => '0'); + APL_TYP_OUT(2*i*3+2 downto 2*i*3) <= (others => '0'); + APL_FIFO_COUNT_OUT(2*i*11+10 downto 2*i*11) <= (others => '0'); + buf_api_stat_fifo_to_int(2*i*32+31 downto 2*i*32) <= (others => '0'); + buf_api_stat_fifo_to_apl(2*i*32+31 downto 2*i*32) <= (others => '0'); + + end generate; end generate; gen_no_api : if USE_CHANNELS(i) = c_NO generate APL_READ_OUT(2*i+1) <= '1'; - APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH) <= (others => '0'); - APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH) <= (others => '0'); - APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3) <= (others => '0'); + APL_READ_OUT(2*i) <= '1'; + APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i)*c_DATA_WIDTH) <= (others => '0'); + APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i)*c_NUM_WIDTH) <= (others => '0'); + APL_TYP_OUT((2*i+2)*3-1 downto (2*i)*3) <= (others => '0'); APL_DATAREADY_OUT(2*i+1) <= '0'; + APL_DATAREADY_OUT(2*i) <= '0'; APL_RUN_OUT(2*i+1) <= '0'; - APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8) <= (others => '0'); - buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32) <= (others => '0'); - buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) <= (others => '0'); + APL_RUN_OUT(2*i) <= '0'; + APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i)*8) <= (others => '0'); + buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i)*32) <= (others => '0'); + buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i)*32) <= (others => '0'); + tmp_apl_to_buf_init_data(i*16+15 downto i*16) <= (others => '0'); + APL_FIFO_COUNT_OUT(2*i*11+21 downto 2*i*11) <= (others => '0'); end generate; end generate; @@ -470,6 +489,9 @@ begin APL : trb_net_bridge_pcie_apl + generic map( + USE_CHANNELS => USE_CHANNELS + ) port map( CLK => CLK, RESET => RESET_i, @@ -490,6 +512,7 @@ begin APL_RUN_IN => APL_RUN_OUT, APL_SEQNR_IN => APL_SEQNR_OUT, APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN, + APL_FIFO_COUNT_IN => APL_FIFO_COUNT_OUT, EXT_TRIGGER_INFO => reg_extended_trigger_information, BUS_ADDR_IN => BUS_ADDR_IN, BUS_WDAT_IN => BUS_WDAT_IN, diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index afaab69..6e34136 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -52,6 +52,7 @@ entity trb_net16_api_base is APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); APL_SEQNR_OUT : out std_logic_vector (7 downto 0); APL_LENGTH_IN : in std_logic_vector (15 downto 0); + APL_FIFO_COUNT_OUT : out std_logic_vector (10 downto 0); -- Internal direction port -- the ports with master or slave in their name are to be mapped by the active api @@ -116,6 +117,7 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal fifo_to_apl_read : std_logic; signal fifo_to_apl_full : std_logic; signal fifo_to_apl_empty : std_logic; + signal fifo_to_apl_data_count : std_logic_vector(10 downto 0); signal next_fifo_to_apl_data_out : std_logic_vector(15 downto 0); signal next_fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0); signal next_fifo_to_apl_full : std_logic; @@ -420,7 +422,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; -- fifo to apl --------------------------------------- - GEN_FIFO_TO_APL: if FIFO_TO_APL_DEPTH >0 generate +-- GEN_FIFO_TO_APL: if FIFO_TO_APL_DEPTH >0 generate FIFO_TO_APL: trb_net16_fifo generic map ( DEPTH => FIFO_TO_APL_DEPTH, @@ -435,10 +437,11 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; DATA_OUT => next_fifo_to_apl_data_out, PACKET_NUM_OUT => next_fifo_to_apl_packet_num_out, READ_ENABLE_IN => fifo_to_apl_read, + DATA_COUNT_OUT => fifo_to_apl_data_count, FULL_OUT => fifo_to_apl_full, EMPTY_OUT => next_fifo_to_apl_empty ); - end generate; +-- end generate; -- GEN_DUMMY_FIFO_TO_APL: if FIFO_TO_APL_DEPTH = 0 generate -- FIFO_TO_APL: trb_net16_dummy_fifo diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index c504bb1..979ccae 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -321,7 +321,7 @@ begin --since we count only 64Bit packets, each counter is updated on the last packet --the EOB and ACK flags must be available when the last packet is sent. --full buffers (despite the sbuf) can only occur on the last packet. - COMB_NEXT_TRANSFER : process(comb_dataready, transfer_counter, current_NOP_word, + COMB_NEXT_TRANSFER : process(transfer_counter, current_NOP_word, int_dataready_in_i, reg_INT_READ_OUT, saved_packet_type, sending_state, current_DATA_word, send_ACK, send_EOB, sbuf_free, RESET, diff --git a/trb_net16_sbuf.vhd b/trb_net16_sbuf.vhd index f7fbbb8..21b93b9 100644 --- a/trb_net16_sbuf.vhd +++ b/trb_net16_sbuf.vhd @@ -82,6 +82,7 @@ begin SYN_READ_IN => SYN_READ_IN, STAT_BUFFER => STAT_BUFFER ); + DEBUG_OUT <= (others => '0'); end generate; gen_version_2 : if VERSION = 2 generate @@ -102,6 +103,7 @@ begin SYN_READ_IN => SYN_READ_IN, STAT_BUFFER => STAT_BUFFER ); + DEBUG_OUT <= (others => '0'); end generate; gen_version_3 : if VERSION = 3 generate @@ -122,6 +124,7 @@ begin SYN_READ_IN => SYN_READ_IN, STAT_BUFFER => STAT_BUFFER ); + DEBUG_OUT <= (others => '0'); end generate; gen_version_4 : if VERSION = 4 generate @@ -142,6 +145,7 @@ begin SYN_READ_IN => SYN_READ_IN, STAT_BUFFER => STAT_BUFFER ); + DEBUG_OUT <= (others => '0'); end generate; gen_version_5 : if VERSION = 5 generate diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 833156f..4c3d88a 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -170,6 +170,7 @@ end component trb_net16_med_scm_sfp_gbe; APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); APL_SEQNR_OUT : out std_logic_vector (7 downto 0); APL_LENGTH_IN : in std_logic_vector (15 downto 0); + APL_FIFO_COUNT_OUT : out std_logic_vector (10 downto 0); -- Internal direction port -- the ports with master or slave in their name are to be mapped by the active api -- to the init respectivly the reply path and vice versa in the passive api. @@ -260,6 +261,9 @@ end component trb_net16_med_scm_sfp_gbe; component trb_net_bridge_pcie_apl is + generic( + USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES) + ); port( CLK : in std_logic; RESET : in std_logic; @@ -282,17 +286,18 @@ end component trb_net16_med_scm_sfp_gbe; APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + APL_FIFO_COUNT_IN : in std_logic_vector (11*2**(c_MUX_WIDTH)-1 downto 0); --Internal Data Bus BUS_ADDR_IN : in std_logic_vector(31 downto 0); - BUS_WDAT_IN : in std_logic_vector(63 downto 0); - BUS_RDAT_OUT : out std_logic_vector(63 downto 0); - BUS_SEL_IN : in std_logic_vector(7 downto 0); + BUS_WDAT_IN : in std_logic_vector(31 downto 0); + BUS_RDAT_OUT : out std_logic_vector(31 downto 0); + BUS_SEL_IN : in std_logic_vector(3 downto 0); BUS_WE_IN : in std_logic; BUS_CYC_IN : in std_logic; BUS_STB_IN : in std_logic; BUS_LOCK_IN : in std_logic; - BUS_CTI_IN : in std_logic_vector(2 downto 0); + -- BUS_CTI_IN : in std_logic_vector(2 downto 0); BUS_ACK_OUT : out std_logic; EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0); @@ -316,14 +321,14 @@ end component trb_net16_med_scm_sfp_gbe; CLK: in std_logic; BUS_ADDR_IN : in std_logic_vector(31 downto 0); - BUS_WDAT_IN : in std_logic_vector(63 downto 0); - BUS_RDAT_OUT : out std_logic_vector(63 downto 0); - BUS_SEL_IN : in std_logic_vector(7 downto 0); + BUS_WDAT_IN : in std_logic_vector(31 downto 0); + BUS_RDAT_OUT : out std_logic_vector(31 downto 0); + BUS_SEL_IN : in std_logic_vector(3 downto 0); BUS_WE_IN : in std_logic; BUS_CYC_IN : in std_logic; BUS_STB_IN : in std_logic; BUS_LOCK_IN : in std_logic; - BUS_CTI_IN : in std_logic_vector(2 downto 0); +-- BUS_CTI_IN : in std_logic_vector(2 downto 0); BUS_ACK_OUT : out std_logic; MED_DATAREADY_IN : in STD_LOGIC; @@ -2550,6 +2555,7 @@ end component; SYN_DATAREADY_OUT: out STD_LOGIC; SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); SYN_READ_IN: in STD_LOGIC; + DEBUG_OUT : out std_logic_vector(15 downto 0); STAT_BUFFER: out STD_LOGIC ); end component;