From: Ludwig Maier Date: Thu, 24 Oct 2013 04:19:43 +0000 (+0200) Subject: nxyter, new working Timestamp Handler, ADC still not working correctly X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f630ced4ed3391b6538e767db42506cd30de8af4;p=trb3.git nxyter, new working Timestamp Handler, ADC still not working correctly --- diff --git a/nxyter/cores/fifo_44_data_delay.ipx b/nxyter/cores/fifo_44_data_delay.ipx index 71fca1c..3181ca9 100644 --- a/nxyter/cores/fifo_44_data_delay.ipx +++ b/nxyter/cores/fifo_44_data_delay.ipx @@ -1,9 +1,9 @@ - + - - - - + + + + diff --git a/nxyter/cores/fifo_44_data_delay.lpc b/nxyter/cores/fifo_44_data_delay.lpc index 6549a89..574e7bf 100644 --- a/nxyter/cores/fifo_44_data_delay.lpc +++ b/nxyter/cores/fifo_44_data_delay.lpc @@ -16,8 +16,8 @@ CoreRevision=4.8 ModuleName=fifo_44_data_delay SourceFormat=VHDL ParameterFileVersion=1.0 -Date=09/29/2013 -Time=20:18:14 +Date=10/20/2013 +Time=20:31:33 [Parameters] Verilog=0 @@ -28,7 +28,7 @@ Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 FIFOImp=EBR Based -Depth=128 +Depth=256 Width=44 regout=1 CtrlByRdEn=1 diff --git a/nxyter/cores/fifo_44_data_delay.vhd b/nxyter/cores/fifo_44_data_delay.vhd index 9acc944..dbb1041 100644 --- a/nxyter/cores/fifo_44_data_delay.vhd +++ b/nxyter/cores/fifo_44_data_delay.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) -- Module Version: 4.8 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 44 -depth 128 -regout -pe 0 -pf -1 -e +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 44 -depth 256 -regout -pe 0 -pf -1 -e --- Sun Sep 29 20:18:15 2013 +-- Sun Oct 20 20:31:33 2013 library IEEE; use IEEE.std_logic_1164.all; @@ -18,7 +18,7 @@ entity fifo_44_data_delay is WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - AmEmptyThresh: in std_logic_vector(6 downto 0); + AmEmptyThresh: in std_logic_vector(7 downto 0); Q: out std_logic_vector(43 downto 0); Empty: out std_logic; Full: out std_logic; @@ -33,7 +33,7 @@ architecture Structure of fifo_44_data_delay is signal rden_i_inv: std_logic; signal invout_0: std_logic; signal r_nw: std_logic; - signal rcnt_reg_6_inv: std_logic; + signal rcnt_reg_7_inv: std_logic; signal fcnt_en: std_logic; signal empty_i: std_logic; signal empty_d: std_logic; @@ -47,6 +47,7 @@ architecture Structure of fifo_44_data_delay is signal wptr_5: std_logic; signal wptr_6: std_logic; signal wptr_7: std_logic; + signal wptr_8: std_logic; signal rptr_0: std_logic; signal rptr_1: std_logic; signal rptr_2: std_logic; @@ -55,6 +56,7 @@ architecture Structure of fifo_44_data_delay is signal rptr_5: std_logic; signal rptr_6: std_logic; signal rptr_7: std_logic; + signal rptr_8: std_logic; signal ffidata_0: std_logic; signal ffidata_1: std_logic; signal ffidata_2: std_logic; @@ -99,7 +101,7 @@ architecture Structure of fifo_44_data_delay is signal ffidata_41: std_logic; signal ffidata_42: std_logic; signal ffidata_43: std_logic; - signal rcnt_reg_7: std_logic; + signal rcnt_reg_8: std_logic; signal ifcount_0: std_logic; signal ifcount_1: std_logic; signal bdcnt_bctr_ci: std_logic; @@ -111,13 +113,16 @@ architecture Structure of fifo_44_data_delay is signal co1: std_logic; signal ifcount_6: std_logic; signal ifcount_7: std_logic; - signal co3: std_logic; - signal cnt_con: std_logic; signal co2: std_logic; + signal ifcount_8: std_logic; + signal co4: std_logic; + signal cnt_con: std_logic; + signal co3: std_logic; signal cmp_ci: std_logic; signal co0_1: std_logic; signal co1_1: std_logic; signal co2_1: std_logic; + signal co3_1: std_logic; signal cmp_le_1: std_logic; signal cmp_le_1_c: std_logic; signal cmp_ci_1: std_logic; @@ -131,9 +136,11 @@ architecture Structure of fifo_44_data_delay is signal fcount_5: std_logic; signal co2_2: std_logic; signal wren_i: std_logic; - signal wren_i_inv: std_logic; signal fcount_6: std_logic; signal fcount_7: std_logic; + signal co3_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_8: std_logic; signal cmp_ge_d1: std_logic; signal cmp_ge_d1_c: std_logic; signal iwcount_0: std_logic; @@ -147,9 +154,11 @@ architecture Structure of fifo_44_data_delay is signal co1_3: std_logic; signal iwcount_6: std_logic; signal iwcount_7: std_logic; - signal co3_1: std_logic; - signal wcount_7: std_logic; signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal co4_1: std_logic; + signal wcount_8: std_logic; + signal co3_3: std_logic; signal scuba_vhi: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; @@ -162,9 +171,11 @@ architecture Structure of fifo_44_data_delay is signal co1_4: std_logic; signal ircount_6: std_logic; signal ircount_7: std_logic; - signal co3_2: std_logic; - signal rcount_7: std_logic; signal co2_4: std_logic; + signal ircount_8: std_logic; + signal co4_2: std_logic; + signal rcount_8: std_logic; + signal co3_4: std_logic; signal rcnt_sub_0: std_logic; signal r_nw_inv_inv: std_logic; signal rcount_0: std_logic; @@ -192,8 +203,13 @@ architecture Structure of fifo_44_data_delay is signal wcount_5: std_logic; signal wcount_6: std_logic; signal rcnt_sub_7: std_logic; - signal co3_3: std_logic; + signal rcnt_sub_8: std_logic; + signal co3_5: std_logic; + signal rcount_7: std_logic; + signal wcount_7: std_logic; signal rcnt_sub_msb: std_logic; + signal co4_3d: std_logic; + signal co4_3: std_logic; signal rden_i: std_logic; signal cmp_ci_2: std_logic; signal rcnt_reg_0: std_logic; @@ -206,6 +222,8 @@ architecture Structure of fifo_44_data_delay is signal rcnt_reg_5: std_logic; signal co2_6: std_logic; signal rcnt_reg_6: std_logic; + signal rcnt_reg_7: std_logic; + signal co3_6: std_logic; signal ae_set_clrsig: std_logic; signal ae_set_setsig: std_logic; signal ae_set_d: std_logic; @@ -342,6 +360,12 @@ architecture Structure of fifo_44_data_delay is attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_44_data_delay.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; attribute GSR of FF_94 : label is "ENABLED"; attribute GSR of FF_93 : label is "ENABLED"; attribute GSR of FF_92 : label is "ENABLED"; @@ -487,19 +511,19 @@ begin port map (A=>r_nw, Z=>r_nw_inv); XOR2_t2: XOR2 - port map (A=>wcount_7, B=>rcount_7, Z=>rcnt_sub_msb); + port map (A=>wcount_8, B=>rcount_8, Z=>rcnt_sub_msb); INV_1: INV port map (A=>r_nw_inv, Z=>r_nw_inv_inv); INV_0: INV - port map (A=>rcnt_reg_6, Z=>rcnt_reg_6_inv); + port map (A=>rcnt_reg_7, Z=>rcnt_reg_7_inv); AND2_t1: AND2 - port map (A=>rcnt_reg_7, B=>rcnt_reg_6_inv, Z=>ae_set_clrsig); + port map (A=>rcnt_reg_8, B=>rcnt_reg_7_inv, Z=>ae_set_clrsig); AND2_t0: AND2 - port map (A=>rcnt_reg_7, B=>rcnt_reg_6, Z=>ae_set_setsig); + port map (A=>rcnt_reg_8, B=>rcnt_reg_7, Z=>ae_set_setsig); pdp_ram_0_0_1: PDPW16KC generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", @@ -516,14 +540,14 @@ begin DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, - ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, + ADR12=>rptr_7, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_18, DO1=>ffidata_19, DO2=>ffidata_20, DO3=>ffidata_21, DO4=>ffidata_22, @@ -555,381 +579,403 @@ begin DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, - ADW6=>wptr_6, ADW7=>scuba_vlo, ADW8=>scuba_vlo, - BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, - DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, - DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, - DO14=>open, DO15=>open, DO16=>open, DO17=>open, - DO18=>ffidata_36, DO19=>ffidata_37, DO20=>ffidata_38, - DO21=>ffidata_39, DO22=>ffidata_40, DO23=>ffidata_41, - DO24=>ffidata_42, DO25=>ffidata_43, DO26=>open, DO27=>open, - DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open, - DO33=>open, DO34=>open, DO35=>open); - - FF_94: FD1P3DX + ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>Clock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, + ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7, + ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo, + CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>open, + DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open, + DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open, + DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open, + DO16=>open, DO17=>open, DO18=>ffidata_36, DO19=>ffidata_37, + DO20=>ffidata_38, DO21=>ffidata_39, DO22=>ffidata_40, + DO23=>ffidata_41, DO24=>ffidata_42, DO25=>ffidata_43, + DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open, + DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open); + + FF_100: FD1P3DX port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_0); - FF_93: FD1P3DX + FF_99: FD1P3DX port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_1); - FF_92: FD1P3DX + FF_98: FD1P3DX port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_2); - FF_91: FD1P3DX + FF_97: FD1P3DX port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_3); - FF_90: FD1P3DX + FF_96: FD1P3DX port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_4); - FF_89: FD1P3DX + FF_95: FD1P3DX port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_5); - FF_88: FD1P3DX + FF_94: FD1P3DX port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_6); - FF_87: FD1P3DX + FF_93: FD1P3DX port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_7); - FF_86: FD1S3BX + FF_92: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_91: FD1S3BX port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); - FF_85: FD1S3DX + FF_90: FD1S3DX port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); - FF_84: FD1P3BX + FF_89: FD1P3BX port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, Q=>wcount_0); - FF_83: FD1P3DX + FF_88: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_1); - FF_82: FD1P3DX + FF_87: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_2); - FF_81: FD1P3DX + FF_86: FD1P3DX port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_3); - FF_80: FD1P3DX + FF_85: FD1P3DX port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_4); - FF_79: FD1P3DX + FF_84: FD1P3DX port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_5); - FF_78: FD1P3DX + FF_83: FD1P3DX port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_6); - FF_77: FD1P3DX + FF_82: FD1P3DX port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_7); - FF_76: FD1P3BX + FF_81: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_80: FD1P3BX port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, Q=>rcount_0); - FF_75: FD1P3DX + FF_79: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_1); - FF_74: FD1P3DX + FF_78: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_2); - FF_73: FD1P3DX + FF_77: FD1P3DX port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_3); - FF_72: FD1P3DX + FF_76: FD1P3DX port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_4); - FF_71: FD1P3DX + FF_75: FD1P3DX port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_5); - FF_70: FD1P3DX + FF_74: FD1P3DX port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_6); - FF_69: FD1P3DX + FF_73: FD1P3DX port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_7); - FF_68: FD1P3DX + FF_72: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_71: FD1P3DX port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_0); - FF_67: FD1P3DX + FF_70: FD1P3DX port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_1); - FF_66: FD1P3DX + FF_69: FD1P3DX port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_2); - FF_65: FD1P3DX + FF_68: FD1P3DX port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_3); - FF_64: FD1P3DX + FF_67: FD1P3DX port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_4); - FF_63: FD1P3DX + FF_66: FD1P3DX port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_5); - FF_62: FD1P3DX + FF_65: FD1P3DX port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_6); - FF_61: FD1P3DX + FF_64: FD1P3DX port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_7); - FF_60: FD1P3DX + FF_63: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_62: FD1P3DX port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_0); - FF_59: FD1P3DX + FF_61: FD1P3DX port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_1); - FF_58: FD1P3DX + FF_60: FD1P3DX port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_2); - FF_57: FD1P3DX + FF_59: FD1P3DX port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_3); - FF_56: FD1P3DX + FF_58: FD1P3DX port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_4); - FF_55: FD1P3DX + FF_57: FD1P3DX port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_5); - FF_54: FD1P3DX + FF_56: FD1P3DX port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_6); - FF_53: FD1P3DX + FF_55: FD1P3DX port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_7); - FF_52: FD1P3DX + FF_54: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_53: FD1P3DX port map (D=>ffidata_0, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(0)); - FF_51: FD1P3DX + FF_52: FD1P3DX port map (D=>ffidata_1, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(1)); - FF_50: FD1P3DX + FF_51: FD1P3DX port map (D=>ffidata_2, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(2)); - FF_49: FD1P3DX + FF_50: FD1P3DX port map (D=>ffidata_3, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(3)); - FF_48: FD1P3DX + FF_49: FD1P3DX port map (D=>ffidata_4, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(4)); - FF_47: FD1P3DX + FF_48: FD1P3DX port map (D=>ffidata_5, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(5)); - FF_46: FD1P3DX + FF_47: FD1P3DX port map (D=>ffidata_6, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(6)); - FF_45: FD1P3DX + FF_46: FD1P3DX port map (D=>ffidata_7, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(7)); - FF_44: FD1P3DX + FF_45: FD1P3DX port map (D=>ffidata_8, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(8)); - FF_43: FD1P3DX + FF_44: FD1P3DX port map (D=>ffidata_9, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(9)); - FF_42: FD1P3DX + FF_43: FD1P3DX port map (D=>ffidata_10, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(10)); - FF_41: FD1P3DX + FF_42: FD1P3DX port map (D=>ffidata_11, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(11)); - FF_40: FD1P3DX + FF_41: FD1P3DX port map (D=>ffidata_12, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(12)); - FF_39: FD1P3DX + FF_40: FD1P3DX port map (D=>ffidata_13, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(13)); - FF_38: FD1P3DX + FF_39: FD1P3DX port map (D=>ffidata_14, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(14)); - FF_37: FD1P3DX + FF_38: FD1P3DX port map (D=>ffidata_15, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(15)); - FF_36: FD1P3DX + FF_37: FD1P3DX port map (D=>ffidata_16, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(16)); - FF_35: FD1P3DX + FF_36: FD1P3DX port map (D=>ffidata_17, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(17)); - FF_34: FD1P3DX + FF_35: FD1P3DX port map (D=>ffidata_18, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(18)); - FF_33: FD1P3DX + FF_34: FD1P3DX port map (D=>ffidata_19, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(19)); - FF_32: FD1P3DX + FF_33: FD1P3DX port map (D=>ffidata_20, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(20)); - FF_31: FD1P3DX + FF_32: FD1P3DX port map (D=>ffidata_21, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(21)); - FF_30: FD1P3DX + FF_31: FD1P3DX port map (D=>ffidata_22, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(22)); - FF_29: FD1P3DX + FF_30: FD1P3DX port map (D=>ffidata_23, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(23)); - FF_28: FD1P3DX + FF_29: FD1P3DX port map (D=>ffidata_24, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(24)); - FF_27: FD1P3DX + FF_28: FD1P3DX port map (D=>ffidata_25, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(25)); - FF_26: FD1P3DX + FF_27: FD1P3DX port map (D=>ffidata_26, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(26)); - FF_25: FD1P3DX + FF_26: FD1P3DX port map (D=>ffidata_27, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(27)); - FF_24: FD1P3DX + FF_25: FD1P3DX port map (D=>ffidata_28, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(28)); - FF_23: FD1P3DX + FF_24: FD1P3DX port map (D=>ffidata_29, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(29)); - FF_22: FD1P3DX + FF_23: FD1P3DX port map (D=>ffidata_30, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(30)); - FF_21: FD1P3DX + FF_22: FD1P3DX port map (D=>ffidata_31, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(31)); - FF_20: FD1P3DX + FF_21: FD1P3DX port map (D=>ffidata_32, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(32)); - FF_19: FD1P3DX + FF_20: FD1P3DX port map (D=>ffidata_33, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(33)); - FF_18: FD1P3DX + FF_19: FD1P3DX port map (D=>ffidata_34, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(34)); - FF_17: FD1P3DX + FF_18: FD1P3DX port map (D=>ffidata_35, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(35)); - FF_16: FD1P3DX + FF_17: FD1P3DX port map (D=>ffidata_36, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(36)); - FF_15: FD1P3DX + FF_16: FD1P3DX port map (D=>ffidata_37, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(37)); - FF_14: FD1P3DX + FF_15: FD1P3DX port map (D=>ffidata_38, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(38)); - FF_13: FD1P3DX + FF_14: FD1P3DX port map (D=>ffidata_39, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(39)); - FF_12: FD1P3DX + FF_13: FD1P3DX port map (D=>ffidata_40, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(40)); - FF_11: FD1P3DX + FF_12: FD1P3DX port map (D=>ffidata_41, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(41)); - FF_10: FD1P3DX + FF_11: FD1P3DX port map (D=>ffidata_42, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(42)); - FF_9: FD1P3DX + FF_10: FD1P3DX port map (D=>ffidata_43, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(43)); - FF_8: FD1S3DX + FF_9: FD1S3DX port map (D=>rcnt_sub_0, CK=>Clock, CD=>Reset, Q=>rcnt_reg_0); - FF_7: FD1S3DX + FF_8: FD1S3DX port map (D=>rcnt_sub_1, CK=>Clock, CD=>Reset, Q=>rcnt_reg_1); - FF_6: FD1S3DX + FF_7: FD1S3DX port map (D=>rcnt_sub_2, CK=>Clock, CD=>Reset, Q=>rcnt_reg_2); - FF_5: FD1S3DX + FF_6: FD1S3DX port map (D=>rcnt_sub_3, CK=>Clock, CD=>Reset, Q=>rcnt_reg_3); - FF_4: FD1S3DX + FF_5: FD1S3DX port map (D=>rcnt_sub_4, CK=>Clock, CD=>Reset, Q=>rcnt_reg_4); - FF_3: FD1S3DX + FF_4: FD1S3DX port map (D=>rcnt_sub_5, CK=>Clock, CD=>Reset, Q=>rcnt_reg_5); - FF_2: FD1S3DX + FF_3: FD1S3DX port map (D=>rcnt_sub_6, CK=>Clock, CD=>Reset, Q=>rcnt_reg_6); - FF_1: FD1S3DX + FF_2: FD1S3DX port map (D=>rcnt_sub_7, CK=>Clock, CD=>Reset, Q=>rcnt_reg_7); + FF_1: FD1S3DX + port map (D=>rcnt_sub_8, CK=>Clock, CD=>Reset, Q=>rcnt_reg_8); + FF_0: FD1S3BX port map (D=>ae_set_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty); @@ -953,6 +999,10 @@ begin port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>open); + e_cmp_ci_a: FADD2B port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, @@ -972,7 +1022,11 @@ begin e_cmp_3: ALEB2 port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co2_1, LE=>cmp_le_1_c); + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c); a0: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -997,8 +1051,12 @@ begin CI=>co1_2, GE=>co2_2); g_cmp_3: AGEB2 - port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i_inv, - CI=>co2_2, GE=>cmp_ge_d1_c); + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co3_2, GE=>cmp_ge_d1_c); a1: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -1023,9 +1081,13 @@ begin NC0=>iwcount_4, NC1=>iwcount_5); w_ctr_3: CU2 - port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_1, + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, NC0=>iwcount_6, NC1=>iwcount_7); + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4_1, + NC0=>iwcount_8, NC1=>open); + scuba_vhi_inst: VHI port map (Z=>scuba_vhi); @@ -1047,9 +1109,13 @@ begin NC0=>ircount_4, NC1=>ircount_5); r_ctr_3: CU2 - port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_2, + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, NC0=>ircount_6, NC1=>ircount_7); + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>scuba_vlo, CO=>co4_2, + NC0=>ircount_8, NC1=>open); + rcnt_0: FSUB2B port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv, B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, @@ -1065,12 +1131,16 @@ begin rcnt_3: FSUB2B port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_5, B1=>rcount_6, - BI=>co2_5, BOUT=>co3_3, S0=>rcnt_sub_5, S1=>rcnt_sub_6); + BI=>co2_5, BOUT=>co3_5, S0=>rcnt_sub_5, S1=>rcnt_sub_6); rcnt_4: FSUB2B - port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co3_3, BOUT=>open, S0=>rcnt_sub_7, - S1=>open); + port map (A0=>wcount_7, A1=>rcnt_sub_msb, B0=>rcount_7, + B1=>scuba_vlo, BI=>co3_5, BOUT=>co4_3, S0=>rcnt_sub_7, + S1=>rcnt_sub_8); + + rcntd: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co4_3, COUT=>open, S0=>co4_3d, S1=>open); ae_set_cmp_ci_a: FADD2B port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, @@ -1089,8 +1159,12 @@ begin B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_6, GE=>co2_6); ae_set_cmp_3: AGEB2 - port map (A0=>AmEmptyThresh(6), A1=>ae_set_setsig, - B0=>rcnt_reg_6, B1=>ae_set_clrsig, CI=>co2_6, GE=>ae_set_d_c); + port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), + B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_6, GE=>co3_6); + + ae_set_cmp_4: AGEB2 + port map (A0=>ae_set_setsig, A1=>scuba_vlo, B0=>ae_set_clrsig, + B1=>scuba_vlo, CI=>co3_6, GE=>ae_set_d_c); scuba_vlo_inst: VLO port map (Z=>scuba_vlo); diff --git a/nxyter/cores/fifo_ts_12to12_dc.ipx b/nxyter/cores/fifo_ts_12to12_dc.ipx deleted file mode 100644 index 269f6d9..0000000 --- a/nxyter/cores/fifo_ts_12to12_dc.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/nxyter/cores/fifo_ts_12to12_dc.lpc b/nxyter/cores/fifo_ts_12to12_dc.lpc deleted file mode 100644 index e76f067..0000000 --- a/nxyter/cores/fifo_ts_12to12_dc.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN672C -SpeedGrade=8 -Package=FPBGA672 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_ts_12to12_dc -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=10/02/2013 -Time=03:07:43 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=2 -Width=12 -RDepth=2 -RWidth=12 -regout=1 -CtrlByRdEn=1 -EmpFlg=0 -PeMode=Static - Single Threshold -PeAssert=2 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/nxyter/cores/fifo_ts_12to12_dc.vhd b/nxyter/cores/fifo_ts_12to12_dc.vhd deleted file mode 100644 index 488b08e..0000000 --- a/nxyter/cores/fifo_ts_12to12_dc.vhd +++ /dev/null @@ -1,481 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 5.4 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2 -width 12 -depth 2 -rdata_width 12 -regout -pe -1 -pf -1 -e - --- Wed Oct 2 03:07:43 2013 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_ts_12to12_dc is - port ( - Data: in std_logic_vector(11 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(11 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_ts_12to12_dc; - -architecture Structure of fifo_ts_12to12_dc is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_gdata_0: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal r_gdata_0: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal co0: std_logic; - signal wcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal co0_1: std_logic; - signal rcount_1: std_logic; - signal r_gctr_ci: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_0: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_0: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_ts_12to12_dc.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - AND2_t4: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t3: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t2: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t1: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t0: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_1, AD2=>rcount_1, AD1=>w_gcount_r21, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_1, AD2=>rcount_1, AD1=>w_gcount_r21, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_1, AD2=>wcount_1, AD1=>r_gcount_w21, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_1, AD2=>wcount_1, AD1=>r_gcount_w21, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>scuba_vlo, DIA13=>scuba_vlo, - DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo, - DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, - ADA5=>scuba_vlo, ADA6=>scuba_vlo, ADA7=>scuba_vlo, - ADA8=>scuba_vlo, ADA9=>scuba_vlo, ADA10=>scuba_vlo, - ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, - ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo, - ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo, - ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, - CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), - DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), - DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11), DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - FF_21: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_20: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_19: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_18: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_17: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_16: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_15: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_14: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_13: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_12: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_11: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_10: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_9: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_8: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_7: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_6: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_5: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_4: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_3: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_2: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>empty_cmp_set, B0=>wcount_r0, - B1=>empty_cmp_clr, CI=>cmp_ci, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>full_cmp_set, B0=>rcount_w0, - B1=>full_cmp_clr, CI=>cmp_ci_1, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_ts_12to12_dc is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/nxyter/cores/pll_nx_clk250.ipx b/nxyter/cores/pll_nx_clk250.ipx index 1b83f83..8bcbb75 100644 --- a/nxyter/cores/pll_nx_clk250.ipx +++ b/nxyter/cores/pll_nx_clk250.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/nxyter/cores/pll_nx_clk250.lpc b/nxyter/cores/pll_nx_clk250.lpc index 62403ff..83f8158 100644 --- a/nxyter/cores/pll_nx_clk250.lpc +++ b/nxyter/cores/pll_nx_clk250.lpc @@ -16,8 +16,8 @@ CoreRevision=5.3 ModuleName=pll_nx_clk250 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=10/02/2013 -Time=16:44:45 +Date=10/20/2013 +Time=03:05:02 [Parameters] Verilog=0 @@ -50,9 +50,9 @@ ClkOSDelay=0 PhaseDuty=Static CLKOK_INPUT=CLKOP SecD=2 -U_KFrq=50 +U_KFrq=125 OK_Tol=0.0 -KFrq= +KFrq=125.000000 ClkRst=0 PCDR=0 FINDELA=0 @@ -61,6 +61,6 @@ Bandwidth=1.753251 ;DelayControl=No EnCLKOS=0 ClkOSBp=0 -EnCLKOK=0 +EnCLKOK=1 ClkOKBp=0 enClkOK2=0 diff --git a/nxyter/cores/pll_nx_clk250.vhd b/nxyter/cores/pll_nx_clk250.vhd index 7a3029e..02f8c81 100644 --- a/nxyter/cores/pll_nx_clk250.vhd +++ b/nxyter/cores/pll_nx_clk250.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) -- Module Version: 5.3 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 125 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw -e --- Wed Oct 2 16:44:46 2013 +-- Sun Oct 20 03:05:02 2013 library IEEE; use IEEE.std_logic_1164.all; @@ -15,6 +15,7 @@ entity pll_nx_clk250 is port ( CLK: in std_logic; CLKOP: out std_logic; + CLKOK: out std_logic; LOCK: out std_logic); attribute dont_touch : boolean; attribute dont_touch of pll_nx_clk250 : entity is true; @@ -53,8 +54,10 @@ architecture Structure of pll_nx_clk250 is end component; attribute FREQUENCY_PIN_CLKOP : string; attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "250.000000"; attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "125.000000"; attribute syn_keep : boolean; attribute syn_noprune : boolean; attribute syn_noprune of Structure : architecture is true; @@ -81,7 +84,7 @@ begin DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, - CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open); CLKOP <= CLKOP_t; diff --git a/nxyter/source/nx_data_delay.vhd b/nxyter/source/nx_data_delay.vhd index a5c8eb9..a988f09 100644 --- a/nxyter/source/nx_data_delay.vhd +++ b/nxyter/source/nx_data_delay.vhd @@ -22,7 +22,7 @@ entity nx_data_delay is ADC_DATA_OUT : out std_logic_vector(11 downto 0); NEW_DATA_OUT : out std_logic; - FIFO_DELAY_IN : in std_logic_vector(6 downto 0); + FIFO_DELAY_IN : in std_logic_vector(7 downto 0); -- Slave bus SLV_READ_IN : in std_logic; @@ -65,7 +65,7 @@ architecture Behavioral of nx_data_delay is signal slv_no_more_data_o : std_logic; signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; - signal fifo_delay : std_logic_vector(6 downto 0); + signal fifo_delay : std_logic_vector(7 downto 0); signal fifo_delay_reset : std_logic; begin @@ -80,7 +80,7 @@ begin DEBUG_OUT(6) <= fifo_read_enable; DEBUG_OUT(7) <= fifo_data_valid; DEBUG_OUT(8) <= new_data_o; - DEBUG_OUT(15 downto 9) <= fifo_delay; + DEBUG_OUT(15 downto 9) <= fifo_delay(6 downto 0); ----------------------------------------------------------------------------- -- FIFO Delay Handler @@ -164,16 +164,18 @@ begin begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1') then - fifo_delay <= "0000001"; + fifo_delay <= x"01"; fifo_delay_reset <= '0'; else fifo_delay_reset <= '0'; - if (fifo_delay /= FIFO_DELAY_IN) then - if (unsigned(FIFO_DELAY_IN) >= 1 and - unsigned(FIFO_DELAY_IN) <= 120) then + if ((FIFO_DELAY_IN /= fifo_delay) and + (unsigned(FIFO_DELAY_IN) >= 1) and + (unsigned(FIFO_DELAY_IN) <= 250) + ) then fifo_delay <= FIFO_DELAY_IN; fifo_delay_reset <= '1'; - end if; + else + fifo_delay_reset <= '0'; end if; end if; end if; @@ -200,8 +202,8 @@ begin if (SLV_READ_IN = '1') then case SLV_ADDR_IN is when x"0000" => - slv_data_o( 6 downto 0) <= fifo_delay; - slv_data_o(31 downto 7) <= (others => '0'); + slv_data_o( 7 downto 0) <= fifo_delay; + slv_data_o(31 downto 8) <= (others => '0'); slv_ack_o <= '1'; when others => diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 1adbea2..7db0342 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -12,7 +12,7 @@ entity nx_data_receiver is port( CLK_IN : in std_logic; RESET_IN : in std_logic; - NX_MAIN_CLK_IN : in std_logic; + NX_DATA_CLK_TEST_IN : in std_logic; TRIGGER_IN : in std_logic; -- nXyter Ports @@ -52,26 +52,17 @@ end entity; architecture Behavioral of nx_data_receiver is - ----------------------------------------------------------------------------- - -- NX_MAIN_CLK Domain - ----------------------------------------------------------------------------- - - -- Check Nxyter Data Clock - signal nx_data_clock_t : std_logic; - signal nx_data_clock : std_logic; - signal nx_data_clock_last : std_logic; - signal nx_data_clock_nok : std_logic; - - -- CLK_IN Domain - signal nx_data_clock_invalid : std_logic; + -- Clock Check + signal counter_nx_domain : unsigned(7 downto 0); + signal counter_nx_ref_domain : unsigned(7 downto 0); + signal counter_nx_diff : unsigned(7 downto 0); ----------------------------------------------------------------------------- -- NX_TIMESTAMP_CLK Domain ----------------------------------------------------------------------------- -- FIFO DC Input Handler - signal nx_timestamp_reg_t : std_logic_vector(7 downto 0); - signal nx_timestamp_reg : std_logic_vector(7 downto 0); + signal nx_timestamp_ff : std_logic_vector(7 downto 0); signal nx_fifo_full : std_logic; signal nx_fifo_reset : std_logic; @@ -102,13 +93,21 @@ architecture Behavioral of nx_data_receiver is -- ADC Ckl Generator signal adc_clk_skip : std_logic; - signal adc_sample_clk : std_logic; + signal adc_sampling_clk : std_logic; signal johnson_ff_0 : std_logic; signal johnson_ff_1 : std_logic; - signal adc_clk_inv : std_logic; - signal adc_clk_delay : std_logic_vector(2 downto 0); + signal johnson_counter_sync : std_logic_vector(1 downto 0); signal adc_clk_ok : std_logic; - + + signal pll_adc_sampling_clk_o : std_logic; + signal pll_adc_sampling_clk_lock : std_logic; + signal pll_adc_sampling_clk_reset : std_logic; + + -- PLL ADC Monitor + signal pll_adc_not_lock : std_logic; + signal pll_adc_not_lock_ctr : unsigned(11 downto 0); + signal pll_adc_not_lock_ctr_clear : std_logic; + -- ADC RESET signal adc_clk_ok_last : std_logic; signal adc_reset_s : std_logic; @@ -140,7 +139,6 @@ architecture Behavioral of nx_data_receiver is signal parity_error_counter : unsigned(11 downto 0); signal parity_error_ctr_inc : std_logic; - signal reg_nx_frame_synced_t : std_logic; signal reg_nx_frame_synced : std_logic; ----------------------------------------------------------------------------- @@ -176,7 +174,17 @@ architecture Behavioral of nx_data_receiver is signal nx_timestamp_o : std_logic_vector(31 downto 0); signal adc_data_o : std_logic_vector(11 downto 0); signal new_data_o : std_logic; - + + -- Check Nxyter Data Clock via Johnson Counter + signal nx_data_clock_test_0 : std_logic; + signal nx_data_clock_test_1 : std_logic; + signal nx_data_clock : std_logic; + signal nx_data_clock_state : std_logic_vector(3 downto 0); + signal nx_data_clock_ok : std_logic; + + signal pll_adc_sample_clk_dphase : std_logic_vector(3 downto 0); + signal pll_adc_sample_clk_finedelb : std_logic_vector(3 downto 0); + -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; @@ -187,7 +195,7 @@ architecture Behavioral of nx_data_receiver is signal reset_parity_error_ctr : std_logic; signal fifo_reset_r : std_logic; signal debug_adc : std_logic_vector(1 downto 0); - + signal pll_adc_sampling_clk_reset_r :std_logic; begin PROC_DEBUG_MULT: process(debug_adc, @@ -227,7 +235,9 @@ begin DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN; DEBUG_OUT(2) <= TRIGGER_IN; DEBUG_OUT(3) <= adc_data_valid; - DEBUG_OUT(15 downto 4) <= test_adc_data; + DEBUG_OUT(7 downto 4) <= (others => '0'); + DEBUG_OUT(15 downto 8) <= counter_nx_diff; + --DEBUG_OUT(15 downto 4) <= test_adc_data; when "11" => DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN; @@ -241,10 +251,10 @@ begin DEBUG_OUT(8) <= adc_reset_s; DEBUG_OUT(9) <= adc_reset; DEBUG_OUT(10) <= nx_new_frame; - DEBUG_OUT(11) <= nx_data_clock; - DEBUG_OUT(12) <= nx_data_clock_last; - DEBUG_OUT(13) <= nx_data_clock_nok; - DEBUG_OUT(14) <= nx_data_clock_invalid; + DEBUG_OUT(11) <= nx_data_clock_ok; + DEBUG_OUT(12) <= '0'; --adc_sampling_clk; + DEBUG_OUT(13) <= pll_adc_sampling_clk_lock; + DEBUG_OUT(14) <= pll_adc_sampling_clk_o; DEBUG_OUT(15) <= '0'; --DEBUG_OUT(15 downto 11) <= adc_reset_ctr(4 downto 0) ; @@ -274,48 +284,86 @@ begin end process PROC_DEBUG_MULT; ----------------------------------------------------------------------------- - -- NX_MAIN_CLK Domain + -- Check NX Data Clk ----------------------------------------------------------------------------- - PROC_CHECK_NX_DATA_CLOCK: process(NX_MAIN_CLK_IN) + PROC_COUNTER_NX_CLOCK: process(NX_TIMESTAMP_CLK_IN) begin - if (rising_edge(NX_MAIN_CLK_IN)) then + if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then if( RESET_IN = '1' ) then - nx_data_clock_t <= '0'; - nx_data_clock <= '0'; - nx_data_clock_last <= '0'; - nx_data_clock_nok <= '0'; + counter_nx_domain <= (others => '0'); else - if (nx_data_clock /= nx_data_clock_last) then - nx_data_clock_nok <= '0'; - else - nx_data_clock_nok <= '1'; - end if; + counter_nx_domain <= counter_nx_domain + 1; + end if; + end if; + end process PROC_COUNTER_NX_CLOCK; - nx_data_clock_t <= NX_TIMESTAMP_CLK_IN; - nx_data_clock <= nx_data_clock_t; - nx_data_clock_last <= nx_data_clock; + PROC_COUNTER_NX_REF_CLOCK: process(NX_DATA_CLK_TEST_IN) + begin + if (rising_edge(NX_DATA_CLK_TEST_IN) ) then + if( RESET_IN = '1' ) then + counter_nx_ref_domain <= (others => '0'); + else + counter_nx_ref_domain <= counter_nx_ref_domain + 1; end if; end if; - end process PROC_CHECK_NX_DATA_CLOCK; + end process PROC_COUNTER_NX_REF_CLOCK; + + counter_nx_diff <= counter_nx_ref_domain - counter_nx_domain; + + ----------------------------------------------------------------------------- + -- ADC CLK DOMAIN + ----------------------------------------------------------------------------- + + pll_adc_sampling_clk_2: pll_adc_sampling_clk + port map ( + CLK => adc_sampling_clk, + + RESET => pll_adc_sampling_clk_reset, + FINEDELB0 => pll_adc_sample_clk_finedelb(0), + FINEDELB1 => pll_adc_sample_clk_finedelb(1), + FINEDELB2 => pll_adc_sample_clk_finedelb(2), + FINEDELB3 => pll_adc_sample_clk_finedelb(3), + DPHASE0 => pll_adc_sample_clk_dphase(0), + DPHASE1 => pll_adc_sample_clk_dphase(1), + DPHASE2 => pll_adc_sample_clk_dphase(2), + DPHASE3 => pll_adc_sample_clk_dphase(3), + CLKOP => open, + CLKOS => pll_adc_sampling_clk_o, + LOCK => pll_adc_sampling_clk_lock + ); - pulse_dtrans_1: pulse_dtrans + pulse_to_level_2: pulse_to_level generic map ( - CLK_RATIO => 3 + NUM_CYCLES => 10 ) port map ( - CLK_A_IN => NX_MAIN_CLK_IN, - RESET_A_IN => RESET_IN, - PULSE_A_IN => nx_data_clock_nok, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => nx_data_clock_invalid + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + PULSE_IN => pll_adc_sampling_clk_reset_r, + LEVEL_OUT => pll_adc_sampling_clk_reset ); + pulse_async_trans_1: pulse_async_trans + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + PULSE_A_IN => not pll_adc_sampling_clk_lock, + PULSE_OUT => pll_adc_not_lock + ); + + PROC_PLL_LOCK_COUNTER: process(CLK_IN) + begin + if (rising_edge(CLK_IN) ) then + if( RESET_IN = '1' or pll_adc_not_lock_ctr_clear = '1') then + pll_adc_not_lock_ctr <= (others => '0'); + else + if (pll_adc_not_lock = '1') then + pll_adc_not_lock_ctr <= pll_adc_not_lock_ctr + 1; + end if; + end if; + end if; + end process PROC_PLL_LOCK_COUNTER; - ----------------------------------------------------------------------------- - -- ADC CLK DOMAIN - ----------------------------------------------------------------------------- - adc_ad9222_1: entity work.adc_ad9222 generic map ( CHANNELS => 4, @@ -324,28 +372,28 @@ begin ) port map ( CLK => CLK_IN, - CLK_ADCREF => adc_sample_clk, + CLK_ADCREF => pll_adc_sampling_clk_o, CLK_ADCDAT => ADC_CLK_DAT_IN, RESTART_IN => adc_reset, ADCCLK_OUT => ADC_SAMPLE_CLK_OUT, - + ADC_DATA(0) => ADC_NX_IN(0), ADC_DATA(1) => ADC_B_IN(0), ADC_DATA(2) => ADC_A_IN(0), ADC_DATA(3) => ADC_D_IN(0), - + ADC_DATA(4) => ADC_NX_IN(1), ADC_DATA(5) => ADC_A_IN(1), ADC_DATA(6) => ADC_B_IN(1), ADC_DATA(7) => ADC_D_IN(1), - + ADC_DCO => ADC_DCLK_IN, ADC_FCO => ADC_FCLK_IN, - + DATA_OUT(11 downto 0) => adc_data, DATA_OUT(23 downto 12) => test_adc_data, DATA_OUT(95 downto 24) => open, - + FCO_OUT => open, DATA_VALID_OUT(0) => adc_data_valid, DATA_VALID_OUT(1) => open, @@ -353,7 +401,7 @@ begin ); adc_reset <= adc_reset_s or adc_reset_l or RESET_IN; - + pulse_to_level_1: pulse_to_level generic map ( NUM_CYCLES => 7 @@ -369,9 +417,9 @@ begin -- NX_TIMESTAMP_CLK_IN Domain ----------------------------------------------------------------------------- - nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); + nx_timestamp_ff <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); - -- Transfer 8 to 32Bit + -- Merge TS Data 8bit to 32Bit Timestamp Frame PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then @@ -383,16 +431,16 @@ begin nx_new_frame <= '0'; case frame_byte_pos is - when "11" => nx_frame_word(31 downto 24) <= nx_timestamp_reg; + when "11" => nx_frame_word(31 downto 24) <= nx_timestamp_ff; frame_byte_ctr <= frame_byte_ctr + 1; - when "10" => nx_frame_word(23 downto 16) <= nx_timestamp_reg; + when "10" => nx_frame_word(23 downto 16) <= nx_timestamp_ff; frame_byte_ctr <= frame_byte_ctr + 1; - when "01" => nx_frame_word(15 downto 8) <= nx_timestamp_reg; + when "01" => nx_frame_word(15 downto 8) <= nx_timestamp_ff; frame_byte_ctr <= frame_byte_ctr + 1; - when "00" => nx_frame_word( 7 downto 0) <= nx_timestamp_reg; + when "00" => nx_frame_word( 7 downto 0) <= nx_timestamp_ff; if (frame_byte_ctr = "11") then nx_new_frame <= '1'; end if; @@ -531,36 +579,25 @@ begin end if; end process PROC_NX_CLK_ACT; - -- Johnson Counter - PROC_ADC_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) + -- ADC Sampling Clock Generator using a Johnson Counter + PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN)) then if (RESET_IN = '1') then - johnson_ff_0 <= '0'; - johnson_ff_1 <= '0'; + johnson_ff_0 <= '0'; + johnson_ff_1 <= '0'; else if (adc_clk_skip = '0') then - johnson_ff_0 <= not johnson_ff_1; - johnson_ff_1 <= johnson_ff_0; + johnson_ff_0 <= not johnson_ff_1; + johnson_ff_1 <= johnson_ff_0; + adc_sampling_clk <= not johnson_ff_1; end if; end if; end if; - end process PROC_ADC_CLK_GENERATOR; + adc_sampling_clk <= johnson_ff_0; + end process PROC_ADC_SAMPLING_CLK_GENERATOR; - PROC_ADC_CLK_DELAY_4NS: process(NX_TIMESTAMP_CLK_IN) - begin - if (falling_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_IN = '1') then - adc_clk_inv <= '0'; - else - adc_clk_inv <= johnson_ff_0; - end if; - end if; - end process PROC_ADC_CLK_DELAY_4NS; - - adc_sample_clk <= adc_clk_inv when adc_clk_delay(0) = '1' else johnson_ff_0; - - PROC_ADC_CLK_DELAY: process(NX_TIMESTAMP_CLK_IN) + PROC_ADC_SAMPLING_CLK_SYNC: process(NX_TIMESTAMP_CLK_IN) variable adc_clk_state : std_logic_vector(1 downto 0); begin if (rising_edge(NX_TIMESTAMP_CLK_IN)) then @@ -571,7 +608,7 @@ begin adc_clk_state := johnson_ff_1 & johnson_ff_0; adc_clk_skip <= '0'; if (nx_new_frame = '1') then - if (adc_clk_state /= adc_clk_delay(2 downto 1)) then + if (adc_clk_state /= johnson_counter_sync) then adc_clk_skip <= '1'; adc_clk_ok <= '0'; else @@ -580,7 +617,7 @@ begin end if; end if; end if; - end process PROC_ADC_CLK_DELAY; + end process PROC_ADC_SAMPLING_CLK_SYNC; PROC_ADC_RESET: process(NX_TIMESTAMP_CLK_IN) begin @@ -611,18 +648,6 @@ begin end if; end process PROC_RESET_CTR; - -- PROC_CAL_RATES: process (CLK_IN) - -- begin - -- if( rising_edge(CLK_IN) ) then - -- if (RESET_IN = '1') then - -- nx_trigger_ctr_t <= (others => '0'); - -- nx_hit_rate <= (others => '0'); - -- nx_frame_rate <= (others => '0'); - -- else - -- end if; - -- end if; - -- end process PROC_CAL_RATES; - ----------------------------------------------------------------------------- -- NX CLK_IN Domain ----------------------------------------------------------------------------- @@ -694,20 +719,16 @@ begin RESET_B_IN => RESET_IN, PULSE_B_OUT => parity_error_ctr_inc ); - - PROC_SYNC_FRAME_SYNC: process(CLK_IN) - begin - if (rising_edge(CLK_IN) ) then - if(RESET_IN = '1' ) then - reg_nx_frame_synced_t <= '0'; - reg_nx_frame_synced <= '0'; - else - reg_nx_frame_synced_t <= nx_frame_synced; - reg_nx_frame_synced <= reg_nx_frame_synced_t; - end if; - end if; - end process PROC_SYNC_FRAME_SYNC; + -- nx_frame_synced --> CLK_IN Domain + signal_async_trans_1: signal_async_trans + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SIGNAL_A_IN => nx_frame_synced, + SIGNAL_OUT => reg_nx_frame_synced + ); + -- Counters PROC_RESYNC_COUNTER: process(CLK_IN) begin @@ -843,6 +864,69 @@ begin end if; end process PROC_OUTPUT_HANDLER; + + ----------------------------------------------------------------------------- + -- Reset Handler CLK_IN Domain + ----------------------------------------------------------------------------- + + -- Check NX Data Clock + -- Johnson Counter 2 + --PROC_NX_DATA_CLOCK_TEST: process(NX_TIMESTAMP_CLK_IN) + --begin + -- if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + -- if (RESET_IN = '1') then + -- nx_data_clock_test_0 <= '0'; + -- nx_data_clock_test_1 <= '0'; + -- else + -- nx_data_clock_test_0 <= not nx_data_clock_test_1; + -- nx_data_clock_test_1 <= nx_data_clock_test_0; + -- end if; + -- end if; + --end process PROC_NX_DATA_CLOCK_TEST; + -- + --signal_async_trans_2: signal_async_trans + -- generic map ( + -- NUM_FF => 2 + -- ) + -- port map ( + -- CLK_IN => CLK_IN, + -- RESET_IN => RESET_IN, + -- SIGNAL_A_IN => nx_data_clock_test_0, + -- SIGNAL_OUT => nx_data_clock + -- ); + -- + --PROC_CHECK_NX_DATA_CLOCK: process(CLK_IN) + --begin + -- if (rising_edge(CLK_IN)) then + -- if( RESET_IN = '1' ) then + -- nx_data_clock_state <= (others => '0'); + -- nx_data_clock_ok <= '0'; + -- else + -- if (nx_data_clock_state = "1111" or + -- nx_data_clock_state = "0000" or + -- + -- nx_data_clock_state = "1110" or + -- nx_data_clock_state = "0111" or + -- + -- nx_data_clock_state = "1100" or + -- nx_data_clock_state = "0011" or + -- + -- nx_data_clock_state = "1000" or + -- nx_data_clock_state = "0001" + -- ) then + -- nx_data_clock_ok <= '0'; + -- else + -- nx_data_clock_ok <= '1'; + -- end if; + -- + -- nx_data_clock_state(0) <= nx_data_clock; + -- nx_data_clock_state(1) <= nx_data_clock_state(0); + -- nx_data_clock_state(2) <= nx_data_clock_state(1); + -- nx_data_clock_state(3) <= nx_data_clock_state(2); + -- end if; + -- end if; + --end process PROC_CHECK_NX_DATA_CLOCK; + ----------------------------------------------------------------------------- -- TRBNet Slave Bus ----------------------------------------------------------------------------- @@ -859,13 +943,14 @@ begin reset_resync_ctr <= '0'; reset_parity_error_ctr <= '0'; fifo_reset_r <= '0'; - adc_clk_delay <= "111"; adc_reset_r <= '0'; debug_adc <= (others => '0'); adc_input_error_enable <= '0'; - -- pll_adc_sample_clk_reset <= '1'; - -- pll_adc_sample_clk_dphase <= (others => '0'); - -- pll_adc_sample_clk_finedelb <= (others => '0'); + johnson_counter_sync <= "00"; + pll_adc_sample_clk_dphase <= (others => '0'); + pll_adc_sample_clk_finedelb <= (others => '0'); + pll_adc_sampling_clk_reset_r <= '0'; + pll_adc_not_lock_ctr_clear <= '0'; else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -875,9 +960,8 @@ begin reset_parity_error_ctr <= '0'; fifo_reset_r <= '0'; adc_reset_r <= '0'; - -- pll_adc_sample_clk_reset <= '0'; - -- pll_adc_sample_clk_dphase <= (others => '0'); - -- pll_adc_sample_clk_finedelb <= (others => '0'); + pll_adc_sampling_clk_reset_r <= '0'; + pll_adc_not_lock_ctr_clear <= '0'; if (SLV_READ_IN = '1') then case SLV_ADDR_IN is @@ -898,7 +982,8 @@ begin slv_ack_o <= '1'; when x"0002" => - slv_data_out_o(11 downto 0) <= std_logic_vector(resync_counter); + slv_data_out_o(11 downto 0) <= + std_logic_vector(resync_counter); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; @@ -908,61 +993,52 @@ begin slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; + when x"0004" => + slv_data_out_o(11 downto 0) <= + std_logic_vector(pll_adc_not_lock_ctr); + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + when x"0005" => - case adc_clk_delay is - when "010" => slv_data_out_o(2 downto 0) <= "000"; - when "011" => slv_data_out_o(2 downto 0) <= "001"; - when "000" => slv_data_out_o(2 downto 0) <= "010"; - when "001" => slv_data_out_o(2 downto 0) <= "011"; - when "100" => slv_data_out_o(2 downto 0) <= "100"; - when "101" => slv_data_out_o(2 downto 0) <= "101"; - when "110" => slv_data_out_o(2 downto 0) <= "110"; - when "111" => slv_data_out_o(2 downto 0) <= "111"; - end case; - - slv_data_out_o(31 downto 3) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(1 downto 0) <= johnson_counter_sync; + slv_data_out_o(31 downto 2) <= (others => '0'); + slv_ack_o <= '1'; when x"0006" => - slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr); - slv_data_out_o(31 downto 12) <= (others => '0'); + slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_dphase; + slv_data_out_o(31 downto 4) <= (others => '0'); slv_ack_o <= '1'; when x"0007" => - slv_data_out_o(1 downto 0) <= debug_adc; - slv_data_out_o(31 downto 2) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb; + slv_data_out_o(31 downto 4) <= (others => '0'); + slv_ack_o <= '1'; when x"0008" => slv_data_out_o(11 downto 0) <= adc_data_t; slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - when x"0009" => + when x"000a" => slv_data_out_o(0) <= adc_input_error_enable; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; - when x"000a" => + when x"000b" => slv_data_out_o(15 downto 0) <= adc_input_error_ctr; slv_data_out_o(31 downto 16) <= (others => '0'); slv_ack_o <= '1'; - -- when x"000b" => - -- slv_data_out_o(0) <= pll_adc_sample_clk_lock; - -- slv_data_out_o(31 downto 1) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"000c" => - -- slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_dphase; - -- slv_data_out_o(31 downto 4) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"000d" => - -- slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb; - -- slv_data_out_o(31 downto 4) <= (others => '0'); - -- slv_ack_o <= '1'; - + when x"000c" => + slv_data_out_o(0) <= nx_data_clock_ok; + slv_data_out_o(31 downto 1) <= (others => '0'); + slv_ack_o <= '1'; + + when x"000f" => + slv_data_out_o(1 downto 0) <= debug_adc; + slv_data_out_o(31 downto 2) <= (others => '0'); + slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; end case; @@ -980,42 +1056,35 @@ begin when x"0003" => reset_parity_error_ctr <= '1'; slv_ack_o <= '1'; - - when x"0005" => - if (SLV_DATA_IN < x"0000_0008") then - case SLV_DATA_IN(2 downto 0) is - when "000" => adc_clk_delay <= "010"; - when "001" => adc_clk_delay <= "011"; - when "010" => adc_clk_delay <= "000"; - when "011" => adc_clk_delay <= "001"; - when "100" => adc_clk_delay <= "100"; - when "101" => adc_clk_delay <= "101"; - when "110" => adc_clk_delay <= "110"; - when "111" => adc_clk_delay <= "111"; - end case; - end if; + + when x"0004" => + pll_adc_not_lock_ctr_clear <= '1'; slv_ack_o <= '1'; + + when x"0005" => + johnson_counter_sync <= SLV_DATA_IN(1 downto 0); + slv_ack_o <= '1'; - when x"0007" => - debug_adc <= SLV_DATA_IN(1 downto 0); - slv_ack_o <= '1'; + when x"0006" => + pll_adc_sample_clk_dphase <= SLV_DATA_IN(3 downto 0); + slv_ack_o <= '1'; + when x"0007" => + pll_adc_sample_clk_finedelb <= SLV_DATA_IN(3 downto 0); + slv_ack_o <= '1'; + when x"0009" => + pll_adc_sampling_clk_reset_r <= '1'; + slv_ack_o <= '1'; + + when x"000a" => adc_input_error_enable <= SLV_DATA_IN(0); slv_ack_o <= '1'; - -- when x"000b" => - -- pll_adc_sample_clk_reset <= '1'; - -- slv_ack_o <= '1'; - -- - -- when x"000c" => - -- pll_adc_sample_clk_dphase <= SLV_DATA_IN(3 downto 0); - -- slv_ack_o <= '1'; - -- - -- when x"000d" => - -- pll_adc_sample_clk_finedelb <= SLV_DATA_IN(3 downto 0); - -- slv_ack_o <= '1'; - + when x"000f" => + debug_adc <= SLV_DATA_IN(1 downto 0); + slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; diff --git a/nxyter/source/nx_fpga_timestamp.vhd b/nxyter/source/nx_fpga_timestamp.vhd index 192a053..6ce9327 100644 --- a/nxyter/source/nx_fpga_timestamp.vhd +++ b/nxyter/source/nx_fpga_timestamp.vhd @@ -7,7 +7,7 @@ use work.nxyter_components.all; entity nx_fpga_timestamp is port ( - CLK_IN : in std_logic; + CLK_IN : in std_logic; RESET_IN : in std_logic; NX_MAIN_CLK_IN : in std_logic; @@ -35,77 +35,54 @@ end entity; architecture Behavioral of nx_fpga_timestamp is signal timestamp_ctr : unsigned(11 downto 0); signal timestamp_current_o : unsigned(11 downto 0); - signal timestamp_hold : std_logic_vector(11 downto 0); - signal trigger_x : std_logic; - signal trigger_l : std_logic; + signal timestamp_hold_o : std_logic_vector(11 downto 0); signal trigger : std_logic; - signal timestamp_sync_x : std_logic; - signal timestamp_sync_l : std_logic; signal timestamp_sync : std_logic; signal nx_timestamp_sync_o : std_logic; - signal fifo_full : std_logic; - signal fifo_write_enable : std_logic; + signal fifo_full : std_logic; + signal fifo_write_enable : std_logic; - -- Main Clock Domain - signal fifo_empty : std_logic; - signal fifo_read_enable : std_logic; - signal fifo_data_valid_t : std_logic; - signal fifo_data_valid : std_logic; - signal fifo_data_out : std_logic_vector(11 downto 0); - signal timestamp_hold_o : unsigned(11 downto 0); - begin DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= TIMESTAMP_SYNC_IN; DEBUG_OUT(2) <= nx_timestamp_sync_o; DEBUG_OUT(3) <= TRIGGER_IN; - DEBUG_OUT(4) <= fifo_full; - DEBUG_OUT(5) <= fifo_write_enable; - DEBUG_OUT(6) <= fifo_empty; - DEBUG_OUT(7) <= fifo_read_enable; - DEBUG_OUT(8) <= fifo_data_valid_t; - DEBUG_OUT(9) <= fifo_data_valid; - DEBUG_OUT(15 downto 10) <= fifo_data_out(5 downto 0); - + DEBUG_OUT(4) <= trigger; + + DEBUG_OUT(15 downto 5) <= timestamp_hold_o(10 downto 0); + + ----------------------------------------------------------------------------- -- NX Clock Domain + ----------------------------------------------------------------------------- - -- Cross Clockdomain for TRIGGER and SYNC - PROC_SYNC: process (NX_MAIN_CLK_IN) - begin - if( rising_edge(NX_MAIN_CLK_IN) ) then - if (RESET_IN = '1') then - trigger_x <= '0'; - trigger_l <= '0'; - timestamp_sync_x <= '0'; - timestamp_sync_l <= '0'; - else - trigger_x <= TRIGGER_IN; - trigger_l <= trigger_x; - timestamp_sync_x <= TIMESTAMP_SYNC_IN; - timestamp_sync_l <= timestamp_sync_x; - end if; - end if; - end process PROC_SYNC; - - -- Convert TRIGGER_IN to Pulse - level_to_pulse_1: level_to_pulse + -- Sync in TRIGGER and Timestamp Sync + pulse_dtrans_1: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) port map ( - CLK_IN => NX_MAIN_CLK_IN, - RESET_IN => RESET_IN, - LEVEL_IN => trigger_l, - PULSE_OUT => trigger + CLK_A_IN => CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => TRIGGER_IN, + CLK_B_IN => NX_MAIN_CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => trigger ); - -- Convert TIMESTAMP_SYNC_IN to Pulse - level_to_pulse_2: level_to_pulse + pulse_dtrans_2: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) port map ( - CLK_IN => NX_MAIN_CLK_IN, - RESET_IN => RESET_IN, - LEVEL_IN => timestamp_sync_l, - PULSE_OUT => timestamp_sync + CLK_A_IN => CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => TIMESTAMP_SYNC_IN, + CLK_B_IN => NX_MAIN_CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => timestamp_sync ); -- Timestamp Process + Trigger @@ -114,24 +91,19 @@ begin begin if( rising_edge(NX_MAIN_CLK_IN) ) then if( RESET_IN = '1' ) then - timestamp_ctr <= (others => '0'); - timestamp_hold <= (others => '0'); - nx_timestamp_sync_o <= '0'; - fifo_write_enable <= '0'; + timestamp_ctr <= (others => '0'); + timestamp_hold_o <= (others => '0'); + nx_timestamp_sync_o <= '0'; else - nx_timestamp_sync_o <= '0'; - fifo_write_enable <= '0'; - + nx_timestamp_sync_o <= '0'; if (timestamp_sync = '1') then - timestamp_ctr <= (others => '0'); - timestamp_hold <= (others => '0'); - nx_timestamp_sync_o <= '1'; + timestamp_ctr <= (others => '0'); + nx_timestamp_sync_o <= '1'; else - if (trigger = '1' and fifo_full = '0') then - timestamp_hold <= std_logic_vector(timestamp_ctr - 3); - fifo_write_enable <= '1'; + if (trigger = '1') then + timestamp_hold_o <= std_logic_vector(timestamp_ctr - 3); end if; - timestamp_ctr <= timestamp_ctr + 1; + timestamp_ctr <= timestamp_ctr + 1; end if; end if; end if; @@ -139,44 +111,6 @@ begin timestamp_current_o <= timestamp_ctr; - ----------------------------------------------------------------------------- - -- Main Clock Domain -> Tranfer TimeStamp - ----------------------------------------------------------------------------- - - fifo_ts_12to12_dc_1: fifo_ts_12to12_dc - port map ( - Data => timestamp_hold, - WrClock => NX_MAIN_CLK_IN, - RdClock => CLK_IN, - WrEn => fifo_write_enable, - RdEn => fifo_read_enable, - Reset => RESET_IN, - RPReset => RESET_IN, - Q => fifo_data_out, - Empty => fifo_empty, - Full => fifo_full - ); - - fifo_read_enable <= not fifo_empty; - - PROC_RECEIVE_TS: process (CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - fifo_data_valid_t <= '0'; - fifo_data_valid <= '0'; - timestamp_hold_o <= (others => '0'); - else - if (fifo_data_valid = '1') then - timestamp_hold_o <= unsigned(fifo_data_out); - end if; - - fifo_data_valid_t <= fifo_read_enable; - fifo_data_valid <= fifo_data_valid_t; - end if; - end if; - end process PROC_RECEIVE_TS; - ----------------------------------------------------------------------------- -- Output Signals ----------------------------------------------------------------------------- diff --git a/nxyter/source/nx_timer.vhd b/nxyter/source/nx_timer.vhd index 3417a17..389525c 100644 --- a/nxyter/source/nx_timer.vhd +++ b/nxyter/source/nx_timer.vhd @@ -4,7 +4,8 @@ use ieee.numeric_std.all; entity nx_timer is generic ( - CTR_WIDTH : integer range 2 to 32 := 12 + CTR_WIDTH : integer range 2 to 32 := 12; + STEP_SIZE : integer range 1 to 100 := 1 ); port( CLK_IN : in std_logic; @@ -61,8 +62,8 @@ begin end if; when S_COUNT => - if (timer_ctr > 0) then - timer_ctr_x <= timer_ctr - 1; + if (timer_ctr > to_unsigned(STEP_SIZE - 1, CTR_WIDTH)) then + timer_ctr_x <= timer_ctr - to_unsigned(STEP_SIZE, CTR_WIDTH); timer_done_o <= '0'; NEXT_STATE <= S_COUNT; else diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index d23c3bb..8d8de50 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -7,24 +7,24 @@ use work.nxyter_components.all; entity nx_trigger_generator is port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + TRIGGER_IN : in std_logic; + TRIGGER_OUT : out std_logic; + TS_RESET_OUT : out std_logic; + TESTPULSE_OUT : out std_logic; + TEST_IN : in std_logic_vector(31 downto 0); - TRIGGER_IN : in std_logic; - - TRIGGER_OUT : out std_logic; - TS_RESET_OUT : out std_logic; - TESTPULSE_OUT : out std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; -- Debug Line DEBUG_OUT : out std_logic_vector(15 downto 0) @@ -65,20 +65,36 @@ architecture Behavioral of nx_trigger_generator is signal reg_trigger_num_cycles : unsigned(7 downto 0); signal reg_ts_reset_on : std_logic; signal testpulse_rate : unsigned(27 downto 0); + + signal test_debug : std_logic; begin -- Debug Line DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= trigger_o; + DEBUG_OUT(1) <= TRIGGER_IN; DEBUG_OUT(2) <= start_cycle; DEBUG_OUT(3) <= wait_timer_done; DEBUG_OUT(4) <= ts_reset_o; DEBUG_OUT(5) <= testpulse_o; - DEBUG_OUT(6) <= TRIGGER_IN; - DEBUG_OUT(7) <= extern_trigger; - DEBUG_OUT(15 downto 8) <= trigger_cycle_ctr; - + DEBUG_OUT(6) <= extern_trigger; + DEBUG_OUT(7) <= test_debug; + DEBUG_OUT(15 downto 8) <= (others => '0'); + + PROC_TEST_DEBUG: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + test_debug <= '0'; + else + if (TEST_IN = x"7f7f7f06" or TEST_IN = x"0000_0000") then + test_debug <= '0'; + else + test_debug <= '1'; + end if; + end if; + end if; + end process PROC_TEST_DEBUG; -- Timer nx_timer_1: nx_timer generic map ( @@ -138,89 +154,6 @@ begin end if; end process PROC_TRIGGER_OUT; - -- PROC_TRIGGER_OUT: process(CLK_IN) - -- begin - -- if( rising_edge(CLK_IN) ) then - -- if (RESET_IN = '1') then - -- trigger_o <= '0'; - -- testpulse_o <= '0'; - -- ts_reset_o <= '0'; - -- wait_timer_init <= (others => '0'); - -- trigger_cycle_ctr <= (others => '0'); - -- extern_trigger <= '0'; - -- STATE <= S_IDLE; - -- else - -- trigger_o <= '0'; - -- testpulse_o <= '0'; - -- ts_reset_o <= '0'; - -- wait_timer_init <= (others => '0'); - -- - -- case STATE is - -- when S_IDLE => - -- if (start_cycle = '1') then - -- trigger_cycle_ctr <= reg_trigger_num_cycles; - -- if (reg_ts_reset_on = '1') then - -- ts_reset_o <= '1'; - -- wait_timer_init <= reg_trigger_period; - -- STATE <= S_WAIT_TRIGGER_END; - -- else - -- STATE <= S_NEXT_CYCLE; - -- end if; - -- extern_trigger <= '0'; - -- elsif (TRIGGER_IN = '1') then - -- trigger_cycle_ctr <= (others => '0'); - -- extern_trigger <= '1'; - -- if (reg_testpulse_length > 0) then - -- wait_timer_init <= reg_testpulse_length; - -- STATE <= S_SET_TESTPULSE; - -- end if; - -- STATE <= S_NEXT_CYCLE ; - -- - -- else - -- extern_trigger <= '0'; - -- STATE <= S_IDLE; - -- end if; - -- - -- when S_NEXT_CYCLE => - -- if (trigger_cycle_ctr > 0) then - -- trigger_o <= '1'; - -- trigger_cycle_ctr <= trigger_cycle_ctr - 1; - -- if (reg_testpulse_length > 0) then - -- wait_timer_init <= reg_testpulse_length; - -- STATE <= S_SET_TESTPULSE; - -- else - -- wait_timer_init <= reg_trigger_period; - -- STATE <= S_WAIT_TRIGGER_END; - -- end if; - -- else - -- STATE <= S_IDLE; - -- end if; - -- - -- when S_SET_TESTPULSE => - -- testpulse_o <= '1'; - -- if (wait_timer_done = '0') then - -- STATE <= S_SET_TESTPULSE; - -- else - -- if (extern_trigger = '0') then - -- wait_timer_init <= reg_trigger_period - reg_testpulse_length; - -- else - -- wait_timer_init <= x"0001"; - -- end if; - -- STATE <= S_WAIT_TRIGGER_END; - -- end if; - -- - -- when S_WAIT_TRIGGER_END => - -- if (wait_timer_done = '0') then - -- STATE <= S_WAIT_TRIGGER_END; - -- else - -- STATE <= S_NEXT_CYCLE; - -- end if; - -- - -- end case; - -- end if; - -- end if; - -- end process PROC_TRIGGER_OUT; - -- Convert TRIGGER_IN to Pulse level_to_pulse_1: level_to_pulse port map ( @@ -262,8 +195,7 @@ begin if( RESET_IN = '1' ) then reg_trigger_period <= x"00ff"; reg_trigger_num_cycles <= x"01"; - --reg_testpulse_length <= (others => '0'); - reg_testpulse_length <= x"0005"; + reg_testpulse_length <= x"0001"; reg_ts_reset_on <= '0'; slv_data_out_o <= (others => '0'); slv_no_more_data_o <= '0'; @@ -280,65 +212,40 @@ begin if (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is when x"0000" => - start_cycle <= '1'; - slv_ack_o <= '1'; + start_cycle <= '1'; + slv_ack_o <= '1'; when x"0001" => - reg_trigger_period <= unsigned(SLV_DATA_IN(15 downto 0)); - slv_ack_o <= '1'; - - when x"0002" => - reg_trigger_num_cycles <= unsigned(SLV_DATA_IN(7 downto 0)); - slv_ack_o <= '1'; - - when x"0003" => if (reg_testpulse_length > 0) then - reg_testpulse_length <= unsigned(SLV_DATA_IN(15 downto 0)); + reg_testpulse_length <= + unsigned(SLV_DATA_IN(15 downto 0)); end if; - slv_ack_o <= '1'; - - when x"0004" => - reg_ts_reset_on <= SLV_DATA_IN(0); - slv_ack_o <= '1'; + slv_ack_o <= '1'; when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; end case; elsif (SLV_READ_IN = '1') then case SLV_ADDR_IN is when x"0001" => - slv_data_out_o(15 downto 0) <= - std_logic_vector(reg_trigger_period); - slv_ack_o <= '1'; - - when x"0002" => - slv_data_out_o(7 downto 0) <= - std_logic_vector(reg_trigger_num_cycles); - slv_ack_o <= '1'; - - when x"0003" => - slv_data_out_o(15 downto 0) <= + slv_data_out_o(15 downto 0) <= std_logic_vector(reg_testpulse_length); - slv_ack_o <= '1'; - - when x"0004" => - slv_data_out_o(0) <= reg_ts_reset_on; - slv_ack_o <= '1'; + slv_ack_o <= '1'; when x"0005" => - slv_data_out_o(27 downto 0) <= std_logic_vector(testpulse_rate); + slv_data_out_o(27 downto 0) <= std_logic_vector(testpulse_rate); slv_data_out_o(31 downto 28) <= (others => '0'); - slv_ack_o <= '1'; + slv_ack_o <= '1'; when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; end case; else - slv_ack_o <= '0'; + slv_ack_o <= '0'; end if; end if; end if; diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index a8d2b62..de15756 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -25,8 +25,8 @@ entity nx_trigger_validate is TRIGGER_IN : in std_logic; FAST_CLEAR_IN : in std_logic; TRIGGER_BUSY_OUT : out std_logic; - TIMESTAMP_REF_IN : in unsigned(11 downto 0); - DATA_FIFO_DELAY_OUT : out std_logic_vector(6 downto 0); + TIMESTAMP_FPGA_IN : in unsigned(11 downto 0); + DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0); -- Outputs DATA_OUT : out std_logic_vector(31 downto 0); @@ -69,12 +69,16 @@ architecture Behavioral of nx_trigger_validate is CS_NONE ); signal channel_status_cmd : CS_CMDS; + + -- Process Calculate Trigger Window + signal ts_window_lower_thr : unsigned(11 downto 0); -- Process Timestamp signal data_o : std_logic_vector(31 downto 0); signal data_clk_o : std_logic; signal out_of_window_l : std_logic; signal out_of_window_h : std_logic; + signal out_of_window_error : std_logic; signal ch_status_cmd_pr : CS_CMDS; -- Process Trigger Handler @@ -82,6 +86,7 @@ architecture Behavioral of nx_trigger_validate is signal trigger_busy_o : std_logic; signal nomore_data_o : std_logic; signal wait_timer_init : unsigned(11 downto 0); + signal wait_timer_init_ns : unsigned(19 downto 0); signal token_return_ctr : std_logic; signal ch_status_cmd_tr : CS_CMDS; @@ -96,42 +101,49 @@ architecture Behavioral of nx_trigger_validate is ); signal STATE : STATES; - signal t_data_o : std_logic_vector(31 downto 0); - signal t_data_clk_o : std_logic; - signal busy_time_ctr : unsigned(11 downto 0); - signal busy_time_min_done : std_logic; - signal wait_timer_reset : std_logic; - signal event_counter : unsigned(9 downto 0); - - signal readout_mode : std_logic_vector(2 downto 0); - signal timestamp_ref : unsigned(11 downto 0); + signal t_data_o : std_logic_vector(31 downto 0); + signal t_data_clk_o : std_logic; + signal busy_time_ctr : unsigned(11 downto 0); + signal busy_time_min_done : std_logic; + signal wait_timer_reset : std_logic; + signal min_val_time_expired : std_logic; + signal event_counter : unsigned(9 downto 0); - -- Timer - signal timer_reset : std_logic; - signal wait_timer_done : std_logic; - - -- Histogram - signal histogram_fill_o : std_logic; - signal histogram_bin_o : std_logic_vector(6 downto 0); - signal histogram_adc_o : std_logic_vector(11 downto 0); - - -- Data FIFO Delay - signal data_fifo_delay_o : std_logic_vector(6 downto 0); - - -- Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - signal readout_mode_r : std_logic_vector(2 downto 0); - signal trigger_window_begin : unsigned(11 downto 0); - signal trigger_window_end : unsigned(11 downto 0); - signal cts_trigger_delay : unsigned(11 downto 0); - signal readout_time_max : unsigned(11 downto 0); - signal window_lower_thr_r : std_logic_vector(11 downto 0); - signal window_upper_thr_r : std_logic_vector(11 downto 0); + signal readout_mode : std_logic_vector(2 downto 0); + signal timestamp_fpga : unsigned(11 downto 0); + signal timestamp_ref : unsigned(11 downto 0); + signal busy_time_ctr_last : unsigned(11 downto 0); + + -- Timers + signal timer_reset : std_logic; + signal wait_timer_done : std_logic; + signal wait_timer_done_ns : std_logic; + + -- Histogram + signal histogram_fill_o : std_logic; + signal histogram_bin_o : std_logic_vector(6 downto 0); + signal histogram_adc_o : std_logic_vector(11 downto 0); + + -- Data FIFO Delay + signal data_fifo_delay_o : unsigned(7 downto 0); + + -- Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal readout_mode_r : std_logic_vector(2 downto 0); + + -- Timestamp Trigger Window Settings + constant nxyter_cv_time : unsigned(11 downto 0) := x"190"; -- 400ns + signal cts_trigger_delay : unsigned(11 downto 0); + signal ts_window_offset : signed(11 downto 0); + signal ts_window_width : unsigned(9 downto 0); + signal readout_time_max : unsigned(11 downto 0); + signal fpga_timestamp_offset : unsigned(11 downto 0); + begin -- Debug Line @@ -141,14 +153,14 @@ begin DEBUG_OUT(3) <= DATA_CLK_IN; DEBUG_OUT(4) <= out_of_window_l; DEBUG_OUT(5) <= out_of_window_h; - DEBUG_OUT(6) <= NX_TOKEN_RETURN_IN; + DEBUG_OUT(6) <= out_of_window_error; --NX_TOKEN_RETURN_IN; DEBUG_OUT(7) <= NX_NOMORE_DATA_IN; DEBUG_OUT(8) <= channel_all_done; DEBUG_OUT(9) <= store_to_fifo; DEBUG_OUT(10) <= data_clk_o; DEBUG_OUT(11) <= t_data_clk_o; DEBUG_OUT(12) <= wait_timer_done; - DEBUG_OUT(13) <= timer_reset; + DEBUG_OUT(13) <= wait_timer_done_ns; DEBUG_OUT(14) <= busy_time_min_done; DEBUG_OUT(15) <= nomore_data_o; @@ -164,6 +176,18 @@ begin TIMER_DONE_OUT => wait_timer_done ); + nx_timer_2: nx_timer + generic map( + CTR_WIDTH => 20, + STEP_SIZE => 10 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => timer_reset, + TIMER_START_IN => wait_timer_init_ns, + TIMER_DONE_OUT => wait_timer_done_ns + ); + timer_reset <= RESET_IN or wait_timer_reset; ----------------------------------------------------------------------------- @@ -171,11 +195,11 @@ begin ----------------------------------------------------------------------------- PROC_FILTER_TIMESTAMPS: process (CLK_IN) - variable ts_ref : unsigned(11 downto 0); - variable window_lower_thr : unsigned(11 downto 0); - variable window_upper_thr : unsigned(11 downto 0); - variable deltaT : unsigned(11 downto 0); - variable deltaTStore : unsigned(11 downto 0); + variable ts_window_offset_unsigned : unsigned(11 downto 0); + variable window_lower_thr : unsigned(11 downto 0); + variable window_upper_thr : unsigned(11 downto 0); + variable ts_window_check_value : unsigned(11 downto 0); + variable deltaTStore : unsigned(13 downto 0); begin if( rising_edge(CLK_IN) ) then @@ -184,128 +208,165 @@ begin data_clk_o <= '0'; out_of_window_l <= '0'; out_of_window_h <= '0'; - window_lower_thr_r <= (others => '0'); - window_upper_thr_r <= (others => '0'); + out_of_window_error <= '0'; + ts_window_lower_thr <= (others => '0'); else data_o <= (others => '0'); data_clk_o <= '0'; out_of_window_l <= '0'; out_of_window_h <= '0'; + out_of_window_error <= '0'; ch_status_cmd_pr <= CS_NONE; histogram_fill_o <= '0'; histogram_bin_o <= (others => '0'); histogram_adc_o <= (others => '0'); + window_lower_thr := timestamp_fpga - cts_trigger_delay; + ----------------------------------------------------------------------- + -- Calculate Thresholds and values for FIFO Delay + ----------------------------------------------------------------------- + if (ts_window_offset(11) = '1') then + ts_window_offset_unsigned := + (unsigned(ts_window_offset) xor x"fff") + 1; + window_lower_thr := + window_lower_thr - ts_window_offset_unsigned; + + -- TS Window Lower Threshold (needed by FIFO Delay) + ts_window_lower_thr <= + cts_trigger_delay + ts_window_offset_unsigned; + + else + window_lower_thr := + window_lower_thr + unsigned(ts_window_offset); + + -- TS Window Lower Threshold (needed by FIFO Delay) + if (cts_trigger_delay > unsigned(ts_window_offset)) then + ts_window_lower_thr <= + cts_trigger_delay - unsigned(ts_window_offset); + else + ts_window_lower_thr <= (others => '0'); + end if; + end if; + + window_upper_thr := + window_lower_thr + resize(ts_window_width, 12); + ts_window_check_value := + unsigned(TIMESTAMP_IN(13 downto 2)) - window_lower_thr; + + ----------------------------------------------------------------------- + -- Validate incomming Data + ----------------------------------------------------------------------- if (DATA_CLK_IN = '1') then if (store_to_fifo = '1') then - ts_ref := timestamp_ref - cts_trigger_delay; - window_lower_thr := trigger_window_begin; - window_upper_thr := window_lower_thr + trigger_window_end; - deltaT := unsigned(TIMESTAMP_IN(13 downto 2)) - ts_ref; - deltaTStore := deltaT - window_lower_thr; - - window_lower_thr_r <= window_lower_thr; - window_upper_thr_r <= window_upper_thr; - + -- Timestamp to be stored + if (readout_mode(2) = '0') then - -- TS window filter Modes - if (deltaT < window_lower_thr) then - out_of_window_l <= '1'; - data_clk_o <= '0'; - -- IN LUT Data bit setzen. - channel_index <= CHANNEL_IN; - ch_status_cmd_pr <= CS_SET_WAIT; - elsif (deltaT > window_upper_thr) then - out_of_window_h <= '1'; - data_clk_o <= '0'; - -- In LUT Done Bit setzen - channel_index <= CHANNEL_IN; - ch_status_cmd_pr <= CS_SET_DONE; - else - -- IN LUT Data bit setzen and Take Data - channel_index <= CHANNEL_IN; - ch_status_cmd_pr <= CS_SET_WAIT; + -- Timestamp to be stored + deltaTStore(13 downto 2) := ts_window_check_value; + deltaTStore( 1 downto 0) := + "00" - unsigned(TIMESTAMP_IN(1 downto 0)); + + -- TS Window Active --> do TS check + + if (ts_window_check_value(11) = '1') then + -- TS below Window: Set WAIT Bit in LUT and discard Data + channel_index <= CHANNEL_IN; + ch_status_cmd_pr <= CS_SET_WAIT; + out_of_window_l <= '1'; + elsif (ts_window_check_value > ts_window_width) then + -- TS above Window: Set DONE Bit in LUT and discard Data + channel_index <= CHANNEL_IN; + ch_status_cmd_pr <= CS_SET_DONE; + out_of_window_h <= '1'; + elsif ((ts_window_check_value >= 0) and + (ts_window_check_value <= ts_window_width)) then + -- TS in between Window: Set WAIT Bit in LUT and Take Data + channel_index <= CHANNEL_IN; + ch_status_cmd_pr <= CS_SET_WAIT; + data_clk_o <= '1'; case readout_mode(1 downto 0) is when "00" => -- RefValue + TS window filter + ovfl valid + parity valid if (TIMESTAMP_STATUS_IN(2) = '0' and TIMESTAMP_STATUS_IN(0) = '0') then - data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0); - data_o(11 downto 2) <= deltaTStore(9 downto 0); + data_o(11 downto 0) <= deltaTStore(11 downto 0); data_o(23 downto 12) <= ADC_DATA_IN; data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= TIMESTAMP_STATUS_IN(2); - data_clk_o <= '1'; + data_o(31) <= TIMESTAMP_STATUS_IN(1); end if; when "01" => -- RefValue + TS window filter + ovfl and pileup valid -- + parity valid if (TIMESTAMP_STATUS_IN(2 downto 1) = "000") then - data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0); - data_o(11 downto 2) <= deltaTStore(9 downto 0); - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= TIMESTAMP_STATUS_IN(2); - data_clk_o <= '1'; + data_o(11 downto 0) <= deltaTStore(11 downto 0); + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= TIMESTAMP_STATUS_IN(1); end if; when others => -- RefValue + TS window filter + ignore status - data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0); - data_o(11 downto 2) <= deltaTStore(9 downto 0); - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= TIMESTAMP_STATUS_IN(2); - data_clk_o <= '1'; - + data_o(11 downto 0) <= deltaTStore(11 downto 0); + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= TIMESTAMP_STATUS_IN(1); + end case; + + else + -- TS Window Error condition, do nothing + out_of_window_error <= '0'; end if; + else - -- No TS window filter Modes + -- Timestamp to be stored + deltaTStore(13 downto 2) := + (timestamp_fpga - cts_trigger_delay) - + unsigned(TIMESTAMP_IN(13 downto 2)); + deltaTStore( 1 downto 0) := + "00" - unsigned(TIMESTAMP_IN(1 downto 0)); + + -- TS Window Inactive,take data anyhow + data_clk_o <= '1'; + case readout_mode(1 downto 0) is when "00" => -- RefValue + ovfl valid + parity valid if (TIMESTAMP_STATUS_IN(2) = '0' and TIMESTAMP_STATUS_IN(0) = '0') then - data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0); - data_o(11 downto 2) <= deltaTStore(9 downto 0); - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= TIMESTAMP_STATUS_IN(2); - data_clk_o <= '1'; + data_o(11 downto 0) <= deltaTStore(11 downto 0); + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= TIMESTAMP_STATUS_IN(1); end if; when "01" => -- RefValue + ovfl and pileup valid -- + parity valid if (TIMESTAMP_STATUS_IN(2 downto 1) = "000") then - data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0); - data_o(11 downto 2) <= deltaTStore(9 downto 0); - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= TIMESTAMP_STATUS_IN(2); - data_clk_o <= '1'; + data_o(11 downto 0) <= deltaTStore(11 downto 0); + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= TIMESTAMP_STATUS_IN(1); end if; when others => -- RefValue + ignore status - data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0); - data_o(11 downto 2) <= deltaTStore(9 downto 0); - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= TIMESTAMP_STATUS_IN(2); - data_clk_o <= '1'; + data_o(11 downto 0) <= deltaTStore(11 downto 0); + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= TIMESTAMP_STATUS_IN(1); end case; end if; -- Fill Histogram - histogram_fill_o <= '1'; - histogram_bin_o <= CHANNEL_IN; - histogram_adc_o <= ADC_DATA_IN; + histogram_fill_o <= '1'; + histogram_bin_o <= CHANNEL_IN; + histogram_adc_o <= ADC_DATA_IN; end if; end if; @@ -318,67 +379,78 @@ begin ----------------------------------------------------------------------------- PROC_TRIGGER_HANDLER: process(CLK_IN) - variable min_validation_time : unsigned(11 downto 0); + variable wait_for_data_time : unsigned(19 downto 0); + variable min_validation_time : unsigned(19 downto 0); begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1' or FAST_CLEAR_IN = '1') then - store_to_fifo <= '0'; - trigger_busy_o <= '0'; - nomore_data_o <= '0'; - wait_timer_init <= (others => '0'); - wait_timer_reset <= '0'; - t_data_o <= (others => '0'); - t_data_clk_o <= '0'; - busy_time_ctr <= (others => '0'); - busy_time_min_done <= '0'; - token_return_ctr <= '0'; - ch_status_cmd_tr <= CS_RESET; - event_counter <= (others => '0'); - readout_mode <= (others => '0'); - timestamp_ref <= (others => '0'); - STATE <= S_IDLE; + store_to_fifo <= '0'; + trigger_busy_o <= '0'; + nomore_data_o <= '0'; + wait_timer_init <= (others => '0'); + wait_timer_init_ns <= (others => '0'); + wait_timer_reset <= '0'; + min_val_time_expired <= '0'; + t_data_o <= (others => '0'); + t_data_clk_o <= '0'; + busy_time_ctr <= (others => '0'); + busy_time_ctr_last <= (others => '0'); + busy_time_min_done <= '0'; + token_return_ctr <= '0'; + ch_status_cmd_tr <= CS_RESET; + event_counter <= (others => '0'); + readout_mode <= (others => '0'); + timestamp_fpga <= (others => '0'); + timestamp_ref <= (others => '0'); + STATE <= S_IDLE; else - store_to_fifo <= '0'; - wait_timer_init <= (others => '0'); - wait_timer_reset <= '0'; - trigger_busy_o <= '1'; - nomore_data_o <= '0'; - t_data_o <= (others => '0'); - t_data_clk_o <= '0'; - ch_status_cmd_tr <= CS_NONE; - - min_validation_time := x"020" + - (trigger_window_begin / 2) + - (trigger_window_end / 2); + store_to_fifo <= '0'; + wait_timer_init <= (others => '0'); + wait_timer_init_ns <= (others => '0'); + wait_timer_reset <= '0'; + trigger_busy_o <= '1'; + nomore_data_o <= '0'; + t_data_o <= (others => '0'); + t_data_clk_o <= '0'; + ch_status_cmd_tr <= CS_NONE; + busy_time_min_done <= '0'; - case STATE is + wait_for_data_time := + resize(nxyter_cv_time, 20) + (data_fifo_delay_o * 32); + min_validation_time := resize(ts_window_width * 4, 20); + + case STATE is when S_IDLE => if (TRIGGER_IN = '1') then - busy_time_ctr <= (others => '0'); - STATE <= S_TRIGGER; + busy_time_ctr <= (others => '0'); + STATE <= S_TRIGGER; else - trigger_busy_o <= '0'; - STATE <= S_IDLE; + trigger_busy_o <= '0'; + min_val_time_expired <= '0'; + STATE <= S_IDLE; end if; when S_TRIGGER => - readout_mode <= readout_mode_r; - ch_status_cmd_tr <= CS_RESET; - wait_timer_init <= x"020"; -- wait 320ns for first event - STATE <= S_WAIT_DATA; + readout_mode <= readout_mode_r; + ch_status_cmd_tr <= CS_RESET; + -- wait for data arrival + wait_timer_init_ns <= wait_for_data_time; + STATE <= S_WAIT_DATA; when S_WAIT_DATA => - if (wait_timer_done = '0') then - STATE <= S_WAIT_DATA; + if (wait_timer_done_ns = '0') then + STATE <= S_WAIT_DATA; else - timestamp_ref <= TIMESTAMP_REF_IN; - STATE <= S_WRITE_HEADER; + timestamp_fpga <= + TIMESTAMP_FPGA_IN + fpga_timestamp_offset; + timestamp_ref <= timestamp_fpga; + STATE <= S_WRITE_HEADER; end if; when S_WRITE_HEADER => - t_data_o(11 downto 0) <= timestamp_ref; - t_data_o(21 downto 12) <= event_counter; + t_data_o(11 downto 0) <= timestamp_ref; + t_data_o(21 downto 12) <= event_counter; -- Readout Mode Mapping (so far) -- 00: Standard -- 01: Special @@ -391,63 +463,62 @@ begin when "101" => t_data_o(23 downto 22) <= "11"; when others => t_data_o(23 downto 22) <= "11"; end case; - t_data_o(31 downto 24) <= BOARD_ID(7 downto 0); - t_data_clk_o <= '1'; + t_data_o(31 downto 24) <= BOARD_ID(7 downto 0); + t_data_clk_o <= '1'; - event_counter <= event_counter + 1; - STATE <= S_PROCESS_START; + event_counter <= event_counter + 1; + STATE <= S_PROCESS_START; when S_PROCESS_START => - token_return_ctr <= '0'; - wait_timer_init <= readout_time_max; - store_to_fifo <= '1'; - STATE <= S_WAIT_PROCESS_END; + token_return_ctr <= '0'; + wait_timer_init <= readout_time_max; + wait_timer_init_ns <= min_validation_time; + store_to_fifo <= '1'; + STATE <= S_WAIT_PROCESS_END; when S_WAIT_PROCESS_END => - if (wait_timer_done = '1' or - channel_all_done = '1' or - (NX_NOMORE_DATA_IN = '1' and - busy_time_ctr > min_validation_time(11 downto 0)) + if (wait_timer_done = '1' or + channel_all_done = '1' or + (readout_mode(2) = '0' and + NX_NOMORE_DATA_IN = '1' and + min_val_time_expired = '1') ) then - wait_timer_reset <= '1'; - STATE <= S_WRITE_TRAILER; + wait_timer_reset <= '1'; + STATE <= S_WRITE_TRAILER; else - store_to_fifo <= '1'; - STATE <= S_WAIT_PROCESS_END; + busy_time_min_done <= wait_timer_done_ns; + min_val_time_expired <= wait_timer_done_ns; + store_to_fifo <= '1'; + STATE <= S_WAIT_PROCESS_END; -- Check Token_Return if (busy_time_ctr > min_validation_time) then if (readout_mode(2) = '0' and NX_TOKEN_RETURN_IN = '1') then if (token_return_ctr = '1') then - ch_status_cmd_tr <= CS_TOKEN_UPDATE; + ch_status_cmd_tr <= CS_TOKEN_UPDATE; end if; - token_return_ctr <= token_return_ctr or '1'; + token_return_ctr <= token_return_ctr or '1'; end if; end if; - end if; when S_WRITE_TRAILER => - t_data_o <= (others => '1'); - t_data_clk_o <= '1'; - ch_status_cmd_tr <= CS_RESET; - STATE <= S_SET_NOMORE_DATA; + t_data_o <= (others => '1'); + t_data_clk_o <= '1'; + ch_status_cmd_tr <= CS_RESET; + STATE <= S_SET_NOMORE_DATA; when S_SET_NOMORE_DATA => - nomore_data_o <= '1'; - STATE <= S_IDLE; + nomore_data_o <= '1'; + busy_time_ctr_last <= busy_time_ctr; + STATE <= S_IDLE; end case; if (STATE /= S_IDLE) then - busy_time_ctr <= busy_time_ctr + 1; + busy_time_ctr <= busy_time_ctr + 1; end if; - if (busy_time_ctr > min_validation_time) then - busy_time_min_done <= '1'; - else - busy_time_min_done <= '0'; - end if; end if; end if; end process PROC_TRIGGER_HANDLER; @@ -468,7 +539,6 @@ begin end if; end process PROC_CHANNEL_STATUS_CMD; - PROC_CHANNEL_STATUS: process(CLK_IN) constant all_one : std_logic_vector(127 downto 0) := (others => '1'); @@ -515,13 +585,14 @@ begin begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1') then - data_fifo_delay_o <= "0000001"; + data_fifo_delay_o <= x"01"; else - fifo_delay := (cts_trigger_delay / 8) + 1; - if (fifo_delay >= 1 and fifo_delay <= 120) then - data_fifo_delay_o <= std_logic_vector(fifo_delay(6 downto 0)); + fifo_delay := (ts_window_lower_thr / 8) + 1; -- in 32ns + if (fifo_delay > 18 and fifo_delay < 250) then + fifo_delay := fifo_delay - 18; + data_fifo_delay_o <= fifo_delay(7 downto 0); else - data_fifo_delay_o <= "0000001"; + data_fifo_delay_o <= x"01"; end if; end if; end if; @@ -541,135 +612,148 @@ begin slv_ack_o <= '0'; slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; + + ts_window_offset <= (others => '0'); + ts_window_width <= "0000110010"; -- 50 + cts_trigger_delay <= x"0c8"; readout_mode_r <= "000"; - trigger_window_begin <= x"000"; - trigger_window_end <= x"040"; - cts_trigger_delay <= x"000"; - readout_time_max <= x"640"; + readout_time_max <= x"3e8"; + fpga_timestamp_offset <= (others => '0'); else slv_data_out_o <= (others => '0'); slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; + + cts_trigger_delay(11 downto 10) <= (others => '0'); + readout_time_max(11 downto 10) <= (others => '0'); if (SLV_READ_IN = '1') then case SLV_ADDR_IN is when x"0000" => - slv_data_out_o( 2 downto 0) <= readout_mode_r; - slv_data_out_o(31 downto 3) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o( 2 downto 0) <= readout_mode_r; + slv_data_out_o(31 downto 3) <= (others => '0'); + slv_ack_o <= '1'; when x"0001" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(trigger_window_begin); - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(11 downto 0) <= + std_logic_vector(ts_window_offset(11 downto 0)); + slv_data_out_o(31 downto 11) <= (others => '0'); + slv_ack_o <= '1'; when x"0002" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(trigger_window_end); - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(9 downto 0) <= + std_logic_vector(ts_window_width); + slv_data_out_o(31 downto 10) <= (others => '0'); + slv_ack_o <= '1'; when x"0003" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(cts_trigger_delay); - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(9 downto 0) <= + std_logic_vector(cts_trigger_delay(9 downto 0)); + slv_data_out_o(31 downto 10) <= (others => '0'); + slv_ack_o <= '1'; when x"0004" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(readout_time_max); - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(9 downto 0) <= + std_logic_vector(readout_time_max(9 downto 0)); + slv_data_out_o(31 downto 10) <= (others => '0'); + slv_ack_o <= '1'; when x"0005" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(busy_time_ctr); - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(11 downto 0) <= + std_logic_vector(fpga_timestamp_offset); + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; when x"0006" => - slv_data_out_o(11 downto 0) <= timestamp_ref; - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(11 downto 0) <= + std_logic_vector(busy_time_ctr_last); + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; when x"0007" => - slv_data_out_o(11 downto 0) <= window_lower_thr_r; - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(11 downto 0) <= timestamp_ref; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; when x"0008" => - slv_data_out_o(11 downto 0) <= window_upper_thr_r; - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(11 downto 0) <= ts_window_lower_thr; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; - when x"0009" => - slv_data_out_o( 6 downto 0) <= + when x"000a" => + slv_data_out_o(7 downto 0) <= std_logic_vector(data_fifo_delay_o); - slv_data_out_o(31 downto 7) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(31 downto 8) <= (others => '0'); + slv_ack_o <= '1'; - when x"000a" => - slv_data_out_o <= + when x"000b" => + slv_data_out_o <= std_logic_vector(channel_done(31 downto 0)); - slv_ack_o <= '1'; + slv_ack_o <= '1'; - when x"000b" => - slv_data_out_o <= + when x"000c" => + slv_data_out_o <= std_logic_vector(channel_done(63 downto 32)); - slv_ack_o <= '1'; + slv_ack_o <= '1'; - when x"000c" => - slv_data_out_o <= + when x"000d" => + slv_data_out_o <= std_logic_vector(channel_done(95 downto 64)); - slv_ack_o <= '1'; + slv_ack_o <= '1'; - when x"000d" => - slv_data_out_o <= + when x"000e" => + slv_data_out_o <= std_logic_vector(channel_done(127 downto 96)); - slv_ack_o <= '1'; + slv_ack_o <= '1'; when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; end case; elsif (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is when x"0000" => - readout_mode_r <= SLV_DATA_IN(2 downto 0); - slv_ack_o <= '1'; - + readout_mode_r <= SLV_DATA_IN(2 downto 0); + slv_ack_o <= '1'; + when x"0001" => - trigger_window_begin <= SLV_DATA_IN(11 downto 0); - slv_ack_o <= '1'; - - when x"0002" => - trigger_window_end <= - unsigned(SLV_DATA_IN(11 downto 0)); - slv_ack_o <= '1'; + if ((signed(SLV_DATA_IN(11 downto 0)) > -1024) and + (signed(SLV_DATA_IN(11 downto 0)) < 1024)) then + ts_window_offset(11 downto 0) <= + signed(SLV_DATA_IN(11 downto 0)); + end if; + slv_ack_o <= '1'; + + when x"0002" => + ts_window_width <= + unsigned(SLV_DATA_IN(9 downto 0)); + slv_ack_o <= '1'; when x"0003" => - if (unsigned(SLV_DATA_IN(11 downto 0)) < 960) then - cts_trigger_delay <= - unsigned(SLV_DATA_IN(11 downto 0)); - end if; - slv_ack_o <= '1'; + cts_trigger_delay(9 downto 0) <= + unsigned(SLV_DATA_IN(9 downto 0)); + slv_ack_o <= '1'; when x"0004" => - if (unsigned(SLV_DATA_IN(11 downto 0)) >= 1) then - readout_time_max <= - unsigned(SLV_DATA_IN(11 downto 0)); - end if; - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - else - slv_ack_o <= '0'; + if (unsigned(SLV_DATA_IN(9 downto 0)) >= 1) then + readout_time_max(9 downto 0) <= + unsigned(SLV_DATA_IN(9 downto 0)); + end if; + slv_ack_o <= '1'; + + when x"0005" => + fpga_timestamp_offset(11 downto 0) <= + unsigned(SLV_DATA_IN(11 downto 0)); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + else + slv_ack_o <= '0'; end if; end if; end if; @@ -683,7 +767,7 @@ begin DATA_OUT <= data_o or t_data_o; DATA_CLK_OUT <= data_clk_o or t_data_clk_o; NOMORE_DATA_OUT <= nomore_data_o; - DATA_FIFO_DELAY_OUT <= data_fifo_delay_o; + DATA_FIFO_DELAY_OUT <= std_logic_vector(data_fifo_delay_o); HISTOGRAM_FILL_OUT <= histogram_fill_o; HISTOGRAM_BIN_OUT <= histogram_bin_o; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 205d8b3..ed62f29 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -20,6 +20,7 @@ package nxyter_components is CLK_ADC_IN : in std_logic; PLL_NX_CLK_LOCK_IN : in std_logic; PLL_ADC_CLK_LOCK_IN : in std_logic; + NX_DATA_CLK_TEST_IN : in std_logic; TRIGGER_OUT : out std_logic; @@ -254,6 +255,14 @@ component nxyter_registers I2C_REG_RESET_OUT : out std_logic; NX_TS_RESET_OUT : out std_logic; OFFLINE_OUT : out std_logic; + + NX_DATA_CLK_DPHASE_OUT : out std_logic_vector(3 downto 0); + NX_DATA_CLK_FINEDELB_OUT : out std_logic_vector(3 downto 0); + NX_DATA_CLK_LOCK_IN : in std_logic; + NX_DATA_CLK_CLKOP_IN : in std_logic; + NX_DATA_CLK_CLKOS_IN : in std_logic; + NX_DATA_CLK_CLKOK_IN : in std_logic; + SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -289,21 +298,6 @@ component fifo_ts_32to32_dc ); end component; -component fifo_ts_12to12_dc - port ( - Data : in std_logic_vector(11 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(11 downto 0); - Empty : out std_logic; - Full : out std_logic - ); -end component; - component fifo_44_data_delay port ( Data : in std_logic_vector(43 downto 0); @@ -311,7 +305,7 @@ component fifo_44_data_delay WrEn : in std_logic; RdEn : in std_logic; Reset : in std_logic; - AmEmptyThresh : in std_logic_vector(6 downto 0); + AmEmptyThresh : in std_logic_vector(7 downto 0); Q : out std_logic_vector(43 downto 0); Empty : out std_logic; Full : out std_logic; @@ -337,7 +331,7 @@ component nx_data_receiver port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - NX_MAIN_CLK_IN : in std_logic; + NX_DATA_CLK_TEST_IN : in std_logic; TRIGGER_IN : in std_logic; NX_TIMESTAMP_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); @@ -375,7 +369,7 @@ component nx_data_delay NX_FRAME_OUT : out std_logic_vector(31 downto 0); ADC_DATA_OUT : out std_logic_vector(11 downto 0); NEW_DATA_OUT : out std_logic; - FIFO_DELAY_IN : in std_logic_vector(6 downto 0); + FIFO_DELAY_IN : in std_logic_vector(7 downto 0); SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -431,8 +425,8 @@ component nx_trigger_validate TRIGGER_IN : in std_logic; FAST_CLEAR_IN : in std_logic; TRIGGER_BUSY_OUT : out std_logic; - TIMESTAMP_REF_IN : in unsigned(11 downto 0); - DATA_FIFO_DELAY_OUT : out std_logic_vector(6 downto 0); + TIMESTAMP_FPGA_IN : in unsigned(11 downto 0); + DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0); DATA_OUT : out std_logic_vector(31 downto 0); DATA_CLK_OUT : out std_logic; NOMORE_DATA_OUT : out std_logic; @@ -545,6 +539,30 @@ component pulse_to_level ); end component; +component pulse_async_trans + generic ( + NUM_FF : integer range 2 to 4 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + PULSE_A_IN : in std_logic; + PULSE_OUT : out std_logic + ); +end component; + +component signal_async_trans + generic ( + NUM_FF : integer range 2 to 4 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + SIGNAL_A_IN : in std_logic; + SIGNAL_OUT : out std_logic + ); +end component; + component pulse_dtrans generic ( CLK_RATIO : integer range 2 to 15 @@ -591,6 +609,7 @@ component pll_nx_clk250 port ( CLK : in std_logic; CLKOP : out std_logic; + CLKOK : out std_logic; LOCK : out std_logic ); end component; @@ -603,6 +622,24 @@ component pll_adc_clk ); end component; +component pll_adc_sampling_clk + port ( + CLK : in std_logic; + RESET : in std_logic; + FINEDELB0 : in std_logic; + FINEDELB1 : in std_logic; + FINEDELB2 : in std_logic; + FINEDELB3 : in std_logic; + DPHASE0 : in std_logic; + DPHASE1 : in std_logic; + DPHASE2 : in std_logic; + DPHASE3 : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + LOCK : out std_logic + ); +end component; + component nx_fpga_timestamp port ( CLK_IN : in std_logic; @@ -667,10 +704,11 @@ component nx_trigger_generator port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - TRIGGER_IN : out std_logic; + TRIGGER_IN : in std_logic; TRIGGER_OUT : out std_logic; TS_RESET_OUT : out std_logic; TESTPULSE_OUT : out std_logic; + TEST_IN : in std_logic_vector(31 downto 0); SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -689,7 +727,8 @@ end component; component nx_timer generic ( - CTR_WIDTH : integer range 2 to 32 + CTR_WIDTH : integer range 2 to 32; + STEP_SIZE : integer ); port ( CLK_IN : in std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 7cbcaa5..969f3db 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -24,8 +24,9 @@ entity nXyter_FEE_board is CLK_ADC_IN : in std_logic; PLL_NX_CLK_LOCK_IN : in std_logic; PLL_ADC_CLK_LOCK_IN : in std_logic; + NX_DATA_CLK_TEST_IN : in std_logic; TRIGGER_OUT : out std_logic; - + -- I2C Ports I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line @@ -144,7 +145,7 @@ architecture Behavioral of nXyter_FEE_board is signal new_timestamp_delayed : std_logic_vector(31 downto 0); signal new_adc_data_delayed : std_logic_vector(11 downto 0); signal new_data_delayed : std_logic; - signal new_data_fifo_delay : std_logic_vector(6 downto 0); + signal new_data_fifo_delay : std_logic_vector(7 downto 0); -- Data Validate signal timestamp : std_logic_vector(13 downto 0); @@ -191,13 +192,21 @@ architecture Behavioral of nXyter_FEE_board is signal nx_timestamp_sync : std_logic; signal nx_timestamp_trigger_o : std_logic; - -- Trigger Generator + -- Trigger Generatorg signal trigger_intern : std_logic; signal nx_testpulse_o : std_logic; -- Debug Handler constant DEBUG_NUM_PORTS : integer := 13; signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1); + + -- Nxyter Data Clock Handler + signal nx1_data_clk_dphase : std_logic_vector(3 downto 0); + signal nx1_data_clk_finedelb : std_logic_vector(3 downto 0); + signal nx1_data_clk_lock : std_logic; + signal nx1_data_clk_clkop : std_logic; + signal nx1_data_clk_clkos : std_logic; + signal nx1_data_clk_clkok : std_logic; begin @@ -298,6 +307,13 @@ begin NX_TS_RESET_OUT => nx_ts_reset_1, OFFLINE_OUT => nxyter_offline, + NX_DATA_CLK_DPHASE_OUT => nx1_data_clk_dphase, + NX_DATA_CLK_FINEDELB_OUT => nx1_data_clk_finedelb, + NX_DATA_CLK_LOCK_IN => nx1_data_clk_lock, + NX_DATA_CLK_CLKOP_IN => nx1_data_clk_clkop, + NX_DATA_CLK_CLKOS_IN => nx1_data_clk_clkos, + NX_DATA_CLK_CLKOK_IN => nx1_data_clk_clkok, + SLV_READ_IN => slv_read(0), SLV_WRITE_IN => slv_write(0), SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), @@ -479,6 +495,7 @@ begin TRIGGER_OUT => trigger_intern, TS_RESET_OUT => nx_ts_reset_2, TESTPULSE_OUT => nx_testpulse_o, + TEST_IN => new_timestamp, SLV_READ_IN => slv_read(5), SLV_WRITE_IN => slv_write(5), SLV_DATA_OUT => slv_data_rd(5*32+31 downto 5*32), @@ -499,7 +516,7 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - NX_MAIN_CLK_IN => CLK_NX_MAIN_IN, + NX_DATA_CLK_TEST_IN => NX_DATA_CLK_TEST_IN, TRIGGER_IN => lvl2_trigger, NX_TIMESTAMP_CLK_IN => NX_DATA_CLK_IN, @@ -519,7 +536,7 @@ begin NEW_DATA_OUT => new_data, TIMESTAMP_CURRENT_IN => timestamp_current, - + SLV_READ_IN => slv_read(2), SLV_WRITE_IN => slv_write(2), SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), @@ -616,7 +633,7 @@ begin TRIGGER_IN => trigger, FAST_CLEAR_IN => fast_clear, TRIGGER_BUSY_OUT => trigger_validate_busy, - TIMESTAMP_REF_IN => timestamp_hold, + TIMESTAMP_FPGA_IN => timestamp_hold, DATA_FIFO_DELAY_OUT => new_data_fifo_delay, DATA_OUT => trigger_data, diff --git a/nxyter/source/nxyter_registers.vhd b/nxyter/source/nxyter_registers.vhd index f2dd7c6..6a82ce6 100644 --- a/nxyter/source/nxyter_registers.vhd +++ b/nxyter/source/nxyter_registers.vhd @@ -19,6 +19,14 @@ entity nxyter_registers is I2C_REG_RESET_OUT : out std_logic; NX_TS_RESET_OUT : out std_logic; OFFLINE_OUT : out std_logic; + + -- NX Data Clock Handler + NX_DATA_CLK_DPHASE_OUT : out std_logic_vector(3 downto 0); + NX_DATA_CLK_FINEDELB_OUT : out std_logic_vector(3 downto 0); + NX_DATA_CLK_LOCK_IN : in std_logic; + NX_DATA_CLK_CLKOP_IN : in std_logic; + NX_DATA_CLK_CLKOS_IN : in std_logic; + NX_DATA_CLK_CLKOK_IN : in std_logic; -- Slave bus SLV_READ_IN : in std_logic; @@ -51,7 +59,8 @@ architecture Behavioral of nxyter_registers is S_I2C_SM_RESET_WAIT, S_I2C_REG_RESET, S_I2C_REG_RESET_WAIT, - S_NX_TS_RESET + S_NX_TS_RESET, + S_NX_TS_RESET_WAIT ); signal STATE : STATES; @@ -61,11 +70,23 @@ architecture Behavioral of nxyter_registers is signal wait_timer_done : std_logic; -- PLL Locks - signal pll_nx_clk_lock_t : std_logic; signal pll_nx_clk_lock : std_logic; - signal pll_adc_clk_lock_t : std_logic; signal pll_adc_clk_lock : std_logic; + signal nx_data_clk_lock : std_logic; + signal pll_nx_clk_notlock : std_logic; + signal pll_adc_clk_notlock : std_logic; + signal nx_data_clk_notlock : std_logic; + + signal pll_nx_clk_notlock_ctr : unsigned(15 downto 0); + signal pll_adc_clk_notlock_ctr : unsigned(15 downto 0); + signal nx_data_clk_notlock_ctr : unsigned(15 downto 0); + signal clear_notlock_counters : std_logic; + + -- Nxyter Data Clock + signal nx_data_clk_dphase_o : std_logic_vector(3 downto 0); + signal nx_data_clk_finedelb_o : std_logic_vector(3 downto 0); + -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; @@ -79,7 +100,13 @@ begin DEBUG_OUT(2) <= i2c_reg_reset_o; DEBUG_OUT(3) <= nx_ts_reset_o; - DEBUG_OUT(15 downto 4) <= (others => '0'); + DEBUG_OUT(4) <= NX_DATA_CLK_LOCK_IN; + DEBUG_OUT(5) <= NX_DATA_CLK_CLKOP_IN; + DEBUG_OUT(6) <= NX_DATA_CLK_CLKOS_IN; + DEBUG_OUT(7) <= NX_DATA_CLK_CLKOK_IN; + + DEBUG_OUT(11 downto 8) <= nx_data_clk_dphase_o; + DEBUG_OUT(15 downto 12) <= nx_data_clk_finedelb_o; nx_timer_1: nx_timer generic map ( @@ -151,31 +178,96 @@ begin when S_NX_TS_RESET => nx_ts_reset_o <= '1'; - STATE <= S_IDLE; + wait_timer_init <= x"01"; + STATE <= S_NX_TS_RESET_WAIT; + when S_NX_TS_RESET_WAIT => + nx_ts_reset_o <= '1'; + if (wait_timer_done = '0') then + STATE <= S_NX_TS_RESET_WAIT; + else + STATE <= S_IDLE; + end if; + end case; end if; end if; end process PROC_I2C_SM_RESET; - PROC_PLL_LOCKS: process (CLK_IN) + ----------------------------------------------------------------------------- + -- PLL Not Lock Counters + ----------------------------------------------------------------------------- + + signal_async_trans_1: signal_async_trans + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SIGNAL_A_IN => PLL_NX_CLK_LOCK_IN, + SIGNAL_OUT => pll_nx_clk_lock + ); + + signal_async_trans_2: signal_async_trans + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SIGNAL_A_IN => PLL_ADC_CLK_LOCK_IN, + SIGNAL_OUT => pll_adc_clk_lock + ); + + signal_async_trans_3: signal_async_trans + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SIGNAL_A_IN => NX_DATA_CLK_LOCK_IN, + SIGNAL_OUT => nx_data_clk_lock + ); + + level_to_pulse_1: level_to_pulse + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + LEVEL_IN => not pll_nx_clk_lock, + PULSE_OUT => pll_nx_clk_notlock + ); + + level_to_pulse_2: level_to_pulse + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + LEVEL_IN => not pll_adc_clk_lock, + PULSE_OUT => pll_adc_clk_notlock + ); + + level_to_pulse_3: level_to_pulse + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + LEVEL_IN => not nx_data_clk_lock, + PULSE_OUT => nx_data_clk_notlock + ); + + PROC_PLL_UNLOCK_COUNTERS: process (CLK_IN) begin if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - pll_nx_clk_lock_t <= '0'; - pll_nx_clk_lock <= '0'; - pll_adc_clk_lock_t <= '0'; - pll_adc_clk_lock <= '0'; + if( RESET_IN = '1' or clear_notlock_counters = '1') then + pll_nx_clk_notlock_ctr <= (others => '0'); + pll_adc_clk_notlock_ctr <= (others => '0'); + nx_data_clk_notlock_ctr <= (others => '0'); else - pll_nx_clk_lock_t <= PLL_NX_CLK_LOCK_IN; - pll_nx_clk_lock <= pll_nx_clk_lock_t; - pll_adc_clk_lock_t <= PLL_ADC_CLK_LOCK_IN; - pll_adc_clk_lock <= pll_adc_clk_lock_t; + if (pll_nx_clk_notlock = '1') then + pll_nx_clk_notlock_ctr <= pll_nx_clk_notlock_ctr + 1; + end if; + if (pll_adc_clk_notlock = '1') then + pll_adc_clk_notlock_ctr <= pll_adc_clk_notlock_ctr + 1; + end if; + if (nx_data_clk_notlock = '1') then + nx_data_clk_notlock_ctr <= nx_data_clk_notlock_ctr + 1; + end if; end if; end if; - end process PROC_PLL_LOCKS; - + end process PROC_PLL_UNLOCK_COUNTERS; + ----------------------------------------------------------------------------- -- Slave Bus ----------------------------------------------------------------------------- @@ -184,22 +276,25 @@ begin begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - - i2c_sm_reset_start <= '0'; - i2c_reg_reset_start <= '0'; - nx_ts_reset_start <= '0'; - offline_o <= '1'; - else - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - slv_data_out_o <= (others => '0'); - i2c_sm_reset_start <= '0'; - i2c_reg_reset_start <= '0'; - nx_ts_reset_start <= '0'; + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + i2c_sm_reset_start <= '0'; + i2c_reg_reset_start <= '0'; + nx_ts_reset_start <= '0'; + offline_o <= '1'; + nx_data_clk_dphase_o <= x"7"; + nx_data_clk_finedelb_o <= x"0"; + clear_notlock_counters <= '0'; + else + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + i2c_sm_reset_start <= '0'; + i2c_reg_reset_start <= '0'; + nx_ts_reset_start <= '0'; + clear_notlock_counters <= '0'; if (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is @@ -218,7 +313,11 @@ begin when x"0003" => offline_o <= SLV_DATA_IN(0); slv_ack_o <= '1'; - + + when x"000a" => + clear_notlock_counters <= '1'; + slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; @@ -240,6 +339,16 @@ begin slv_data_out_o(0) <= pll_adc_clk_lock; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; + + when x"000a" => + slv_data_out_o(15 downto 0) <= pll_nx_clk_notlock_ctr; + slv_data_out_o(31 downto 6) <= (others => '0'); + slv_ack_o <= '1'; + + when x"000b" => + slv_data_out_o(15 downto 0) <= pll_adc_clk_notlock_ctr; + slv_data_out_o(31 downto 6) <= (others => '0'); + slv_ack_o <= '1'; when others => slv_unknown_addr_o <= '1'; @@ -253,7 +362,13 @@ begin end if; end process PROC_NX_REGISTERS; --- Output Signals + + -- Clock Handler + NX_DATA_CLK_DPHASE_OUT <= nx_data_clk_dphase_o; + NX_DATA_CLK_FINEDELB_OUT <= nx_data_clk_finedelb_o; + + + -- Output Signals SLV_DATA_OUT <= slv_data_out_o; SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; diff --git a/nxyter/source/pulse_async_trans.vhd b/nxyter/source/pulse_async_trans.vhd new file mode 100644 index 0000000..bfb9660 --- /dev/null +++ b/nxyter/source/pulse_async_trans.vhd @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.nxyter_components.all; + +entity pulse_async_trans is + generic ( + NUM_FF : integer range 2 to 4 := 2 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + PULSE_A_IN : in std_logic; + PULSE_OUT : out std_logic + ); + +end entity; + +architecture Behavioral of pulse_async_trans is + signal pulse_ff : std_logic_vector(NUM_FF - 1 downto 0); + signal pulse_o : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Clock CLK_IN Domain + ----------------------------------------------------------------------------- + + PROC_SYNC_PULSE: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + pulse_ff(NUM_FF - 1) <= PULSE_A_IN; + if( RESET_IN = '1' ) then + for i in NUM_FF - 2 downto 0 loop + pulse_ff(i) <= '0'; + end loop; + else + for i in NUM_FF - 2 downto 0 loop + pulse_ff(i) <= pulse_ff(i + 1); + end loop; + end if; + end if; + end process PROC_SYNC_PULSE; + + level_to_pulse_1: level_to_pulse + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + LEVEL_IN => pulse_ff(0), + PULSE_OUT => pulse_o + ); + + -- Outputs + PULSE_OUT <= pulse_o; + +end Behavioral; diff --git a/nxyter/source/pulse_dtrans.vhd b/nxyter/source/pulse_dtrans.vhd index 2e66bec..c188f5f 100644 --- a/nxyter/source/pulse_dtrans.vhd +++ b/nxyter/source/pulse_dtrans.vhd @@ -22,9 +22,6 @@ end entity; architecture Behavioral of pulse_dtrans is signal pulse_a_l : std_logic; - - signal pulse_b_t : std_logic; - signal pulse_b_l : std_logic; signal pulse_b_o : std_logic; begin @@ -47,25 +44,15 @@ begin -- Clock B Domain ----------------------------------------------------------------------------- - PROC_SYNC_PULSE: process(CLK_B_IN) - begin - if( rising_edge(CLK_B_IN) ) then - if( RESET_B_IN = '1' ) then - pulse_b_t <= '0'; - pulse_b_l <= '0'; - else - pulse_b_t <= pulse_a_l; - pulse_b_l <= pulse_b_t; - end if; - end if; - end process PROC_SYNC_PULSE; - - level_to_pulse_1: level_to_pulse + pulse_async_trans_1: pulse_async_trans + generic map ( + NUM_FF => 2 + ) port map ( - CLK_IN => CLK_B_IN, - RESET_IN => RESET_B_IN, - LEVEL_IN => pulse_b_l, - PULSE_OUT => pulse_b_o + CLK_IN => CLK_B_IN, + RESET_IN => RESET_B_IN, + PULSE_A_IN => pulse_a_l, + PULSE_OUT => pulse_b_o ); -- Outputs diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index baa9298..11c3c4e 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -2,9 +2,12 @@ 0x8100 : w w: reset I2C State Machine 0x8101 : w w: reset I2C all Register 0x8102 : w w: Reset and Sync Timestamps (nXyter and FPGA) -0x8103 : r/w Put nxyter into offline mode -0x8104 : r PLL Lock nXyter Main Clock (250MHz) -0x8105 : r PLL Lock ADC Clock (31.25MHz) +0x8103 : r/w Put Nxyter into offline mode +0x8104 : r Nxyter Main Clock Lock (125 MHz) +0x8105 : r ADC Data Clock Lock (187.5MHz) +0x810a : r/w r: PLL Nxyter Main Clock NotLock Counter + w: Clear all pll_nx_clk_notlock_ctr +0x810b : r PLL ADC Data Clock NotLock Counter -- NX I2C Setup Handler 0x8200 : r/w I2C Memeory Register (Depth: 0 - 45 ... 0x822c) @@ -15,12 +18,8 @@ 0x8243 : w Write Memory to Trim DAC Register(129 deep FIFO) -- Trigger Generator -#0x8140 : w If writing just start trigger cycle, keep current setting -#0x8141 : r/w Bit 15-0 : periodic time (in 10ns) -#0x8142 : r/w Bit0 7-0 : number of triggers to be sent consecutive -0x8143 : r/w Bit 15-0 : Length of trigger pulse (in 10ns), if 0: skip it -#0x8144 : r/w Bit0 : 1: send timestamp-reset before trigger -0x8145 : r : Testpulse Rate (in Hz) +0x8141 : r/w Length of Trigger TestPulse (12 Bit, in 10ns) +0x8145 : r Testpulse Rate (in Hz) -- Trigger Handler 0x8160 : r/w Bit 7-0 : Delay Testpulse Signal after Trigger (10ns) @@ -36,62 +35,63 @@ 3..29: ignore 31: nx_frame_synced w: adc reset -0x8502 : r/w r: Resync Counter(12bit) +0x8502 : r/w r: Resync Counter(12 Bit) w: clear Resync Counter -0x8503 : r/w r: Parity Error Counter (12bit) - w: clear Parity Error Counter -0x8505 : r/w ADC CLK Delay 4ns steps (3Bit: range 0..7) - 0: 4ns after frame_valid - 1: 8ns -------"--------- - ...... -------"--------- - 6: 28ns -------"--------- - 7: 32ns -------"--------- <= this shoud be correct - i.e. 2ns before new frame clock -0x8506 : r ADC Reset Counter -0x8507 : r/w Debug Multiplexer: +0x8503 : r/w r: Parity Error Counter (12 Bit) + w: clear Parity Error Counter +0x8504 : r/w ADC Sampling PLL Clock Not Lock Counter + w: clear counter +0x8505 : r/w johnson_counter_sync(2 Bit), do not touch, experts only register +0x8506 : r/w PLL ADC Sampling Clock DPHASE (4 Bit) +0x8507 : r/w PLL ADC Sampling Clock FINEDELB (4 Bit) + +0x8508 : r current ADC FIFO value +0x8509 : w PLL ADC Sampling CLK Reset +0x850a : r/w Enable Test ADC Input Data Error Test +0x850b : r ADC Input Data Error Counter (16 Bit) + (only valid in case of 0x8509 is 1, see line above) +0x850c : r Nxyter Data Clock Status (1 = O.K.) + +0x850f : r/w Debug Multiplexer: 0: no ADC Values, normal Debug 1: ADC Value Nxyter 2: ADC Value Testchannel 3: ADC Reset Handler -0x8508 : r current ADC FIFO value -0x8509 : r/w Enable Test ADC Input Data Error Test -0x850a : r ADC Input Data Error Counter (16 Bit) - (only valid in case of 0x8509 is 1, see line above) -- NX Data Delay -0x8130 : r FIFO Delay, i.e. Trigger Delay (7Bit, in 32ns, Range 1..120) - --- NX Data Validate -0x8120 : r/w Invalid Frame Counter (16 bit) / w: clear all counters -0x8121 : r Overflow Counter (16 bit) -0x8122 : r Pileup Counter (16 bit) -0x8123 : r Parity Error Counter (16 bit) -0x8124 : r Hit Rate (in Hz) -0x8125 : r Frame Rate (in Hz) +0x8130 : r FIFO Delay, i.e. Trigger Delay (8 Bit, in 32ns). + Calculation is based on CTS Trigger Delay + (see NX Trigger Validate) -- NX Trigger Validate -0x8180 : r/w Readout Mode (0: Ref + [DeltaTS + ovfl + parity] valid - 1: Ref + [DeltaTS + ovfl + pileup + parity] valid - 2: UNDEF - 3: UNDEF - 4: Ref + [ ovfl + + parity] valid - 5: Ref + [ ovfl + pileup + parity] valid - 6: UNDEF - 7: UNDEF -0x8181 : r/w Trigger Window Delay (12 bit, in 4ns) -0x8182 : r/w Trigger Window Width (12 bit, in 4ns) -0x8183 : r/w CTS Trigger Delay (12 bit, in 4ns) -0x8184 : r/w Readout Time Max (12 bit, in 10ns) - -0x8185 : r Busy Time Counter (12 bit, in 10ns) -0x8186 : r timestamp_ref -0x8187 : r window_lower_thr -0x8188 : r window_upper_thr -0x8189 : r data_fifo_delay (7 bit, in 32ns) -0x818a : r done counter ch 0..31 -0x818b : r done counter ch 32..63 -0x818c : r done counter ch 94..95 -0x818d : r done counter ch 96..127 +0x8180 : r/w Readout Mode: 3 Bits + Bit #2: 0: activate TS Selection Window + 1: data wil be written to disk as long as + Readout Time Max (Reg.: 0x8184) is valid + Bit #1..0 0: TS Ovfl and Parity Bit valid + 1: TS Ovfl, Parity and Pileup Bit valid + 2: ignore TS Status Bits + 3: -------- " ------- + +0x8181 : r/w Trigger Window Offset [TS_Offset] (11 Bit signed, in 4ns) +0x8182 : r/w Trigger Window Width [TS_Width] (10 Bit, in 4ns) +0x8183 : r/w CTS Trigger Delay [CTS_Delay] (10 Bit, in 4ns) + FPGA_Timestamp = TS_Ref + Trigger Window Lower Threshold = + TS_FPGA - CTS_Delay +/- TS_Offset + Trigger Window Upper Threshold = + TS_FPGA - CTS_Delay + TS_Offset + TS_Width +0x8184 : r/w Readout Time Max (10 Bit, in 10ns) + +0x8185 : r/w FPGA Timestamp Offset (12 Bit, in 4ns) +0x8186 : r Busy Time Counter (12 Bit, in 10ns) +0x8187 : r timestamp_ref +0x8188 : r window_lower_thr +0x818a : r data_fifo_delay (7 Bit, in 32ns) +0x818b : r done counter ch 0..31 +0x818c : r done counter ch 32..63 +0x818d : r done counter ch 94..95 +0x818e : r done counter ch 96..127 -- Event Data Buffer 0x8600 : r read FIFO buffer @@ -113,7 +113,7 @@ 0x8800 : r/w r: Read Channel Statistic (128 channel in a row) w: reset all Histograms 0x8880 : r Read Channel Trigger Rate (128 channel in a row, 1/s) -0x8900 : r Read Channel ADC Value (128 channel in a row) +0x8900 : r Read Channel ADC Value (128 channel in a row) -- Debug Multiplexer 0x8020 : r/w Select Debug Entity @@ -131,3 +131,32 @@ 11: nx_event_buffer 12: nx_histograms + +--- Trigger Selction Window Setup + + _ +Physics Trigger [PT] _______________| |___________________________________ + _ +NX_TS_Trigger [NXT] ____________________| |______________________________ + _ +CTS Trigger [CT] _____________________________________| |_____________ + _ +FPGA TS Trigger [FT] _________________________________________| |_________ + | +CTS+FPGA Trigger Delay |--------------------| + | | +FPGA TS-Ref stored in Event Header | | + | | +Trigger Window Offset(-) |----------| | +Trigger Window Width(-) |----------------| | +Timestamps stored in Event(-) |--|---|--|-||--|---------------| + | | + | | +Trigger Window Offset(+) |-----| | +Trigger Window Width(+) |---------| | +Timestamps stored in Event(+) -----------------|--||--|-|-----| + +TIME ----------------------------------------------------------------------> + + + diff --git a/nxyter/source/signal_async_trans.vhd b/nxyter/source/signal_async_trans.vhd new file mode 100644 index 0000000..edfb6ec --- /dev/null +++ b/nxyter/source/signal_async_trans.vhd @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity signal_async_trans is + generic ( + NUM_FF : integer range 2 to 4 := 2 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + SIGNAL_A_IN : in std_logic; + SIGNAL_OUT : out std_logic + ); + +end entity; + +architecture Behavioral of signal_async_trans is + signal signal_ff : std_logic_vector(NUM_FF - 1 downto 0); + signal signal_o : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Clock CLK_IN Domain + ----------------------------------------------------------------------------- + + PROC_SYNC_SIGNAL: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + signal_ff(NUM_FF - 1) <= SIGNAL_A_IN; + if( RESET_IN = '1' ) then + for i in NUM_FF - 2 downto 0 loop + signal_ff(i) <= '0'; + end loop; + else + for i in NUM_FF - 2 downto 0 loop + signal_ff(i) <= signal_ff(i + 1); + end loop; + end if; + end if; + end process PROC_SYNC_SIGNAL; + signal_o <= signal_ff(0); + +-- Outpu Signals + SIGNAL_OUT <= signal_o; + +end Behavioral; diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 80d5d26..fb9c00b 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -144,10 +144,10 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd" add_file -vhdl -lib "work" "cores/pll_adc_clk.vhd" +add_file -vhdl -lib "work" "cores/pll_adc_sampling_clk.vhd" add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd" add_file -vhdl -lib "work" "cores/fifo_44_data_delay.vhd" add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" -add_file -vhdl -lib "work" "cores/fifo_ts_12to12_dc.vhd" add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" @@ -156,6 +156,8 @@ add_file -vhdl -lib "work" "source/nxyter_components.vhd" add_file -vhdl -lib "work" "source/level_to_pulse.vhd" add_file -vhdl -lib "work" "source/pulse_to_level.vhd" add_file -vhdl -lib "work" "source/pulse_dtrans.vhd" +add_file -vhdl -lib "work" "source/pulse_async_trans.vhd" +add_file -vhdl -lib "work" "source/signal_async_trans.vhd" add_file -vhdl -lib "work" "source/gray_decoder.vhd" add_file -vhdl -lib "work" "source/gray_encoder.vhd" add_file -vhdl -lib "work" "source/nx_timer.vhd" diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index b438635..4373737 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -161,8 +161,10 @@ architecture trb3_periph_arch of trb3_periph is -- For 250MHz PLL nxyter clock, THE_32M_ODDR_1 attribute ODDRAPPS : string; - attribute ODDRAPPS of THE_250M_ODDR_1 : label is "SCLK_ALIGNED"; - attribute ODDRAPPS of THE_250M_ODDR_2 : label is "SCLK_ALIGNED"; + attribute ODDRAPPS of THE_NX_MAIN_ODDR_1 : label is "SCLK_ALIGNED"; + attribute ODDRAPPS of THE_NX_MAIN_ODDR_2 : label is "SCLK_ALIGNED"; + -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_1 : label is "SCLK_ALIGNED"; + -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_2 : label is "SCLK_ALIGNED"; --Constants constant REGIO_NUM_STAT_REGS : integer := 5; @@ -285,6 +287,7 @@ architecture trb3_periph_arch of trb3_periph is -- nXyter-FEB-Board Clocks signal nx_main_clk : std_logic; + signal nx_data_clk_test : std_logic; signal pll_nx_clk_lock : std_logic; signal clk_adc_dat_1 : std_logic; signal clk_adc_dat_2 : std_logic; @@ -704,6 +707,7 @@ begin CLK_ADC_IN => clk_adc_dat_1, PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock, PLL_ADC_CLK_LOCK_IN => pll_adc_clk_lock_1, + NX_DATA_CLK_TEST_IN => nx_data_clk_test, TRIGGER_OUT => fee1_trigger, @@ -784,6 +788,7 @@ begin CLK_ADC_IN => clk_adc_dat_2, PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock, PLL_ADC_CLK_LOCK_IN => pll_adc_clk_lock_2, + NX_DATA_CLK_TEST_IN => nx_data_clk_test, TRIGGER_OUT => fee2_trigger, I2C_SDA_INOUT => NX2_I2C_SDA_INOUT, @@ -848,7 +853,6 @@ begin DEBUG_LINE_OUT => open ); - ADDON_TRIGGER_OUT <= fee1_trigger or fee2_trigger; ----------------------------------------------------------------------------- @@ -860,14 +864,12 @@ begin port map ( CLK => CLK_PCLK_RIGHT, CLKOP => nx_main_clk, + CLKOK => nx_data_clk_test, LOCK => pll_nx_clk_lock ); - - --NX1_MAIN_CLK_OUT <= nx_main_clk; - --NX2_MAIN_CLK_OUT <= nx_main_clk; - -- Drivers for Nxyter Main Clocks - THE_250M_ODDR_1: ODDRXD1 + -- Port FF for Nxyter Main Clocks + THE_NX_MAIN_ODDR_1: ODDRXD1 port map( SCLK => nx_main_clk, DA => '1', @@ -875,13 +877,36 @@ begin Q => NX1_MAIN_CLK_OUT ); - THE_250M_ODDR_2: ODDRXD1 + THE_NX_MAIN_ODDR_2: ODDRXD1 port map( SCLK => nx_main_clk, DA => '1', DB => '0', Q => NX2_MAIN_CLK_OUT ); + + --NX1_MAIN_CLK_OUT <= nx_main_clk; + --NX2_MAIN_CLK_OUT <= nx_main_clk; + + -- -- ADC Sample Clocks + -- THE_ADC_SAMPLE_ODDR_1: ODDRXD1 + -- port map( + -- SCLK => nx1_adc_sample_clk, + -- DA => '1', + -- DB => '0', + -- Q => NX1_ADC_SAMPLE_CLK_OUT + -- ); + -- + -- THE_ADC_SAMPLE_ODDR_2: ODDRXD1 + -- port map( + -- SCLK => nx2_adc_sample_clk, + -- DA => '1', + -- DB => '0', + -- Q => NX2_ADC_SAMPLE_CLK_OUT + -- ); + + NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk; + NX2_ADC_SAMPLE_CLK_OUT <= nx2_adc_sample_clk; -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be -- based on same ClockSource as nXyter Main Clock) @@ -899,17 +924,4 @@ begin LOCK => pll_adc_clk_lock_2 ); - -- ADC Sample Clocks - NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk; - NX2_ADC_SAMPLE_CLK_OUT <= nx2_adc_sample_clk; - ---------------------------------------------------------------------------- --- Test Connector - Logic Analyser ---------------------------------------------------------------------------- - - -- TEST_LINE(0) <= clk_100_i; - -- TEST_LINE(1) <= NX1_DATA_CLK_IN; - -- TEST_LINE(15 downto 2) <= (others => '0'); - - end architecture;