From: Jan Michel Date: Thu, 30 Jun 2022 20:09:07 +0000 (+0200) Subject: add bug fix for read signal in slow control interface in GbE X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f6cfb511570e5982f044d5e33358bab81e15d332;p=trbnet.git add bug fix for read signal in slow control interface in GbE --- diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd index 467ceaf..3c7306c 100644 --- a/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd @@ -312,7 +312,7 @@ GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0); ------ TODO: change it to synchronous GSC_INIT_PACKET_NUM_OUT <= packet_num; GSC_INIT_DATAREADY_OUT <= gsc_init_dataready; -gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or +gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or --TODO Ob das so richtig ist, ohne auf fifo_rd zu schauen? (dissect_current_state = WAIT_FOR_HUB) else '0'; PACKET_NUM_PROC : process(CLK) @@ -320,7 +320,7 @@ begin if rising_edge(CLK) then if (dissect_current_state = IDLE) then packet_num <= "100"; - elsif (GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100") then + elsif (GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100" and dissect_current_state /= READ_FRAME) then --BUG zählt schon hoch beim fifo_rd weil read schon 1 ist. read geht aber nur auf 1 wenn dataready auf 1 ist packet_num <= "000"; elsif (rx_fifo_rd = '1' and packet_num /= "100") then packet_num <= packet_num + "1"; @@ -538,8 +538,10 @@ begin when READ_FRAME => state <= x"2"; - if (PS_DATA_IN(8) = '1') then + if (PS_DATA_IN(8) = '1' and (GSC_INIT_READ_IN = '0')) then dissect_next_state <= WAIT_FOR_HUB; + elsif (PS_DATA_IN(8) = '1' and (GSC_INIT_READ_IN = '1')) then + dissect_next_state <= LOAD_TO_HUB; else dissect_next_state <= READ_FRAME; end if;