From: hadeshyp Date: Wed, 27 May 2009 14:44:41 +0000 (+0000) Subject: added trb2_control_endpoint X-Git-Tag: oldGBE~446 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f6d96fef2401a53c8c632a4906ef1204ab518e21;p=trbnet.git added trb2_control_endpoint --- diff --git a/special/trb2_control_endpoint_tlk.vhd b/special/trb2_control_endpoint_tlk.vhd new file mode 100644 index 0000000..0df7fee --- /dev/null +++ b/special/trb2_control_endpoint_tlk.vhd @@ -0,0 +1,364 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + + + + +entity trb2_control is + port( + VIRT_CLK : in std_logic; + RESET_VIRT : in std_logic; + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector(15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector(15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + SFP_LOS : in std_logic; + SFP_TX_DIS : out std_logic; + FS_PB : out std_logic_vector(17 downto 0); + FS_PC : inout std_logic_vector(17 downto 0); + ETRAX_IRQ : out std_logic; + DBAD : out std_logic; + DGOOD : out std_logic; + DINT : out std_logic; + DWAIT : out std_logic; + ADO_TTL : inout std_logic_vector(46 downto 0) + ); +end entity; + + +architecture trb2_control_arch of trb2_control is + + component trb_net16_med_tlk is + port ( + RESET : in std_logic; + CLK : in std_logic; + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector(15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector(15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + SFP_LOS : in std_logic; + SFP_TX_DIS : out std_logic; + MED_DATAREADY_IN : in std_logic; + MED_READ_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + STAT : out std_logic_vector (63 downto 0); + STAT_MONITOR : out std_logic_vector ( 100 downto 0); + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) + --connect STAT(0) to LED + ); + end component; +component trb_net_bridge_etrax_endpoint is + generic( + USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_NO,c_NO,c_NO,c_NO) + ); + port( + RESET : in std_logic; + CLK: in std_logic; + + CPU_READ: in STD_LOGIC; -- Read strobe + CPU_WRITE: in STD_LOGIC; -- Write strobe + CPU_DATA_OUT: out STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus + CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus + CPU_DATAREADY_OUT : out std_logic; + CPU_ADDRESS: in STD_LOGIC_VECTOR (15 downto 0); -- Adress lines for the given space + + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + + MED_ERROR_IN : in std_logic_vector(2 downto 0); + STAT : out std_logic_vector(31 downto 0); + STAT_ENDP : out std_logic_vector(31 downto 0); + STAT_API1 : out std_logic_vector(31 downto 0) + ); +end component; + + component etrax_interface is + generic( + STATUS_REGISTERS : integer := 4; + CONTROL_REGISTERS : integer := 4 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + --Connection to Etrax + ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0); + ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0); + ETRAX_BUS_BUSY : out std_logic; + ETRAX_IS_READY_TO_READ : out std_logic; + --Connection to internal FPGA logic (all addresses above 0x100) + INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); + INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); + INTERNAL_READ_OUT : out std_logic; + INTERNAL_WRITE_OUT : out std_logic; + INTERNAL_DATAREADY_IN : in std_logic; + INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0); + --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl) + FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0); + FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0); + --Reset FPGA via Etrax + EXTERNAL_RESET : out std_logic; + STAT : out std_logic_vector(7 downto 0) + ); + end component; + + component trb_net_onewire is + generic( + USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; + CLK_PERIOD : integer := 10 --clk period in ns + ); + port( + CLK : in std_logic; + RESET : in std_logic; + --connection to 1-wire interface + ONEWIRE : inout std_logic; + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + signal CLK : std_logic; + signal RESET : std_logic; + signal CLK_EN : std_logic; + signal counter: std_logic_vector(15 downto 0); + + signal TLK_STAT : std_logic_vector(63 downto 0); + + signal MED_DATAREADY_IN, MED_DATAREADY_OUT : std_logic; + signal MED_DATA_IN, MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal MED_PACKET_NUM_IN, MED_PACKET_NUM_OUT: std_logic_vector(2 downto 0); + signal MED_ERROR_IN : std_logic_vector(2 downto 0); + signal MED_READ_IN, MED_READ_OUT : std_logic; + + + signal buf_ADO_TTL : std_logic_vector(46 downto 0); + signal tmp : std_logic; + signal API_STAT_FIFO_TO_INT : std_logic_vector(31 downto 0); + signal RESET_CNT : std_logic_vector(1 downto 0); + + signal TEMP_OUT : std_logic_vector(11 downto 0); + + signal etrax_state : std_logic_vector(2 downto 0); + signal etrax_data_in, etrax_data_out : std_logic_vector(31 downto 0); + signal etrax_read : std_logic; + signal etrax_write : std_logic; + signal etrax_dataready : std_logic; + signal etrax_address : std_logic_vector(15 downto 0); + signal STAT_REGS : std_logic_vector(63 downto 0); + signal CTRL_REGS : std_logic_vector(31 downto 0); + signal APL_STAT : std_logic_vector(31 downto 0); + signal STAT_ENDP : std_logic_vector(31 downto 0); + signal STAT_API1 : std_logic_vector(31 downto 0); + signal MED_STAT_OP : std_logic_vector(15 downto 0); + signal EI_STAT : std_logic_vector(7 downto 0); + +begin + CLK <= VIRT_CLK; + + CLK_EN <= '1'; + ETRAX_IRQ <= '1'; + +--------------------------------------------------------------------- +--Reset +--------------------------------------------------------------------- + + process(CLK) + begin + if rising_edge(CLK) then + if RESET_VIRT = '0' then + RESET <= '1'; + RESET_CNT <= "00"; + else + RESET_CNT <= RESET_CNT + 1; + RESET <= '1'; + if RESET_CNT = "11" then + counter <= counter + 1; + RESET <= '0'; + RESET_CNT <= "11"; + end if; + end if; + end if; + end process; + + +--------------------------------------------------------------------- +--LED outputs +--------------------------------------------------------------------- + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + tmp <= '0'; + else + tmp <= (not TLK_STAT(7)) or tmp; + end if; + end if; + end process; + + DGOOD <= not TLK_STAT(0); + + DBAD <= not (TLK_STAT(36)); -- no error, but not ERROR_OK + DINT <= not (tmp ); --RX_ER and RX_DV; + DWAIT <= not (MED_PACKET_NUM_IN(1)); + +--------------------------------------------------------------------- +--Media Interface: Optical Link +--------------------------------------------------------------------- + + TLK : trb_net16_med_tlk + port map( + RESET => RESET, + CLK => CLK, + TLK_CLK => TLK_CLK, + TLK_ENABLE => TLK_ENABLE, + TLK_LCKREFN => TLK_LCKREFN, + TLK_LOOPEN => TLK_LOOPEN, + TLK_PRBSEN => TLK_PRBSEN, + TLK_RXD => TLK_RXD, + TLK_RX_CLK => TLK_RX_CLK, + TLK_RX_DV => TLK_RX_DV, + TLK_RX_ER => TLK_RX_ER, + TLK_TXD => TLK_TXD, + TLK_TX_EN => TLK_TX_EN, + TLK_TX_ER => TLK_TX_ER, + SFP_LOS => SFP_LOS, + SFP_TX_DIS => SFP_TX_DIS, + MED_DATAREADY_IN => MED_DATAREADY_OUT, + MED_READ_IN => MED_READ_OUT, + MED_DATA_IN => MED_DATA_OUT, + MED_PACKET_NUM_IN => MED_PACKET_NUM_OUT, + MED_DATAREADY_OUT => MED_DATAREADY_IN, + MED_READ_OUT => MED_READ_IN, + MED_DATA_OUT => MED_DATA_IN, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN, + STAT => TLK_STAT, + STAT_OP => MED_STAT_OP, + CTRL_OP => MED_STAT_OP + ); + + MED_ERROR_IN <= MED_STAT_OP(2 downto 0); + +--------------------------------------------------------------------- +--The Endpoint generating the connection to etrax-read/write/able registers +--------------------------------------------------------------------- + + bridge: trb_net_bridge_etrax_endpoint + generic map( + AUTO_ANSWER_INCOMING_REQUESTS => (c_YES,c_YES,c_YES,c_YES) + ) + port map( + RESET => RESET, + CLK => CLK, + + CPU_READ => etrax_read, + CPU_WRITE => etrax_write, + CPU_DATA_OUT => etrax_data_out, + CPU_DATA_IN => etrax_data_in, + CPU_DATAREADY_OUT=> etrax_dataready, + CPU_ADDRESS => etrax_address, + + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN=> MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + + MED_ERROR_IN => MED_ERROR_IN, + STAT => APL_STAT, + STAT_ENDP => STAT_ENDP, + STAT_API1 => STAT_API1 + ); + + +--------------------------------------------------------------------- +--Interface to Etrax (trbcmd-compatible) +--------------------------------------------------------------------- + THE_ETRAX_INTERFACE_LOGIC : etrax_interface + generic map( + STATUS_REGISTERS => 2, + CONTROL_REGISTERS => 1 + ) + port map ( + CLK => CLK, + RESET => RESET, + ETRAX_DATA_BUS_B => FS_PB, + ETRAX_DATA_BUS_C => FS_PC, + ETRAX_BUS_BUSY => etrax_state(0), + ETRAX_IS_READY_TO_READ => etrax_state(1), + INTERNAL_DATA_OUT => etrax_data_in, + INTERNAL_DATA_IN => etrax_data_out, + INTERNAL_READ_OUT => etrax_read, + INTERNAL_WRITE_OUT => etrax_write, + INTERNAL_DATAREADY_IN => etrax_dataready, + INTERNAL_ADDRESS_OUT => etrax_address, + FPGA_REGISTER_IN => STAT_REGS, + FPGA_REGISTER_OUT => CTRL_REGS, + EXTERNAL_RESET => etrax_state(2), + STAT => EI_STAT + ); + +--------------------------------------------------------------------- +--Debugging Outputs +--------------------------------------------------------------------- + STAT_REGS(63 downto 0) <= APL_STAT & STAT_ENDP; + + buf_ADO_TTL(0) <= etrax_read; + buf_ADO_TTL(6 downto 1) <= EI_STAT(5 downto 0); + buf_ADO_TTL(14 downto 7) <= (others => 'Z'); + buf_ADO_TTL(46 downto 16) <= (others => 'Z'); + + PROC_LA_CLK : process(CLK) + begin + if rising_edge(CLK) then + buf_ADO_TTL(15) <= not buf_ADO_TTL(15); + end if; + end process; + +-- D2D3: 31 downto 16 +-- A0A1: 46 downto 32 + + ADO_TTL(46 downto 0) <= buf_ADO_TTL(46 downto 0); + +end architecture; diff --git a/special/trb_net_bridge_etrax_endpoint.vhd b/special/trb_net_bridge_etrax_endpoint.vhd index 63db4a6..3c43d39 100644 --- a/special/trb_net_bridge_etrax_endpoint.vhd +++ b/special/trb_net_bridge_etrax_endpoint.vhd @@ -7,6 +7,10 @@ library work; use work.trb_net_std.all; entity trb_net_bridge_etrax_endpoint is + generic( + USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_NO,c_NO,c_NO,c_NO) + ); port( RESET : in std_logic; CLK: in std_logic; @@ -38,6 +42,30 @@ end entity; architecture trb_net_bridge_etrax_endpoint_arch of trb_net_bridge_etrax_endpoint is + component trb_net16_term_buf is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic + ); + end component; + component trb_net16_io_multiplexer is port( -- Misc @@ -344,175 +372,294 @@ begin ); gen_iobufs : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate - IOBUF: trb_net16_iobuf - port map ( - -- Misc - CLK => CLK , - RESET => RESET_i, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), - MED_INIT_READ_IN => m_READ_IN(i*2), - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), - MED_REPLY_READ_IN => m_READ_IN(i*2+1), - MED_DATAREADY_IN => m_DATAREADY_IN(i), - MED_DATA_IN => m_DATA_IN(c_DATA_WIDTH-1 downto 0), - MED_PACKET_NUM_IN => m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), - MED_READ_OUT => m_READ_OUT(i), - MED_ERROR_IN => MED_ERROR_IN, - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), - INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), - INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), - INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), - INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), - INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), - INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), - INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), - -- Status and control port - STAT_GEN => STAT_GEN((i+1)*32-1 downto i*32), - STAT_IBUF_BUFFER => STAT_INIT_BUFFER((i+1)*32-1 downto i*32), - CTRL_GEN => CTRL_GEN((i+1)*32-1 downto i*32) - ); - end generate; - - CTRL_GEN <= (others => '0'); - - gen_pas_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate - DAT_PASSIVE_API: trb_net16_api_base - generic map ( - API_TYPE => c_API_PASSIVE, - FIFO_TO_INT_DEPTH => c_FIFO_BRAM, - FIFO_TO_APL_DEPTH => c_FIFO_BRAM, - FORCE_REPLY => cfg_FORCE_REPLY(i), - SBUF_VERSION => 0, - USE_VENDOR_CORES => c_YES, - SECURE_MODE_TO_APL => c_YES, - SECURE_MODE_TO_INT => c_YES, - APL_WRITE_ALL_WORDS => c_YES, - BROADCAST_BITMASK => x"FF" - ) + gen_used_channel : if USE_CHANNELS(i) = c_YES generate + IOBUF: trb_net16_iobuf port map ( -- Misc - CLK => CLK, - RESET => RESET_i, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), - APL_DATAREADY_IN => APL_DATAREADY_IN(2*i), - APL_READ_OUT => APL_READ_OUT(2*i), - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i), - APL_DTYPE_IN => APL_DTYPE_IN((2*i+1)*4-1 downto 2*i*4), - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+1)*32-1 downto 2*i*32), - APL_SEND_IN => APL_SEND_IN(2*i), - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+1)*16-1 downto 2*i*16), - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), - APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), - APL_TYP_OUT => APL_TYP_OUT((2*i+1)*3-1 downto 2*i*3), - APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i), - APL_READ_IN => APL_READ_IN(2*i), - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT(2*i), - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_LENGTH_IN => x"FFFF", - APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+1)*8-1 downto 2*i*8), + CLK => CLK , + RESET => RESET_i, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + MED_DATAREADY_IN => m_DATAREADY_IN(i), + MED_DATA_IN => m_DATA_IN(c_DATA_WIDTH-1 downto 0), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), + MED_READ_OUT => m_READ_OUT(i), + MED_ERROR_IN => MED_ERROR_IN, -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), - INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i), - INT_MASTER_DATAREADY_IN => '0', - INT_MASTER_DATA_IN => (others => '0'), - INT_MASTER_PACKET_NUM_IN => (others => '0'), - INT_MASTER_READ_OUT => open, - INT_SLAVE_DATAREADY_OUT => open, - INT_SLAVE_DATA_OUT => open, - INT_SLAVE_PACKET_NUM_OUT => open, - INT_SLAVE_READ_IN => '1', - INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), - INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), -- Status and control port - STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+1)*32-1 downto 2*i*32), - STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+1)*32-1 downto 2*i*32) + STAT_GEN => STAT_GEN((i+1)*32-1 downto i*32), + STAT_IBUF_BUFFER => STAT_INIT_BUFFER((i+1)*32-1 downto i*32), + CTRL_GEN => CTRL_GEN((i+1)*32-1 downto i*32) ); - end generate; - gen_act_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate - DAT_ACTIVE_API: trb_net16_api_base - generic map ( - API_TYPE => c_API_ACTIVE, - FIFO_TO_INT_DEPTH => c_FIFO_BRAM, - FIFO_TO_APL_DEPTH => c_FIFO_BRAM, - FORCE_REPLY => cfg_FORCE_REPLY(i), - SBUF_VERSION => 0, - USE_VENDOR_CORES => c_YES, - SECURE_MODE_TO_APL => c_YES, - SECURE_MODE_TO_INT => c_YES, - APL_WRITE_ALL_WORDS => c_YES, - BROADCAST_BITMASK => x"FF" - ) - port map ( - -- Misc + end generate; + gen_not_used_channel : if USE_CHANNELS(i) = c_NO generate + apl_to_buf_INIT_READ(i) <= '0'; + apl_to_buf_INIT_DATAREADY(i) <= '0'; + apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + apl_to_buf_REPLY_DATAREADY(i) <= '0'; + apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + apl_to_buf_REPLY_READ(i) <= '0'; + apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_to_apl_INIT_READ(i) <= '0'; + buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + buf_to_apl_INIT_DATAREADY(i) <= '0'; + buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_to_apl_REPLY_DATAREADY(i) <= '0'; + buf_to_apl_REPLY_READ(i) <= '0'; + buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + CTRL_GEN((i+1)*32-1 downto i*32) <= (others => '0'); + STAT_GEN((i+1)*32-1 downto i*32) <= (others => '0'); + STAT_INIT_BUFFER((i+1)*32-1 downto i*32) <= (others => '0'); + + termbuf: trb_net16_term_buf + port map( CLK => CLK, - RESET => RESET_i, + RESET => RESET, CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), - APL_DATAREADY_IN => APL_DATAREADY_IN(2*i+1), - APL_READ_OUT => APL_READ_OUT(2*i+1), - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i+1), - APL_DTYPE_IN => APL_DTYPE_IN((2*i+2)*4-1 downto (2*i+1)*4), - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+2)*32-1 downto (2*i+1)*32), - APL_SEND_IN => APL_SEND_IN(2*i+1), - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+2)*16-1 downto (2*i+1)*16), - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), - APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), - APL_TYP_OUT => APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3), - APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i+1), - APL_READ_IN => APL_READ_IN(2*i+1), - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT(2*i+1), - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_LENGTH_IN => x"FFFF", - APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8), - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), - INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), - INT_MASTER_DATAREADY_IN => '0', - INT_MASTER_DATA_IN => (others => '0'), - INT_MASTER_PACKET_NUM_IN => (others => '0'), - INT_MASTER_READ_OUT => open, - INT_SLAVE_DATAREADY_OUT => open, - INT_SLAVE_DATA_OUT => open, - INT_SLAVE_PACKET_NUM_OUT => open, - INT_SLAVE_READ_IN => '1', - INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), - INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), - -- Status and control port - STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32), - STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) + MED_DATAREADY_IN => m_DATAREADY_IN(i), + MED_DATA_IN => m_DATA_IN, + MED_PACKET_NUM_IN => m_PACKET_NUM_IN, + MED_READ_OUT => m_READ_OUT(i), + + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => m_READ_IN(i*2+1) ); + end generate; + end generate; + + CTRL_GEN <= (others => '0'); + + gen_pas_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate + gen_used_api : if USE_CHANNELS(i) = c_YES generate + gen_passive_api : if AUTO_ANSWER_INCOMING_REQUESTS(i) = c_NO generate + DAT_PASSIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_PASSIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i), + APL_READ_OUT => APL_READ_OUT(2*i), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+1)*4-1 downto 2*i*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+1)*32-1 downto 2*i*32), + APL_SEND_IN => APL_SEND_IN(2*i), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+1)*16-1 downto 2*i*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+1)*3-1 downto 2*i*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i), + APL_READ_IN => APL_READ_IN(2*i), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_LENGTH_IN => x"FFFF", + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+1)*8-1 downto 2*i*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i), + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+1)*32-1 downto 2*i*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+1)*32-1 downto 2*i*32) + ); + + DAT_ACTIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_ACTIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i+1), + APL_READ_OUT => APL_READ_OUT(2*i+1), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i+1), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+2)*4-1 downto (2*i+1)*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+2)*32-1 downto (2*i+1)*32), + APL_SEND_IN => APL_SEND_IN(2*i+1), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+2)*16-1 downto (2*i+1)*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i+1), + APL_READ_IN => APL_READ_IN(2*i+1), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i+1), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_LENGTH_IN => x"FFFF", + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) + ); + end generate; + gen_auto_answer : if AUTO_ANSWER_INCOMING_REQUESTS(i) = c_YES generate + DAT_ACTIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_ACTIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i+1), + APL_READ_OUT => APL_READ_OUT(2*i+1), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i+1), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+2)*4-1 downto (2*i+1)*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+2)*32-1 downto (2*i+1)*32), + APL_SEND_IN => APL_SEND_IN(2*i+1), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+2)*16-1 downto (2*i+1)*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i+1), + APL_READ_IN => APL_READ_IN(2*i+1), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i+1), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_LENGTH_IN => x"FFFF", + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), + INT_MASTER_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), + INT_MASTER_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_OUT => apl_to_buf_REPLY_READ(i), + INT_SLAVE_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_IN => buf_to_apl_INIT_READ(i), + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) + ); + end generate; + end generate; + gen_no_api : if USE_CHANNELS(i) = c_NO generate + APL_READ_OUT(2*i+1) <= '1'; + APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH) <= (others => '0'); + APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH) <= (others => '0'); + APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3) <= (others => '0'); + APL_DATAREADY_OUT(2*i+1) <= '0'; + APL_RUN_OUT(2*i+1) <= '0'; + APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8) <= (others => '0'); + buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32) <= (others => '0'); + buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) <= (others => '0'); + end generate; end generate; APL : trb_net_bridge_etrax_apl