From: hadaq Date: Thu, 28 Jan 2010 10:26:09 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: v1.0~4 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f6f8058017f40bb7fc622673fdf807e0fd0f2e49;p=adcm.git *** empty log message *** --- diff --git a/ADCM_slave_bus.txt b/ADCM_slave_bus.txt new file mode 100755 index 0000000..5b7d5b7 --- /dev/null +++ b/ADCM_slave_bus.txt @@ -0,0 +1,355 @@ +Slave bus usage +=============== + +0x8000 - 0x8001 : test register + +0x8040 - 0x8040 X: I2C master for APV slow control + +0xa000 - 0xa07f : pedestal memory APV0 +0xa080 - 0xa0ff : pedestal memory APV1 +0xa100 - 0xa17f : pedestal memory APV2 +0xa180 - 0xa1ff : pedestal memory APV3 +0xa200 - 0xa27f : pedestal memory APV4 +0xa280 - 0xa2ff : pedestal memory APV5 +0xa300 - 0xa37f : pedestal memory APV6 +0xa380 - 0xa3ff : pedestal memory APV7 +0xa400 - 0xa47f : pedestal memory APV8 +0xa480 - 0xa4ff : pedestal memory APV9 +0xa500 - 0xa57f : pedestal memory APV10 +0xa580 - 0xa5ff : pedestal memory APV11 +0xa600 - 0xa67f : pedestal memory APV12 +0xa680 - 0xa6ff : pedestal memory APV13 +0xa700 - 0xa77f : pedestal memory APV14 +0xa780 - 0xa7ff : pedestal memory APV15 + +0xa800 - 0xa87f : threshold memory APV0 +0xa880 - 0xa8ff : threshold memory APV1 +0xa900 - 0xa97f : threshold memory APV2 +0xa980 - 0xa9ff : threshold memory APV3 +0xaa00 - 0xaa7f : threshold memory APV4 +0xaa80 - 0xaaff : threshold memory APV5 +0xab00 - 0xab7f : threshold memory APV6 +0xab80 - 0xabff : threshold memory APV7 +0xac00 - 0xac7f : threshold memory APV8 +0xac80 - 0xacff : threshold memory APV9 +0xad00 - 0xad7f : threshold memory APV10 +0xad80 - 0xadff : threshold memory APV11 +0xae00 - 0xae7f : threshold memory APV12 +0xae80 - 0xaeff : threshold memory APV13 +0xaf00 - 0xaf7f : threshold memory APV14 +0xaf80 - 0xafff : threshold memory APV15 + +0xb000 - 0xb00f X: APV control and status + +0xb010 - 0xb010 X: ADC level settings + +0xb020 - 0xb020 X: trigger settings + +0xb030 - 0xb030 X: PLL settings + +0xc000 - 0xc03f X: 1Wire master for APV and backplane + +0xd000 - 0xd001 X: SPI master for FlashROM + +0xd010 - 0xd010 X: ADC0 control and SPI + +0xd020 - 0xd020 X: ADC1 control and SPI + +0xd100 - 0xd03f X: SPI data memory (FlashROM) + +0xf000 - 0xf3ff : ADC 0 snooper + +0xf400 - 0xf7ff : ADC 1 snooper + + +========================================================================== +== Detailed description +========================================================================== + + +################################################################################# +# # +# SPI master for ADC slow control, ADC configuration bits, APV reset # +# # +################################################################################# + +0xd010 - 0xd010 : ADC0 control and SPI +0xd020 - 0xd020 : ADC0 control and SPI +--------------------------------------- + +D[31:24] SPI command +D[23:12] ADC channel 4 current data for testing +D[11:9] reserved +D[8] ADC PLL status 0 -> bad, 1 -> locked +D[7:4] ADC input delay (0x6 is standard) +D[3] SPI start 0 -> wait, 1 -> start +D[2] APV reset 0 -> normal, 1 -> reset +D[1] ADC power down 0 -> normal, 1 -> powerdown +D[0] ADC reset 0 -> normal, 1 -> reset + +This register is 32bit wide with full read/write access. +It controls a simple (one byte only) SPI master for configuring the ADC via SPI. +Besides it allows to reset the ADC, power it down and also reset the connected +APVs (eight modules). + +Take care not to change bits unintentionally when working with this register. +A read-modify-write sequence is mandatory. + + +SPI access to ADC is handled as following: + +(1) be sure that SPI start bit D[16] is zero +(2) read register and set D[31:24] to the command to be sent +(3) write back new value with SPI start bit set +(4) clear the SPI start bit + +The SPI hardware access is 25MHz based and will be over before next TRBnet access +to this register is possible. This SPI master can only transfer command to the ADC, +and not read back (due to ADC constraints). + + +Reset value of register is 0x00000060. + +################################################################################# +# # +# APV control and status register # +# # +################################################################################# + +0xb000 - 0xb00f : APV control and status +----------------------------------------- + +D[31] buffer good 1 -> APV switched on and sync'ed +D[30] buffer broken 1 -> APV switched on and off sync +D[29] buffer ignore 1 -> APV not used +D[28:24] number of events in buffer +D[23:20] reserved +D[19:16] hardware APV number before mapping([15:8] -> ADC1, [7:0] -> ADC0) +D[15:1] reserved +D[0] APV on 0 -> off, 1 -> on + +This register is divided into read only bits (D[31:16]) and read/write bits (D[15:0]). + +APV on bit (D[0]) is on by default. +D[31] (buffer good) will only be set if the APV is switched on and a SYNC trigger has +been sent. +To activate an APV it is mandatory to set APV on bit (D[0]) and send a SYNC trigger. + + +Reset value of register is 0xZZZZ0001 (Z depends on APV connections). + +################################################################################# +# # +# configuration register for ADC levels (bit recognition) # +# # +################################################################################# + +0xb010 - 0xb010 : ADC level settings +------------------------------------- + +D[31:24] bit high D[11:4] setting, D[3:0] is fixed to 0x0 +D[23:16] bit low D[11:4] setting, D[3:0] is fixed to 0x0 +D[15:8] flat high D[11:4] setting, D[3:0] is fixed to 0x0 +D[7:0] flat low D[11:4] setting, D[3:0] is fixed to 0x0 + +This register is 32bit wide with full read/write access. +It is used to configure the APV digital header reconstruction. The ADCs use 12bit, +with 0x000 as lowest value and 0xfff as highest value. There is no OutOfRange, UnderFlow +or OverFlow bit in the ADC. +"Flat low" and "Flat high" set the recognition limits for a missing ADC module: in this case +the ADC will deliver a flat line around 0x800. +"Bit low" is the upper limit for recognizing an ADC value as digital low bit. +"Bit high" is the lower limit for recognizing an ADC value as digital high bit. + +This register must be initialized correctly before sending any triggers to the APVs. + +Recommended setting is 0xd0208878 at time of this writing, giving +Flat Low = 0x780 +Flat High = 0x880 +Bit Low = 0x200 +Bit High = 0xd00 + + +Reset value of register is 0x00000000. + +################################################################################# +# # +# configuration register for triggers # +# # +################################################################################# + +0xb020 - 0xb020 : trigger settings +----------------------------------- + +D[31:28] TRG3 number of triggers +D[27:24] TRG3 delay +D[23:20] TRG2 number of triggers +D[19:16] TRG2 delay +D[15:12] TRG1 number of triggers +D[11:8] TRG1 delay +D[7:4] TRG0 number of triggers +D[3:0] TRG0 delay + +This register is 32bit wide with full read/write access. +It sets up the APV readout functionality (per external trigger input) + +For all four trigger inputs (external and slow control) the number of APV readout +triggers to be sent as well as the number of clock cycles between APV readout +triggers can be set up. + +It is not recommended to take more than 8 APV readout triggers per external trigger. + +Take care: the data format may change with setting up more than one APV readout trigger. + + +Reset value of register is 0x10101010. + + +################################################################################# +# # +# configuration register for PLLs # +# # +################################################################################# + +0xb030 - 0xb030 : PLL settings +------------------------------- + +D[31] 100MHZ DLL locked 0 -> bad, 1 -> locked +D[30] 40MHZ PLL locked 0 -> bad, 1 -> locked +D[29] ADC1 PLL locked 0 -> bad, 1 -> locked +D[28] ADC0 PLL locked 0 -> bad, 1 -> locked +D[27:24] reserved +D[23] reserved +D[22:20] sector ID as given by backplane switch +D[19] reserved +D[18:16] module ID as given by backplane switch +D[15:8] external trigger setup +-> D[15] EXT_IN[3] active +-> D[14] EXT_IN[2] active +-> D[13] EXT_IN[1] active +-> D[12] EXT_IN[0] active +-> D[11] invert external trigger 3 +-> D[10] invert external trigger 2 +-> D[9] invert external trigger 1 +-> D[8] invert external trigger 0 +D[7] 40MHz PLL reset +D[6] ADC1 PLL reset +D[5] ADC0 PLL reset +D[4] reserved +D[3:0] 40MHz clock phase setting + +This register is divided into read only bits (D[31:16]) and read/write bits (D[15:0]). +It configures the ADCM hardware resource: setup of FPGA internal PLLs, clock phase between +ADC and APV 40MHz clock and external trigger inputs. + +PLLs must not be in reset during normal operation. +Please note that after reset the PLLs may take some 100ms to be stable again. + +The clock phase shift between ADC and APV clock must be adjusted to accommodate +for delays on PCB and cables. It is mandatory to set this correctly to have the +ADCs sampling the analog signal returning from APVs at the right point in time. + +To activate external trigger inputs set the corresponding bit to 1. +If connected correctly to the CTS no signal inversion is needed. + +Reset value of register is 0x00000000. + +################################################################################# +# # +# 1Wire master for APVs and backplane # +# # +################################################################################# + +0xc000 - 0xc03f : 1Wire master for APV and backplane +----------------------------------------------------- + +Writing the offset 0xc000 with any value starts one full 1Wire action. +This takes about 1.0s - there is no busy locking for reading the memory. + +offset 0: lower 32bit of serial number +offset 1: upper 32bit of serial number +offset 2: D[15] 0 -> no 1Wire found, 1 -> 1Wire found + D[11:0] temperature of 1Wire IC +offset 3: reserved + + +################################################################################# +# # +# SPI master for FlashROM access # +# # +################################################################################# + +0xd000 - 0xd001 : SPI master for FlashROM +------------------------------------------ + +0xd000: SPI control register + +D[31:24] SPI command +D[23:16] address byte high (A[23:16]) +D[15:8] address byte mid (A[15:8]) +D[7:0] address byte low (A[7:0]) + +Full read/write access; writing this register starts the SPI hardware access. +This register is busy locked. + +Reset value of register is 0x00000000. + + +0xd001: SPI status register + +D[31:24] number of data words to be transfered (0x00 -> 1, 0xff -> 256) +D[23:8] reserved +D[7:0] debug information (state machine bits) + +This register is divided into read only bits (D[7:0]) and read/write bits (D[31:24]). + +Reset value of register is 0x00000000. + + +0xd100 - 0xd03f : SPI data memory (FlashROM) +--------------------------------------------- + +Memory bank for read / write data in SPI transfer. This memory block is not busy locked. + +D[7:0] first byte +D[15:8] second byte +D[23:16] third byte +D[31:24] fourth byte +.... + + +################################################################################# +# # +# I2C master for APV slowcontrol access # +# # +################################################################################# + +0x8040 - 0x8040 : I2C master for APV slow control +-------------------------------------------------- + +This I2C master is tailor made for APV25S1 ASICs. + + write access +D[31] I2C start bit +D[30] I2C ??? +D[29:24] I2C speed +D[23:16] I2C address +D[15:8] I2C command +D[7:0] I2C write data + + read access +D[31:24] status bits +-> D[31] "running" or "busy" bit +-> D[30] "access done" bit +-> D[29] "e_ranak" -> I2C repeated address NAK +-> D[28] "e_rsf" -> error generating repeated start condition +-> D[27] "e_dnak" -> I2C data NAK +-> D[26] "e_cnak" -> I2C command NAK +-> D[25] "e_anak" -> I2C address NAK +-> D[24] "e_sf" -> error generating start condition +D[23:21] reserved +D[20:16] debug +D[15:8] reserved +D[7:0] I2C read data + + diff --git a/lookup_adc.txt b/lookup_adc.txt new file mode 100755 index 0000000..b07211d --- /dev/null +++ b/lookup_adc.txt @@ -0,0 +1,119 @@ +Backplane 0 +=========== + +ADC0/0 0 0/6 3 0xb000 0x20030001 +ADC0/1 1 0/7 5 0xb001 0x20050001 +ADC0/2 2 0/0 10 0xb002 0x200a0001 +ADC0/3 3 0/2 12 0xb003 0x200c0001 +ADC0/4 4 0/1 9 0xb004 0x20090001 +ADC0/5 5 0/3 7 0xb005 0x20070001 +ADC0/6 6 0/5 0 0xb006 0x20000001 +ADC0/7 7 -/- -- 0xb007 0x200f0001 + +ADC1/0 8 1/6 4 0xb008 0x20040001 +ADC1/1 9 1/7 6 0xb009 0x20060001 +ADC1/2 10 1/1 11 0xb00a 0x200b0001 +ADC1/3 11 1/0 8 0xb00b 0x20080001 +ADC1/4 12 1/3 14 0xb00c 0x200e0001 +ADC1/5 13 1/2 13 0xb00d 0x200d0001 +ADC1/6 14 1/5 2 0xb00e 0x20020001 +ADC1/7 15 1/4 1 0xb00f 0x20010001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1 + +Backplane 1 +========== + +ADC0/0 0 0/6 12 0xb000 0x200c0001 +ADC0/1 1 0/7 11 0xb001 0x200b0001 +ADC0/2 2 0/0 10 0xb002 0x200a0001 +ADC0/3 3 0/2 9 0xb003 0x20090001 +ADC0/4 4 0/1 8 0xb004 0x20080001 +ADC0/5 5 0/3 7 0xb005 0x20070001 +ADC0/6 6 0/5 13 0xb006 0x200d0001 +ADC0/7 7 0/4 14 0xb007 0x200e0001 + +ADC1/0 8 1/6 3 0xb008 0x20030001 +ADC1/1 9 1/7 2 0xb009 0x20020001 +ADC1/2 10 1/1 1 0xb00a 0x20010001 +ADC1/3 11 1/0 0 0xb00b 0x20000001 +ADC1/4 12 1/3 6 0xb00c 0x20060001 +ADC1/5 13 1/2 5 0xb00d 0x20050001 +ADC1/6 14 1/5 4 0xb00e 0x20040001 +ADC1/7 15 -/- -- 0xb00f 0x200f0001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 - + +Backplane 2 +=========== + +ADC0/0 0 -/- -- 0xb000 0x200f0001 +ADC0/1 1 0/7 4 0xb001 0x20040001 +ADC0/2 2 0/0 5 0xb002 0x20050001 +ADC0/3 3 0/2 6 0xb003 0x20060001 +ADC0/4 4 0/1 0 0xb004 0x20000001 +ADC0/5 5 0/3 1 0xb005 0x20010001 +ADC0/6 6 0/5 2 0xb006 0x20020001 +ADC0/7 7 0/4 3 0xb007 0x20030001 + +ADC1/0 8 1/6 14 0xb008 0x200e0001 +ADC1/1 9 1/7 13 0xb009 0x200d0001 +ADC1/2 10 1/1 7 0xb00a 0x20070001 +ADC1/3 11 1/0 8 0xb00b 0x20080001 +ADC1/4 12 1/3 9 0xb00c 0x20090001 +ADC1/5 13 1/2 10 0xb00d 0x200a0001 +ADC1/6 14 1/5 11 0xb00e 0x200b0001 +ADC1/7 15 1/4 12 0xb00f 0x200c0001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12 + +Backplane 3 +=========== + +ADC0/0 0 0/6 10 0xb000 0x200a0001 +ADC0/1 1 0/7 9 0xb001 0x20090001 +ADC0/2 2 0/0 8 0xb002 0x20080001 +ADC0/3 3 0/2 7 0xb003 0x20070001 +ADC0/4 4 0/1 6 0xb004 0x20060001 +ADC0/5 5 0/3 5 0xb005 0x20050001 +ADC0/6 6 0/5 12 0xb006 0x200c0001 +ADC0/7 7 0/4 11 0xb007 0x200b0001 + +ADC1/0 8 1/6 4 0xb008 0x20040001 +ADC1/1 9 1/7 3 0xb009 0x20030001 +ADC1/2 10 1/1 0 0xb00a 0x20000001 +ADC1/3 11 1/0 2 0xb00b 0x20020001 +ADC1/4 12 1/3 1 0xb00c 0x20010001 +ADC1/5 13 -/- -- 0xb00d 0x200f0001 +ADC1/6 14 1/5 13 0xb00e 0x200d0001 +ADC1/7 15 1/4 14 0xb00f 0x200e0001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14 + +Backplane 4 +=========== + +ADC0/0 0 0/6 14 0xb000 0x200e0001 +ADC0/1 1 0/7 13 0xb001 0x200d0001 +ADC0/2 2 -/- -- 0xb002 0x200f0001 +ADC0/3 3 0/2 1 0xb003 0x20010001 +ADC0/4 4 0/1 2 0xb004 0x20020001 +ADC0/5 5 0/3 0 0xb005 0x20000001 +ADC0/6 6 0/5 3 0xb006 0x20030001 +ADC0/7 7 0/4 4 0xb007 0x20040001 + +ADC1/0 8 1/6 11 0xb008 0x200b0001 +ADC1/1 9 1/7 12 0xb009 0x200c0001 +ADC1/2 10 1/1 5 0xb00a 0x20050001 +ADC1/3 11 1/0 6 0xb00b 0x20060001 +ADC1/4 12 1/3 7 0xb00c 0x20070001 +ADC1/5 13 1/2 8 0xb00d 0x20080001 +ADC1/6 14 1/5 9 0xb00e 0x20090001 +ADC1/7 15 1/4 10 0xb00f 0x200a0001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10 diff --git a/src/adc_apv_map_mem.lpc b/src/adc_apv_map_mem.lpc new file mode 100644 index 0000000..b5c3e13 --- /dev/null +++ b/src/adc_apv_map_mem.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_ROM +CoreRevision=2.4 +ModuleName=adc_apv_map_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/04/2009 +Time=16:11:12 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=128 +Data=4 +LUT=0 +MemFile=i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem +MemFormat=orca diff --git a/src/adc_apv_map_mem.srp b/src/adc_apv_map_mem.srp new file mode 100644 index 0000000..c4a1fc4 --- /dev/null +++ b/src/adc_apv_map_mem.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Nov 04 16:11:12 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e + Circuit name : adc_apv_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem + EDIF output : suppressed + VHDL output : adc_apv_map_mem.vhd + VHDL template : adc_apv_map_mem_tmpl.vhd + VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_apv_map_mem.srp + Element Usage : + ROM128X1 : 4 + Estimated Resource Usage: + LUT : 16 diff --git a/src/adc_apv_map_mem.vhd b/src/adc_apv_map_mem.vhd new file mode 100644 index 0000000..b301f1b --- /dev/null +++ b/src/adc_apv_map_mem.vhd @@ -0,0 +1,81 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 7 -num_rows 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e + +-- Wed Nov 04 16:11:12 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity adc_apv_map_mem is + port ( + Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end adc_apv_map_mem; + +architecture Structure of adc_apv_map_mem is + + -- local component declarations + component ROM128X1 + -- synopsys translate_off + generic (INITVAL : in String); + -- synopsys translate_on + port (AD6: in std_logic; AD5: in std_logic; AD4: in std_logic; + AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + attribute initval : string; + attribute initval of mem_0_3 : label is "0xFF00FF00FF00E307E0C7FB0180DF3C9C"; + attribute initval of mem_0_2 : label is "0xF0F0F0F0F0F01E87E178870FF0E133AA"; + attribute initval of mem_0_1 : label is "0xCCCCCCCCCCCC9955AA9965C993A656A5"; + attribute initval of mem_0_0 : label is "0xAAAAAAAAAAAA554E72AA56A5A56AA4B3"; + +begin + -- component instantiation statements + mem_0_3: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xFF00FF00FF00E307E0C7FB0180DF3C9C") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(3)); + + mem_0_2: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xF0F0F0F0F0F01E87E178870FF0E133AA") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(2)); + + mem_0_1: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xCCCCCCCCCCCC9955AA9965C993A656A5") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(1)); + + mem_0_0: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xAAAAAAAAAAAA554E72AA56A5A56AA4B3") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(0)); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of adc_apv_map_mem is + for Structure + for all:ROM128X1 use entity ecp2m.ROM128X1(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/adc_apv_map_mem_generate.log b/src/adc_apv_map_mem_generate.log new file mode 100644 index 0000000..e7ce86b --- /dev/null +++ b/src/adc_apv_map_mem_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Nov 04 16:11:12 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e + Circuit name : adc_apv_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Data width : 4 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem + EDIF output : suppressed + VHDL output : adc_apv_map_mem.vhd + VHDL template : adc_apv_map_mem_tmpl.vhd + VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_apv_map_mem.srp + Estimated Resource Usage: + LUT : 16 + +END SCUBA Module Synthesis + +File: ..\src\adc_apv_map_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/adc_apv_map_mem_tmpl.vhd b/src/adc_apv_map_mem_tmpl.vhd new file mode 100644 index 0000000..0386612 --- /dev/null +++ b/src/adc_apv_map_mem_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Wed Nov 04 16:11:12 2009 + +-- parameterized module component declaration +component adc_apv_map_mem + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : adc_apv_map_mem + port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/src/adc_apv_mapping.mem b/src/adc_apv_mapping.mem new file mode 100644 index 0000000..af89bc5 --- /dev/null +++ b/src/adc_apv_mapping.mem @@ -0,0 +1,152 @@ +#Format=Address-Hex +#Depth=128 +#DataWidth=4 +#AddrRadix=3 +#DataRadix=3 + +# Backplane 0 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1 +00: 3 +01: 5 +02: a +03: c +04: 9 +05: 7 +06: 0 +07: f +08: 4 +09: 6 +0a: b +0b: 8 +0c: e +0d: d +0e: 2 +0f: 1 +# Backplane 1 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 - +10: c +11: b +12: a +13: 9 +14: 8 +15: 7 +16: d +17: e +18: 3 +19: 2 +1a: 1 +1b: 0 +1c: 6 +1d: 5 +1e: 4 +1f: f +# Backplane 2 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12 +20: f +21: 4 +22: 5 +23: 6 +24: 0 +25: 1 +26: 2 +27: 3 +28: e +29: d +2a: 7 +2b: 8 +2c: 9 +2d: a +2e: b +2f: c +# Backplane 3 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14 +30: a +31: 9 +32: 8 +33: 7 +34: 6 +35: 5 +36: c +37: b +38: 4 +39: 3 +3a: 0 +3b: 2 +3c: 1 +3d: f +3e: d +3f: e +# Backplane 4 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10 +40: e +41: d +42: f +43: 1 +44: 2 +45: 0 +46: 3 +47: 4 +48: b +49: c +4a: 5 +4b: 6 +4c: 7 +4d: 8 +4e: 9 +4f: a +# unused (5) => 1:1 +50: 0 +51: 1 +52: 2 +53: 3 +54: 4 +55: 5 +56: 6 +57: 7 +58: 8 +59: 9 +5a: a +5b: b +5c: c +5d: d +5e: e +5f: f +# unused (6) => 1:1 +60: 0 +61: 1 +62: 2 +63: 3 +64: 4 +65: 5 +66: 6 +67: 7 +68: 8 +69: 9 +6a: a +6b: b +6c: c +6d: d +6e: e +6f: f +# unused (7) => 1:1 +70: 0 +71: 1 +72: 2 +73: 3 +74: 4 +75: 5 +76: 6 +77: 7 +78: 8 +79: 9 +7a: a +7b: b +7c: c +7d: d +7e: e +7f: f diff --git a/src/adc_ch_in.lpc b/src/adc_ch_in.lpc new file mode 100644 index 0000000..b256dd4 --- /dev/null +++ b/src/adc_ch_in.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=3.6 +ModuleName=adc_ch_in +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/24/2009 +Time=11:41:10 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Input +width=1 +reg=DDR +gear=1x +rst=Edge +del=Dynamic +cdel=0 +fdel=0 +cdiv=1 +clk1x=0 +clk2x=0 +ail=0 +step=2 +ckedge=1 +swap=Off +bf=Off +AilAW=400 +val=0 diff --git a/src/adc_ch_in.srp b/src/adc_ch_in.srp new file mode 100644 index 0000000..e3fea71 --- /dev/null +++ b/src/adc_ch_in.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Apr 24 11:41:10 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_ch_in -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type iol -mode in -width 1 -gear 1 -del 16 -e + Circuit name : adc_ch_in + Module type : iol + Module Version : 3.6 + Ports : + Inputs : Del[3:0], ECLK, SCLK, Rst, Data[0:0] + Outputs : Q[1:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : adc_ch_in.vhd + VHDL template : adc_ch_in_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_ch_in.srp + Element Usage : + IB : 1 + IDDRFXA : 1 + DELAYB : 1 + Estimated Resource Usage: diff --git a/src/adc_ch_in.vhd b/src/adc_ch_in.vhd new file mode 100644 index 0000000..a041076 --- /dev/null +++ b/src/adc_ch_in.vhd @@ -0,0 +1,81 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 3.6 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_ch_in -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type iol -mode in -width 1 -gear 1 -del 16 -e + +-- Fri Apr 24 11:41:10 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity adc_ch_in is + port ( + Del: in std_logic_vector(3 downto 0); + ECLK: in std_logic; + SCLK: in std_logic; + Rst: in std_logic; + Data: in std_logic_vector(0 downto 0); + Q: out std_logic_vector(1 downto 0)); + attribute dont_touch : string; + attribute dont_touch of adc_ch_in : entity is "true"; +end adc_ch_in; + +architecture Structure of adc_ch_in is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal Data_t0: std_logic; + signal buf_Data0: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component IB + port (I: in std_logic; O: out std_logic); + end component; + component IDDRFXA + port (D: in std_logic; CLK1: in std_logic; CLK2: in std_logic; + CE: in std_logic; RST: in std_logic; QA: out std_logic; + QB: out std_logic); + end component; + component DELAYB + port (A: in std_logic; DEL0: in std_logic; DEL1: in std_logic; + DEL2: in std_logic; DEL3: in std_logic; Z: out std_logic); + end component; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + ud_0: IDDRFXA + port map (D=>Data_t0, CLK1=>ECLK, CLK2=>SCLK, CE=>scuba_vhi, + RST=>Rst, QA=>Q(0), QB=>Q(1)); + + udel_0: DELAYB + port map (A=>buf_Data0, DEL0=>Del(0), DEL1=>Del(1), DEL2=>Del(2), + DEL3=>Del(3), Z=>Data_t0); + + buf_Data0_in_inst: IB + port map (I=>Data(0), O=>buf_Data0); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of adc_ch_in is + for Structure + for all:VHI use entity ecp2m.VHI(V); end for; + for all:IB use entity ecp2m.IB(V); end for; + for all:IDDRFXA use entity ecp2m.IDDRFXA(V); end for; + for all:DELAYB use entity ecp2m.DELAYB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/adc_ch_in_tmpl.vhd b/src/adc_ch_in_tmpl.vhd new file mode 100644 index 0000000..fc15c1b --- /dev/null +++ b/src/adc_ch_in_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 3.6 +-- Fri Apr 24 11:41:10 2009 + +-- parameterized module component declaration +component adc_ch_in + port (Del: in std_logic_vector(3 downto 0); ECLK: in std_logic; + SCLK: in std_logic; Rst: in std_logic; + Data: in std_logic_vector(0 downto 0); + Q: out std_logic_vector(1 downto 0)); +end component; + +-- parameterized module component instance +__ : adc_ch_in + port map (Del(3 downto 0)=>__, ECLK=>__, SCLK=>__, Rst=>__, Data(0 downto 0)=>__, + Q(1 downto 0)=>__); diff --git a/src/adc_channel_select.vhd b/src/adc_channel_select.vhd new file mode 100644 index 0000000..20e653b --- /dev/null +++ b/src/adc_channel_select.vhd @@ -0,0 +1,98 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity adc_channel_select is + port( RESET_IN : in std_logic; + ADC_CLK_IN : in std_logic; + ADC_SEL_IN : in std_logic_vector(2 downto 0); + ADC_7_IN : in std_logic_vector(11 downto 0); + ADC_6_IN : in std_logic_vector(11 downto 0); + ADC_5_IN : in std_logic_vector(11 downto 0); + ADC_4_IN : in std_logic_vector(11 downto 0); + ADC_3_IN : in std_logic_vector(11 downto 0); + ADC_2_IN : in std_logic_vector(11 downto 0); + ADC_1_IN : in std_logic_vector(11 downto 0); + ADC_0_IN : in std_logic_vector(11 downto 0); + ADC_CH_OUT : out std_logic_vector(11 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of adc_channel_select is + + -- Placer Directives + + -- normal signals + signal adc_ch : std_logic_vector(11 downto 0); + signal adc_sel : std_logic_vector(2 downto 0); + signal reset : std_logic; + + signal debug : std_logic_vector(15 downto 0); + + +begin + +-- Reset synchronizer +THE_RESET_SYNC: state_sync +port map( STATE_A_IN => reset_in, + CLK_B_IN => adc_clk_in, + RESET_B_IN => '0', + STATE_B_OUT => reset + ); + +-- select signals are from 100MHz clock domain! +THE_SEL2_SYNC: state_sync +port map( STATE_A_IN => adc_sel_in(2), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => adc_sel(2) + ); +THE_SEL1_SYNC: state_sync +port map( STATE_A_IN => adc_sel_in(1), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => adc_sel(1) + ); +THE_SEL0_SYNC: state_sync +port map( STATE_A_IN => adc_sel_in(0), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => adc_sel(0) + ); + + +-- registered multiplexer +THE_SEL_PROC: process( adc_clk_in ) +begin + if( rising_edge(adc_clk_in) ) then + if( reset = '1' ) then + adc_ch <= (others => '0'); + else + case adc_sel is + when b"000" => adc_ch <= adc_0_in; + when b"001" => adc_ch <= adc_1_in; + when b"010" => adc_ch <= adc_2_in; + when b"011" => adc_ch <= adc_3_in; + when b"100" => adc_ch <= adc_4_in; + when b"101" => adc_ch <= adc_5_in; + when b"110" => adc_ch <= adc_6_in; + when b"111" => adc_ch <= adc_7_in; + when others => adc_ch <= x"000"; -- never + end case; + end if; + end if; +end process THE_SEL_PROC; + +-- debug signals +debug(15 downto 0) <= (others => '0'); + +-- output signals +adc_ch_out <= adc_ch; +debug_out <= debug; + +end behavioral; diff --git a/src/adc_crossover.vhd b/src/adc_crossover.vhd new file mode 100644 index 0000000..870c990 --- /dev/null +++ b/src/adc_crossover.vhd @@ -0,0 +1,141 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity adc_crossover is + port( CLK_APV_IN : in std_logic; -- APV 40MHz local clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- ADC clock domain signals + ADC_CLK_IN : in std_logic; + ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse... + ADC_DATA_VALID_IN : in std_logic; + ADC_DATA_7_IN : in std_logic_vector(11 downto 0); + ADC_DATA_6_IN : in std_logic_vector(11 downto 0); + ADC_DATA_5_IN : in std_logic_vector(11 downto 0); + ADC_DATA_4_IN : in std_logic_vector(11 downto 0); + ADC_DATA_3_IN : in std_logic_vector(11 downto 0); + ADC_DATA_2_IN : in std_logic_vector(11 downto 0); + ADC_DATA_1_IN : in std_logic_vector(11 downto 0); + ADC_DATA_0_IN : in std_logic_vector(11 downto 0); + LEVEL_WR_OUT : out std_logic_vector(4 downto 0); + -- APV clock domain signals + APV_DATA_7_OUT : out std_logic_vector(11 downto 0); + APV_DATA_6_OUT : out std_logic_vector(11 downto 0); + APV_DATA_5_OUT : out std_logic_vector(11 downto 0); + APV_DATA_4_OUT : out std_logic_vector(11 downto 0); + APV_DATA_3_OUT : out std_logic_vector(11 downto 0); + APV_DATA_2_OUT : out std_logic_vector(11 downto 0); + APV_DATA_1_OUT : out std_logic_vector(11 downto 0); + APV_DATA_0_OUT : out std_logic_vector(11 downto 0); + APV_DATA_VALID_OUT : out std_logic; + LEVEL_RD_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end; + +architecture behavioral of adc_crossover is + + signal debug : std_logic_vector(31 downto 0); + + signal fifo_rd_level : std_logic_vector(4 downto 0); + signal fifo_wr_level : std_logic_vector(4 downto 0); + signal next_fifo_rd_ena : std_logic; + signal fifo_rd_ena : std_logic; + signal next_fifo_wr_ena : std_logic; + signal fifo_wr_ena : std_logic; + signal next_reset : std_logic; + signal reset : std_logic; + signal apv_data_valid : std_logic_vector(2 downto 0); + +begin + +--------------------------------------------------------------------------- +-- Debugging signals +--------------------------------------------------------------------------- +debug(31 downto 0) <= (others => '0'); + + +--------------------------------------------------------------------------- +-- Reset: we keep the FIFO in reset as long as the PLL is not locked +--------------------------------------------------------------------------- +next_reset <= reset_in or not adc_data_valid_in; + +THE_RESET_STATE_SYNC: state_sync +port map( STATE_A_IN => next_reset, + CLK_B_IN => clk_apv_in, + RESET_B_IN => '0', + STATE_B_OUT => reset + ); + + +--------------------------------------------------------------------------- +-- Crossover fifo for ADC +--------------------------------------------------------------------------- +next_fifo_wr_ena <= adc_ce_in and adc_data_valid_in; +next_fifo_rd_ena <= '1' when ( fifo_rd_level > b"0_0101" ) else '0'; + +SYNC_WRCLK_PROC: process( adc_clk_in ) +begin + if( rising_edge(adc_clk_in) ) then + fifo_wr_ena <= next_fifo_wr_ena; + end if; +end process SYNC_WRCLK_PROC; + +SYNC_RDCLK_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + fifo_rd_ena <= next_fifo_rd_ena; + apv_data_valid <= apv_data_valid(1 downto 0) & fifo_rd_ena; + end if; +end process SYNC_RDCLK_PROC; + +THE_CROSSOVER: crossover +port map( DATA(95 downto 84) => adc_data_7_in, + DATA(83 downto 72) => adc_data_6_in, + DATA(71 downto 60) => adc_data_5_in, + DATA(59 downto 48) => adc_data_4_in, + DATA(47 downto 36) => adc_data_3_in, + DATA(35 downto 24) => adc_data_2_in, + DATA(23 downto 12) => adc_data_1_in, + DATA(11 downto 0) => adc_data_0_in, + WRCLOCK => adc_clk_in, + RDCLOCK => clk_apv_in, + WREN => fifo_wr_ena, + RDEN => fifo_rd_ena, + RESET => reset, -- this is an async clear input! + RPRESET => '0', -- not needed, as OR'ed with RESET + Q(95 downto 84) => apv_data_7_out, + Q(83 downto 72) => apv_data_6_out, + Q(71 downto 60) => apv_data_5_out, + Q(59 downto 48) => apv_data_4_out, + Q(47 downto 36) => apv_data_3_out, + Q(35 downto 24) => apv_data_2_out, + Q(23 downto 12) => apv_data_1_out, + Q(11 downto 0) => apv_data_0_out, + WCNT => fifo_wr_level, + RCNT => fifo_rd_level, + EMPTY => open, + FULL => open + ); + + +--------------------------------------------------------------------------- +-- Output signals +--------------------------------------------------------------------------- +level_rd_out <= fifo_rd_level; +level_wr_out <= fifo_wr_level; +apv_data_valid_out <= apv_data_valid(2); + + +--------------------------------------------------------------------------- +-- DEBUG signals +--------------------------------------------------------------------------- +debug_out <= debug; + + +end behavioral; diff --git a/src/adc_data_handler_new.vhd b/src/adc_data_handler_new.vhd new file mode 100644 index 0000000..d4b7a17 --- /dev/null +++ b/src/adc_data_handler_new.vhd @@ -0,0 +1,325 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity adc_data_handler_new is + port( RESET_IN : in std_logic; + ADC_LCLK_IN : in std_logic; -- LCLK from ADC + ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC + ADC_CHNL_IN : in std_logic_vector(7 downto 0); + PLL_CTRL_IN : in std_logic_vector(3 downto 0); + ADC_DATA7_OUT : out std_logic_vector(11 downto 0); + ADC_DATA6_OUT : out std_logic_vector(11 downto 0); + ADC_DATA5_OUT : out std_logic_vector(11 downto 0); + ADC_DATA4_OUT : out std_logic_vector(11 downto 0); + ADC_DATA3_OUT : out std_logic_vector(11 downto 0); + ADC_DATA2_OUT : out std_logic_vector(11 downto 0); + ADC_DATA1_OUT : out std_logic_vector(11 downto 0); + ADC_DATA0_OUT : out std_logic_vector(11 downto 0); + ADC_CE_OUT : out std_logic; + ADC_VALID_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of adc_data_handler_new is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of behavioral : architecture is "ADC_DATA_HANDLER_group"; + + -- normal signals + signal adc_adclk_vec : std_logic_vector(0 downto 0); + signal adc_adclk : std_logic_vector(1 downto 0); + + signal adc_ch_7_mux : std_logic_vector(1 downto 0); + signal adc_ch_6_mux : std_logic_vector(1 downto 0); + signal adc_ch_5_mux : std_logic_vector(1 downto 0); + signal adc_ch_4_mux : std_logic_vector(1 downto 0); + signal adc_ch_3_mux : std_logic_vector(1 downto 0); + signal adc_ch_2_mux : std_logic_vector(1 downto 0); + signal adc_ch_1_mux : std_logic_vector(1 downto 0); + signal adc_ch_0_mux : std_logic_vector(1 downto 0); + + signal last_adc_7_ch : std_logic_vector(11 downto 0); + signal last_adc_6_ch : std_logic_vector(11 downto 0); + signal last_adc_5_ch : std_logic_vector(11 downto 0); + signal last_adc_4_ch : std_logic_vector(11 downto 0); + signal last_adc_3_ch : std_logic_vector(11 downto 0); + signal last_adc_2_ch : std_logic_vector(11 downto 0); + signal last_adc_1_ch : std_logic_vector(11 downto 0); + signal last_adc_0_ch : std_logic_vector(11 downto 0); + + signal buf_adc_7_ch : std_logic_vector(11 downto 0); + signal buf_adc_6_ch : std_logic_vector(11 downto 0); + signal buf_adc_5_ch : std_logic_vector(11 downto 0); + signal buf_adc_4_ch : std_logic_vector(11 downto 0); + signal buf_adc_3_ch : std_logic_vector(11 downto 0); + signal buf_adc_2_ch : std_logic_vector(11 downto 0); + signal buf_adc_1_ch : std_logic_vector(11 downto 0); + signal buf_adc_0_ch : std_logic_vector(11 downto 0); + + signal realstore : std_logic_vector(3 downto 0); + signal next_recstore : std_logic; + signal recstore : std_logic_vector(3 downto 0); + + signal reset : std_logic; -- synchronized to 240MHz local clock + + signal input_delay : std_logic_vector(3 downto 0); + + signal bitcounter : std_logic_vector(2 downto 0); + signal synccounter : std_logic_vector(2 downto 0); + signal next_ce_inc : std_logic; + signal ce_inc : std_logic; + signal next_ce_dec : std_logic; + signal ce_dec : std_logic; + signal next_sync_low : std_logic; + signal sync_low : std_logic; + signal next_sync_high : std_logic; + signal sync_high : std_logic; + + signal debug : std_logic_vector(15 downto 0); + +begin + +-- input delay for IDDR, 50ps / unit +input_delay <= pll_ctrl_in; + +-- Reset synchronizer +THE_RESET_SYNC: state_sync +port map( STATE_A_IN => reset_in, + CLK_B_IN => adc_lclk_in, + RESET_B_IN => '0', + STATE_B_OUT => reset + ); + +-- We have to reconstruct the ADC word clock (ADCLK). +-- Mind the vector! +adc_adclk_vec(0) <= adc_adclk_in; + +THE_ADC_ADCLK_IN: adc_ch_in +port map( DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_adclk_vec, + Q => adc_adclk + ); + +-- First group of channels (0 and 1) +THE_DIN_0: adc_ch_in +port map( DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(0 downto 0), + Q => adc_ch_0_mux + ); +THE_DIN_1: adc_ch_in +port map( DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(1 downto 1), + Q => adc_ch_1_mux + ); +THE_ADC_0_1_CH: adc_twochannels +port map( CLK_IN => adc_lclk_in, + RESET_IN => reset, + CLOCK_IN => adc_adclk, + DATA_0_IN => adc_ch_0_mux, + DATA_1_IN => adc_ch_1_mux, + DATA_0_OUT => last_adc_0_ch, + DATA_1_OUT => last_adc_1_ch, + STORE_OUT => realstore(0), + SWAP_OUT => open, + CLOCK_OUT => open, + DEBUG_OUT => open + ); + +-- Second group of channels (2 and 3) +THE_DIN_2: adc_ch_in +port map( DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(2 downto 2), + Q => adc_ch_2_mux + ); +THE_DIN_3: adc_ch_in +port map( DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(3 downto 3), + Q => adc_ch_3_mux + ); +THE_ADC_2_3_CH: adc_twochannels +port map( CLK_IN => adc_lclk_in, + RESET_IN => reset, + CLOCK_IN => adc_adclk, + DATA_0_IN => adc_ch_2_mux, + DATA_1_IN => adc_ch_3_mux, + DATA_0_OUT => last_adc_2_ch, + DATA_1_OUT => last_adc_3_ch, + STORE_OUT => realstore(1), + SWAP_OUT => open, + CLOCK_OUT => open, + DEBUG_OUT => open + ); + +-- Third group of channels (4 and 5) +THE_DIN_4: adc_ch_in +port map( DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(4 downto 4), + Q => adc_ch_4_mux + ); +THE_DIN_5: adc_ch_in +port map( DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(5 downto 5), + Q => adc_ch_5_mux + ); +THE_ADC_4_5_CH: adc_twochannels +port map( CLK_IN => adc_lclk_in, + RESET_IN => reset, + CLOCK_IN => adc_adclk, + DATA_0_IN => adc_ch_4_mux, + DATA_1_IN => adc_ch_5_mux, + DATA_0_OUT => last_adc_4_ch, + DATA_1_OUT => last_adc_5_ch, + STORE_OUT => realstore(2), + SWAP_OUT => open, + CLOCK_OUT => open, + DEBUG_OUT => open + ); + +-- Fourth group of channels (6 and 7) +THE_DIN_6: adc_ch_in +port map( DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(6 downto 6), + Q => adc_ch_6_mux + ); +THE_DIN_7: adc_ch_in +port map( DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(7 downto 7), + Q => adc_ch_7_mux + ); +THE_ADC_6_7_CH: adc_twochannels +port map( CLK_IN => adc_lclk_in, + RESET_IN => reset, + CLOCK_IN => adc_adclk, + DATA_0_IN => adc_ch_6_mux, + DATA_1_IN => adc_ch_7_mux, + DATA_0_OUT => last_adc_6_ch, + DATA_1_OUT => last_adc_7_ch, + STORE_OUT => realstore(3), + SWAP_OUT => open, + CLOCK_OUT => open, + DEBUG_OUT => open + ); + +-- Clock reconstruction (will only work if all four units work in perfect alignment) +next_recstore <= '1' when ( realstore = b"1111" ) else '0'; + +-- Synchronising stage +THE_SYNC_PROC: process( adc_lclk_in ) +begin + if( rising_edge(adc_lclk_in) ) then + recstore(3 downto 0) <= recstore(2 downto 0) & next_recstore; + sync_low <= next_sync_low; + sync_high <= next_sync_high; + ce_inc <= next_ce_inc; + ce_dec <= next_ce_dec; + end if; +end process THE_SYNC_PROC; + +THE_BIT_COUNTER: process( adc_lclk_in ) +begin + if( rising_edge(adc_lclk_in) ) then + if( recstore(0) = '1' ) then + bitcounter <= (others => '0'); + else + bitcounter <= bitcounter + 1; + end if; + end if; +end process THE_BIT_COUNTER; + +next_sync_low <= '1' when (synccounter = b"000") else '0'; +next_sync_high <= '1' when (synccounter = b"111") else '0'; + +next_ce_inc <= '1' when ( (bitcounter = b"101") and (recstore(0) = '1') and (sync_high = '0') ) else '0'; +next_ce_dec <= '1' when ( (bitcounter = b"101") and (recstore(0) = '0') and (sync_low = '0') ) else '0'; + +THE_SYNC_COUNTER: process( adc_lclk_in ) +begin + if( rising_edge(adc_lclk_in) ) then + if( reset = '1' ) then + synccounter <= (others => '0'); + elsif( (ce_inc = '1') and (ce_dec = '0') ) then + synccounter <= synccounter + 1; + elsif( (ce_inc = '0') and (ce_dec = '1') ) then + synccounter <= synccounter - 1; + end if; + end if; +end process THE_SYNC_COUNTER; + +debug(15 downto 11) <= (others => '0'); +debug(10 downto 8) <= synccounter; +debug(7) <= sync_low; +debug(6) <= sync_high; +debug(5) <= ce_dec; +debug(4) <= ce_inc; +debug(3) <= '0'; +debug(2 downto 0) <= bitcounter; + +----------------------------------------------------------------------- +-- generate 8 ADC channel inputs and clock transfer registers +----------------------------------------------------------------------- +THE_DATA_DELAY_PROC: process( adc_lclk_in ) +begin + if( rising_edge(adc_lclk_in) ) then + buf_adc_7_ch <= last_adc_7_ch; + buf_adc_6_ch <= last_adc_6_ch; + buf_adc_5_ch <= last_adc_5_ch; + buf_adc_4_ch <= last_adc_4_ch; + buf_adc_3_ch <= last_adc_3_ch; + buf_adc_2_ch <= last_adc_2_ch; + buf_adc_1_ch <= last_adc_1_ch; + buf_adc_0_ch <= last_adc_0_ch; + end if; +end process THE_DATA_DELAY_PROC; + + +-- output signals +adc_data7_out <= buf_adc_7_ch; +adc_data6_out <= buf_adc_6_ch; +adc_data5_out <= buf_adc_5_ch; +adc_data4_out <= buf_adc_4_ch; +adc_data3_out <= buf_adc_3_ch; +adc_data2_out <= buf_adc_2_ch; +adc_data1_out <= buf_adc_1_ch; +adc_data0_out <= buf_adc_0_ch; +adc_ce_out <= recstore(3); +adc_valid_out <= sync_high; + +debug_out(15 downto 0) <= debug; + +end behavioral; + \ No newline at end of file diff --git a/src/adc_onewire_map_mem.lpc b/src/adc_onewire_map_mem.lpc new file mode 100644 index 0000000..19bef2d --- /dev/null +++ b/src/adc_onewire_map_mem.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_ROM +CoreRevision=2.4 +ModuleName=adc_onewire_map_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/05/2009 +Time=10:27:05 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=128 +Data=4 +LUT=0 +MemFile=\\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem +MemFormat=orca diff --git a/src/adc_onewire_map_mem.srp b/src/adc_onewire_map_mem.srp new file mode 100644 index 0000000..a45415a --- /dev/null +++ b/src/adc_onewire_map_mem.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Nov 05 10:27:05 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e + Circuit name : adc_onewire_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem + EDIF output : suppressed + VHDL output : adc_onewire_map_mem.vhd + VHDL template : adc_onewire_map_mem_tmpl.vhd + VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_onewire_map_mem.srp + Element Usage : + ROM128X1 : 4 + Estimated Resource Usage: + LUT : 16 diff --git a/src/adc_onewire_map_mem.vhd b/src/adc_onewire_map_mem.vhd new file mode 100644 index 0000000..7aba8b5 --- /dev/null +++ b/src/adc_onewire_map_mem.vhd @@ -0,0 +1,81 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 7 -num_rows 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e + +-- Thu Nov 05 10:27:05 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity adc_onewire_map_mem is + port ( + Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end adc_onewire_map_mem; + +architecture Structure of adc_onewire_map_mem is + + -- local component declarations + component ROM128X1 + -- synopsys translate_off + generic (INITVAL : in String); + -- synopsys translate_on + port (AD6: in std_logic; AD5: in std_logic; AD4: in std_logic; + AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + attribute initval : string; + attribute initval of mem_0_3 : label is "0xFF00FF00FF001FE0E01F7F80807F6956"; + attribute initval of mem_0_2 : label is "0xF0F0F0F0F0F07E187E18F81CF81C807F"; + attribute initval of mem_0_1 : label is "0xCCCCCCCCCCCC798386BAE6521AEC70F8"; + attribute initval of mem_0_0 : label is "0xAAAAAAAAAAAA32AD326B2A9729D64AE5"; + +begin + -- component instantiation statements + mem_0_3: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xFF00FF00FF001FE0E01F7F80807F6956") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(3)); + + mem_0_2: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xF0F0F0F0F0F07E187E18F81CF81C807F") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(2)); + + mem_0_1: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xCCCCCCCCCCCC798386BAE6521AEC70F8") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(1)); + + mem_0_0: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xAAAAAAAAAAAA32AD326B2A9729D64AE5") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(0)); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of adc_onewire_map_mem is + for Structure + for all:ROM128X1 use entity ecp2m.ROM128X1(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/adc_onewire_map_mem_generate.log b/src/adc_onewire_map_mem_generate.log new file mode 100644 index 0000000..ed0c0f5 --- /dev/null +++ b/src/adc_onewire_map_mem_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Nov 05 10:27:05 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e + Circuit name : adc_onewire_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Data width : 4 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem + EDIF output : suppressed + VHDL output : adc_onewire_map_mem.vhd + VHDL template : adc_onewire_map_mem_tmpl.vhd + VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_onewire_map_mem.srp + Estimated Resource Usage: + LUT : 16 + +END SCUBA Module Synthesis + +File: adc_onewire_map_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/adc_onewire_map_mem_tmpl.vhd b/src/adc_onewire_map_mem_tmpl.vhd new file mode 100644 index 0000000..8659f3d --- /dev/null +++ b/src/adc_onewire_map_mem_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Thu Nov 05 10:27:05 2009 + +-- parameterized module component declaration +component adc_onewire_map_mem + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : adc_onewire_map_mem + port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/src/adc_onewire_mapping.mem b/src/adc_onewire_mapping.mem new file mode 100644 index 0000000..32b44fd --- /dev/null +++ b/src/adc_onewire_mapping.mem @@ -0,0 +1,152 @@ +#Format=Address-Hex +#Depth=128 +#DataWidth=4 +#AddrRadix=3 +#DataRadix=3 + +# Backplane 0 +# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# 1Wire 5 12 13 6 14 7 15 3 8 1 0 9 2 10 11 (4) +00: 5 +01: c +02: d +03: 6 +04: e +05: 7 +06: f +07: 3 +08: 8 +09: 1 +0a: 0 +0b: 9 +0c: 2 +0d: a +0e: b +0f: 4 +# Backplane 1 +# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# 1Wire 8 9 15 14 13 10 11 3 1 2 0 7 6 5 4 (12) +10: 8 +11: 9 +12: f +13: e +14: d +15: a +16: b +17: 3 +18: 1 +19: 2 +1a: 0 +1b: 7 +1c: 6 +1d: 5 +1e: 4 +1f: c +# Backplane 2 +# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# 1Wire 1 3 5 4 7 0 2 9 8 11 10 13 12 15 14 (6) +20: 1 +21: 3 +22: 5 +23: 4 +24: 7 +25: 0 +26: 2 +27: 9 +28: 8 +29: b +2a: a +2b: d +2c: c +2d: f +2e: e +2f: 6 +# Backplane 3 +# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# 1Wire 9 11 8 15 14 3 1 2 0 7 6 4 5 13 12 (10) +30: 9 +31: b +32: 8 +33: f +34: e +35: 3 +36: 1 +37: 2 +38: 0 +39: 7 +3a: 6 +3b: 4 +3c: 5 +3d: d +3e: c +3f: a +# Backplane 4 +# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# 1Wire 3 2 1 5 4 9 8 11 10 13 12 14 15 7 6 (0) +40: 3 +41: 2 +42: 1 +43: 5 +44: 4 +45: 9 +46: 8 +47: b +48: a +49: d +4a: c +4b: e +4c: f +4d: 7 +4e: 6 +4f: 0 +# unused (5) => 1:1 +50: 0 +51: 1 +52: 2 +53: 3 +54: 4 +55: 5 +56: 6 +57: 7 +58: 8 +59: 9 +5a: a +5b: b +5c: c +5d: d +5e: e +5f: f +# unused (6) => 1:1 +60: 0 +61: 1 +62: 2 +63: 3 +64: 4 +65: 5 +66: 6 +67: 7 +68: 8 +69: 9 +6a: a +6b: b +6c: c +6d: d +6e: e +6f: f +# unused (7) => 1:1 +70: 0 +71: 1 +72: 2 +73: 3 +74: 4 +75: 5 +76: 6 +77: 7 +78: 8 +79: 9 +7a: a +7b: b +7c: c +7d: d +7e: e +7f: f diff --git a/src/adc_pll.lpc b/src/adc_pll.lpc new file mode 100644 index 0000000..a11a5e3 --- /dev/null +++ b/src/adc_pll.lpc @@ -0,0 +1,56 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=4.2 +ModuleName=adc_pll +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/16/2009 +Time=11:20:59 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=40 +OFrq=40.000000 +KFrq= +U_OFrq=40 +U_KFrq=50 +OP_Tol=0.0 +OK_Tol=0.0 +Div=1 +Mult=1 +Post=32 +SecD=2 +fb_mode=CLKOP +PhaseDuty=Static +DelayControl=SPLL_NO_DELAY +External=DISABLED +PCDR=1 +ClkOPBp=0 +EnCLKOS=0 +ClkOSBp=0 +Phase=0.0 +Duty=8 +DPD=50% Duty +EnCLKOK=0 +ClkOKBp=0 +ClkRst=0 diff --git a/src/adc_pll.vhd b/src/adc_pll.vhd new file mode 100644 index 0000000..b09a7f5 --- /dev/null +++ b/src/adc_pll.vhd @@ -0,0 +1,121 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 4.2 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_pll -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 40 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -delay_cntl SPLL_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -use_rst -e + +-- Thu Apr 16 11:20:59 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity adc_pll is + port ( + CLK: in std_logic; + RESET: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : string; + attribute dont_touch of adc_pll : entity is "true"; +end adc_pll; + +architecture Structure of adc_pll is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + signal CLK_t: std_logic; + + -- local component declarations + component VLO + port (Z: out std_logic); + end component; + component EPLLD + -- synopsys translate_off + generic (PLLCAP : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + DUTY : in Integer; PHASEADJ : in String; + PHASE_CNTL : in String; CLKOK_DIV : in Integer; + CLKFB_DIV : in Integer; CLKOP_DIV : in Integer; + CLKI_DIV : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; + CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + attribute PLLCAP : string; + attribute PLLTYPE : string; + attribute CLKOK_BYPASS : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute CLKOK_DIV : string; + attribute CLKOS_BYPASS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute CLKOP_BYPASS : string; + attribute PHASE_CNTL : string; + attribute FDEL : string; + attribute DUTY : string; + attribute PHASEADJ : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute FIN : string; + attribute PLLCAP of PLLDInst_0 : label is "DISABLED"; + attribute PLLTYPE of PLLDInst_0 : label is "SPLL"; + attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000"; + attribute CLKOK_DIV of PLLDInst_0 : label is "2"; + attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "40.000000"; + attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC"; + attribute FDEL of PLLDInst_0 : label is "0"; + attribute DUTY of PLLDInst_0 : label is "8"; + attribute PHASEADJ of PLLDInst_0 : label is "0.0"; + attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "40.000000"; + attribute CLKOP_DIV of PLLDInst_0 : label is "32"; + attribute CLKFB_DIV of PLLDInst_0 : label is "1"; + attribute CLKI_DIV of PLLDInst_0 : label is "1"; + attribute FIN of PLLDInst_0 : label is "40.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLDInst_0: EPLLD + -- synopsys translate_off + generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED", + CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 32, + CLKFB_DIV=> 1, CLKI_DIV=> 1) + -- synopsys translate_on + port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>RESET, + RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; + CLK_t <= CLK; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of adc_pll is + for Structure + for all:VLO use entity ecp2m.VLO(V); end for; + for all:EPLLD use entity ecp2m.EPLLD(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/adc_pll_tmpl.vhd b/src/adc_pll_tmpl.vhd new file mode 100644 index 0000000..221ccc4 --- /dev/null +++ b/src/adc_pll_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 4.2 +-- Thu Apr 16 11:20:59 2009 + +-- parameterized module component declaration +component adc_pll + port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic; + LOCK: out std_logic); +end component; + +-- parameterized module component instance +__ : adc_pll + port map (CLK=>__, RESET=>__, CLKOP=>__, LOCK=>__); diff --git a/src/adc_snoop_mem.lpc b/src/adc_snoop_mem.lpc new file mode 100644 index 0000000..0153bba --- /dev/null +++ b/src/adc_snoop_mem.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP +CoreRevision=6.1 +ModuleName=adc_snoop_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/13/2009 +Time=16:03:30 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +RAddress=1024 +RData=16 +WAddress=1024 +WData=16 +enByte=0 +ByteSize=9 +adPipeline=0 +inPipeline=0 +outPipeline=1 +MOR=0 +InData=Registered +AdControl=Registered +MemFile= +MemFormat=bin +Reset=Sync +GSR=Enabled +Pad=0 +EnECC=0 +Optimization=Speed +EnSleep=ENABLED +Pipeline=0 diff --git a/src/adc_snoop_mem.srp b/src/adc_snoop_mem.srp new file mode 100644 index 0000000..8f43024 --- /dev/null +++ b/src/adc_snoop_mem.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Oct 13 16:03:30 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + Circuit name : adc_snoop_mem + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[15:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : adc_snoop_mem.vhd + VHDL template : adc_snoop_mem_tmpl.vhd + VHDL testbench : tb_adc_snoop_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_snoop_mem.srp + Element Usage : + DP16KB : 1 + Estimated Resource Usage: + EBR : 1 diff --git a/src/adc_snoop_mem.vhd b/src/adc_snoop_mem.vhd new file mode 100644 index 0000000..501b487 --- /dev/null +++ b/src/adc_snoop_mem.vhd @@ -0,0 +1,194 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 6.1 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 10 -rp 0011 -rdata_width 16 -data_width 16 -num_rows 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + +-- Tue Oct 13 16:03:30 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity adc_snoop_mem is + port ( + WrAddress: in std_logic_vector(9 downto 0); + RdAddress: in std_logic_vector(9 downto 0); + Data: in std_logic_vector(15 downto 0); + WE: in std_logic; + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + WrClock: in std_logic; + WrClockEn: in std_logic; + Q: out std_logic_vector(15 downto 0)); +end adc_snoop_mem; + +architecture Structure of adc_snoop_mem is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute GSR : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute MEM_LPC_FILE of adc_snoop_mem_0_0_0 : label is "adc_snoop_mem.lpc"; + attribute MEM_INIT_FILE of adc_snoop_mem_0_0_0 : label is ""; + attribute CSDECODE_B of adc_snoop_mem_0_0_0 : label is "0b000"; + attribute CSDECODE_A of adc_snoop_mem_0_0_0 : label is "0b000"; + attribute WRITEMODE_B of adc_snoop_mem_0_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of adc_snoop_mem_0_0_0 : label is "NORMAL"; + attribute GSR of adc_snoop_mem_0_0_0 : label is "DISABLED"; + attribute RESETMODE of adc_snoop_mem_0_0_0 : label is "SYNC"; + attribute REGMODE_B of adc_snoop_mem_0_0_0 : label is "OUTREG"; + attribute REGMODE_A of adc_snoop_mem_0_0_0 : label is "OUTREG"; + attribute DATA_WIDTH_B of adc_snoop_mem_0_0_0 : label is "18"; + attribute DATA_WIDTH_A of adc_snoop_mem_0_0_0 : label is "18"; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + adc_snoop_mem_0_0_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>scuba_vlo, + DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>WrAddress(0), + ADA5=>WrAddress(1), ADA6=>WrAddress(2), ADA7=>WrAddress(3), + ADA8=>WrAddress(4), ADA9=>WrAddress(5), ADA10=>WrAddress(6), + ADA11=>WrAddress(7), ADA12=>WrAddress(8), + ADA13=>WrAddress(9), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>RdAddress(0), + ADB5=>RdAddress(1), ADB6=>RdAddress(2), ADB7=>RdAddress(3), + ADB8=>RdAddress(4), ADB9=>RdAddress(5), ADB10=>RdAddress(6), + ADB11=>RdAddress(7), ADB12=>RdAddress(8), + ADB13=>RdAddress(9), CEB=>RdClockEn, CLKB=>RdClock, + WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), + DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), + DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11), + DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15), + DOB16=>open, DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of adc_snoop_mem is + for Structure + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/adc_snoop_mem_generate.log b/src/adc_snoop_mem_generate.log new file mode 100644 index 0000000..6e9dac6 --- /dev/null +++ b/src/adc_snoop_mem_generate.log @@ -0,0 +1,44 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Oct 13 16:03:30 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + Circuit name : adc_snoop_mem + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[15:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : adc_snoop_mem.vhd + VHDL template : adc_snoop_mem_tmpl.vhd + VHDL testbench : tb_adc_snoop_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_snoop_mem.srp + Estimated Resource Usage: + EBR : 1 + +END SCUBA Module Synthesis + +File: adc_snoop_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/adc_snoop_mem_tmpl.vhd b/src/adc_snoop_mem_tmpl.vhd new file mode 100644 index 0000000..899a664 --- /dev/null +++ b/src/adc_snoop_mem_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 6.1 +-- Tue Oct 13 16:03:30 2009 + +-- parameterized module component declaration +component adc_snoop_mem + port (WrAddress: in std_logic_vector(9 downto 0); + RdAddress: in std_logic_vector(9 downto 0); + Data: in std_logic_vector(15 downto 0); WE: in std_logic; + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; WrClock: in std_logic; + WrClockEn: in std_logic; Q: out std_logic_vector(15 downto 0)); +end component; + +-- parameterized module component instance +__ : adc_snoop_mem + port map (WrAddress(9 downto 0)=>__, RdAddress(9 downto 0)=>__, Data(15 downto 0)=>__, + WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__, + WrClockEn=>__, Q(15 downto 0)=>__); diff --git a/src/adc_twochannels.vhd b/src/adc_twochannels.vhd new file mode 100644 index 0000000..f48f729 --- /dev/null +++ b/src/adc_twochannels.vhd @@ -0,0 +1,211 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity adc_twochannels is + port( CLK_IN : in std_logic; -- DDR bit clock + RESET_IN : in std_logic; + CLOCK_IN : in std_logic_vector(1 downto 0); -- word clock + DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one + DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two + DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one + DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two + STORE_OUT : out std_logic; + SWAP_OUT : out std_logic; + CLOCK_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behaviour of adc_twochannels is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of behaviour : architecture is "TWOCHANNELS_group"; + + type half_data_t is array (0 to 1) of std_logic_vector(5 downto 0); + signal qda : half_data_t; -- serial input data, raising edge + signal qdb : half_data_t; -- serial input data, falling edge + signal parda : half_data_t; -- parallel input data, raising edge + signal pardb : half_data_t; -- parallel input data, falling edge + signal qc : half_data_t; -- serial ADCLK signal, (0) raising edge, (1) falling edge + type full_data_t is array (0 to 1) of std_logic_vector(11 downto 0); + signal muxed : full_data_t; + signal data : full_data_t; + + signal next_store_a : std_logic; + signal store_a : std_logic; -- store serial data A to parallel temp register + signal next_store_b : std_logic; + signal store_b : std_logic; -- store serial data B to parallel temp register + signal check : std_logic; -- auxiliary signal for swapping + signal next_swap : std_logic; + signal swap : std_logic; -- swap half words before assembling + signal store : std_logic; -- assemble full word + +begin + +------------------------------------------------------------------------- +-- Data reconstruction +------------------------------------------------------------------------- +-- Shift registers for both data streams from DDR input block +THE_INSHIFT_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + qda(0) <= (others => '0'); + qdb(0) <= (others => '0'); + qda(1) <= (others => '0'); + qdb(1) <= (others => '0'); + qc(0) <= (others => '0'); + qc(1) <= (others => '0'); + else + -- first channel + qda(0) <= qda(0)(4 downto 0) & data_0_in(0); + qdb(0) <= qdb(0)(4 downto 0) & data_0_in(1); + -- second channel + qda(1) <= qda(1)(4 downto 0) & data_1_in(0); + qdb(1) <= qdb(1)(4 downto 0) & data_1_in(1); + -- clock channel + qc(0) <= qc(0)(4 downto 0) & clock_in(0); + qc(1) <= qc(1)(4 downto 0) & clock_in(1); + end if; + end if; +end process THE_INSHIFT_PROC; + +-- parallel temp registers to store raw serial data for multiplexing +THE_PARALLEL_STORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( store_a = '1' ) then + parda(0) <= qda(0); + parda(1) <= qda(1); + end if; + if( store_b = '1' ) then + pardb(0) <= qdb(0); + pardb(1) <= qdb(1); + end if; + end if; +end process THE_PARALLEL_STORE_PROC; + +-- synchronize combinatorial signals +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + store_a <= next_store_a; + store_b <= next_store_b; + check <= store_b; + swap <= next_swap; + store <= store_a; + end if; +end process THE_SYNC_PROC; + +-- store signals for half words +next_store_a <= '1' when (qc(0)(5 downto 2) = b"0111") else '0'; +next_store_b <= '1' when (qc(1)(5 downto 2) = b"0111") else '0'; + +-- swap half words indicator (can be improved: 10 -> preswap, preswap 01 -> swap) +next_swap <= '1' when ( (store_a = '1') and (store_b = '0') and (check = '1') ) else '0'; + +-- halfword swapping +THE_SWAP_PROC: process( parda, pardb, swap ) +begin + case swap is + when '1' => -- first channel + muxed(0)(0) <= pardb(0)(5); + muxed(0)(1) <= parda(0)(5); + muxed(0)(2) <= pardb(0)(4); + muxed(0)(3) <= parda(0)(4); + muxed(0)(4) <= pardb(0)(3); + muxed(0)(5) <= parda(0)(3); + muxed(0)(6) <= pardb(0)(2); + muxed(0)(7) <= parda(0)(2); + muxed(0)(8) <= pardb(0)(1); + muxed(0)(9) <= parda(0)(1); + muxed(0)(10) <= pardb(0)(0); + muxed(0)(11) <= parda(0)(0); + -- second channel + muxed(1)(0) <= pardb(1)(5); + muxed(1)(1) <= parda(1)(5); + muxed(1)(2) <= pardb(1)(4); + muxed(1)(3) <= parda(1)(4); + muxed(1)(4) <= pardb(1)(3); + muxed(1)(5) <= parda(1)(3); + muxed(1)(6) <= pardb(1)(2); + muxed(1)(7) <= parda(1)(2); + muxed(1)(8) <= pardb(1)(1); + muxed(1)(9) <= parda(1)(1); + muxed(1)(10) <= pardb(1)(0); + muxed(1)(11) <= parda(1)(0); + when '0' => -- first channel + muxed(0)(0) <= parda(0)(5); + muxed(0)(1) <= pardb(0)(5); + muxed(0)(2) <= parda(0)(4); + muxed(0)(3) <= pardb(0)(4); + muxed(0)(4) <= parda(0)(3); + muxed(0)(5) <= pardb(0)(3); + muxed(0)(6) <= parda(0)(2); + muxed(0)(7) <= pardb(0)(2); + muxed(0)(8) <= parda(0)(1); + muxed(0)(9) <= pardb(0)(1); + muxed(0)(10) <= parda(0)(0); + muxed(0)(11) <= pardb(0)(0); + -- second channel + muxed(1)(0) <= parda(1)(5); + muxed(1)(1) <= pardb(1)(5); + muxed(1)(2) <= parda(1)(4); + muxed(1)(3) <= pardb(1)(4); + muxed(1)(4) <= parda(1)(3); + muxed(1)(5) <= pardb(1)(3); + muxed(1)(6) <= parda(1)(2); + muxed(1)(7) <= pardb(1)(2); + muxed(1)(8) <= parda(1)(1); + muxed(1)(9) <= pardb(1)(1); + muxed(1)(10) <= parda(1)(0); + muxed(1)(11) <= pardb(1)(0); + when others => + end case; +end process THE_SWAP_PROC; + +-- store parallel data +THE_STORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( store = '1' ) then + data(0) <= muxed(0); + data(1) <= muxed(1); + end if; + end if; +end process THE_STORE_PROC; + +---- output signals +data_0_out <= data(0); +data_1_out <= data(1); + +store_out <= store; + +swap_out <= swap; + +clock_out <= qc(0)(3); -- timing adjustment + +-- debug signals +debug_out(15) <= store; +debug_out(14) <= swap; +debug_out(13) <= store_b; +debug_out(12) <= store_a; +debug_out(11 downto 0) <= data(0); + +--debug_out(15 downto 15) <= (others => '0'); +--debug_out(14) <= swap; +--debug_out(13) <= store_b; +--debug_out(12) <= store_a; +--debug_out(11 downto 6) <= parda(0); +--debug_out(5 downto 0) <= pardb(0); + + +end behaviour; + diff --git a/src/adcmv3.vhd b/src/adcmv3.vhd new file mode 100755 index 0000000..83a52c4 --- /dev/null +++ b/src/adcmv3.vhd @@ -0,0 +1,1271 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.trb_net_std.all; +use work.adcmv3_components.all; + +entity adcmv3 is + port( CLK100M : in std_logic; -- OK -- 100MHz LVDS clock + -- trigger inputs + EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers + -- APV stuff + APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock + APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock + APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out + APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out + APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active + APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA + APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL + ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers + APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock + APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock + APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out + APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out + APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active + APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA + APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL + ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers + -- ADC0 stuff + ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL + ADC0_RST : out std_logic; -- OK -- ADC reset signal + ADC0_PD : out std_logic; -- OK -- ADC powerdown signal + ADC0_CS : out std_logic; -- OK -- ADC /CS signal + ADC0_SDI : out std_logic; -- OK -- ADC serial data in + ADC0_SCK : out std_logic; -- OK -- ADC serial clock + ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock + ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock + ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams + -- ADC1 stuff + ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL + ADC1_RST : out std_logic; -- OK -- ADC reset signal + ADC1_PD : out std_logic; -- OK -- ADC powerdown signal + ADC1_CS : out std_logic; -- OK -- ADC /CS signal + ADC1_SDI : out std_logic; -- OK -- ADC serial data in + ADC1_SCK : out std_logic; -- OK -- ADC serial clock + ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock + ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock + ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams + -- uC connections + UC_RESET : in std_logic; -- OK -- uC reset, high active + UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot + -- SerDes pins + HDINN2 : in std_logic; -- highspeed INPUT + HDINP2 : in std_logic; -- + HDOUTN2 : out std_logic; -- highspeed OUTPUT + HDOUTP2 : out std_logic; -- + SD_PRESENT : in std_logic; -- OK -- Present signal from SFP + SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP + SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable + ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM + -- Backplane sense wires + BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane + BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane + BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane + BP_LED : out std_logic; -- OK -- backplane LED + -- LEDs + FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS + FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2) + FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1) + FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0) + FPGA_LED_PLL : out std_logic; -- OK -- PLL locked + FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED + -- 1Wire chips on APV FEs + APV0_1W : inout std_logic_vector(7 downto 0); + APV1_1W : inout std_logic_vector(7 downto 0); + -- SPI FlashROM connections + U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM + U_SPI_SCK : out std_logic; -- OK -- clock + U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM + U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM + -- Debug connections + DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header + ); +end; + +architecture adcmv3 of adcmv3 is + +-- Signals + -- Clock related signals + signal clk100m_locked : std_logic; -- not needed at the moment + signal sysclk : std_logic; -- clean 100MHz for distribution + + signal adc0_ce : std_logic; + signal adc0_valid : std_logic; + signal adc0_reset : std_logic; + signal adc0_powerdown : std_logic; + signal adc1_ce : std_logic; + signal adc1_valid : std_logic; + signal adc1_reset : std_logic; + signal adc1_powerdown : std_logic; + + signal clk_adc : std_logic; -- 40MHz for ADC operation + signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!) + signal clk40m_locked : std_logic; + signal clk40m_reset : std_logic; + + signal async_reset : std_logic; + + -- APV related signals + signal apv_sda_out : std_logic; -- APV SDA + signal apv_sda_in : std_logic; + signal apv_scl_out : std_logic; -- APV SCL + signal apv_scl_in : std_logic; + signal apv_trg : std_logic; -- real APV trigger signal + signal apv_sync : std_logic; -- artificial signal + signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame + signal apv0_reset : std_logic; + signal apv1_reset : std_logic; + signal apv_reset : std_logic; + signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] + signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] + + -- Control signals + signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register + signal status_pll : std_logic_vector(15 downto 0); -- PLL status register + signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register + signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register + + signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header + signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header + signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting + signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting + + signal maximum_trg : std_logic_vector(3 downto 0); + + signal raw_buf_full : std_logic; + signal eds_buf_full : std_logic; + signal eds_buf_level : std_logic_vector(4 downto 0); + + -- regIO data bus + signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + signal regio_read_enable : std_logic; + signal regio_write_enable : std_logic; + signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + signal regio_dataready : std_logic; + signal regio_no_more_data : std_logic; + signal regio_write_ack : std_logic; + signal regio_unknown_addr : std_logic; + signal regio_timeout : std_logic; + + -- common status / control registers from RegIO + signal common_stat_reg : std_logic_vector(63 downto 0); + signal common_ctrl_reg : std_logic_vector(63 downto 0); + + -- user defined "quick'n'dirty" registers + signal simple_status : std_logic_vector(127 downto 0); + signal simple_control : std_logic_vector(63 downto 0); + + -- debug signals + signal test_reg : std_logic_vector(31 downto 0); + signal trbrich_debug : std_logic_vector(63 downto 0); + signal trgctrl_debug : std_logic_vector(63 downto 0); + signal slave_debug : std_logic_vector(63 downto 0); + signal fifo_debug : std_logic_vector(63 downto 0); + signal raw_buf_debug : std_logic_vector(63 downto 0); + + -- EDS / BUFFER signals (raw buf -> ped corr) + signal eds_data : std_logic_vector(39 downto 0); + signal eds_avail : std_logic; + signal eds_done : std_logic; + signal buf_addr : std_logic_vector(6 downto 0); + signal buf_done : std_logic; + signal buf_tick : std_logic_vector(15 downto 0); + signal buf_start : std_logic_vector(15 downto 0); + signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging! + + type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0); + signal buf_data : reg_38bit_t; + + signal thr_addr : std_logic_vector(6 downto 0); + type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0); + signal thr_data : reg_18bit_t; + signal ped_data : reg_18bit_t; + + -- FIFO / DHDR signals (ped corr -> ipu stage) + signal dhdr_data : std_logic_vector(31 downto 0); + signal dhdr_length : std_logic_vector(15 downto 0); + signal dhdr_store : std_logic; + signal dhdr_buf_full : std_logic; + + signal fifo_start : std_logic; + signal fifo_done : std_logic; + signal fifo_we : std_logic_vector(15 downto 0); + type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0); + signal fifo_data : reg_40bit_t; + + -- APV control / status signals + type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0); + signal adc_ctrl_reg : reg_16bit_t; + signal adc_stat_reg : reg_16bit_t; + + signal debug : std_logic_vector(42 downto 0); + signal debug_q : std_logic_vector(42 downto 0); + signal debug_qq : std_logic_vector(42 downto 0); + signal debug_clk : std_logic; + + -- LVL1 application interface + signal lvl1_trg_type : std_logic_vector(3 downto 0); + signal lvl1_trg_received : std_logic; + signal lvl1_trg_number : std_logic_vector(15 downto 0); + signal lvl1_trg_code : std_logic_vector(7 downto 0); + signal lvl1_trg_information : std_logic_vector(23 downto 0); + signal lvl1_error_pattern : std_logic_vector(31 downto 0); + signal lvl1_trg_release : std_logic; + signal lvl1_trg_missing : std_logic; + signal timing_trg_found : std_logic; + + -- IPU application interface + signal ipu_number : std_logic_vector(15 downto 0); + signal ipu_information : std_logic_vector(7 downto 0); + signal ipu_start_readout : std_logic; + signal ipu_data : std_logic_vector(31 downto 0); + signal ipu_dataready : std_logic; + signal ipu_readout_finished : std_logic; + signal ipu_read : std_logic; + signal ipu_length : std_logic_vector(15 downto 0); + signal ipu_error_pattern : std_logic_vector(31 downto 0); + + signal local_lvl1_counter : std_logic_vector(15 downto 0); + signal local_lvl2_counter : std_logic_vector(15 downto 0); + + -- ADC signals + type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0); + signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain + signal adc_data : reg_12bit_t; -- common APV clock domain + + signal adc1_testdata : std_logic_vector(11 downto 0); + signal adc0_testdata : std_logic_vector(11 downto 0); + signal adc1_select : std_logic_vector(2 downto 0); + signal adc0_select : std_logic_vector(2 downto 0); + + -- input synchronizing + signal bp_sector_q : std_logic_vector(3 downto 0); + signal bp_sector_qq : std_logic_vector(3 downto 0); + signal bp_module_q : std_logic_vector(3 downto 0); + signal bp_module_qq : std_logic_vector(3 downto 0); + + signal lsm_state_bits : std_logic_vector(3 downto 0); + signal reset_by_trb : std_logic; + signal global_sync_reset : std_logic; + + signal adc0_iodelay : std_logic_vector(3 downto 0); + signal adc1_iodelay : std_logic_vector(3 downto 0); + + + +-- Components + -- are now in adcmv2_components.vhd + +begin + +---------------------------------------- +-- Async reset assignment -- +---------------------------------------- +--async_reset <= '0'; -- no async reset +async_reset <= uc_reset; -- uC reset pin + + +---------------------------------------- +-- Reset handler / spike surpression -- +---------------------------------------- +THE_RESET_HANDLER: reset_handler +port map( CLEAR_IN => async_reset, + RESET_IN => '0', + CLK_IN => sysclk, + TRB_RESET_IN => reset_by_trb, + RESET_OUT => global_sync_reset, + DEBUG_OUT => open + ); + + +---------------------------------------- +-- 100MHz PLL -> 40MHz / 100MHz -- +---------------------------------------- +-- 100MHz PLL, generating 40MHz and phase shifted 40MHz +THE_40M_PLL: PLL_40M +port map( CLK => clk100m, + RESET => clk40m_reset, + DPAMODE => '1', -- dynamic control + DPHASE0 => ctrl_pll(0), + DPHASE1 => ctrl_pll(1), + DPHASE2 => ctrl_pll(2), + DPHASE3 => ctrl_pll(3), + CLKOP => clk_apv, -- fixed phase, used for logic + CLKOS => clk_adc, -- phase adjustable, for ODDRXC only + LOCK => clk40m_locked + ); +clk40m_reset <= ctrl_pll(7); + +-- 100MHz DLL, used for clock injection delay removal +THE_100M_DLL: dll_100m +port map( CLK => clk100m, + RESETN => '1', + ALUHOLD => '0', + CLKOP => sysclk, + CLKOS => open, + LOCK => clk100m_locked + ); + + +---------------------------------------- +-- TRB endpoint -- +---------------------------------------- +THE_RICH_TRB: rich_trb +port map( CLK100M_IN => clk100m, -- SerDes exclusive clock + SYSCLK_IN => sysclk, -- fabric clock + RESET_IN => global_sync_reset, + SD_RXD_P_IN => hdinp2, + SD_RXD_N_IN => hdinn2, + SD_TXD_P_OUT => hdoutp2, + SD_TXD_N_OUT => hdoutn2, + SD_PRESENT_IN => sd_present, + SD_TXDIS_OUT => sd_txdis, + SD_LOS_IN => sd_los, + ONEWIRE_INOUT => adcm_onewire, + -- common regIO status / control registers + COMMON_STAT_REG_IN => common_stat_reg, + COMMON_CTRL_REG_OUT => common_ctrl_reg, + -- status register input to regIO / control register output from regIO + CONTROL_OUT => simple_control, + STATUS_IN => simple_status, + -- LVL1 signals + LVL1_TRG_TYPE_OUT => lvl1_trg_type, + LVL1_TRG_RECEIVED_OUT => lvl1_trg_received, + LVL1_TRG_NUMBER_OUT => lvl1_trg_number, + LVL1_TRG_CODE_OUT => lvl1_trg_code, + LVL1_TRG_INFORMATION_OUT => lvl1_trg_information, + LVL1_ERROR_PATTERN_IN => lvl1_error_pattern, + LVL1_TRG_RELEASE_IN => lvl1_trg_release, + TIMING_TRG_FOUND_IN => timing_trg_found, + -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) + IPU_NUMBER_OUT => ipu_number, + IPU_INFORMATION_OUT => ipu_information, + IPU_START_READOUT_OUT => ipu_start_readout, + IPU_DATA_IN => ipu_data, + IPU_DATAREADY_IN => ipu_dataready, + IPU_READOUT_FINISHED_IN => ipu_readout_finished, + IPU_READ_OUT => ipu_read, + IPU_LENGTH_IN => ipu_length, + IPU_ERROR_PATTERN_IN => ipu_error_pattern, + -- regIO bus + REGIO_ADDR_OUT => regio_addr, + REGIO_READ_ENABLE_OUT => regio_read_enable, + REGIO_WRITE_ENABLE_OUT => regio_write_enable, + REGIO_DATA_OUT => regio_data_wr, + REGIO_DATA_IN => regio_data_rd, + REGIO_DATAREADY_IN => regio_dataready, + REGIO_NO_MORE_DATA_IN => regio_no_more_data, + REGIO_WRITE_ACK_IN => regio_write_ack, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr, + REGIO_TIMEOUT_OUT => regio_timeout, + -- status LEDs + LED_LINK_STAT => fpga_led_link, + LED_LINK_TXD => fpga_led_txd, + LED_LINK_RXD => fpga_led_rxd, + LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits + RESET_OUT => reset_by_trb, + DEBUG => trbrich_debug --open + ); + +-- LVL1 error pattern, to be sent back to CTS with each trigger +lvl1_error_pattern(31 downto 22) <= (others => '0'); +lvl1_error_pattern(21) <= '0'; -- buffers almost full +lvl1_error_pattern(20) <= '0'; -- buffers half full +lvl1_error_pattern(19 downto 18) <= (others => '0'); +lvl1_error_pattern(17) <= '0'; -- lvl1_trg_missing; -- missing timing trigger +lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan) +lvl1_error_pattern(15 downto 0) <= (others => '0'); + + +------------------------------------------------------------------ +-- DEBUG DEBUG DEBUG +------------------------------------------------------------------ +debug_clk <= sysclk; + +--debug(42 downto 0) <= (others => '0'); + +debug(42 downto 39) <= (others => '0'); +-- IPU signals +debug(38 downto 35) <= ipu_number(3 downto 0); +debug(34) <= ipu_start_readout; +debug(33) <= ipu_dataready; +debug(32) <= ipu_read; +debug(31) <= ipu_readout_finished; +-- FIFO signals +debug(30) <= fifo_start; -- ped_corr_ctrl -> ipu_stage => data procession starts (unused in ipu_stage) +debug(29) <= fifo_we(0); -- ped_corr_ctrl -> ipu_stage => transfer processed data into data FIFO (0) +debug(28) <= fifo_done; -- ped_corr_ctrl -> ipu_stage => store length count data in small FIFOs +debug(27) <= dhdr_store; -- ped_corr_ctrl -> ipu_stage => store DHDR information for IPU +debug(26) <= dhdr_buf_full; -- ipu_stage -> +-- EventDataSheet / buffer signals +debug(25) <= buf_done; -- ped_corr_ctrl -> raw_buf_stage => raw data has been processed +debug(24) <= buf_tick(0); -- raw_buf_stage -> ped_corr_ctrl => synced tickmarks +debug(23) <= buf_ready(0); -- raw_buf_stage => adc_last +debug(22) <= buf_start(0); -- raw_buf_stage -> ped_corr_ctrl => adc_start +debug(21 downto 17) <= buf_data(0)(34 downto 30); +debug(16) <= raw_buf_full; -- raw_buf_stage -> apv_trgctrl => at least one raw buffer is full +debug(15) <= eds_done; -- ped_corr_ctrl -> apv_trgctrl => EDS data has been transfered, release buffer entry +debug(14) <= eds_avail; -- apv_trgctrl -> ped_corr_ctrl => at least one EDS is available +debug(13) <= eds_buf_full; -- apv_trgctrl => EDS buffer is full +debug(12 downto 8) <= eds_buf_level; +-- timing trigger signals +debug(7) <= timing_trg_found; -- apv_trgctrl -> endpoint => timing trigger has arrived +debug(6) <= lvl1_trg_received; -- endpoint -> apv_trgctrl => LVL1 trigger packet has arrived +debug(5) <= lvl1_trg_missing; -- apv_trgctrl -> endpoint => two consecutive timing triggers found +debug(4) <= lvl1_trg_release; -- apv_trgctrl -> endpoint => release LVL1 busy +debug(3 downto 0) <= lvl1_trg_number(3 downto 0); + + +---------------------------------------------- +-- mixed status and control bit definitions -- +---------------------------------------------- + +-- Common status register +common_stat_reg(63 downto 48) <= (others => '0'); -- LVL2 counter +common_stat_reg(47 downto 32) <= (others => '0'); -- LVL1 counter (doen by Jan) +common_stat_reg(31 downto 20) <= x"000"; -- reserved for temp sensor +common_stat_reg(19 downto 6) <= (others => '0'); +common_stat_reg(5) <= '0'; -- LVL2 counter mismatch +common_stat_reg(4) <= '0'; -- LVL1 counter mismatch (done by Jan) +common_stat_reg(3 downto 0) <= (others => '0'); + +-- Control register bit padding +ctrl_bithigh <= ctrl_lvl(31 downto 24) & x"0"; +ctrl_bitlow <= ctrl_lvl(23 downto 16) & x"0"; +ctrl_flathigh <= ctrl_lvl(15 downto 8) & x"0"; +ctrl_flatlow <= ctrl_lvl(7 downto 0) & x"0"; + +-- LVDS driver enable +ena_lvds(0) <= adc_on(4) or lvds_on(4); +ena_lvds(1) <= adc_on(3) or lvds_on(3); +ena_lvds(2) <= adc_on(5) or lvds_on(5); +ena_lvds(3) <= adc_on(2) or lvds_on(2); +ena_lvds(4) <= adc_on(6) or lvds_on(6); +ena_lvds(5) <= adc_on(1) or lvds_on(1); +ena_lvds(6) <= adc_on(7) or lvds_on(7); +ena_lvds(7) <= adc_on(0) or lvds_on(0); + +enb_lvds(0) <= adc_on(13) or lvds_on(13); +enb_lvds(1) <= adc_on(10) or lvds_on(10); +enb_lvds(2) <= adc_on(12) or lvds_on(12); +enb_lvds(3) <= adc_on(11) or lvds_on(11); +enb_lvds(4) <= adc_on(15) or lvds_on(15); +enb_lvds(5) <= adc_on(8) or lvds_on(8); +enb_lvds(6) <= adc_on(14) or lvds_on(14); +enb_lvds(7) <= adc_on(9) or lvds_on(9); + +bp_led <= '1'; -- LED is against GND! + + +---------------------------------------- +-- internal slave bus -> slow control -- +---------------------------------------- +THE_SLAVE_BUS: slave_bus +port map( CLK_IN => sysclk, + RESET_IN => global_sync_reset, + -- RegIO signals + REGIO_ADDR_IN => regio_addr, + REGIO_DATA_IN => regio_data_wr, + REGIO_DATA_OUT => regio_data_rd, + REGIO_READ_ENABLE_IN => regio_read_enable, + REGIO_WRITE_ENABLE_IN => regio_write_enable, + REGIO_TIMEOUT_IN => regio_timeout, + REGIO_DATAREADY_OUT => regio_dataready, + REGIO_WRITE_ACK_OUT => regio_write_ack, + REGIO_NO_MORE_DATA_OUT => regio_no_more_data, + REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr, + -- I2C connections + SDA_IN => apv_sda_in, + SDA_OUT => apv_sda_out, + SCL_IN => apv_scl_in, + SCL_OUT => apv_scl_out, + -- 1Wire connections + ONEWIRE_START_IN => '0', -- not used yet + ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0), + ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0), + BP_ONEWIRE_INOUT => bp_onewire, + -- SPI connections + SPI_CS_OUT => u_spi_cs, + SPI_SCK_OUT => u_spi_sck, + SPI_SDI_IN => u_spi_sdo, + SPI_SDO_OUT => u_spi_sdi, + -- ADC 0 SPI connections + SPI_ADC0_CS_OUT => adc0_cs, + SPI_ADC0_SCK_OUT => adc0_sck, + SPI_ADC0_SDO_OUT => adc0_sdi, + ADC0_PLL_LOCKED_IN => adc0_valid, + ADC0_PD_OUT => adc0_powerdown, + ADC0_RST_OUT => adc0_reset, + ADC0_DEL_OUT => adc0_iodelay, + ADC0_CLK_IN => clk_apv, + ADC0_DATA_IN => adc0_testdata, + ADC0_SEL_OUT => adc0_select, + APV0_RST_OUT => apv0_reset, + -- ADC 0 SPI connections + SPI_ADC1_CS_OUT => adc1_cs, + SPI_ADC1_SCK_OUT => adc1_sck, + SPI_ADC1_SDO_OUT => adc1_sdi, + ADC1_PLL_LOCKED_IN => adc1_valid, + ADC1_PD_OUT => adc1_powerdown, + ADC1_RST_OUT => adc1_reset, + ADC1_DEL_OUT => adc1_iodelay, + ADC1_CLK_IN => clk_apv, + ADC1_DATA_IN => adc1_testdata, + ADC1_SEL_OUT => adc1_select, + APV1_RST_OUT => apv1_reset, + -- backplane identifier + BACKPLANE_IN => bp_module_qq(2 downto 0), + -- pedestal interface + PED_ADDR_IN => buf_addr, + PED_DATA_0_OUT => ped_data(0), + PED_DATA_1_OUT => ped_data(1), + PED_DATA_2_OUT => ped_data(2), + PED_DATA_3_OUT => ped_data(3), + PED_DATA_4_OUT => ped_data(4), + PED_DATA_5_OUT => ped_data(5), + PED_DATA_6_OUT => ped_data(6), + PED_DATA_7_OUT => ped_data(7), + PED_DATA_8_OUT => ped_data(8), + PED_DATA_9_OUT => ped_data(9), + PED_DATA_10_OUT => ped_data(10), + PED_DATA_11_OUT => ped_data(11), + PED_DATA_12_OUT => ped_data(12), + PED_DATA_13_OUT => ped_data(13), + PED_DATA_14_OUT => ped_data(14), + PED_DATA_15_OUT => ped_data(15), + -- threshold interface + THR_ADDR_IN => thr_addr, + THR_DATA_0_OUT => thr_data(0), + THR_DATA_1_OUT => thr_data(1), + THR_DATA_2_OUT => thr_data(2), + THR_DATA_3_OUT => thr_data(3), + THR_DATA_4_OUT => thr_data(4), + THR_DATA_5_OUT => thr_data(5), + THR_DATA_6_OUT => thr_data(6), + THR_DATA_7_OUT => thr_data(7), + THR_DATA_8_OUT => thr_data(8), + THR_DATA_9_OUT => thr_data(9), + THR_DATA_10_OUT => thr_data(10), + THR_DATA_11_OUT => thr_data(11), + THR_DATA_12_OUT => thr_data(12), + THR_DATA_13_OUT => thr_data(13), + THR_DATA_14_OUT => thr_data(14), + THR_DATA_15_OUT => thr_data(15), + -- APV control / status + CTRL_0_OUT => adc_ctrl_reg(0), + CTRL_1_OUT => adc_ctrl_reg(1), + CTRL_2_OUT => adc_ctrl_reg(2), + CTRL_3_OUT => adc_ctrl_reg(3), + CTRL_4_OUT => adc_ctrl_reg(4), + CTRL_5_OUT => adc_ctrl_reg(5), + CTRL_6_OUT => adc_ctrl_reg(6), + CTRL_7_OUT => adc_ctrl_reg(7), + CTRL_8_OUT => adc_ctrl_reg(8), + CTRL_9_OUT => adc_ctrl_reg(9), + CTRL_10_OUT => adc_ctrl_reg(10), + CTRL_11_OUT => adc_ctrl_reg(11), + CTRL_12_OUT => adc_ctrl_reg(12), + CTRL_13_OUT => adc_ctrl_reg(13), + CTRL_14_OUT => adc_ctrl_reg(14), + CTRL_15_OUT => adc_ctrl_reg(15), + STAT_0_IN => adc_stat_reg(0), + STAT_1_IN => adc_stat_reg(1), + STAT_2_IN => adc_stat_reg(2), + STAT_3_IN => adc_stat_reg(3), + STAT_4_IN => adc_stat_reg(4), + STAT_5_IN => adc_stat_reg(5), + STAT_6_IN => adc_stat_reg(6), + STAT_7_IN => adc_stat_reg(7), + STAT_8_IN => adc_stat_reg(8), + STAT_9_IN => adc_stat_reg(9), + STAT_10_IN => adc_stat_reg(10), + STAT_11_IN => adc_stat_reg(11), + STAT_12_IN => adc_stat_reg(12), + STAT_13_IN => adc_stat_reg(13), + STAT_14_IN => adc_stat_reg(14), + STAT_15_IN => adc_stat_reg(15), + -- some control signals + CTRL_LVL_OUT => ctrl_lvl, + CTRL_TRG_OUT => ctrl_trg, + CTRL_PLL_OUT => ctrl_pll, + STATUS_PLL_IN => status_pll, + -- temporary stuff + TEST_REG_IN => test_reg, -- short cut + TEST_REG_OUT => test_reg, + -- Debug + DEBUG_OUT => slave_debug, --open + STAT => open + ); + +-- PLL status register +status_pll(15) <= clk100m_locked; +status_pll(14) <= clk40m_locked; +status_pll(13) <= adc1_valid; +status_pll(12) <= adc0_valid; +status_pll(11 downto 8) <= (others => '0'); +status_pll(7) <= '0'; -- make it human readable +status_pll(6 downto 4) <= bp_sector_qq(2 downto 0); -- given by backplane DIP switch, for readback only +status_pll(3) <= '0'; -- make it human readable +status_pll(2 downto 0) <= bp_module_qq(2 downto 0); -- given by backplane DIP switch, for readback only + +-- Common status register, do not use. +simple_status(127 downto 104) <= (others => '0'); +simple_status(103 downto 96) <= trgctrl_debug(39 downto 32); +simple_status(95 downto 64) <= trgctrl_debug(31 downto 0); +simple_status(63 downto 32) <= (others => '0'); +simple_status(31 downto 16) <= local_lvl2_counter; +simple_status(15 downto 0) <= local_lvl1_counter; + +-- all APVs are reset together +apv_reset <= apv0_reset or apv1_reset; + +-- APV status registers +adc_stat_reg(15) <= buf_data(15)(37 downto 30) & raw_buf_debug(63 downto 60) & x"f"; +adc_stat_reg(14) <= buf_data(14)(37 downto 30) & raw_buf_debug(59 downto 56) & x"e"; +adc_stat_reg(13) <= buf_data(13)(37 downto 30) & raw_buf_debug(55 downto 52) & x"d"; +adc_stat_reg(12) <= buf_data(12)(37 downto 30) & raw_buf_debug(51 downto 48) & x"c"; +adc_stat_reg(11) <= buf_data(11)(37 downto 30) & raw_buf_debug(47 downto 44) & x"b"; +adc_stat_reg(10) <= buf_data(10)(37 downto 30) & raw_buf_debug(43 downto 40) & x"a"; +adc_stat_reg(9) <= buf_data(9)(37 downto 30) & raw_buf_debug(39 downto 36) & x"9"; +adc_stat_reg(8) <= buf_data(8)(37 downto 30) & raw_buf_debug(35 downto 32) & x"8"; +adc_stat_reg(7) <= buf_data(7)(37 downto 30) & raw_buf_debug(31 downto 28) & x"7"; +adc_stat_reg(6) <= buf_data(6)(37 downto 30) & raw_buf_debug(27 downto 24) & x"6"; +adc_stat_reg(5) <= buf_data(5)(37 downto 30) & raw_buf_debug(23 downto 20) & x"5"; +adc_stat_reg(4) <= buf_data(4)(37 downto 30) & raw_buf_debug(19 downto 16) & x"4"; +adc_stat_reg(3) <= buf_data(3)(37 downto 30) & raw_buf_debug(15 downto 12) & x"3"; +adc_stat_reg(2) <= buf_data(2)(37 downto 30) & raw_buf_debug(11 downto 8) & x"2"; +adc_stat_reg(1) <= buf_data(1)(37 downto 30) & raw_buf_debug(7 downto 4) & x"1"; +adc_stat_reg(0) <= buf_data(0)(37 downto 30) & raw_buf_debug(3 downto 0) & x"0"; + +adc_on(15) <= adc_ctrl_reg(15)(0); +adc_on(14) <= adc_ctrl_reg(14)(0); +adc_on(13) <= adc_ctrl_reg(13)(0); +adc_on(12) <= adc_ctrl_reg(12)(0); +adc_on(11) <= adc_ctrl_reg(11)(0); +adc_on(10) <= adc_ctrl_reg(10)(0); +adc_on(9) <= adc_ctrl_reg(9)(0); +adc_on(8) <= adc_ctrl_reg(8)(0); +adc_on(7) <= adc_ctrl_reg(7)(0); +adc_on(6) <= adc_ctrl_reg(6)(0); +adc_on(5) <= adc_ctrl_reg(5)(0); +adc_on(4) <= adc_ctrl_reg(4)(0); +adc_on(3) <= adc_ctrl_reg(3)(0); +adc_on(2) <= adc_ctrl_reg(2)(0); +adc_on(1) <= adc_ctrl_reg(1)(0); +adc_on(0) <= adc_ctrl_reg(0)(0); + +lvds_on(15) <= adc_ctrl_reg(15)(1); +lvds_on(14) <= adc_ctrl_reg(14)(1); +lvds_on(13) <= adc_ctrl_reg(13)(1); +lvds_on(12) <= adc_ctrl_reg(12)(1); +lvds_on(11) <= adc_ctrl_reg(11)(1); +lvds_on(10) <= adc_ctrl_reg(10)(1); +lvds_on(9) <= adc_ctrl_reg(9)(1); +lvds_on(8) <= adc_ctrl_reg(8)(1); +lvds_on(7) <= adc_ctrl_reg(7)(1); +lvds_on(6) <= adc_ctrl_reg(6)(1); +lvds_on(5) <= adc_ctrl_reg(5)(1); +lvds_on(4) <= adc_ctrl_reg(4)(1); +lvds_on(3) <= adc_ctrl_reg(3)(1); +lvds_on(2) <= adc_ctrl_reg(2)(1); +lvds_on(1) <= adc_ctrl_reg(1)(1); +lvds_on(0) <= adc_ctrl_reg(0)(1); + + +---------------------------------------- +-- IPU endpoint for data transport -- +---------------------------------------- +THE_IPU_STAGE: ipu_fifo_stage +port map( CLK_IN => sysclk, + RESET_IN => global_sync_reset, + -- Slow control signals + SECTOR_IN => bp_sector_qq(2 downto 0), + MODULE_IN => bp_module_qq(2 downto 0), + -- IPU channel connections + IPU_NUMBER_IN => ipu_number, + IPU_INFORMATION_IN => ipu_information, + IPU_START_READOUT_IN => ipu_start_readout, + IPU_DATA_OUT => ipu_data, + IPU_DATAREADY_OUT => ipu_dataready, + IPU_READOUT_FINISHED_OUT => ipu_readout_finished, + IPU_READ_IN => ipu_read, + IPU_LENGTH_OUT => ipu_length, + IPU_ERROR_PATTERN_OUT => ipu_error_pattern, + LVL2_COUNTER_OUT => local_lvl2_counter, + -- DHDR buffer input + DHDR_DATA_IN => dhdr_data, + DHDR_LENGTH_IN => dhdr_length, + DHDR_STORE_IN => dhdr_store, + DHDR_BUF_FULL_OUT => dhdr_buf_full, + -- processed data input + FIFO_START_IN => fifo_start, + FIFO_0_DATA_IN => fifo_data(0), + FIFO_1_DATA_IN => fifo_data(1), + FIFO_2_DATA_IN => fifo_data(2), + FIFO_3_DATA_IN => fifo_data(3), + FIFO_4_DATA_IN => fifo_data(4), + FIFO_5_DATA_IN => fifo_data(5), + FIFO_6_DATA_IN => fifo_data(6), + FIFO_7_DATA_IN => fifo_data(7), + FIFO_8_DATA_IN => fifo_data(8), + FIFO_9_DATA_IN => fifo_data(9), + FIFO_10_DATA_IN => fifo_data(10), + FIFO_11_DATA_IN => fifo_data(11), + FIFO_12_DATA_IN => fifo_data(12), + FIFO_13_DATA_IN => fifo_data(13), + FIFO_14_DATA_IN => fifo_data(14), + FIFO_15_DATA_IN => fifo_data(15), + FIFO_WE_IN => fifo_we, + FIFO_DONE_IN => fifo_done, + -- Debug signals + DBG_BSM_OUT => open, + DBG_OUT => fifo_debug --open + ); + + +---------------------------------------- +-- Data processing unit -- +---------------------------------------- +THE_PED_CORR_STAGE: ped_corr_ctrl +port map( CLK_IN => sysclk, + RESET_IN => global_sync_reset, + EDS_DATA_IN => eds_data, + EDS_AVAIL_IN => eds_avail, + EDS_DONE_OUT => eds_done, + EVT_TYPE_IN => b"000", -- BUG + -- DHDR information -- to next stage + DHDR_DATA_OUT => dhdr_data, + DHDR_LENGTH_OUT => dhdr_length, + DHDR_STORE_OUT => dhdr_store, + DHDR_BUF_FULL_IN => dhdr_buf_full, + -- data buffers -- from raw_buf_stage + BUF_ADDR_OUT => buf_addr, + BUF_DONE_OUT => buf_done, + BUF_TICK_IN => buf_tick, + BUF_START_IN => buf_start, + -- raw data + BUF_0_DATA_IN => buf_data(0), + BUF_1_DATA_IN => buf_data(1), + BUF_2_DATA_IN => buf_data(2), + BUF_3_DATA_IN => buf_data(3), + BUF_4_DATA_IN => buf_data(4), + BUF_5_DATA_IN => buf_data(5), + BUF_6_DATA_IN => buf_data(6), + BUF_7_DATA_IN => buf_data(7), + BUF_8_DATA_IN => buf_data(8), + BUF_9_DATA_IN => buf_data(9), + BUF_10_DATA_IN => buf_data(10), + BUF_11_DATA_IN => buf_data(11), + BUF_12_DATA_IN => buf_data(12), + BUF_13_DATA_IN => buf_data(13), + BUF_14_DATA_IN => buf_data(14), + BUF_15_DATA_IN => buf_data(15), + -- Pedestal data + PED_ADDR_OUT => open, -- BUGBUGBUG + PED_0_DATA_IN => ped_data(0), + PED_1_DATA_IN => ped_data(1), + PED_2_DATA_IN => ped_data(2), + PED_3_DATA_IN => ped_data(3), + PED_4_DATA_IN => ped_data(4), + PED_5_DATA_IN => ped_data(5), + PED_6_DATA_IN => ped_data(6), + PED_7_DATA_IN => ped_data(7), + PED_8_DATA_IN => ped_data(8), + PED_9_DATA_IN => ped_data(9), + PED_10_DATA_IN => ped_data(10), + PED_11_DATA_IN => ped_data(11), + PED_12_DATA_IN => ped_data(12), + PED_13_DATA_IN => ped_data(13), + PED_14_DATA_IN => ped_data(14), + PED_15_DATA_IN => ped_data(15), + -- Threshold data + THR_ADDR_OUT => thr_addr, + THR_0_DATA_IN => thr_data(0), + THR_1_DATA_IN => thr_data(1), + THR_2_DATA_IN => thr_data(2), + THR_3_DATA_IN => thr_data(3), + THR_4_DATA_IN => thr_data(4), + THR_5_DATA_IN => thr_data(5), + THR_6_DATA_IN => thr_data(6), + THR_7_DATA_IN => thr_data(7), + THR_8_DATA_IN => thr_data(8), + THR_9_DATA_IN => thr_data(9), + THR_10_DATA_IN => thr_data(10), + THR_11_DATA_IN => thr_data(11), + THR_12_DATA_IN => thr_data(12), + THR_13_DATA_IN => thr_data(13), + THR_14_DATA_IN => thr_data(14), + THR_15_DATA_IN => thr_data(15), + -- processed data + FIFO_START_OUT => fifo_start, + FIFO_0_DATA_OUT => fifo_data(0), + FIFO_1_DATA_OUT => fifo_data(1), + FIFO_2_DATA_OUT => fifo_data(2), + FIFO_3_DATA_OUT => fifo_data(3), + FIFO_4_DATA_OUT => fifo_data(4), + FIFO_5_DATA_OUT => fifo_data(5), + FIFO_6_DATA_OUT => fifo_data(6), + FIFO_7_DATA_OUT => fifo_data(7), + FIFO_8_DATA_OUT => fifo_data(8), + FIFO_9_DATA_OUT => fifo_data(9), + FIFO_10_DATA_OUT => fifo_data(10), + FIFO_11_DATA_OUT => fifo_data(11), + FIFO_12_DATA_OUT => fifo_data(12), + FIFO_13_DATA_OUT => fifo_data(13), + FIFO_14_DATA_OUT => fifo_data(14), + FIFO_15_DATA_OUT => fifo_data(15), + FIFO_WE_OUT => fifo_we, + FIFO_DONE_OUT => fifo_done, + -- Debug signals + DBG_BSM_OUT => open, + DBG_OUT => open + ); + + +------------------------------------------ +-- Raw data processing and storage unit -- +------------------------------------------ +THE_RAW_BUF_STAGE: raw_buf_stage_new +port map( CLK_IN => sysclk, + CLK_APV_IN => clk_apv, + RESET_IN => reset_by_trb, + -- trigger related signals + APV_RESET_IN => apv_reset, -- (100MHz clock) + APV_SYNC_IN => apv_sync, -- (40MHz APV clock) + APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock) + -- ADC0 signals + ADC0_VALID_IN => adc0_valid, + ADC0_0_DATA_IN => adc_data(0), + ADC0_1_DATA_IN => adc_data(1), + ADC0_2_DATA_IN => adc_data(2), + ADC0_3_DATA_IN => adc_data(3), + ADC0_4_DATA_IN => adc_data(4), + ADC0_5_DATA_IN => adc_data(5), + ADC0_6_DATA_IN => adc_data(6), + ADC0_7_DATA_IN => adc_data(7), + -- ADC1 signals + ADC1_VALID_IN => adc1_valid, + ADC1_0_DATA_IN => adc_data(8), + ADC1_1_DATA_IN => adc_data(9), + ADC1_2_DATA_IN => adc_data(10), + ADC1_3_DATA_IN => adc_data(11), + ADC1_4_DATA_IN => adc_data(12), + ADC1_5_DATA_IN => adc_data(13), + ADC1_6_DATA_IN => adc_data(14), + ADC1_7_DATA_IN => adc_data(15), + -- Slow control registers + MAX_TRG_NUM_IN => maximum_trg, -- automatically determined + BIT_LOW_IN => ctrl_bitlow, -- from slow control + BIT_HIGH_IN => ctrl_bithigh, -- from slow control + FL_LOW_IN => ctrl_flatlow, -- from slow control + FL_HIGH_IN => ctrl_flathigh, -- from slow control + APV_ON_IN => adc_on, + -- 100MHZ synchronous interface + -- APV raw buffers + BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW + BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl + BUF_DONE_IN => buf_done, -- from ped_corr_ctrl + BUF_TICK_OUT => buf_tick, + BUF_START_OUT => buf_start, + BUF_READY_OUT => buf_ready, + BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl + BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl + BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl + BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl + BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl + BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl + BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl + BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl + BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl + BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl + BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl + BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl + BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl + BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl + BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl + BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl + -- Debug signals + DEBUG_OUT => raw_buf_debug --open + ); + + +---------------------------------------- +-- ADC1 data handler -- +---------------------------------------- +THE_ADC1_HANDLER: adc_data_handler_new +port map( RESET_IN => reset_by_trb, + ADC_LCLK_IN => adc1_lclk, + ADC_ADCLK_IN => adc1_adclk, + ADC_CHNL_IN => adc1_out, + PLL_CTRL_IN => adc1_iodelay, + ADC_DATA7_OUT => adc_raw_data(15), + ADC_DATA6_OUT => adc_raw_data(14), + ADC_DATA5_OUT => adc_raw_data(13), + ADC_DATA4_OUT => adc_raw_data(12), + ADC_DATA3_OUT => adc_raw_data(11), + ADC_DATA2_OUT => adc_raw_data(10), + ADC_DATA1_OUT => adc_raw_data(9), + ADC_DATA0_OUT => adc_raw_data(8), + ADC_CE_OUT => adc1_ce, + ADC_VALID_OUT => adc1_valid, + DEBUG_OUT => open + ); + + +---------------------------------------- +-- ADC1 clock domain crossover -- +---------------------------------------- +THE_ADC1_CROSSOVER: adc_crossover +port map( CLK_APV_IN => clk_apv, + RESET_IN => global_sync_reset, + -- ADC clock domain signals + ADC_CLK_IN => adc1_lclk, + ADC_CE_IN => adc1_ce, + ADC_DATA_VALID_IN => adc1_valid, + ADC_DATA_7_IN => adc_raw_data(15), + ADC_DATA_6_IN => adc_raw_data(14), + ADC_DATA_5_IN => adc_raw_data(13), + ADC_DATA_4_IN => adc_raw_data(12), + ADC_DATA_3_IN => adc_raw_data(11), + ADC_DATA_2_IN => adc_raw_data(10), + ADC_DATA_1_IN => adc_raw_data(9), + ADC_DATA_0_IN => adc_raw_data(8), + LEVEL_WR_OUT => open, + -- APV clock domain signals + APV_DATA_7_OUT => adc_data(15), + APV_DATA_6_OUT => adc_data(14), + APV_DATA_5_OUT => adc_data(13), + APV_DATA_4_OUT => adc_data(12), + APV_DATA_3_OUT => adc_data(11), + APV_DATA_2_OUT => adc_data(10), + APV_DATA_1_OUT => adc_data(9), + APV_DATA_0_OUT => adc_data(8), + APV_DATA_VALID_OUT => open, + LEVEL_RD_OUT => open, + -- Debug signals + DEBUG_OUT => open + ); + + +---------------------------------------- +-- ADC1 test data multiplexer -- +---------------------------------------- +THE_ADC_1_SELECT: adc_channel_select +port map( RESET_IN => reset_by_trb, + ADC_CLK_IN => clk_apv, + ADC_SEL_IN => adc1_select, + ADC_7_IN => adc_data(15), + ADC_6_IN => adc_data(14), + ADC_5_IN => adc_data(13), + ADC_4_IN => adc_data(12), + ADC_3_IN => adc_data(11), + ADC_2_IN => adc_data(10), + ADC_1_IN => adc_data(9), + ADC_0_IN => adc_data(8), + ADC_CH_OUT => adc1_testdata, + DEBUG_OUT => open + ); + + +---------------------------------------- +-- ADC0 data handler -- +---------------------------------------- +THE_ADC0_HANDLER: adc_data_handler_new +port map( RESET_IN => reset_by_trb, + ADC_LCLK_IN => adc0_lclk, + ADC_ADCLK_IN => adc0_adclk, + ADC_CHNL_IN => adc0_out, + PLL_CTRL_IN => adc0_iodelay, + ADC_DATA7_OUT => adc_raw_data(7), + ADC_DATA6_OUT => adc_raw_data(6), + ADC_DATA5_OUT => adc_raw_data(5), + ADC_DATA4_OUT => adc_raw_data(4), + ADC_DATA3_OUT => adc_raw_data(3), + ADC_DATA2_OUT => adc_raw_data(2), + ADC_DATA1_OUT => adc_raw_data(1), + ADC_DATA0_OUT => adc_raw_data(0), + ADC_CE_OUT => adc0_ce, + ADC_VALID_OUT => adc0_valid, + DEBUG_OUT => open + ); + + +---------------------------------------- +-- ADC0 clock domain crossover -- +---------------------------------------- +THE_ADC0_CROSSOVER: adc_crossover +port map( CLK_APV_IN => clk_apv, + RESET_IN => global_sync_reset, + -- ADC clock domain signals + ADC_CLK_IN => adc0_lclk, + ADC_CE_IN => adc0_ce, + ADC_DATA_VALID_IN => adc0_valid, + ADC_DATA_7_IN => adc_raw_data(7), + ADC_DATA_6_IN => adc_raw_data(6), + ADC_DATA_5_IN => adc_raw_data(5), + ADC_DATA_4_IN => adc_raw_data(4), + ADC_DATA_3_IN => adc_raw_data(3), + ADC_DATA_2_IN => adc_raw_data(2), + ADC_DATA_1_IN => adc_raw_data(1), + ADC_DATA_0_IN => adc_raw_data(0), + LEVEL_WR_OUT => open, + -- APV clock domain signals + APV_DATA_7_OUT => adc_data(7), + APV_DATA_6_OUT => adc_data(6), + APV_DATA_5_OUT => adc_data(5), + APV_DATA_4_OUT => adc_data(4), + APV_DATA_3_OUT => adc_data(3), + APV_DATA_2_OUT => adc_data(2), + APV_DATA_1_OUT => adc_data(1), + APV_DATA_0_OUT => adc_data(0), + APV_DATA_VALID_OUT => open, + LEVEL_RD_OUT => open, + -- Debug signals + DEBUG_OUT => open + ); + + +---------------------------------------- +-- ADC0 test data multiplexer -- +---------------------------------------- +THE_ADC_0_SELECT: adc_channel_select +port map( RESET_IN => reset_by_trb, + ADC_CLK_IN => clk_apv, + ADC_SEL_IN => adc0_select, + ADC_7_IN => adc_data(7), + ADC_6_IN => adc_data(6), + ADC_5_IN => adc_data(5), + ADC_4_IN => adc_data(4), + ADC_3_IN => adc_data(3), + ADC_2_IN => adc_data(2), + ADC_1_IN => adc_data(1), + ADC_0_IN => adc_data(0), + ADC_CH_OUT => adc0_testdata, + DEBUG_OUT => open + ); + + +---------------------------------------- +-- Trigger handler (APV specific) -- +---------------------------------------- +THE_APV_TRGCTRL: apv_trgctrl +port map( CLK_IN => sysclk, + RESET_IN => global_sync_reset, + CLK_APV_IN => clk_apv, + -- Triggers + SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse + TIME_TRG_IN => ext_in, -- external trigger inputs + TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers + STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers. + TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint + -- slow control settings + TRG_MAX_OUT => maximum_trg, + TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control + TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control + TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control + TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control + TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control + TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control + TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control + TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control + TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control + -- TRB LVL1 signals + TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint + TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint + TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint + TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint + TRB_MISSING_OUT => lvl1_trg_missing, + TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint + TRB_RST_COUNTER_IN => common_ctrl_reg(30), -- depreciated! + TRB_COUNTER_OUT => local_lvl1_counter, + -- EDS signals + EDS_DATA_OUT => eds_data, -- to ped_corr_stage + EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage + EDS_DONE_IN => eds_done, -- from ped_corr_stage + EDS_FULL_OUT => eds_buf_full, + EDS_LEVEL_OUT => eds_buf_level, + FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock) + -- APV signals + APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock) + APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock) + DEBUG_OUT => trgctrl_debug + ); + + +---------------------------------------- +-- ADC signals -- +---------------------------------------- +adc1_rst <= adc1_reset; +adc1_pd <= adc1_powerdown; + +THE_ADC1CLK_OUT: ODDRXC +port map( DA => '1', + DB => '0', + CLK => clk_adc, + RST => '0', + Q => adc1_clk + ); + +adc0_rst <= adc0_reset; +adc0_pd <= adc0_powerdown; + +THE_ADC0CLK_OUT: ODDRXC +port map( DA => '1', + DB => '0', + CLK => clk_adc, + RST => '0', + Q => adc0_clk + ); + + +---------------------------------------- +-- APV signals -- +---------------------------------------- +-- SDA line output +apv0_sda <= '0' when (apv_sda_out = '0') else 'Z'; +apv1_sda <= '0' when (apv_sda_out = '0') else 'Z'; +-- SDA line input (wired OR negative logic) +apv_sda_in <= apv0_sda and apv1_sda; + +-- SCL line output +apv0_scl <= '0' when (apv_scl_out = '0') else 'Z'; +apv1_scl <= '0' when (apv_scl_out = '0') else 'Z'; +-- SCL line input (wired OR negative logic) +apv_scl_in <= apv0_scl and apv1_scl; + +-- Reset signal with correct polarity +apv0_rst <= not apv_reset; +apv1_rst <= not apv_reset; + +-- CLK and TRG signal +-- CLK is shifted to meet timing constraints of APV +THE_APV0ACLK_OUT: ODDRXC +port map( DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv0a_clk + ); + +THE_APV0BCLK_OUT: ODDRXC +port map( DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv0b_clk + ); + +THE_APV1ACLK_OUT: ODDRXC +port map( DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv1a_clk + ); + +THE_APV1BCLK_OUT: ODDRXC +port map( DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv1b_clk + ); + +THE_APV0ATRG_OUT: ODDRXC +port map( DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv0a_trg + ); +THE_APV0BTRG_OUT: ODDRXC +port map( DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv0b_trg + ); +THE_APV1ATRG_OUT: ODDRXC +port map( DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv1a_trg + ); +THE_APV1BTRG_OUT: ODDRXC +port map( DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv1b_trg + ); + + +---------------------------------------- +-- DIP switch input registers -- +---------------------------------------- +-- switch "OFF" => '1', switch "ON" => '0'; so invert it +THE_BP_SYNC_PROC: process( sysclk ) +begin + if( rising_edge(sysclk) ) then + bp_module_qq <= bp_module_q; + bp_module_q <= not bp_module; + bp_sector_qq <= bp_sector_q; + bp_sector_q <= not bp_sector; + end if; +end process THE_BP_SYNC_PROC; + + +---------------------------------------- +-- Reboot handler (pulse triggered) -- +---------------------------------------- +THE_REBOOT_HANDLER: reboot_handler +port map( RESET_IN => reset_by_trb, + CLK_IN => sysclk, + START_IN => common_ctrl_reg(15), + REBOOT_OUT => uc_reboot, + DEBUG_OUT => open + ); + + +---------------------------------------- +-- FPGA debug header driver -- +---------------------------------------- +THE_DBG_CLK_OUT: ODDRXC +port map( DA => '1', + DB => '0', + CLK => debug_clk, + RST => '0', + Q => dbg_exp(43) + ); + +THE_DEBUG_REG_PROC: process( debug_clk ) +begin + if( rising_edge(debug_clk) ) then + dbg_exp(42 downto 0) <= debug_qq(42 downto 0); + debug_qq(42 downto 0) <= debug_q(42 downto 0); + debug_q(42 downto 0) <= debug(42 downto 0); + end if; +end process THE_DEBUG_REG_PROC; + + +---------------------------------------- +-- LED drivers -- +---------------------------------------- +fpga_led_adc(1) <= not adc1_valid; +fpga_led_adc(0) <= not adc0_valid; +fpga_led(6) <= not lsm_state_bits(0); -- LED "0" +fpga_led(5) <= not lsm_state_bits(1); -- LED "1" +fpga_led(4) <= not lsm_state_bits(2); -- LED "2" +fpga_led(3) <= not lsm_state_bits(3); -- LED "3" +fpga_led_pll <= not clk40m_locked; + + +---------------------------------------- +-- "unused" pins -- +---------------------------------------- + +end adcmv3; diff --git a/src/adcmv3_components.vhd b/src/adcmv3_components.vhd new file mode 100755 index 0000000..f09bf78 --- /dev/null +++ b/src/adcmv3_components.vhd @@ -0,0 +1,1587 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.ALL; +use IEEE.std_logic_UNSIGNED.ALL; + +--library work; +--use work.trb_net_std.all; + +package adcmv3_components is + + component raw_buf_stage_new is + port( CLK_IN : in std_logic; -- 100MHz local clock + CLK_APV_IN : in std_logic; -- 40MHz APV clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- trigger related signals + APV_RESET_IN : in std_logic; -- APV reset signal (100MHz) + APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz) + APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz) + -- ADC0 signals + ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0 + ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1 + ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2 + ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3 + ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4 + ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5 + ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6 + ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7 + -- ADC1 signals + ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0 + ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1 + ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2 + ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3 + ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4 + ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5 + ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6 + ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7 + -- Slow control registers + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold + FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold + APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control + -- 100MHZ synchronous interface + -- APV raw buffers + BUF_FULL_OUT : out std_logic; + BUF_ADDR_IN : in std_logic_vector(6 downto 0); + BUF_DONE_IN : in std_logic; + BUF_TICK_OUT : out std_logic_vector(15 downto 0); + BUF_START_OUT : out std_logic_vector(15 downto 0); + BUF_READY_OUT : out std_logic_vector(15 downto 0); + BUF_0_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_1_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_2_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_3_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_4_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_5_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_6_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_7_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_8_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_9_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_10_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_11_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_12_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_13_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_14_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_15_DATA_OUT : out std_logic_vector(37 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); + end component raw_buf_stage_new; + + component adc_data_handler_new is + port( RESET_IN : in std_logic; + ADC_LCLK_IN : in std_logic; -- LCLK from ADC + ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC + ADC_CHNL_IN : in std_logic_vector(7 downto 0); + PLL_CTRL_IN : in std_logic_vector(3 downto 0); + ADC_DATA7_OUT : out std_logic_vector(11 downto 0); + ADC_DATA6_OUT : out std_logic_vector(11 downto 0); + ADC_DATA5_OUT : out std_logic_vector(11 downto 0); + ADC_DATA4_OUT : out std_logic_vector(11 downto 0); + ADC_DATA3_OUT : out std_logic_vector(11 downto 0); + ADC_DATA2_OUT : out std_logic_vector(11 downto 0); + ADC_DATA1_OUT : out std_logic_vector(11 downto 0); + ADC_DATA0_OUT : out std_logic_vector(11 downto 0); + ADC_CE_OUT : out std_logic; + ADC_VALID_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component adc_data_handler_new; + + component adc_crossover is + port( CLK_APV_IN : in std_logic; -- APV 40MHz local clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- ADC clock domain signals + ADC_CLK_IN : in std_logic; + ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse... + ADC_DATA_VALID_IN : in std_logic; + ADC_DATA_7_IN : in std_logic_vector(11 downto 0); + ADC_DATA_6_IN : in std_logic_vector(11 downto 0); + ADC_DATA_5_IN : in std_logic_vector(11 downto 0); + ADC_DATA_4_IN : in std_logic_vector(11 downto 0); + ADC_DATA_3_IN : in std_logic_vector(11 downto 0); + ADC_DATA_2_IN : in std_logic_vector(11 downto 0); + ADC_DATA_1_IN : in std_logic_vector(11 downto 0); + ADC_DATA_0_IN : in std_logic_vector(11 downto 0); + LEVEL_WR_OUT : out std_logic_vector(4 downto 0); + -- APV clock domain signals + APV_DATA_7_OUT : out std_logic_vector(11 downto 0); + APV_DATA_6_OUT : out std_logic_vector(11 downto 0); + APV_DATA_5_OUT : out std_logic_vector(11 downto 0); + APV_DATA_4_OUT : out std_logic_vector(11 downto 0); + APV_DATA_3_OUT : out std_logic_vector(11 downto 0); + APV_DATA_2_OUT : out std_logic_vector(11 downto 0); + APV_DATA_1_OUT : out std_logic_vector(11 downto 0); + APV_DATA_0_OUT : out std_logic_vector(11 downto 0); + APV_DATA_VALID_OUT : out std_logic; + LEVEL_RD_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + end component adc_crossover; + + component crossover is + port( DATA : in std_logic_vector(95 downto 0); + WRCLOCK : in std_logic; + RDCLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; -- asynchronous reset! + RPRESET : in std_logic; + Q : out std_logic_vector(95 downto 0); + WCNT : out std_logic_vector(4 downto 0); + RCNT : out std_logic_vector(4 downto 0); + EMPTY : out std_logic; + FULL : out std_logic + ); + end component crossover; + + component slv_adc_la is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component slv_adc_la; + +-- NOT USED YET + component logic_analyzer is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- control signals + ARM_IN : in std_logic; -- arm the machine + TRG_IN : in std_logic; -- trigger the data acquisition + MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); + -- status signals + SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses + SM_CE_OUT : out std_logic; + SM_WE_OUT : out std_logic; -- write enable for sample RAM + CLEAR_OUT : out std_logic; -- sample memory is being cleared + RUN_OUT : out std_logic; -- ready for trigger + SAMPLE_OUT : out std_logic; -- data acquisition running + READY_OUT : out std_logic; -- data acquisition is finished + LAST_OUT : out std_logic; -- last data word of sampling + -- Status lines + BSM_OUT : out std_logic_vector(3 downto 0); + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component logic_analyzer; + + component onewire_spare_one is + port( ADDRESS : in std_logic_vector(2 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component onewire_spare_one; + + component adc_onewire_map_mem is + port( ADDRESS : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component adc_onewire_map_mem; + + component adc_channel_select is + port( RESET_IN : in std_logic; + ADC_CLK_IN : in std_logic; + ADC_SEL_IN : in std_logic_vector(2 downto 0); + ADC_7_IN : in std_logic_vector(11 downto 0); + ADC_6_IN : in std_logic_vector(11 downto 0); + ADC_5_IN : in std_logic_vector(11 downto 0); + ADC_4_IN : in std_logic_vector(11 downto 0); + ADC_3_IN : in std_logic_vector(11 downto 0); + ADC_2_IN : in std_logic_vector(11 downto 0); + ADC_1_IN : in std_logic_vector(11 downto 0); + ADC_0_IN : in std_logic_vector(11 downto 0); + ADC_CH_OUT : out std_logic_vector(11 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component slv_adc_snoop is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + component adc_snoop_mem is + port( WRADDRESS : in std_logic_vector(9 downto 0); + RDADDRESS : in std_logic_vector(9 downto 0); + DATA : in std_logic_vector(15 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(15 downto 0) + ); + end component; + + + component max_data is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + TODO_3_IN : in std_logic_vector(3 downto 0); + TODO_2_IN : in std_logic_vector(3 downto 0); + TODO_1_IN : in std_logic_vector(3 downto 0); + TODO_0_IN : in std_logic_vector(3 downto 0); + TODO_MAX_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component comp4bit is + port( DATAA : in std_logic_vector(3 downto 0); + DATAB : in std_logic_vector(3 downto 0); + AGTB : out std_logic + ); + end component; + + component slv_register_bank is + generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" ); + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(3 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + BACKPLANE_IN : in std_logic_vector(2 downto 0); + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + component pulse_stretch is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + PULSE_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component apv_adc_map_mem is + port( ADDRESS : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + component adc_apv_map_mem is + port( ADDRESS : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + + component ped_thr_true is + port( DATAINA : in std_logic_vector(17 downto 0); + DATAINB : in std_logic_vector(17 downto 0); + ADDRESSA : in std_logic_vector(6 downto 0); + ADDRESSB : in std_logic_vector(6 downto 0); + CLOCKA : in std_logic; + CLOCKB : in std_logic; + CLOCKENA : in std_logic; + CLOCKENB : in std_logic; + WRA : in std_logic; + WRB : in std_logic; + RESETA : in std_logic; + RESETB : in std_logic; + QA : out std_logic_vector(17 downto 0); + QB : out std_logic_vector(17 downto 0) + ); + end component; + + component slv_ped_thr_mem is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(10 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(6 downto 0); + MEM_0_D_OUT : out std_logic_vector(17 downto 0); + MEM_1_D_OUT : out std_logic_vector(17 downto 0); + MEM_2_D_OUT : out std_logic_vector(17 downto 0); + MEM_3_D_OUT : out std_logic_vector(17 downto 0); + MEM_4_D_OUT : out std_logic_vector(17 downto 0); + MEM_5_D_OUT : out std_logic_vector(17 downto 0); + MEM_6_D_OUT : out std_logic_vector(17 downto 0); + MEM_7_D_OUT : out std_logic_vector(17 downto 0); + MEM_8_D_OUT : out std_logic_vector(17 downto 0); + MEM_9_D_OUT : out std_logic_vector(17 downto 0); + MEM_10_D_OUT : out std_logic_vector(17 downto 0); + MEM_11_D_OUT : out std_logic_vector(17 downto 0); + MEM_12_D_OUT : out std_logic_vector(17 downto 0); + MEM_13_D_OUT : out std_logic_vector(17 downto 0); + MEM_14_D_OUT : out std_logic_vector(17 downto 0); + MEM_15_D_OUT : out std_logic_vector(17 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + component reset_handler is + port( CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0') + RESET_IN : in std_logic; -- for testing, if not needed, set to '0' + CLK_IN : in std_logic; + TRB_RESET_IN : in std_logic; + RESET_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component pll_40m is + port( CLK : in std_logic; + RESET : in std_logic; + DPAMODE : in std_logic; + DPHASE0 : in std_logic; + DPHASE1 : in std_logic; + DPHASE2 : in std_logic; + DPHASE3 : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + LOCK : out std_logic + ); + end component; + + component dll_100m is + port( CLK : in std_logic; + RESETN : in std_logic; + ALUHOLD : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + LOCK : out std_logic + ); + end component; + + component state_sync is + port( STATE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + STATE_B_OUT : out std_logic + ); + end component; + + component pulse_sync is + port( CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic + ); + end component; + + component rich_trb is + port( CLK100M_IN : in std_logic; + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_PRESENT_IN : in std_logic; + SD_TXDIS_OUT : out std_logic; + SD_LOS_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic; + -- common regIO status / control registers +-- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI + COMMON_STAT_REG_IN : in std_logic_vector(2*32-1 downto 0); -- common status register, bit definitions like in WIKI +-- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI + COMMON_CTRL_REG_OUT : out std_logic_vector(2*32-1 downto 0); -- common control register, bit definitions like in WIKI + -- status register input to regIO / control register output from regIO + CONTROL_OUT : out std_logic_vector(63 downto 0); + STATUS_IN : in std_logic_vector(127 downto 0); + -- LVL1 signals + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_OUT : out std_logic; + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_IN : in std_logic; + TIMING_TRG_FOUND_IN : in std_logic; + -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) + IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_OUT : out std_logic; -- gimme data! + IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_IN : in std_logic; -- data is valid + IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM + IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle + IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern + -- regIO bus +-- REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; +-- REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); +-- REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0); + REGIO_DATAREADY_IN : in std_logic; + REGIO_NO_MORE_DATA_IN : in std_logic; + REGIO_WRITE_ACK_IN : in std_logic; + REGIO_UNKNOWN_ADDR_IN : in std_logic; + REGIO_TIMEOUT_OUT : out std_logic; + -- status LEDs + LED_LINK_STAT : out std_logic; + LED_LINK_TXD : out std_logic; + LED_LINK_RXD : out std_logic; + LINK_BSM_OUT : out std_logic_vector(3 downto 0); + RESET_OUT : out std_logic; + -- Debug + DEBUG : out std_logic_vector(63 downto 0) + ); + end component; + + component slave_bus is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- RegIO signals + REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus + REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint + REGIO_READ_ENABLE_IN : in std_logic; -- read pulse + REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse + REGIO_TIMEOUT_IN : in std_logic; -- access timed out + REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested + REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted + REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now + REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- 1Wire connections + ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse) + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); -- 1Wire ID on APV FEs + BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + -- ADC 0 SPI connections + SPI_ADC0_CS_OUT : out std_logic; + SPI_ADC0_SCK_OUT : out std_logic; + SPI_ADC0_SDO_OUT : out std_logic; + ADC0_PLL_LOCKED_IN : in std_logic; + ADC0_PD_OUT : out std_logic; + ADC0_RST_OUT : out std_logic; + ADC0_DEL_OUT : out std_logic_vector(3 downto 0); + ADC0_CLK_IN : in std_logic; + ADC0_DATA_IN : in std_logic_vector(11 downto 0); + ADC0_SEL_OUT : out std_logic_vector(2 downto 0); + APV0_RST_OUT : out std_logic; + -- ADC 0 SPI connections + SPI_ADC1_CS_OUT : out std_logic; + SPI_ADC1_SCK_OUT : out std_logic; + SPI_ADC1_SDO_OUT : out std_logic; + ADC1_PLL_LOCKED_IN : in std_logic; + ADC1_PD_OUT : out std_logic; + ADC1_RST_OUT : out std_logic; + ADC1_DEL_OUT : out std_logic_vector(3 downto 0); + ADC1_CLK_IN : in std_logic; + ADC1_DATA_IN : in std_logic_vector(11 downto 0); + ADC1_SEL_OUT : out std_logic_vector(2 downto 0); + APV1_RST_OUT : out std_logic; + -- User specific inputs / outputs + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- pedestal interface + PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers + PED_DATA_0_OUT : out std_logic_vector(17 downto 0); + PED_DATA_1_OUT : out std_logic_vector(17 downto 0); + PED_DATA_2_OUT : out std_logic_vector(17 downto 0); + PED_DATA_3_OUT : out std_logic_vector(17 downto 0); + PED_DATA_4_OUT : out std_logic_vector(17 downto 0); + PED_DATA_5_OUT : out std_logic_vector(17 downto 0); + PED_DATA_6_OUT : out std_logic_vector(17 downto 0); + PED_DATA_7_OUT : out std_logic_vector(17 downto 0); + PED_DATA_8_OUT : out std_logic_vector(17 downto 0); + PED_DATA_9_OUT : out std_logic_vector(17 downto 0); + PED_DATA_10_OUT : out std_logic_vector(17 downto 0); + PED_DATA_11_OUT : out std_logic_vector(17 downto 0); + PED_DATA_12_OUT : out std_logic_vector(17 downto 0); + PED_DATA_13_OUT : out std_logic_vector(17 downto 0); + PED_DATA_14_OUT : out std_logic_vector(17 downto 0); + PED_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- threshold interface + THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers + THR_DATA_0_OUT : out std_logic_vector(17 downto 0); + THR_DATA_1_OUT : out std_logic_vector(17 downto 0); + THR_DATA_2_OUT : out std_logic_vector(17 downto 0); + THR_DATA_3_OUT : out std_logic_vector(17 downto 0); + THR_DATA_4_OUT : out std_logic_vector(17 downto 0); + THR_DATA_5_OUT : out std_logic_vector(17 downto 0); + THR_DATA_6_OUT : out std_logic_vector(17 downto 0); + THR_DATA_7_OUT : out std_logic_vector(17 downto 0); + THR_DATA_8_OUT : out std_logic_vector(17 downto 0); + THR_DATA_9_OUT : out std_logic_vector(17 downto 0); + THR_DATA_10_OUT : out std_logic_vector(17 downto 0); + THR_DATA_11_OUT : out std_logic_vector(17 downto 0); + THR_DATA_12_OUT : out std_logic_vector(17 downto 0); + THR_DATA_13_OUT : out std_logic_vector(17 downto 0); + THR_DATA_14_OUT : out std_logic_vector(17 downto 0); + THR_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- APV control / status + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- some control signals + CTRL_LVL_OUT : out std_logic_vector(31 downto 0); + CTRL_TRG_OUT : out std_logic_vector(31 downto 0); + CTRL_PLL_OUT : out std_logic_vector(15 downto 0); + STATUS_PLL_IN : in std_logic_vector(15 downto 0); + -- temporary stuff + TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing! + TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing! + -- Debug + DEBUG_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + component oddrxc is + port( DA : in std_logic; + DB : in std_logic; + CLK : in std_logic; + RST : in std_logic; + Q : out std_logic + ); + end component; + + component apv_trgctrl is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + -- Triggers + SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow + TRG_FOUND_OUT : out std_logic; -- trigger found + -- slow control settings + TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + -- TRB LVL1 signals + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type + TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received + TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger + TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel + TRB_RST_COUNTER_IN : in std_logic; -- reset timing trigger counter + TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); + -- EDS signals + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word + EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done + EDS_DONE_IN : in std_logic; -- release current EDS buffer + EDS_FULL_OUT : out std_logic; -- EDS buffer is full + EDS_LEVEL_OUT : out std_logic_vector(4 downto 0); + FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement) + -- APV signals + APV_TRG_OUT : out std_logic; + APV_SYNC_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); + end component; + + component ped_corr_ctrl is + port( CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control registers + -- EDS buffer -- back to previous source stage + EDS_DATA_IN : in std_logic_vector(39 downto 0); + EDS_AVAIL_IN : in std_logic; + EDS_DONE_OUT : out std_logic; + EVT_TYPE_IN : in std_logic_vector(2 downto 0); + -- DHDR information -- to next stage + DHDR_DATA_OUT : out std_logic_vector(31 downto 0); + DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0); + DHDR_STORE_OUT : out std_logic; + DHDR_BUF_FULL_IN : in std_logic; + -- data buffers -- from raw_buf_stage + BUF_ADDR_OUT : out std_logic_vector(6 downto 0); + BUF_DONE_OUT : out std_logic; + BUF_TICK_IN : in std_logic_vector(15 downto 0); + BUF_START_IN : in std_logic_vector(15 downto 0); + -- raw data + BUF_0_DATA_IN : in std_logic_vector(37 downto 0); + BUF_1_DATA_IN : in std_logic_vector(37 downto 0); + BUF_2_DATA_IN : in std_logic_vector(37 downto 0); + BUF_3_DATA_IN : in std_logic_vector(37 downto 0); + BUF_4_DATA_IN : in std_logic_vector(37 downto 0); + BUF_5_DATA_IN : in std_logic_vector(37 downto 0); + BUF_6_DATA_IN : in std_logic_vector(37 downto 0); + BUF_7_DATA_IN : in std_logic_vector(37 downto 0); + BUF_8_DATA_IN : in std_logic_vector(37 downto 0); + BUF_9_DATA_IN : in std_logic_vector(37 downto 0); + BUF_10_DATA_IN : in std_logic_vector(37 downto 0); + BUF_11_DATA_IN : in std_logic_vector(37 downto 0); + BUF_12_DATA_IN : in std_logic_vector(37 downto 0); + BUF_13_DATA_IN : in std_logic_vector(37 downto 0); + BUF_14_DATA_IN : in std_logic_vector(37 downto 0); + BUF_15_DATA_IN : in std_logic_vector(37 downto 0); + -- Pedestal data + PED_ADDR_OUT : out std_logic_vector(6 downto 0); + PED_0_DATA_IN : in std_logic_vector(17 downto 0); + PED_1_DATA_IN : in std_logic_vector(17 downto 0); + PED_2_DATA_IN : in std_logic_vector(17 downto 0); + PED_3_DATA_IN : in std_logic_vector(17 downto 0); + PED_4_DATA_IN : in std_logic_vector(17 downto 0); + PED_5_DATA_IN : in std_logic_vector(17 downto 0); + PED_6_DATA_IN : in std_logic_vector(17 downto 0); + PED_7_DATA_IN : in std_logic_vector(17 downto 0); + PED_8_DATA_IN : in std_logic_vector(17 downto 0); + PED_9_DATA_IN : in std_logic_vector(17 downto 0); + PED_10_DATA_IN : in std_logic_vector(17 downto 0); + PED_11_DATA_IN : in std_logic_vector(17 downto 0); + PED_12_DATA_IN : in std_logic_vector(17 downto 0); + PED_13_DATA_IN : in std_logic_vector(17 downto 0); + PED_14_DATA_IN : in std_logic_vector(17 downto 0); + PED_15_DATA_IN : in std_logic_vector(17 downto 0); + -- Threshold data + THR_ADDR_OUT : out std_logic_vector(6 downto 0); + THR_0_DATA_IN : in std_logic_vector(17 downto 0); + THR_1_DATA_IN : in std_logic_vector(17 downto 0); + THR_2_DATA_IN : in std_logic_vector(17 downto 0); + THR_3_DATA_IN : in std_logic_vector(17 downto 0); + THR_4_DATA_IN : in std_logic_vector(17 downto 0); + THR_5_DATA_IN : in std_logic_vector(17 downto 0); + THR_6_DATA_IN : in std_logic_vector(17 downto 0); + THR_7_DATA_IN : in std_logic_vector(17 downto 0); + THR_8_DATA_IN : in std_logic_vector(17 downto 0); + THR_9_DATA_IN : in std_logic_vector(17 downto 0); + THR_10_DATA_IN : in std_logic_vector(17 downto 0); + THR_11_DATA_IN : in std_logic_vector(17 downto 0); + THR_12_DATA_IN : in std_logic_vector(17 downto 0); + THR_13_DATA_IN : in std_logic_vector(17 downto 0); + THR_14_DATA_IN : in std_logic_vector(17 downto 0); + THR_15_DATA_IN : in std_logic_vector(17 downto 0); + -- processed data + FIFO_START_OUT : out std_logic; + FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_WE_OUT : out std_logic_vector(15 downto 0); + FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component ipu_fifo_stage is + port( CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control signals + SECTOR_IN : in std_logic_vector(2 downto 0); + MODULE_IN : in std_logic_vector(2 downto 0); + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter + -- DHDR buffer input + DHDR_DATA_IN : in std_logic_vector(31 downto 0); + DHDR_LENGTH_IN : in std_logic_vector(15 downto 0); + DHDR_STORE_IN : in std_logic; + DHDR_BUF_FULL_OUT : out std_logic; + -- processed data input + FIFO_START_IN : in std_logic; + FIFO_0_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_1_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_2_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_3_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_4_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_5_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_6_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_7_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_8_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_9_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_10_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_11_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_12_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_13_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_14_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_15_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_WE_IN : in std_logic_vector(15 downto 0); + FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(63 downto 0) + ); + end component; + + component ipu_dummy is + port( CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control signals + MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value + MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value + CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + -- DHDR buffer + LVL1_FIFO_RD_OUT : out std_logic; + LVL1_FIFO_EMPTY_IN : in std_logic; + LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0); + LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0); + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(63 downto 0) + ); + end component; + + component reboot_handler is + port( RESET_IN : in std_logic; + CLK_IN : in std_logic; + START_IN : in std_logic; + REBOOT_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component real_trg_handler is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse) + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type + TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB + TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger + RST_LVL1_COUNTER_IN : in std_logic; -- reset LVL1 counter + LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); -- LVL1 counter + BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator + APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine + APV_TRGSTART_OUT : out std_logic; -- start one APV trigger state machine + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data + EDS_WE_OUT : out std_logic; -- EDS write enable (general interface) + EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level + EDS_READY_OUT : out std_logic; -- APV trigger sequence done, TERMinate the TRB LVL1 trigger + DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); + end component; + + component apv_trg_handler is + port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- synced reset signal (100MHz) + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers + APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished + APV_TRG_OUT : out std_logic; + APV_TRGSENT_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component apv_sync_handler is + port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- synced reset signal (100MHz) + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished + APV_TRG_OUT : out std_logic; + APV_SYNC_OUT : out std_logic; -- signal for statemachines + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component eds_buf is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + -- EDS input, all synced to CLK_IN + EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input + EDS_WE_IN : in std_logic; -- EDS write enable + EDS_DONE_IN : in std_logic; -- release EDS + EDS_DATA_OUT : out std_logic_vector(39 downto 0); + EDS_AVAILABLE_OUT : out std_logic; + -- trigger busy information + BUF_FULL_OUT : out std_logic; + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component adc_pll is + port( CLK : in std_logic; + RESET : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic + ); + end component; + + component adc_ch_in is + port( DEL : in std_logic_vector(3 downto 0); + ECLK : in std_logic; + SCLK : in std_logic; + RST : in std_logic; + DATA : in std_logic_vector(0 downto 0); + Q : out std_logic_vector(1 downto 0) + ); + end component; + + component adc_twochannels is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLOCK_IN : in std_logic_vector(1 downto 0); -- DDR bit clock + DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one + DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two + DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one + DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two + STORE_OUT : out std_logic; + SWAP_OUT : out std_logic; + CLOCK_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component apv_locker is + port( CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to ADC_CLK_IN + ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid + SYNC_IN : in std_logic; -- sync trigger input + APV_ON_IN : in std_logic; -- this APV channel is switched on + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0' + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1' + FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline + STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off) + STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet + STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid + STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully + STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong + STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully + STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected + STATUS_TICKMARK_OUT : out std_logic; + FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header + FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header + FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?) + FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow + FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow + FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames + APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID + APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high + APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low + APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data + APV_ANALOG_OUT : out std_logic; -- APV analog data is valid + APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer + APV_LAST_OUT : out std_logic; -- last APV channel of dataframe + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component apv_raw_buffer is + port( CLK_APV_IN : in std_logic; -- write clock from APV handling stage + RESET_IN : in std_logic; + FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event + ADC_ANALOG_IN : in std_logic; -- write enable for ADC data + ADC_START_IN : in std_logic; -- data frame detected, block the buffer page + ADC_LAST_IN : in std_logic; -- last channel signal + ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID + ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR + ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV + ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame + BUF_CLK_IN : in std_logic; -- read clock + BUF_RESET_IN : in std_logic; -- 100MHz reset + BUF_START_OUT : out std_logic; -- one block starts writing + BUF_READY_OUT : out std_logic; -- one block has been written + BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer + BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer) + BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer + BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output + BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output + BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation + BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation + BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer + BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler + BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set! + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component slv_register is + generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" ); + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + REG_DATA_IN : in std_logic_vector(31 downto 0); + REG_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + component slv_half_register is + generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" ); + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + STATUS_REG_IN : in std_logic_vector(15 downto 0); + CTRL_REG_OUT : out std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + component i2c_master is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + component slv_onewire_memory is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(5 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- 1Wire lines + ONEWIRE_START_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); + BP_ONEWIRE_INOUT : inout std_logic; + -- Status lines + STAT : out std_logic_vector(63 downto 0) -- DEBUG + ); + end component; + + component spi_real_slim is + port( SYSCLK : in std_logic; -- 100MHz sysclock + RESET : in std_logic; -- synchronous reset + -- Command interface + START_IN : in std_logic; -- one start pulse + BUSY_OUT : out std_logic; -- SPI transactions are ongoing + CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte + -- SPI interface + SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + -- DEBUG + CLK_EN_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + component spi_adc_master is + generic( RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" ); + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + -- ADC connections + ADC_LOCKED_IN : in std_logic; + ADC_PD_OUT : out std_logic; + ADC_RST_OUT : out std_logic; + ADC_DEL_OUT : out std_logic_vector(3 downto 0); + -- APV connections + APV_RST_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + component i2c_slim is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- I2C command / setup + I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions + ACTION_IN : in std_logic; -- '0' -> write, '1' -> read + I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined) + I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte) + I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command + I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command + STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits + I2C_BUSY_OUT : out std_logic; + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Debug + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + component i2c_gstart is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + DOSTART_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector(7 downto 0); + SDONE_OUT : out std_logic; + SOK_OUT : out std_logic; + SDA_IN : in std_logic; + SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0) + ); + end component; + + component i2c_sendb is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + DOBYTE_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector(7 downto 0); + I2C_BYTE_IN : in std_logic_vector(8 downto 0); + I2C_BACK_OUT : out std_logic_vector(8 downto 0); + SDA_IN : in std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; +-- SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + BDONE_OUT : out std_logic; + BOK_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0) + ); + end component; + + component onewire_master is + generic( CLK_PERIOD : integer := 10 ); -- clock perion in nanoseconds + port( CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic; + -- connection to 1-wire interface (16 APV FEs) + ONEWIRE : inout std_logic_vector(15 downto 0); + BP_ONEWIRE : inout std_logic; + -- connection to external DPRAM for slow control readout + BP_DATA_OUT : out std_logic_vector(15 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(6 downto 0); + WRITE_OUT : out std_logic; + BUSY_OUT : out std_logic; + -- debug + BSM_OUT : out std_logic_vector(7 downto 0); + STAT : out std_logic_vector(15 downto 0) + ); + end component; + + component slv_onewire_dpram + port( WRADDRESS : in std_logic_vector(6 downto 0); + RDADDRESS : in std_logic_vector(5 downto 0); + DATA : in std_logic_vector(15 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(31 downto 0) + ); + end component; + + component dhdr_buf is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + -- DHDR information block + DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input + DHDR_WE_IN : in std_logic; -- EDS write enable + DHDR_DONE_IN : in std_logic; -- release EDS + DHDR_DATA_OUT : out std_logic_vector(47 downto 0); + DHDR_AVAILABLE_OUT : out std_logic; + -- trigger busy information + BUF_FULL_OUT : out std_logic; + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component fifo_2kx27 is + port( DATA : in std_logic_vector(26 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(26 downto 0); + WCNT : out std_logic_vector(11 downto 0); + EMPTY : out std_logic; + FULL : out std_logic + ); + end component fifo_2kx27; + + component fifo_16x11 is + port( DATA : in std_logic_vector(10 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(10 downto 0); + WCNT : out std_logic_vector(4 downto 0); + EMPTY : out std_logic; + FULL : out std_logic + ); + end component fifo_16x11; + + component dhdr_buffer_dpram is + port( WRADDRESS : in std_logic_vector(3 downto 0); + DATA : in std_logic_vector(47 downto 0); + WRCLOCK : in std_logic; + WE : in std_logic; + WRCLOCKEN : in std_logic; + RDADDRESS : in std_logic_vector(3 downto 0); + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(47 downto 0) + ); + end component; + + component decoder_8bit is + port( ADDRESS : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component decoder_8bit; + + component adder_5bit is + port( DATAA : in std_logic_vector(4 downto 0); + DATAB : in std_logic_vector(4 downto 0); + CLOCK : in std_logic; + RESET : in std_logic; + CLOCKEN : in std_logic; + RESULT : out std_logic_vector(4 downto 0) + ); + end component adder_5bit; + + component adder_16bit is + port( DATAA : in std_logic_vector(15 downto 0); + DATAB : in std_logic_vector(15 downto 0); + CLOCK : in std_logic; + RESET : in std_logic; + CLOCKEN : in std_logic; + RESULT : out std_logic_vector(15 downto 0) + ); + end component adder_16bit; + + component suber_12bit is + port( DATAA : in std_logic_vector(11 downto 0); + DATAB : in std_logic_vector(11 downto 0); + CLOCK : in std_logic; + RESET : in std_logic; + CLOCKEN : in std_logic; + RESULT : out std_logic_vector(11 downto 0) + ); + end component suber_12bit; + + + component buf_toc is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUF_TICK_IN : in std_logic; -- tickmark from raw buffer + BUF_START_IN : in std_logic; -- start of frame from raw buffer + WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode + FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS + BUF_LVL_IN : in std_logic_vector(7 downto 0); + GOODDATA_OUT : out std_logic; + BADDATA_OUT : out std_logic; + NODATA_OUT : out std_logic; + READY_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) + ); + end component buf_toc; + + component ref_row_sel is + port( CLK_IN : in std_logic; + READY_IN : in std_logic_vector(15 downto 0); + GOODDATA_IN : in std_logic_vector(15 downto 0); + FRAME_0_IN : in std_logic_vector(11 downto 0); + FRAME_1_IN : in std_logic_vector(11 downto 0); + FRAME_2_IN : in std_logic_vector(11 downto 0); + FRAME_3_IN : in std_logic_vector(11 downto 0); + FRAME_4_IN : in std_logic_vector(11 downto 0); + FRAME_5_IN : in std_logic_vector(11 downto 0); + FRAME_6_IN : in std_logic_vector(11 downto 0); + FRAME_7_IN : in std_logic_vector(11 downto 0); + FRAME_8_IN : in std_logic_vector(11 downto 0); + FRAME_9_IN : in std_logic_vector(11 downto 0); + FRAME_10_IN : in std_logic_vector(11 downto 0); + FRAME_11_IN : in std_logic_vector(11 downto 0); + FRAME_12_IN : in std_logic_vector(11 downto 0); + FRAME_13_IN : in std_logic_vector(11 downto 0); + FRAME_14_IN : in std_logic_vector(11 downto 0); + FRAME_15_IN : in std_logic_vector(11 downto 0); + VALID_BUFS_OUT : out std_logic; + READY_OUT : out std_logic; + ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong + APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit + APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0); + REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row + DBG_OUT : out std_logic_vector(15 downto 0) + ); + end component ref_row_sel; + + component frmctr_check is + port( CLK_IN : in std_logic; + GOODDATA_IN : in std_logic_vector(15 downto 0); + FRAMECOUNTER_IN : in std_logic_vector(3 downto 0); + FRM_NR_0_IN : in std_logic_vector(3 downto 0); + FRM_NR_1_IN : in std_logic_vector(3 downto 0); + FRM_NR_2_IN : in std_logic_vector(3 downto 0); + FRM_NR_3_IN : in std_logic_vector(3 downto 0); + FRM_NR_4_IN : in std_logic_vector(3 downto 0); + FRM_NR_5_IN : in std_logic_vector(3 downto 0); + FRM_NR_6_IN : in std_logic_vector(3 downto 0); + FRM_NR_7_IN : in std_logic_vector(3 downto 0); + FRM_NR_8_IN : in std_logic_vector(3 downto 0); + FRM_NR_9_IN : in std_logic_vector(3 downto 0); + FRM_NR_10_IN : in std_logic_vector(3 downto 0); + FRM_NR_11_IN : in std_logic_vector(3 downto 0); + FRM_NR_12_IN : in std_logic_vector(3 downto 0); + FRM_NR_13_IN : in std_logic_vector(3 downto 0); + FRM_NR_14_IN : in std_logic_vector(3 downto 0); + FRM_NR_15_IN : in std_logic_vector(3 downto 0); + FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong + DBG_OUT : out std_logic_vector(15 downto 0) + ); + end component frmctr_check; + + component apv_pc_nc_alu is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + START_IN : in std_logic; + MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested + CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number + LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + BUF_GOOD_IN : in std_logic; + BUF_BAD_IN : in std_logic; + BUF_IGNORE_IN : in std_logic; + ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers + DO_HEADER_IN : in std_logic; + DO_ERROR_IN : in std_logic; + EVT_TYPE_IN : in std_logic_vector(2 downto 0); + RAW_ADDR_IN : in std_logic_vector(6 downto 0); + RAW_DATA_IN : in std_logic_vector(37 downto 0); + PED_DATA_IN : in std_logic_vector(17 downto 0); + THR_DATA_IN : in std_logic_vector(17 downto 0); + FRAME_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0] + WE_OUT : out std_logic; + COUNT_OUT : out std_logic_vector(9 downto 0); + ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout + DBG_OUT : out std_logic_vector(15 downto 0) + ); + end component apv_pc_nc_alu; + + component comp14bit is + port( DATAA : in std_logic_vector(13 downto 0); + DATAB : in std_logic_vector(13 downto 0); + CLOCK : in std_logic; + CLOCKEN : in std_logic; + ACLR : in std_logic; + AGEB : out std_logic + ); + end component; + + component input_bram is + port( WRADDRESS : in std_logic_vector(10 downto 0); + RDADDRESS : in std_logic_vector(10 downto 0); + DATA : in std_logic_vector(17 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(17 downto 0) + ); + end component; + + component frame_status_mem is + port( WRADDRESS : in std_logic_vector(3 downto 0); + DATA : in std_logic_vector(11 downto 0); + WRCLOCK : in std_logic; + WE : in std_logic; + WRCLOCKEN : in std_logic; + RDADDRESS : in std_logic_vector(3 downto 0); + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(11 downto 0) + ); + end component; + + component adder_6bit is + port( DATAA : in std_logic_vector(5 downto 0); + DATAB : in std_logic_vector(5 downto 0); + CLOCK : in std_logic; + RESET : in std_logic; + CLOCKEN : in std_logic; + RESULT : out std_logic_vector(5 downto 0) + ); + end component; + + component apv_lock_sm is + port( CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + SYNC_IN : in std_logic; -- start APV synchronisation + ADC_VALID_IN : in std_logic; -- ADC delivers valid data + TIMED_IN : in std_logic; -- synchronisation timeout + MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter + LOCKED_IN : in std_logic; -- enough good tickmarks + TICK_IN : in std_logic; -- tickmark from digital parser + HEADER_IN : in std_logic; -- header from digital parser + FLATLINE_IN : in std_logic; -- flatline from digital parser + RST_PC_OUT : out std_logic; -- reset period counter + RST_TC_OUT : out std_logic; -- reset timeout counter + INC_TC_OUT : out std_logic; + RST_LC_OUT : out std_logic; -- reset lock counter + INC_LC_OUT : out std_logic; + UNKNOWN_OUT : out std_logic; + BADADC_OUT : out std_logic; -- ADC data invalid + LOCKED_OUT : out std_logic; + LOST_OUT : out std_logic; + NOSYNC_OUT : out std_logic; + NOAPV_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component apv_digital is + port( CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); + BIT_LOW_IN : in std_logic_vector(11 downto 0); + BIT_HIGH_IN : in std_logic_vector(11 downto 0); + FL_LOW_IN : in std_logic_vector(11 downto 0); + FL_HIGH_IN : in std_logic_vector(11 downto 0); + BIT_DATA_OUT : out std_logic_vector(11 downto 0); + BIT_VALID_OUT : out std_logic_vector(11 downto 0); + BIT_HIGH_OUT : out std_logic; + BIT_LOW_OUT : out std_logic; + TICKMARK_OUT : out std_logic; + HEADER_OUT : out std_logic; + FLAT_LINE_OUT : out std_logic + ); + end component; + + component eds_buffer_dpram is + port( WRADDRESS : in std_logic_vector(3 downto 0); + DATA : in std_logic_vector(39 downto 0); + WRCLOCK : in std_logic; + WE : in std_logic; + WRCLOCKEN : in std_logic; + RDADDRESS : in std_logic_vector(3 downto 0); + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(39 downto 0) + ); + end component; + +end package; + +-- Down in the Dumps... + diff --git a/src/adder_16bit.lpc b/src/adder_16bit.lpc new file mode 100644 index 0000000..7d5f791 --- /dev/null +++ b/src/adder_16bit.lpc @@ -0,0 +1,36 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Adder +CoreRevision=3.1 +ModuleName=adder_16bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/03/2009 +Time=10:27:46 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +InputWidth=16 +Representation=Unsigned +UseCIport=0 +COport=None +OutReg=1 +Complex=0 +Stage=0 diff --git a/src/adder_16bit.vhd b/src/adder_16bit.vhd new file mode 100644 index 0000000..07ddeea --- /dev/null +++ b/src/adder_16bit.vhd @@ -0,0 +1,303 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 3.1 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type add -width 16 -unsigned -output_reg -enable -pipeline 0 -e + +-- Tue Mar 03 10:27:46 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity adder_16bit is + port ( + DataA: in std_logic_vector(15 downto 0); + DataB: in std_logic_vector(15 downto 0); + Clock: in std_logic; + Reset: in std_logic; + ClockEn: in std_logic; + Result: out std_logic_vector(15 downto 0)); +end adder_16bit; + +architecture Structure of adder_16bit is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal r0_sum15: std_logic; + signal r0_sum14: std_logic; + signal r0_sum13: std_logic; + signal r0_sum12: std_logic; + signal r0_sum11: std_logic; + signal r0_sum10: std_logic; + signal r0_sum9: std_logic; + signal r0_sum8: std_logic; + signal r0_sum7: std_logic; + signal r0_sum6: std_logic; + signal r0_sum5: std_logic; + signal r0_sum4: std_logic; + signal r0_sum3: std_logic; + signal r0_sum2: std_logic; + signal r0_sum1: std_logic; + signal r0_sum0: std_logic; + signal addsub_cod_0: std_logic; + signal tsum0: std_logic; + signal tsum1: std_logic; + signal tsum2: std_logic; + signal tsum3: std_logic; + signal co0: std_logic; + signal tsum4: std_logic; + signal tsum5: std_logic; + signal co1: std_logic; + signal tsum6: std_logic; + signal tsum7: std_logic; + signal co2: std_logic; + signal tsum8: std_logic; + signal tsum9: std_logic; + signal co3: std_logic; + signal tsum10: std_logic; + signal tsum11: std_logic; + signal co4: std_logic; + signal tsum12: std_logic; + signal tsum13: std_logic; + signal co5: std_logic; + signal tsum14: std_logic; + signal tsum15: std_logic; + signal co6: std_logic; + signal co7d: std_logic; + signal co7: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum15, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum15); + + FF_15: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum14, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum14); + + FF_14: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum13, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum13); + + FF_13: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum12, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum12); + + FF_12: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum11, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum11); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum10, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum10); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum9, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum9); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum8, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum8); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum7, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum7); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum6, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum6); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum5, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum5); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum4); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum3); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum2); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum1); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum0); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>co7d, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>addsub_cod_0); + + addsub_0: FADD2B + port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1), + CI=>scuba_vlo, COUT=>co0, S0=>tsum0, S1=>tsum1); + + addsub_1: FADD2B + port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3), + CI=>co0, COUT=>co1, S0=>tsum2, S1=>tsum3); + + addsub_2: FADD2B + port map (A0=>DataA(4), A1=>DataA(5), B0=>DataB(4), B1=>DataB(5), + CI=>co1, COUT=>co2, S0=>tsum4, S1=>tsum5); + + addsub_3: FADD2B + port map (A0=>DataA(6), A1=>DataA(7), B0=>DataB(6), B1=>DataB(7), + CI=>co2, COUT=>co3, S0=>tsum6, S1=>tsum7); + + addsub_4: FADD2B + port map (A0=>DataA(8), A1=>DataA(9), B0=>DataB(8), B1=>DataB(9), + CI=>co3, COUT=>co4, S0=>tsum8, S1=>tsum9); + + addsub_5: FADD2B + port map (A0=>DataA(10), A1=>DataA(11), B0=>DataB(10), + B1=>DataB(11), CI=>co4, COUT=>co5, S0=>tsum10, S1=>tsum11); + + addsub_6: FADD2B + port map (A0=>DataA(12), A1=>DataA(13), B0=>DataB(12), + B1=>DataB(13), CI=>co5, COUT=>co6, S0=>tsum12, S1=>tsum13); + + addsub_7: FADD2B + port map (A0=>DataA(14), A1=>DataA(15), B0=>DataB(14), + B1=>DataB(15), CI=>co6, COUT=>co7, S0=>tsum14, S1=>tsum15); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + addsubd: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co7, COUT=>open, S0=>co7d, S1=>open); + + Result(15) <= r0_sum15; + Result(14) <= r0_sum14; + Result(13) <= r0_sum13; + Result(12) <= r0_sum12; + Result(11) <= r0_sum11; + Result(10) <= r0_sum10; + Result(9) <= r0_sum9; + Result(8) <= r0_sum8; + Result(7) <= r0_sum7; + Result(6) <= r0_sum6; + Result(5) <= r0_sum5; + Result(4) <= r0_sum4; + Result(3) <= r0_sum3; + Result(2) <= r0_sum2; + Result(1) <= r0_sum1; + Result(0) <= r0_sum0; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of adder_16bit is + for Structure + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/adder_16bit_tmpl.vhd b/src/adder_16bit_tmpl.vhd new file mode 100644 index 0000000..5251448 --- /dev/null +++ b/src/adder_16bit_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 3.1 +-- Tue Mar 03 10:27:46 2009 + +-- parameterized module component declaration +component adder_16bit + port (DataA: in std_logic_vector(15 downto 0); + DataB: in std_logic_vector(15 downto 0); Clock: in std_logic; + Reset: in std_logic; ClockEn: in std_logic; + Result: out std_logic_vector(15 downto 0)); +end component; + +-- parameterized module component instance +__ : adder_16bit + port map (DataA(15 downto 0)=>__, DataB(15 downto 0)=>__, Clock=>__, + Reset=>__, ClockEn=>__, Result(15 downto 0)=>__); diff --git a/src/adder_5bit.lpc b/src/adder_5bit.lpc new file mode 100644 index 0000000..d47643d --- /dev/null +++ b/src/adder_5bit.lpc @@ -0,0 +1,36 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Adder +CoreRevision=3.1 +ModuleName=adder_5bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/03/2009 +Time=10:10:12 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +InputWidth=5 +Representation=Unsigned +UseCIport=0 +COport=None +OutReg=1 +Complex=0 +Stage=0 diff --git a/src/adder_5bit.vhd b/src/adder_5bit.vhd new file mode 100644 index 0000000..55258be --- /dev/null +++ b/src/adder_5bit.vhd @@ -0,0 +1,142 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 3.1 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type add -width 5 -unsigned -output_reg -enable -e + +-- Tue Mar 03 10:10:12 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity adder_5bit is + port ( + DataA: in std_logic_vector(4 downto 0); + DataB: in std_logic_vector(4 downto 0); + Clock: in std_logic; + Reset: in std_logic; + ClockEn: in std_logic; + Result: out std_logic_vector(4 downto 0)); +end adder_5bit; + +architecture Structure of adder_5bit is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal r0_sum4: std_logic; + signal r0_sum3: std_logic; + signal r0_sum2: std_logic; + signal r0_sum1: std_logic; + signal r0_sum0: std_logic; + signal tsum0: std_logic; + signal tsum1: std_logic; + signal tsum2: std_logic; + signal tsum3: std_logic; + signal co0: std_logic; + signal tsum4: std_logic; + signal co1: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum4); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum3); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum2); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum1); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum0); + + addsub_0: FADD2B + port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1), + CI=>scuba_vlo, COUT=>co0, S0=>tsum0, S1=>tsum1); + + addsub_1: FADD2B + port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3), + CI=>co0, COUT=>co1, S0=>tsum2, S1=>tsum3); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + addsub_2: FADD2B + port map (A0=>DataA(4), A1=>scuba_vlo, B0=>DataB(4), + B1=>scuba_vlo, CI=>co1, COUT=>open, S0=>tsum4, S1=>open); + + Result(4) <= r0_sum4; + Result(3) <= r0_sum3; + Result(2) <= r0_sum2; + Result(1) <= r0_sum1; + Result(0) <= r0_sum0; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of adder_5bit is + for Structure + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/adder_5bit_tmpl.vhd b/src/adder_5bit_tmpl.vhd new file mode 100644 index 0000000..27e9025 --- /dev/null +++ b/src/adder_5bit_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 3.1 +-- Tue Mar 03 10:10:12 2009 + +-- parameterized module component declaration +component adder_5bit + port (DataA: in std_logic_vector(4 downto 0); + DataB: in std_logic_vector(4 downto 0); Clock: in std_logic; + Reset: in std_logic; ClockEn: in std_logic; + Result: out std_logic_vector(4 downto 0)); +end component; + +-- parameterized module component instance +__ : adder_5bit + port map (DataA(4 downto 0)=>__, DataB(4 downto 0)=>__, Clock=>__, + Reset=>__, ClockEn=>__, Result(4 downto 0)=>__); diff --git a/src/adder_6bit.lpc b/src/adder_6bit.lpc new file mode 100644 index 0000000..b8caa0a --- /dev/null +++ b/src/adder_6bit.lpc @@ -0,0 +1,36 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M35E +PartName=LFE2M35E-6F672C +SpeedGrade=-6 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Adder +CoreRevision=3.1 +ModuleName=adder_6bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/27/2008 +Time=11:31:51 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +InputWidth=6 +Representation=Unsigned +UseCIport=0 +COport=None +OutReg=1 +Complex=0 +Stage=0 diff --git a/src/adder_6bit.vhd b/src/adder_6bit.vhd new file mode 100644 index 0000000..29a1593 --- /dev/null +++ b/src/adder_6bit.vhd @@ -0,0 +1,168 @@ +-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58) +-- Module Version: 3.1 +--X:\Programme\ispTOOLS_71\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type add -width 6 -unsigned -output_reg -enable -e + +-- Wed Aug 27 11:31:51 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity adder_6bit is + port ( + DataA: in std_logic_vector(5 downto 0); + DataB: in std_logic_vector(5 downto 0); + Clock: in std_logic; + Reset: in std_logic; + ClockEn: in std_logic; + Result: out std_logic_vector(5 downto 0)); +end adder_6bit; + +architecture Structure of adder_6bit is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal r0_sum5: std_logic; + signal r0_sum4: std_logic; + signal r0_sum3: std_logic; + signal r0_sum2: std_logic; + signal r0_sum1: std_logic; + signal r0_sum0: std_logic; + signal addsub_cod_0: std_logic; + signal tsum0: std_logic; + signal tsum1: std_logic; + signal tsum2: std_logic; + signal tsum3: std_logic; + signal co0: std_logic; + signal tsum4: std_logic; + signal tsum5: std_logic; + signal co1: std_logic; + signal co2d: std_logic; + signal co2: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum5, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum5); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum4); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum3); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum2); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum1); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_sum0); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>co2d, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>addsub_cod_0); + + addsub_0: FADD2B + port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1), + CI=>scuba_vlo, COUT=>co0, S0=>tsum0, S1=>tsum1); + + addsub_1: FADD2B + port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3), + CI=>co0, COUT=>co1, S0=>tsum2, S1=>tsum3); + + addsub_2: FADD2B + port map (A0=>DataA(4), A1=>DataA(5), B0=>DataB(4), B1=>DataB(5), + CI=>co1, COUT=>co2, S0=>tsum4, S1=>tsum5); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + addsubd: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2, COUT=>open, S0=>co2d, S1=>open); + + Result(5) <= r0_sum5; + Result(4) <= r0_sum4; + Result(3) <= r0_sum3; + Result(2) <= r0_sum2; + Result(1) <= r0_sum1; + Result(0) <= r0_sum0; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of adder_6bit is + for Structure + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/adder_6bit_tmpl.vhd b/src/adder_6bit_tmpl.vhd new file mode 100644 index 0000000..fbf6eb1 --- /dev/null +++ b/src/adder_6bit_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58) +-- Module Version: 3.1 +-- Wed Aug 27 11:31:51 2008 + +-- parameterized module component declaration +component adder_6bit + port (DataA: in std_logic_vector(5 downto 0); + DataB: in std_logic_vector(5 downto 0); Clock: in std_logic; + Reset: in std_logic; ClockEn: in std_logic; + Result: out std_logic_vector(5 downto 0)); +end component; + +-- parameterized module component instance +__ : adder_6bit + port map (DataA(5 downto 0)=>__, DataB(5 downto 0)=>__, Clock=>__, + Reset=>__, ClockEn=>__, Result(5 downto 0)=>__); diff --git a/src/apv_adc_map_mem.lpc b/src/apv_adc_map_mem.lpc new file mode 100644 index 0000000..fadf9ca --- /dev/null +++ b/src/apv_adc_map_mem.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_ROM +CoreRevision=2.4 +ModuleName=apv_adc_map_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/04/2009 +Time=16:10:56 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=128 +Data=4 +LUT=0 +MemFile=i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem +MemFormat=orca diff --git a/src/apv_adc_map_mem.srp b/src/apv_adc_map_mem.srp new file mode 100644 index 0000000..5e3fe40 --- /dev/null +++ b/src/apv_adc_map_mem.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Nov 04 16:10:56 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e + Circuit name : apv_adc_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem + EDIF output : suppressed + VHDL output : apv_adc_map_mem.vhd + VHDL template : apv_adc_map_mem_tmpl.vhd + VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : apv_adc_map_mem.srp + Element Usage : + ROM128X1 : 4 + Estimated Resource Usage: + LUT : 16 diff --git a/src/apv_adc_map_mem.vhd b/src/apv_adc_map_mem.vhd new file mode 100644 index 0000000..861a722 --- /dev/null +++ b/src/apv_adc_map_mem.vhd @@ -0,0 +1,81 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 7 -num_rows 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e + +-- Wed Nov 04 16:10:56 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity apv_adc_map_mem is + port ( + Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end apv_adc_map_mem; + +architecture Structure of apv_adc_map_mem is + + -- local component declarations + component ROM128X1 + -- synopsys translate_off + generic (INITVAL : in String); + -- synopsys translate_on + port (AD6: in std_logic; AD5: in std_logic; AD4: in std_logic; + AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + attribute initval : string; + attribute initval of mem_0_3 : label is "0xFF00FF00FF001FE0E01F7F80807F6956"; + attribute initval of mem_0_2 : label is "0xF0F0F0F0F0F0079DF8621E0FE1F0E287"; + attribute initval of mem_0_1 : label is "0xCCCCCCCCCCCC867A798519ECE6139D07"; + attribute initval of mem_0_0 : label is "0xAAAAAAAAAAAA3553CAAC355ACAA5B1E2"; + +begin + -- component instantiation statements + mem_0_3: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xFF00FF00FF001FE0E01F7F80807F6956") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(3)); + + mem_0_2: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xF0F0F0F0F0F0079DF8621E0FE1F0E287") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(2)); + + mem_0_1: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xCCCCCCCCCCCC867A798519ECE6139D07") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(1)); + + mem_0_0: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xAAAAAAAAAAAA3553CAAC355ACAA5B1E2") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(0)); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of apv_adc_map_mem is + for Structure + for all:ROM128X1 use entity ecp2m.ROM128X1(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/apv_adc_map_mem_generate.log b/src/apv_adc_map_mem_generate.log new file mode 100644 index 0000000..ea70ce7 --- /dev/null +++ b/src/apv_adc_map_mem_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Nov 04 16:10:56 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e + Circuit name : apv_adc_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Data width : 4 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem + EDIF output : suppressed + VHDL output : apv_adc_map_mem.vhd + VHDL template : apv_adc_map_mem_tmpl.vhd + VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : apv_adc_map_mem.srp + Estimated Resource Usage: + LUT : 16 + +END SCUBA Module Synthesis + +File: ..\src\apv_adc_map_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/apv_adc_map_mem_tmpl.vhd b/src/apv_adc_map_mem_tmpl.vhd new file mode 100644 index 0000000..b14294d --- /dev/null +++ b/src/apv_adc_map_mem_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Wed Nov 04 16:10:56 2009 + +-- parameterized module component declaration +component apv_adc_map_mem + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : apv_adc_map_mem + port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/src/apv_adc_mapping.mem b/src/apv_adc_mapping.mem new file mode 100644 index 0000000..1c4a8c6 --- /dev/null +++ b/src/apv_adc_mapping.mem @@ -0,0 +1,155 @@ +#Format=Address-Hex +#Depth=128 +#DataWidth=4 +#AddrRadix=3 +#DataRadix=3 + +# Backplane 0 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1 +# +# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# realADC 6 15 14 0 8 1 9 5 b 4 2 a 3 d c 7 +00: 6 +01: f +02: e +03: 0 +04: 8 +05: 1 +06: 9 +07: 5 +08: b +09: 4 +0a: 2 +0b: a +0c: 3 +0d: d +0e: c +0f: 7 +# Backplane 1 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 - +10: b +11: a +12: 9 +13: 8 +14: e +15: d +16: c +17: 5 +18: 4 +19: 3 +1a: 2 +1b: 1 +1c: 0 +1d: 6 +1e: 7 +1f: f +# Backplane 2 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12 +20: 4 +21: 5 +22: 6 +23: 7 +24: 1 +25: 2 +26: 3 +27: a +28: b +29: c +2a: d +2b: e +2c: f +2d: 9 +2e: 8 +2f: 0 +# Backplane 3 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14 +30: a +31: c +32: b +33: 9 +34: 8 +35: 5 +36: 4 +37: 3 +38: 2 +39: 1 +3a: 0 +3b: 7 +3c: 6 +3d: e +3e: f +3f: d +# Backplane 4 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10 +40: 5 +41: 3 +42: 4 +43: 6 +44: 7 +45: a +46: b +47: c +48: d +49: e +4a: f +4b: 8 +4c: 9 +4d: 1 +4e: 0 +4f: 2 +# unused (5) => 1:1 +50: 0 +51: 1 +52: 2 +53: 3 +54: 4 +55: 5 +56: 6 +57: 7 +58: 8 +59: 9 +5a: a +5b: b +5c: c +5d: d +5e: e +5f: f +# unused (6) => 1:1 +60: 0 +61: 1 +62: 2 +63: 3 +64: 4 +65: 5 +66: 6 +67: 7 +68: 8 +69: 9 +6a: a +6b: b +6c: c +6d: d +6e: e +6f: f +# unused (7) => 1:1 +70: 0 +71: 1 +72: 2 +73: 3 +74: 4 +75: 5 +76: 6 +77: 7 +78: 8 +79: 9 +7a: a +7b: b +7c: c +7d: d +7e: e +7f: f diff --git a/src/apv_digital.vhd b/src/apv_digital.vhd new file mode 100755 index 0000000..a7dedc7 --- /dev/null +++ b/src/apv_digital.vhd @@ -0,0 +1,207 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity apv_digital is + port( CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); + BIT_LOW_IN : in std_logic_vector(11 downto 0); + BIT_HIGH_IN : in std_logic_vector(11 downto 0); + FL_LOW_IN : in std_logic_vector(11 downto 0); + FL_HIGH_IN : in std_logic_vector(11 downto 0); + BIT_DATA_OUT : out std_logic_vector(11 downto 0); + BIT_VALID_OUT : out std_logic_vector(11 downto 0); + BIT_HIGH_OUT : out std_logic; + BIT_LOW_OUT : out std_logic; + TICKMARK_OUT : out std_logic; + HEADER_OUT : out std_logic; + FLAT_LINE_OUT : out std_logic + ); +end; + +architecture behavioral of apv_digital is + + signal next_bit_low : std_logic; + signal bit_low : std_logic; + signal next_bit_high : std_logic; + signal bit_high : std_logic; + signal next_bit_data : std_logic; + signal bit_data : std_logic_vector(11 downto 0); + signal next_bit_valid : std_logic; + signal bit_valid : std_logic_vector(11 downto 0); + signal next_fl_low : std_logic; + signal fl_low : std_logic; + signal next_fl_high : std_logic; + signal fl_high : std_logic; + signal next_fl_found : std_logic; + signal fl_found : std_logic_vector(2 downto 0); + signal next_flat_line : std_logic; + signal flat_line : std_logic; + signal next_tickmark : std_logic; + signal tickmark : std_logic; + signal next_header : std_logic; + signal header : std_logic; + +begin + +-- ADC data is registered already, so we can operate on the inputs directly. + +-------------------------------------------------------------------------------------- +-- compare ADC raw data against "bit low" threshold, +-- generate combinatorial "low" bit +THE_BL_COMP: process( adc_raw_in, bit_low_in ) +begin + if( adc_raw_in < bit_low_in ) then + next_bit_low <= '1'; + else + next_bit_low <= '0'; + end if; +end process THE_BL_COMP; + +-- compare ADC raw data against "bit high" threshold, +--generate combinatorial "high" bit +THE_BH_COMP: process( adc_raw_in, bit_high_in ) +begin + if( adc_raw_in > bit_high_in ) then + next_bit_high <= '1'; + else + next_bit_high <= '0'; + end if; +end process THE_BH_COMP; + +-- store comparator result, enable pipelining +THE_BIT_STORE_ONE: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + bit_high <= '0'; + bit_low <= '0'; + else + bit_high <= next_bit_high; + bit_low <= next_bit_low; + end if; + end if; +end process THE_BIT_STORE_ONE; + +-- decode real bits with valid signal (10 => '1', 01 => '0', rest invalid) +next_bit_data <= bit_high and not bit_low; +next_bit_valid <= bit_high xor bit_low; + +THE_BIT_SHIFT: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + bit_valid <= (others => '0'); + bit_data <= (others => '0'); + else + bit_valid(11 downto 1) <= bit_valid(10 downto 0); + bit_valid(0) <= next_bit_valid; + bit_data(11 downto 1 ) <= bit_data(10 downto 0); + bit_data(0) <= next_bit_data; + end if; + end if; +end process THE_BIT_SHIFT; + +-- tickmark recognition: as stupid as possible, as easy as possible +next_tickmark <= '1' when (bit_data(2 downto 0) = "100") else '0'; + +-- header recognition: as stupid as possible, as easy as possible +next_header <= '1' when (bit_data(2 downto 0) = "111") else '0'; + +-- store tickmark and header result, enable pipelining +THE_BIT_STORE_TWO: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + tickmark <= '0'; + header <= '0'; + else + tickmark <= next_tickmark; + header <= next_header; + end if; + end if; +end process THE_BIT_STORE_TWO; + + +-------------------------------------------------------------------------------------- +-- flatline recognition: in case of missing APV the ADC amplifier stage is +-- "shortcut" by 100Ohm and will give a flat line on half on the ADC range. +THE_FLL_COMP: process( adc_raw_in, fl_low_in ) +begin + if( adc_raw_in > fl_low_in ) then + next_fl_low <= '1'; + else + next_fl_low <= '0'; + end if; +end process THE_FLL_COMP; + +THE_FLH_COMP: process( adc_raw_in, fl_high_in ) +begin + if( adc_raw_in < fl_high_in ) then + next_fl_high <= '1'; + else + next_fl_high <= '0'; + end if; +end process THE_FLH_COMP; + +-- register stage one: avoid long combinatorial delays +THE_FL_REG_STAGE_ONE: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + fl_high <= '0'; + fl_low <= '0'; + else + fl_high <= next_fl_high; + fl_low <= next_fl_low; + end if; + end if; +end process THE_FL_REG_STAGE_ONE; + +-- ADC signal must between lower and upper range +next_fl_found <= fl_high and fl_low; + +-- flatline shift register +THE_FL_SHIFTER: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + fl_found <= (others => '0'); + else + fl_found(2 downto 0) <= fl_found(1 downto 0) & next_fl_found; + end if; + end if; +end process THE_FL_SHIFTER; + +-- majority decision +next_flat_line <= ( fl_found(2) and fl_found(1) and fl_found(0)) or + (not fl_found(2) and fl_found(1) and fl_found(0)) or + ( fl_found(2) and fl_found(1) and not fl_found(0)); + +-- register stage two: avoid long combinatorial delays +THE_FL_REG_STAGE_TWO: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + flat_line <= '0'; + else + flat_line <= next_flat_line; + end if; + end if; +end process THE_FL_REG_STAGE_TWO; + +-- output signals +bit_data_out <= bit_data; +bit_valid_out <= bit_valid; +flat_line_out <= flat_line; +tickmark_out <= tickmark; +header_out <= header; +bit_high_out <= bit_high; +bit_low_out <= bit_low; + +end behavioral; diff --git a/src/apv_lock_sm.vhd b/src/apv_lock_sm.vhd new file mode 100755 index 0000000..57b56f7 --- /dev/null +++ b/src/apv_lock_sm.vhd @@ -0,0 +1,454 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity apv_lock_sm is + port( CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + SYNC_IN : in std_logic; -- start APV synchronisation + ADC_VALID_IN : in std_logic; -- ADC delivers valid data + TIMED_IN : in std_logic; -- synchronisation timeout + MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter + LOCKED_IN : in std_logic; -- enough good tickmarks + TICK_IN : in std_logic; -- tickmark from digital parser + HEADER_IN : in std_logic; -- header from digital parser + FLATLINE_IN : in std_logic; -- flatline from digital parser + RST_PC_OUT : out std_logic; -- reset period counter + RST_TC_OUT : out std_logic; -- reset timeout counter + INC_TC_OUT : out std_logic; + RST_LC_OUT : out std_logic; -- reset lock counter + INC_LC_OUT : out std_logic; + UNKNOWN_OUT : out std_logic; -- status unknown + BADADC_OUT : out std_logic; -- ADC data invalid + LOCKED_OUT : out std_logic; -- APV locked successfully + LOST_OUT : out std_logic; -- APV sync is lost + NOSYNC_OUT : out std_logic; -- APV sync failed + NOAPV_OUT : out std_logic; -- no APV connected + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of apv_lock_sm is + + -- State definition + -- SLEEP : initial reset state + -- CLEAR : clear counters and registers + -- UWSYNC : wait for SYNC_IN to deassert + -- USYNC : teaching phase, not synchronized yet + -- U_BADM : tickmark found, but local counter mismatch + -- U_BADP : local counter match, but no tickmark found + -- U_GOOD : local counter and tickmark match + -- U_TIME : locking timed out + -- U_FLAT : no APV connected (open input) + -- U_ADC : ADC data is marked invaled (ser2par failed) + -- SYNCED : APV is locked, normal operation state + -- S_BADM : spurious tickmark found => fatal + -- S_BADM : missing tickmark => fatal + -- S_BADD : spurious data frame found, or bad tickmark after dataframe => fatal + -- S_GOOD : local counter and tickmark match + -- S_DATA : data frame header found at correct position + -- S_FR0 : first tickmark period of data frame + -- S_FR1 : second tickmark period of data frame + -- S_FR2 : third tickmark period of data frame + -- S_FR3 : fourth tickmark period of data frame + -- S_ADC : ADC data is marked invalid (ser2par failed) + -- S_LOST : lock lost in normal operation => fatal + + -- state machine signals + type STATES is (SLEEP, CLEAR, USYNC, UWSYNC, U_BADM, U_BADP, U_GOOD, U_TIME, U_FLAT, U_ADC, + SYNCED, S_BADP, S_BADM, S_GOOD, S_DATA, S_FR0, S_FR1, S_FR2, S_FR3, + S_BADD, S_LOST, S_ADC); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- normal signals + signal bsm : std_logic_vector(7 downto 0); + signal debug : std_logic_vector(15 downto 0); + signal next_rst_tc : std_logic; + signal rst_tc : std_logic; + signal next_inc_tc : std_logic; + signal inc_tc : std_logic; + signal next_rst_lc : std_logic; + signal rst_lc : std_logic; + signal next_inc_lc : std_logic; + signal inc_lc : std_logic; + signal next_rst_pc : std_logic; + signal rst_pc : std_logic; + signal next_unknown : std_logic; + signal unknown : std_logic; + signal next_badadc : std_logic; + signal badadc : std_logic; + signal next_locked : std_logic; + signal locked : std_logic; + signal next_lost : std_logic; + signal lost : std_logic; + signal next_nosync : std_logic; + signal nosync : std_logic; + signal next_noapv : std_logic; + signal noapv : std_logic; + signal next_dataframe : std_logic; + signal dataframe : std_logic; + +begin + +debug <= (others => '0'); + +-- state machine for handling synchronisation +-- state registers +STATE_MEM: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + rst_pc <= '0'; + rst_lc <= '0'; + inc_lc <= '0'; + rst_tc <= '0'; + inc_tc <= '0'; + unknown <= '1'; + badadc <= '0'; + locked <= '0'; + lost <= '0'; + nosync <= '0'; + noapv <= '0'; + dataframe <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + rst_pc <= next_rst_pc; + rst_lc <= next_rst_lc; + inc_lc <= next_inc_lc; + rst_tc <= next_rst_tc; + inc_tc <= next_inc_tc; + unknown <= next_unknown; + badadc <= next_badadc; + locked <= next_locked; + lost <= next_lost; + nosync <= next_nosync; + noapv <= next_noapv; + dataframe <= next_dataframe; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, sync_in, match_in, tick_in, header_in, timed_in, locked_in, flatline_in, adc_valid_in ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + next_rst_pc <= '0'; + next_rst_lc <= '0'; + next_inc_lc <= '0'; + next_rst_tc <= '0'; + next_inc_tc <= '0'; + next_unknown <= '0'; + next_badadc <= '0'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + next_dataframe <= '0'; + case CURRENT_STATE is + when SLEEP => if( sync_in = '1' ) then + NEXT_STATE <= CLEAR; -- start synchronisation + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + else + NEXT_STATE <= SLEEP; + next_unknown <= '1'; + end if; + when CLEAR => NEXT_STATE <= UWSYNC; + next_unknown <= '1'; + when UWSYNC => if ( (sync_in = '0') and (adc_valid_in = '1') ) then + NEXT_STATE <= USYNC; + next_unknown <= '1'; + elsif( (sync_in = '0') and (adc_valid_in = '0') ) then + NEXT_STATE <= U_ADC; + next_badadc <= '1'; + else + NEXT_STATE <= UWSYNC; + next_unknown <= '1'; + end if; + when USYNC => if ( (timed_in = '0') and (tick_in = '1') and (match_in = '0') ) then + NEXT_STATE <= U_BADM; -- local timer not correct + next_rst_pc <= '1'; + next_inc_tc <= '1'; + next_rst_lc <= '1'; + next_unknown <= '1'; + elsif( (timed_in = '0') and (tick_in = '0') and (match_in = '1') ) then + NEXT_STATE <= U_BADP; -- tickmark position not correct + next_rst_lc <= '1'; + next_inc_tc <= '1'; + next_unknown <= '1'; + elsif( (timed_in = '1') and (flatline_in = '0') ) then + NEXT_STATE <= U_TIME; -- timeout + next_nosync <= '1'; + elsif( (timed_in = '1') and (flatline_in = '1') ) then + NEXT_STATE <= U_FLAT; -- no APV connected + next_noapv <= '1'; + elsif( (timed_in = '0') and (tick_in = '1') and (locked_in = '0') ) then + NEXT_STATE <= U_GOOD; -- tickmark and counter match + next_inc_lc <= '1'; + next_inc_tc <= '1'; + next_unknown <= '1'; + elsif( (timed_in = '0') and (tick_in = '1') and (locked_in = '1') ) then + NEXT_STATE <= SYNCED; -- finally locked + next_locked <= '1'; + else + NEXT_STATE <= USYNC; -- wait for events + next_unknown <= '1'; + end if; + when U_BADM => NEXT_STATE <= USYNC; + next_unknown <= '1'; + when U_BADP => NEXT_STATE <= USYNC; + next_unknown <= '1'; + when U_GOOD => NEXT_STATE <= USYNC; + next_unknown <= '1'; + when U_FLAT => if( sync_in = '1' ) then + NEXT_STATE <= CLEAR; -- next try + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + else + NEXT_STATE <= U_FLAT; + next_noapv <= '1'; + end if; + when U_TIME => if( sync_in = '1' ) then + NEXT_STATE <= CLEAR; -- next try + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + else + NEXT_STATE <= U_TIME; + next_nosync <= '1'; + end if; + when U_ADC => if( sync_in = '1' ) then + NEXT_STATE <= CLEAR; -- next try + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + else + NEXT_STATE <= U_ADC; + next_badadc <= '1'; + end if; + when SYNCED => if ( sync_in = '1' ) then + NEXT_STATE <= CLEAR; + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + elsif( (sync_in = '0') and (adc_valid_in = '0') ) then + NEXT_STATE <= S_ADC; + next_badadc <= '1'; + elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '0') and (tick_in = '1') and (header_in = '0') ) then + NEXT_STATE <= S_BADM; + next_lost <= '1'; + elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '0') and (tick_in = '0') and (header_in = '1') ) then + NEXT_STATE <= S_BADD; + next_lost <= '1'; + elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '1') and (tick_in = '0') and (header_in = '0') ) then + NEXT_STATE <= S_BADP; + next_lost <= '1'; + elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '1') and (tick_in = '1') ) then + NEXT_STATE <= S_GOOD; + next_locked <= '1'; + elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '1') and (header_in = '1') ) then + NEXT_STATE <= S_DATA; + next_locked <= '1'; + else + NEXT_STATE <= SYNCED; + next_locked <= '1'; + end if; + when S_GOOD => NEXT_STATE <= SYNCED; + next_locked <= '1'; + when S_DATA => if( sync_in = '1' ) then + NEXT_STATE <= CLEAR; + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + else + NEXT_STATE <= S_FR0; + next_dataframe <= '1'; + next_locked <= '1'; + end if; + when S_FR0 => if ( sync_in = '1' ) then + NEXT_STATE <= CLEAR; + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + elsif( (sync_in = '0') and (match_in = '1') ) then + NEXT_STATE <= S_FR1; + next_dataframe <= '1'; + next_locked <= '1'; + else + NEXT_STATE <= S_FR0; + next_dataframe <= '1'; + next_locked <= '1'; + end if; + when S_FR1 => if ( sync_in = '1' ) then + NEXT_STATE <= CLEAR; + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + elsif( (sync_in = '0') and (match_in = '1') ) then + NEXT_STATE <= S_FR2; + next_dataframe <= '1'; + next_locked <= '1'; + else + NEXT_STATE <= S_FR1; + next_dataframe <= '1'; + next_locked <= '1'; + end if; + when S_FR2 => if ( sync_in = '1' ) then + NEXT_STATE <= CLEAR; + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + elsif( (sync_in = '0') and (match_in = '1') ) then + NEXT_STATE <= S_FR3; + next_dataframe <= '1'; + next_locked <= '1'; + else + NEXT_STATE <= S_FR2; + next_dataframe <= '1'; + next_locked <= '1'; + end if; + when S_FR3 => if ( sync_in = '1' ) then + NEXT_STATE <= CLEAR; + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + elsif( (sync_in = '0') and (match_in = '1') and (tick_in = '1') ) then + NEXT_STATE <= SYNCED; + next_locked <= '1'; + elsif( (sync_in = '0') and (match_in = '1') and (header_in = '1') ) then + NEXT_STATE <= S_DATA; + next_locked <= '1'; + elsif( (sync_in = '0') and (match_in = '1') and (header_in = '0') and (tick_in = '0') ) then + NEXT_STATE <= S_BADD; + else + NEXT_STATE <= S_FR3; + next_dataframe <= '1'; + next_locked <= '1'; + end if; + when S_BADD => NEXT_STATE <= S_LOST; + next_lost <= '1'; + when S_BADM => NEXT_STATE <= S_LOST; + next_lost <= '1'; + when S_BADP => NEXT_STATE <= S_LOST; + next_lost <= '1'; + when S_ADC => NEXT_STATE <= S_LOST; + next_lost <= '1'; + when S_LOST => if( sync_in = '1' ) then + NEXT_STATE <= CLEAR; -- next try + next_rst_pc <= '1'; + next_rst_lc <= '1'; + next_rst_tc <= '1'; + next_unknown <= '1'; + next_locked <= '0'; + next_lost <= '0'; + next_nosync <= '0'; + next_noapv <= '0'; + else + NEXT_STATE <= S_LOST; + next_lost <= '1'; + end if; + when others => NEXT_STATE <= SLEEP; + next_unknown <= '1'; + end case; +end process STATE_TRANSFORM; + +-- state decoding +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SLEEP => bsm <= x"00"; + when CLEAR => bsm <= x"01"; + when UWSYNC => bsm <= x"20"; + when USYNC => bsm <= x"02"; + when U_BADM => bsm <= x"03"; + when U_BADP => bsm <= x"04"; + when U_FLAT => bsm <= x"05"; + when U_GOOD => bsm <= x"06"; + when U_TIME => bsm <= x"07"; + when U_ADC => bsm <= x"08"; + when SYNCED => bsm <= x"09"; + when S_BADP => bsm <= x"0a"; + when S_BADM => bsm <= x"0b"; + when S_GOOD => bsm <= x"0c"; + when S_DATA => bsm <= x"0d"; + when S_FR0 => bsm <= x"0e"; + when S_FR1 => bsm <= x"0f"; + when S_FR2 => bsm <= x"10"; + when S_FR3 => bsm <= x"11"; + when S_BADD => bsm <= x"12"; + when S_ADC => bsm <= x"13"; + when S_LOST => bsm <= x"14"; + when others => bsm <= x"ff"; + end case; +end process STATE_DECODE; + +-- output signals +debug_out <= debug; +bsm_out <= bsm; +unknown_out <= unknown; +badadc_out <= badadc; +locked_out <= locked; +lost_out <= lost; +nosync_out <= nosync; +noapv_out <= noapv; +rst_pc_out <= rst_pc; +rst_lc_out <= rst_lc; +rst_tc_out <= rst_tc; +inc_lc_out <= inc_lc; +inc_tc_out <= inc_tc; + +end behavioral; diff --git a/src/apv_locker.vhd b/src/apv_locker.vhd new file mode 100755 index 0000000..ee48a47 --- /dev/null +++ b/src/apv_locker.vhd @@ -0,0 +1,434 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +-- This block takes care of syncing in the APVs. Only "synced" APVs are allowed to deliver data streams +-- to the processing units. + +entity apv_locker is + port( CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to CLK_APV_IN + ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid + -- Slow control input, mainly digital thresholds here + SYNC_IN : in std_logic; -- sync pulse input + APV_ON_IN : in std_logic; -- this APV channel is switched on + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0' + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1' + FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline + -- Generic APV status outputs (valid only if ADC_CLK_IN is working!) + STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off) + STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid + STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet + STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully + STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong + STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully + STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected + STATUS_TICKMARK_OUT : out std_logic; + -- Frame related status, to be stored in the raw status buffer + -- Information is valid with APV_LAST_OUT, except FRAME_ERROR_OUT, FRAME_ROW_OUT and + -- FRAME_CTR_OUT which are valid with beginning of APV_ANALOG_OUT. + FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header + FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header + FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?) + FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow + FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow + FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames + -- Channel related information, to be stored in the raw data buffer + APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID + APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high + APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low + APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data + APV_ANALOG_OUT : out std_logic; -- APV analog data is valid + APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer + APV_LAST_OUT : out std_logic; -- last APV channel of dataframe + -- Debug information + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of apv_locker is + + -- normal signals + signal lock_bsm : std_logic_vector(7 downto 0); + signal tickmark_found : std_logic; + signal header_found : std_logic; + signal flatline_found : std_logic; + signal status_unknown : std_logic; + signal status_badadc : std_logic; + signal status_locked : std_logic; + signal status_lost : std_logic; + signal status_nosync : std_logic; + signal status_missing : std_logic; + signal next_status_ignore : std_logic; + signal status_ignore : std_logic; + signal frame_flat : std_logic; + signal next_frame_ovf : std_logic; + signal frame_ovf : std_logic; + signal next_frame_udf : std_logic; + signal frame_udf : std_logic; + signal frame_row : std_logic_vector(7 downto 0); + signal frame_error : std_logic; + signal bit_data : std_logic_vector(11 downto 0); + signal bit_valid : std_logic_vector(11 downto 0); + + signal rst_pc_sm : std_logic; + signal rst_pc_ctr : std_logic; + signal pc_ctr : std_logic_vector(5 downto 0); + signal next_pc_match : std_logic; + signal pc_match : std_logic; + + signal rst_tc_sm : std_logic; + signal inc_tc_sm : std_logic; + signal tc_ctr : std_logic_vector(3 downto 0); + signal next_sync_timeout : std_logic; + signal sync_timeout : std_logic; + + signal rst_lc_sm : std_logic; + signal inc_lc_sm : std_logic; + signal lc_ctr : std_logic_vector(3 downto 0); + signal next_sync_success : std_logic; + signal sync_success : std_logic; + + signal delay_store : std_logic_vector(7 downto 0); + signal store_header : std_logic; + + signal apv_channel : std_logic_vector(6 downto 0); + signal ce_chnl_ctr : std_logic; + signal frame_analog : std_logic; + signal set_frame_analog : std_logic; + signal rst_frame_analog : std_logic; + signal next_apv_last : std_logic; + signal apv_last : std_logic; + signal apv_start : std_logic; + + signal adc_raw_one : std_logic_vector(11 downto 0); + signal adc_raw_two : std_logic_vector(11 downto 0); + + signal bit_high : std_logic; + signal bit_low : std_logic; + signal apv_overflow : std_logic; + signal apv_underflow : std_logic; + + signal next_ce_underflow : std_logic; + signal next_ce_overflow : std_logic; + + signal sum_ovf : std_logic_vector(7 downto 0); + signal sum_udf : std_logic_vector(7 downto 0); + + signal frame_ctr : std_logic_vector(3 downto 0); + signal comb_ce_frame_ctr : std_logic; + + signal debug : std_logic_vector(15 downto 0); + + signal apv_on : std_logic; -- 40MHz clock domain register + +begin + +-- Debug signals +debug <= (others => '0'); + +-- Clock domain crossing +THE_APVON_SYNCER: state_sync +port map( STATE_A_IN => apv_on_in, + CLK_B_IN => clk_apv_in, + RESET_B_IN => reset_in, + STATE_B_OUT => apv_on + ); + +-- Input stage, for tickmark and header recognition, and bit decoding. +-- Also detects missing APVs by flatline. +THE_APV_DIGITAL: apv_digital +port map( CLK_APV_IN => clk_apv_in, + RESET_IN => reset_in, + ADC_RAW_IN => adc_raw_in, + BIT_LOW_IN => bit_low_in, + BIT_HIGH_IN => bit_high_in, + FL_LOW_IN => fl_low_in, + FL_HIGH_IN => fl_high_in, + BIT_DATA_OUT => bit_data, + BIT_VALID_OUT => bit_valid, -- for testing! + BIT_HIGH_OUT => bit_high, -- for analog off recognition, one cycle earlier + BIT_LOW_OUT => bit_low, -- for analog off recognition, one cycle earlier + TICKMARK_OUT => tickmark_found, + HEADER_OUT => header_found, + FLAT_LINE_OUT => flatline_found + ); + +-- Count enables for the underflow / overflow counters +next_ce_underflow <= '1' when (bit_high = '0' and bit_low = '1' and frame_analog = '1') else '0'; +next_ce_overflow <= '1' when (bit_high = '1' and bit_low = '0' and frame_analog = '1') else '0'; + +-- Counter for underflow channels +THE_UNDERFLOW_CTR_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( (reset_in = '1') or (delay_store(1) = '1') ) then + sum_udf <= (others => '0'); + elsif( next_ce_underflow = '1' ) then + sum_udf <= sum_udf + 1; + end if; + end if; +end process THE_UNDERFLOW_CTR_PROC; + +-- Reduced information: at least one channel was underflow +next_frame_udf <= '1' when (sum_udf /= x"00") else '0'; +-- Reduced information: all channels in a frame were underflow +frame_flat <= sum_udf(7); + +-- Counter for Overflow channels +THE_OVERFLOW_CTR_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( (reset_in = '1') or (delay_store(1) = '1') ) then + sum_ovf <= (others => '0'); + elsif( next_ce_overflow = '1' ) then + sum_ovf <= sum_ovf + 1; + end if; + end if; +end process THE_OVERFLOW_CTR_PROC; + +-- Reduced information: at least one channel was underflow +next_frame_ovf <= '1' when (sum_ovf /= x"00") else '0'; + +THE_SYNC_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + apv_overflow <= next_ce_overflow; + apv_underflow <= next_ce_underflow; + frame_ovf <= next_frame_ovf; + frame_udf <= next_frame_udf; + status_ignore <= next_status_ignore; + end if; +end process THE_SYNC_PROC; + +-- locking state machine +THE_APV_LOCK_SM: apv_lock_sm +port map( CLK_APV_IN => clk_apv_in, + RESET_IN => reset_in, + SYNC_IN => sync_in, -- 40 MHz signal! + ADC_VALID_IN => adc_valid_in, + TIMED_IN => sync_timeout, + MATCH_IN => pc_match, + LOCKED_IN => sync_success, + TICK_IN => tickmark_found, + HEADER_IN => header_found, + FLATLINE_IN => flatline_found, + RST_PC_OUT => rst_pc_sm, + RST_TC_OUT => rst_tc_sm, + INC_TC_OUT => inc_tc_sm, + RST_LC_OUT => rst_lc_sm, + INC_LC_OUT => inc_lc_sm, + UNKNOWN_OUT => status_unknown, + BADADC_OUT => status_badadc, + LOCKED_OUT => status_locked, + LOST_OUT => status_lost, + NOSYNC_OUT => status_nosync, + NOAPV_OUT => status_missing, + BSM_OUT => lock_bsm, + DEBUG_OUT => open + ); + +next_status_ignore <= not apv_on; + + +-- synchronous reset for period counter (either by counter, or by state machine) +next_pc_match <= '1' when ( pc_ctr = "100000" ) else '0'; -- "100001" + +-- period counter (0..34) for one tickmark period +THE_PERIOD_COUNTER: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if ( (reset_in = '1') or (rst_pc_sm = '1') or (rst_pc_ctr = '1')) then + pc_ctr <= (others => '0'); + pc_match <= '0'; + rst_pc_ctr <= '0'; + else + pc_ctr <= pc_ctr + 1; + pc_match <= next_pc_match; + rst_pc_ctr <= pc_match; + end if; + end if; +end process THE_PERIOD_COUNTER; + +-- watermark for the synchronisation timeout +next_sync_timeout <= '1' when ( tc_ctr = x"f" ) else '0'; + +-- timeout counter for the lock process +THE_TIMEOUT_COUNTER: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if ( (reset_in = '1') or (rst_tc_sm = '1') ) then + tc_ctr <= (others => '0'); + sync_timeout <= '0'; + elsif( inc_tc_sm = '1' ) then + tc_ctr <= tc_ctr + 1; + sync_timeout <= next_sync_timeout; + end if; + end if; +end process THE_TIMEOUT_COUNTER; + +-- watermark for the successful synchronisation +next_sync_success <= '1' when ( lc_ctr = x"8" ) else '0'; + +-- lock counter for the lock process +THE_LOCK_COUNTER: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if ( (reset_in = '1') or (rst_lc_sm = '1') ) then + lc_ctr <= (others => '0'); + sync_success <= '0'; + elsif( inc_lc_sm = '1' ) then + lc_ctr <= lc_ctr + 1; + sync_success <= next_sync_success; + end if; + end if; +end process THE_LOCK_COUNTER; + +-- registering the APV header needs some delay for header_found +THE_DELAY_LINE: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + delay_store <= (others => '0'); + else + delay_store(7 downto 1) <= delay_store(6 downto 0); + -- we only accept data frames when they arrive at a well defined tickmark place, + -- when the APV is really switched on, and it is in locked state. + delay_store(0) <= header_found and pc_match and apv_on and status_locked; + end if; + end if; +end process THE_DELAY_LINE; + +-- frame start signal for early blocking of the buffer page +apv_start <= delay_store(0); + +-- here we can adjust the correct delay for the pipelining +store_header <= delay_store(7); + +-- enable signal for underflow / overflow counters +next_apv_last <= '1' when (apv_channel = "1111110") else '0'; +set_frame_analog <= '1' when (delay_store(6) = '1') else '0'; +rst_frame_analog <= '1' when (next_apv_last = '1') else '0'; + +-- frame counter clock enable +comb_ce_frame_ctr <= apv_last; + +-- analog frame, one cycle before output data. +THE_FRAME_ANALOG_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + frame_analog <= '0'; + elsif( set_frame_analog = '1' ) then + frame_analog <= '1'; + elsif( rst_frame_analog = '1' ) then + frame_analog <= '0'; + end if; + end if; +end process THE_FRAME_ANALOG_PROC; + +-- real counter for channels is one cycle later +THE_CE_CHNL_CTR_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_in = '1' ) then + ce_chnl_ctr <= '0'; + else + ce_chnl_ctr <= frame_analog; + end if; + end if; +end process THE_CE_CHNL_CTR_PROC; + +-- Channel counter, used for timing and PID generation +THE_CHANNEL_CTR: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if ( reset_in = '1' ) then + apv_channel <= (others => '0'); + apv_last <= '0'; + elsif( ce_chnl_ctr = '1' ) then + apv_channel <= apv_channel + 1; + apv_last <= next_apv_last; + end if; + end if; +end process THE_CHANNEL_CTR; + +THE_APV_RAW_DELAY: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + adc_raw_two <= adc_raw_one; + adc_raw_one <= adc_raw_in; + end if; +end process THE_APV_RAW_DELAY; + +-- storage registers +THE_HEADER_STORAGE_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if ( reset_in = '1' ) then + frame_error <= '0'; -- bit is inverted! + frame_row <= (others => '0'); + elsif( store_header = '1' ) then + frame_error <= not bit_data(0); -- bit is inverted! + frame_row <= bit_data(8 downto 1); + end if; + end if; +end process THE_HEADER_STORAGE_PROC; + +-- frame counter logic +THE_FRAME_CTR_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if ( reset_in = '1' ) then + frame_ctr <= (others => '0'); + elsif( comb_ce_frame_ctr = '1' ) then + frame_ctr <= frame_ctr + 1; + end if; + end if; +end process THE_FRAME_CTR_PROC; + + +-- output signals +status_ignore_out <= status_ignore; +status_unknown_out <= status_unknown; +status_badadc_out <= status_badadc; +status_locked_out <= status_locked; +status_lost_out <= status_lost; +status_nosync_out <= status_nosync; +status_missing_out <= status_missing; +status_tickmark_out <= pc_match; + +-- Changing SID to PID on the fly for free +-- Keep in mind: 1- 0- 3- 2- 6- 5- 4 +apv_channel_out(6) <= apv_channel(1); +apv_channel_out(5) <= apv_channel(0); +apv_channel_out(4) <= apv_channel(3); +apv_channel_out(3) <= apv_channel(2); +apv_channel_out(2) <= apv_channel(6); +apv_channel_out(1) <= apv_channel(5); +apv_channel_out(0) <= apv_channel(4); + +apv_raw_out <= adc_raw_two; +apv_overflow_out <= apv_overflow; +apv_underflow_out <= apv_underflow; +apv_analog_out <= ce_chnl_ctr; +apv_start_out <= apv_start; +apv_last_out <= apv_last; + +frame_flat_out <= frame_flat; +frame_ovf_out <= frame_ovf; +frame_udf_out <= frame_udf; +frame_ctr_out <= frame_ctr; +frame_error_out <= frame_error; +frame_row_out <= frame_row; + +-- Debug signals, do not use! +debug_out <= debug; + +end behavioral; diff --git a/src/apv_map_mem.lpc b/src/apv_map_mem.lpc new file mode 100644 index 0000000..d52bb95 --- /dev/null +++ b/src/apv_map_mem.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_ROM +CoreRevision=2.4 +ModuleName=apv_map_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/14/2009 +Time=17:47:59 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=128 +Data=4 +LUT=0 +MemFile=i:/vhdl_pro/adcmv3/src/apv_mapping.mem +MemFormat=orca diff --git a/src/apv_map_mem.srp b/src/apv_map_mem.srp new file mode 100644 index 0000000..d3b5189 --- /dev/null +++ b/src/apv_map_mem.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Oct 14 17:47:59 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e + Circuit name : apv_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem + EDIF output : suppressed + VHDL output : apv_map_mem.vhd + VHDL template : apv_map_mem_tmpl.vhd + VHDL testbench : tb_apv_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : apv_map_mem.srp + Element Usage : + ROM128X1 : 4 + Estimated Resource Usage: + LUT : 16 diff --git a/src/apv_map_mem.vhd b/src/apv_map_mem.vhd new file mode 100644 index 0000000..3c2f90e --- /dev/null +++ b/src/apv_map_mem.vhd @@ -0,0 +1,81 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 7 -num_rows 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e + +-- Wed Oct 14 17:47:59 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity apv_map_mem is + port ( + Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end apv_map_mem; + +architecture Structure of apv_map_mem is + + -- local component declarations + component ROM128X1 + -- synopsys translate_off + generic (INITVAL : in String); + -- synopsys translate_on + port (AD6: in std_logic; AD5: in std_logic; AD4: in std_logic; + AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + attribute initval : string; + attribute initval of mem_0_3 : label is "0xFF00FF00FF001FE0E01F7F80807F6956"; + attribute initval of mem_0_2 : label is "0xF0F0F0F0F0F0079DF8621E0FE1F0E287"; + attribute initval of mem_0_1 : label is "0xCCCCCCCCCCCC867A798519ECE6139D07"; + attribute initval of mem_0_0 : label is "0xAAAAAAAAAAAA3553CAAC355ACAA5B1E2"; + +begin + -- component instantiation statements + mem_0_3: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xFF00FF00FF001FE0E01F7F80807F6956") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(3)); + + mem_0_2: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xF0F0F0F0F0F0079DF8621E0FE1F0E287") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(2)); + + mem_0_1: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xCCCCCCCCCCCC867A798519ECE6139D07") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(1)); + + mem_0_0: ROM128X1 + -- synopsys translate_off + generic map (initval=> "0xAAAAAAAAAAAA3553CAAC355ACAA5B1E2") + -- synopsys translate_on + port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4), + AD3=>Address(3), AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(0)); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of apv_map_mem is + for Structure + for all:ROM128X1 use entity ecp2m.ROM128X1(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/apv_map_mem_generate.log b/src/apv_map_mem_generate.log new file mode 100644 index 0000000..49afe96 --- /dev/null +++ b/src/apv_map_mem_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Oct 14 17:47:59 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e + Circuit name : apv_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Data width : 4 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem + EDIF output : suppressed + VHDL output : apv_map_mem.vhd + VHDL template : apv_map_mem_tmpl.vhd + VHDL testbench : tb_apv_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : apv_map_mem.srp + Estimated Resource Usage: + LUT : 16 + +END SCUBA Module Synthesis + +File: ..\src\apv_map_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/apv_map_mem_tmpl.vhd b/src/apv_map_mem_tmpl.vhd new file mode 100644 index 0000000..daaa9a8 --- /dev/null +++ b/src/apv_map_mem_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Wed Oct 14 17:47:59 2009 + +-- parameterized module component declaration +component apv_map_mem + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : apv_map_mem + port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/src/apv_mapping.mem b/src/apv_mapping.mem new file mode 100644 index 0000000..1c4a8c6 --- /dev/null +++ b/src/apv_mapping.mem @@ -0,0 +1,155 @@ +#Format=Address-Hex +#Depth=128 +#DataWidth=4 +#AddrRadix=3 +#DataRadix=3 + +# Backplane 0 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1 +# +# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# realADC 6 15 14 0 8 1 9 5 b 4 2 a 3 d c 7 +00: 6 +01: f +02: e +03: 0 +04: 8 +05: 1 +06: 9 +07: 5 +08: b +09: 4 +0a: 2 +0b: a +0c: 3 +0d: d +0e: c +0f: 7 +# Backplane 1 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 - +10: b +11: a +12: 9 +13: 8 +14: e +15: d +16: c +17: 5 +18: 4 +19: 3 +1a: 2 +1b: 1 +1c: 0 +1d: 6 +1e: 7 +1f: f +# Backplane 2 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12 +20: 4 +21: 5 +22: 6 +23: 7 +24: 1 +25: 2 +26: 3 +27: a +28: b +29: c +2a: d +2b: e +2c: f +2d: 9 +2e: 8 +2f: 0 +# Backplane 3 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14 +30: a +31: c +32: b +33: 9 +34: 8 +35: 5 +36: 4 +37: 3 +38: 2 +39: 1 +3a: 0 +3b: 7 +3c: 6 +3d: e +3e: f +3f: d +# Backplane 4 +# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +# mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10 +40: 5 +41: 3 +42: 4 +43: 6 +44: 7 +45: a +46: b +47: c +48: d +49: e +4a: f +4b: 8 +4c: 9 +4d: 1 +4e: 0 +4f: 2 +# unused (5) => 1:1 +50: 0 +51: 1 +52: 2 +53: 3 +54: 4 +55: 5 +56: 6 +57: 7 +58: 8 +59: 9 +5a: a +5b: b +5c: c +5d: d +5e: e +5f: f +# unused (6) => 1:1 +60: 0 +61: 1 +62: 2 +63: 3 +64: 4 +65: 5 +66: 6 +67: 7 +68: 8 +69: 9 +6a: a +6b: b +6c: c +6d: d +6e: e +6f: f +# unused (7) => 1:1 +70: 0 +71: 1 +72: 2 +73: 3 +74: 4 +75: 5 +76: 6 +77: 7 +78: 8 +79: 9 +7a: a +7b: b +7c: c +7d: d +7e: e +7f: f diff --git a/src/apv_pc_nc_alu.vhd b/src/apv_pc_nc_alu.vhd new file mode 100644 index 0000000..04668c7 --- /dev/null +++ b/src/apv_pc_nc_alu.vhd @@ -0,0 +1,360 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +-- IMPORTANT: 0,2,4,...,126 => physics channels +-- 1,3,5,...,127 => empty channels + +-- This unit takes frame data (channel order is fixed) and +-- applies different steps of analysis depening on evt_type_in. +-- Data is piped out directly. + +entity apv_pc_nc_alu is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + START_IN : in std_logic; -- start signal, used for initialisation of counters + MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested + CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number + LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + BUF_GOOD_IN : in std_logic; -- process buffer + BUF_BAD_IN : in std_logic; -- write only error header + BUF_IGNORE_IN : in std_logic; -- do not write anything + ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers + DO_HEADER_IN : in std_logic; + DO_ERROR_IN : in std_logic; + EVT_TYPE_IN : in std_logic_vector(2 downto 0); + RAW_ADDR_IN : in std_logic_vector(6 downto 0); + RAW_DATA_IN : in std_logic_vector(37 downto 0); + PED_DATA_IN : in std_logic_vector(17 downto 0); + THR_DATA_IN : in std_logic_vector(17 downto 0); + FRAME_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0] + WE_OUT : out std_logic; + COUNT_OUT : out std_logic_vector(9 downto 0); + ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout + DBG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +---------------------------------------------------------------------- +-- LIMITATION: 4 frames with 128 channels each => 512 +-- + debug words <= 1023!!!! +---------------------------------------------------------------------- + +architecture behavioral of apv_pc_nc_alu is + + -- normal signals + signal raw_data_q : std_logic_vector(12 downto 0); -- input register + signal ped_data_q : std_logic_vector(12 downto 0); -- input register + signal ped_corr_data_q : std_logic_vector(12 downto 0); -- registered pedestal corrected value + signal ped_corr_data_qq : std_logic_vector(12 downto 0); -- registered pedestal corrected value + signal ped_corr_data_qqq : std_logic_vector(12 downto 0); -- registered pedestal corrected value + signal loc_baseline_q : std_logic_vector(13 downto 0); + signal nc_corr_data_q : std_logic_vector(13 downto 0); + signal nc_corr_data_qq : std_logic_vector(13 downto 0); + signal nc_corr_data_qqq : std_logic_vector(21 downto 0); + signal thr_data_q : std_logic_vector(13 downto 0); + signal udf_int : std_logic_vector(6 downto 0); + signal ovf_int : std_logic_vector(6 downto 0); + signal frame_int : std_logic_vector(6 downto 0); + signal off_int : std_logic_vector(6 downto 0); + signal next_data_we : std_logic; + signal data_we : std_logic; + + signal thr_pass : std_logic; + + -- data steering signals + signal next_ped_off : std_logic; + signal ped_off : std_logic; -- switch off pedestals + signal next_lcb_off : std_logic; + signal lcb_off : std_logic; -- switch off local baseline correction + signal next_clip_max : std_logic; + signal clip_max : std_logic; -- clip OVF values to maximum + signal next_clip_min : std_logic; + signal clip_min : std_logic; -- clip UDF values to minimum + signal next_bad_corr : std_logic_vector(6 downto 2); + signal bad_corr : std_logic_vector(6 downto 2); + signal toggle : std_logic_vector(6 downto 0); + + -- Channel counter + signal channel : std_logic_vector(6 downto 0); + + signal count : std_logic_vector(9 downto 0); + + signal anydata : std_logic; + + -- Debug signals + signal debug : std_logic_vector(15 downto 0); + +begin + +--------------------------------------------------------------------------------- +-- Data steering signals: they decide, which stages of the calculation are taken. +-- +-- evt_type mnemonic channels actions +-- 000 RAW128 128 raw data (+ 4096 + 8192) +-- 001 PED128 128 pedestal data (+ 4096 - pedestal) +-- 010 PED128THR <=128 pedestal data above threshold +-- 011 --- --- --- +-- 100 NC64PED64 128 do NC on physic channels, corr. channels pedestal corrected +-- 101 NC64 64 only NC physic channels +-- 110 NC64GOOD <=64 only good NC channels +-- 111 NC64THR <=64 only good NC channels above threshold +--------------------------------------------------------------------------------- + +-- Switch off pedestals (RAW128 mode) +next_ped_off <= '1' when ( evt_type_in = "000" ) else '0'; + +-- Switch off local baseline (RAW128, PED128, PED128THR modes) +next_lcb_off <= '1' when ( (evt_type_in = "000") or (evt_type_in = "001") or (evt_type_in = "010") ) else '0'; + +-- Clipping function for neighbour corrected values (all modes except RAW128) +next_clip_min <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or (evt_type_in = "011") or + (evt_type_in(2) = '1') ) and (udf_int(2) = '1') ) + else '0'; +next_clip_max <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or (evt_type_in = "011") or + (evt_type_in(2) = '1') ) and (ovf_int(2) = '1') ) + else '0'; + +-- Neighbour correction: handle broken or switched off correction channels. +-- A broken (UDF/OVF) or switched off (OFF) correction channel kills its two physical neighbour channels. +next_bad_corr(2) <= '1' when ( (udf_int(0) = '1') or (udf_int(2) = '1') or + (ovf_int(0) = '1') or (ovf_int(2) = '1') or + (off_int(0) = '1') or (off_int(2) = '1') ) + else '0'; + +next_bad_corr(3) <= '1' when ( (bad_corr(2) = '1') and (evt_type_in(2) = '1') ) else '0'; + +next_bad_corr(4) <= '1' when ( ((bad_corr(3) = '1') and (toggle(3) = '1') and (frame_int(3) = '1')) or + (off_int(3) = '1') ) + else '0'; +next_bad_corr(5) <= bad_corr(4); +next_bad_corr(6) <= bad_corr(5); + +-- We carry the OVF/UDF/OFF information all through the chain! +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + ped_off <= next_ped_off; + lcb_off <= next_lcb_off; + clip_min <= next_clip_min; + clip_max <= next_clip_max; + bad_corr(6 downto 2) <= next_bad_corr(6 downto 2); -- combinatorial feed + toggle(6 downto 0) <= toggle(5 downto 0) & raw_addr_in(0); + udf_int(6 downto 0) <= udf_int(5 downto 0) & raw_data_in(12); + ovf_int(6 downto 0) <= ovf_int(5 downto 0) & raw_data_in(13); + frame_int(6 downto 0) <= frame_int(5 downto 0) & frame_in; + off_int(6 downto 0) <= off_int(5 downto 0) & ped_data_in(16); + data_we <= next_data_we; + end if; +end process THE_SYNC_PROC; + +-- Input register, add 4096 to raw ADC values +THE_RAW_INPUT_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + raw_data_q <= '1' & raw_data_in(11 downto 0); + end if; +end process THE_RAW_INPUT_PROC; + +-- Input register, either pipe in the pedestal value, or set it to zero +THE_PED_INPUT_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( (reset_in = '1') or (ped_off = '1') ) then + ped_data_q <= (others => '0'); + else + ped_data_q <= '0' & ped_data_in(11 downto 0); + end if; + end if; +end process THE_PED_INPUT_PROC; + +-- Pedestal correction, store PC value, shift it for NC +THE_PED_CORR_STORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + ped_corr_data_q <= raw_data_q - ped_data_q; + end if; +end process THE_PED_CORR_STORE_PROC; + +-- Delay the pedestal corrected values by two clock cycles +THE_PED_CORR_DELAY_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + ped_corr_data_qqq <= ped_corr_data_qq; + ped_corr_data_qq <= ped_corr_data_q; + end if; +end process THE_PED_CORR_DELAY_PROC; + +-- Mean value calculation for local baseline correction +THE_MEAN_CALC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( (reset_in = '1') or (lcb_off = '1') ) then + loc_baseline_q <= (others => '0'); + else + loc_baseline_q <= ('0' & ped_corr_data_q) + ('0' & ped_corr_data_qqq); + end if; + end if; +end process THE_MEAN_CALC_PROC; + +-- Do the neighbour correction +THE_NC_CORR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (reset_in = '1') or (clip_min = '1') ) then + nc_corr_data_q <= (others => '0'); -- channel is underflow + elsif( clip_max = '1' ) then + nc_corr_data_q <= (others => '1'); -- channel is overflow + else + nc_corr_data_q <= ('1' & ped_corr_data_qqq) - ('0' & loc_baseline_q(13 downto 1)); + end if; + end if; +end process THE_NC_CORR_PROC; + +-- One caveat: in PED128 our artificial baseline is 4096, in NC64THR it is 8192. +thr_data_q(13) <= '1'; --'1' when (evt_type_in = "111") else '0'; +thr_data_q(12) <= '0' when (evt_type_in = "111") else '1'; + +-- Threshold comparison +THE_THR_COMP: comp14bit +port map( DATAA => nc_corr_data_q, + DATAB => thr_data_q, + CLOCK => clk_in, + CLOCKEN => '1', + ACLR => reset_in, -- BUG 10092009 + AGEB => thr_pass + ); + +-- Delay NCD by one cycle, store THR data +THE_NC_DELAY_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + nc_corr_data_qqq <= (others => '0'); + nc_corr_data_qq <= (others => '0'); + thr_data_q(11 downto 0) <= (others => '0'); + else + if ( (do_header_in = '0') and (do_error_in = '0') ) then + nc_corr_data_qqq(21) <= '0'; -- DATA + nc_corr_data_qqq(20 downto 14) <= channel; + nc_corr_data_qqq(13 downto 0) <= nc_corr_data_qq; + elsif( (do_header_in = '1') ) then + nc_corr_data_qqq(21) <= '1'; -- HEADER + nc_corr_data_qqq(20) <= buf_bad_in; + nc_corr_data_qqq(19 downto 16) <= error_in; + nc_corr_data_qqq(15 downto 12) <= max_frames_in; + nc_corr_data_qqq(11 downto 8) <= curr_frame_in; + nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18); + elsif( (do_error_in = '1') ) then + nc_corr_data_qqq(21) <= '1'; -- HEADER + nc_corr_data_qqq(20) <= raw_data_in(26); -- error + nc_corr_data_qqq(19 downto 16) <= eds_frm_ctr_in; -- EDS start frame + nc_corr_data_qqq(15 downto 12) <= loc_frm_ctr_in; -- local frame counter value + nc_corr_data_qqq(11 downto 8) <= raw_data_in(17 downto 14); -- frame counter + nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18); -- row + end if; + nc_corr_data_qq <= nc_corr_data_q; + thr_data_q(11 downto 0) <= thr_data_in(11 downto 0); + end if; + end if; +end process THE_NC_DELAY_PROC; + +-- Judgement day: will data survive? +next_data_we <= '1' when ( ((buf_good_in = '1') and (evt_type_in = "000") and (frame_int(5) = '1')) or + ((buf_good_in = '1') and (evt_type_in = "001") and (frame_int(5) = '1')) or + ((buf_good_in = '1') and (evt_type_in = "010") and (frame_int(5) = '1') and (thr_pass = '1') and (bad_corr(5) = '0')) or + ((buf_good_in = '1') and (evt_type_in = "100") and (frame_int(5) = '1')) or + ((buf_good_in = '1') and (evt_type_in = "101") and (frame_int(5) = '1') and (toggle(5) = '1')) or + ((buf_good_in = '1') and (evt_type_in = "110") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0')) or + ((buf_good_in = '1') and (evt_type_in = "111") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0') and (thr_pass = '1')) or + (((buf_good_in = '1') or (buf_bad_in = '1')) and (do_header_in = '1')) or +-- ((buf_bad_in = '1') and (do_error_in = '1')) + ((do_error_in = '1')) + ) + else '0'; + +-- Channel counter for outgoing data +THE_CHANNEL_CTR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (reset_in = '1') or (start_in = '1') ) then + channel <= (others => '0'); + elsif( frame_int(5) = '1' ) then + channel <= channel + 1; + end if; + end if; +end process THE_CHANNEL_CTR_PROC; + +-- Channel counter for outgoing data +THE_DATA_CTR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (reset_in = '1') or (start_in = '1') ) then + count <= (others => '0'); + anydata <= '0'; + elsif( (data_we = '1') and (anydata = '0') ) then + anydata <= '1'; + elsif( (data_we = '1') and (anydata = '1') ) then + count <= count + 1; + end if; + end if; +end process THE_DATA_CTR_PROC; + +-- output signals (most of them are only needed for simulation!) +we_out <= data_we; +count_out <= count; +anydata_out <= anydata; + +-- Real FIFO input. We use a 2kx27 FIFO, with only 22bit carrying real information. +-- [26:22] are used for debugging information +-- [21] will become D[31] in data (flag for data/header) +-- [20:14] gives channel number +-- [13:0] ADC data +fifo_data_out(26) <= frame_int(6); +fifo_data_out(25) <= data_we; +fifo_data_out(24) <= bad_corr(6); +fifo_data_out(23) <= ovf_int(6); +fifo_data_out(22) <= udf_int(6); +fifo_data_out(21 downto 0) <= nc_corr_data_qqq; + +-- Debug signals +--debug(31 downto 16) <= (others => '0'); +debug(15) <= thr_pass; +debug(14) <= '0'; +debug(13 downto 0) <= thr_data_q; + +dbg_out <= debug; + +end behavioral; + +--THE_NC_DELAY_PROC: process( clk_in ) +--begin +-- if( rising_edge(clk_in) ) then +-- if( reset_in = '1' ) then +-- nc_corr_data_qqq <= (others => '0'); +-- nc_corr_data_qq <= (others => '0'); +-- thr_data_q(11 downto 0) <= (others => '0'); +-- else +-- if( (do_header_in = '0') and (do_error_in = '0') ) then +-- nc_corr_data_qqq(21) <= '0'; -- DATA +-- nc_corr_data_qqq(20 downto 14) <= channel; +-- nc_corr_data_qqq(13 downto 0) <= nc_corr_data_qq; +-- else +-- nc_corr_data_qqq(21) <= '1'; -- HEADER +-- nc_corr_data_qqq(20) <= buf_bad_in; +-- nc_corr_data_qqq(19 downto 16) <= error_in; +-- nc_corr_data_qqq(15 downto 12) <= max_frames_in; +-- nc_corr_data_qqq(11 downto 8) <= curr_frame_in; +-- nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18); +-- end if; +-- nc_corr_data_qq <= nc_corr_data_q; +-- thr_data_q(11 downto 0) <= thr_data_in(11 downto 0); +-- end if; +-- end if; +--end process THE_NC_DELAY_PROC; diff --git a/src/apv_raw_buffer.vhd b/src/apv_raw_buffer.vhd new file mode 100755 index 0000000..47d3f24 --- /dev/null +++ b/src/apv_raw_buffer.vhd @@ -0,0 +1,394 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +-- This entity is used to decouple the ADC/APV part (with 40MHz) from the data +-- handling part (which runs with 100MHz). +-- Signals: +-- - all signals starting with ADC_* are synchronous to CLK_APV_IN +-- - all signals starting with BUF_* are synchronous to BUF_CLK_IN +-- - BUF_GOOD_OUT, BUF_BROKEN_OUT and BUF_IGNORE_OUT are to be checked if BUF_LEVEL_OUT[4:0] = 0 +-- - otherwise BUF_LEVEL_OUT[4:0] tells you how many frames are in the buffer +-- - take care of the one clock delay between BUF_ADDR_IN and BUF_DATA_OUT. + +entity apv_raw_buffer is + port( CLK_APV_IN : in std_logic; -- write clock from APV handling stage + RESET_IN : in std_logic; + -- buffer level control signals + FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event + -- CLK_APV_IN sync'ed signals from APV_LOCKER + ADC_ANALOG_IN : in std_logic; -- write enable for ADC data + ADC_START_IN : in std_logic; -- data frame detected, block the buffer page + ADC_LAST_IN : in std_logic; -- last channel signal + ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID + ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR + ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV + ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame + -- BUF_CLK_IN sync'ed signals from back side logic + BUF_CLK_IN : in std_logic; -- read clock + BUF_RESET_IN : in std_logic; -- 100MHz reset + BUF_START_OUT : out std_logic; -- one block starts writing (aka ADC_START) + BUF_READY_OUT : out std_logic; -- one block has been written (aka ADC_LAST) + BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer + BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer) + BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer + BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output + BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output + BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation + BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation + BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer + BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler+ + BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set! + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of apv_raw_buffer is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of behavioral : architecture is "APV_RAW_BUF_group"; + + -- normal signals + signal adc_status_q : std_logic_vector(7 downto 0); + signal adc_status_qq : std_logic_vector(7 downto 0); + + signal adc_start_x : std_logic; + signal adc_start : std_logic; + signal adc_last_x : std_logic; + signal adc_last : std_logic; + + signal ce_wr_pointer : std_logic; + signal wr_pointer : std_logic_vector(3 downto 0); + signal ce_rd_pointer : std_logic; + signal rd_pointer : std_logic_vector(3 downto 0); + + signal buf_good_x : std_logic; + signal buf_good : std_logic; + signal buf_broken_x : std_logic; + signal buf_broken : std_logic; + signal buf_ignore_x : std_logic; + signal buf_ignore : std_logic; + + signal buf_level : std_logic_vector(4 downto 0); + signal buf_level_up_x : std_logic; + signal buf_level_down_x : std_logic; + + signal wr_data_addr : std_logic_vector(10 downto 0); + signal wr_data_d : std_logic_vector(17 downto 0); + signal wr_data_ena : std_logic; + signal rd_data_addr : std_logic_vector(10 downto 0); + signal rd_data_d : std_logic_vector(17 downto 0); + signal rd_data_ena : std_logic; + + signal buf_frame : std_logic_vector(11 downto 0); + + signal adc_tickmark : std_logic; + signal buf_tickmark : std_logic; + + -- Alias names for status bits + signal apv_on_x : std_logic; -- 40MHz clock domain signal + signal apv_on : std_logic; + signal apv_adcok_x : std_logic; -- 40MHz clock domain signal + signal apv_adcok : std_logic; + signal apv_locked_x : std_logic; -- 40MHz clock domain signal + signal apv_locked : std_logic; + + -- from old APV_BUFHANDLER block + signal apv_free_ctr : std_logic_vector(4 downto 0); + signal apv_free_up : std_logic; + signal apv_free_down : std_logic; + signal buf_free_ctr : std_logic_vector(4 downto 0); + signal buf_free_up : std_logic; + signal buf_free_down : std_logic; + + signal sum_apv_buf : std_logic_vector(5 downto 0); + signal sum_apv : std_logic_vector(5 downto 0); + signal sum_buf : std_logic_vector(5 downto 0); + signal trg_limit : std_logic_vector(5 downto 0); + + signal debug : std_logic_vector(15 downto 0); + + signal apv_or_buf_full_x : std_logic; + signal apv_or_buf_full : std_logic; + +begin + +-- Debugging signals +debug <= (others => '0'); + +-- Aliasing of status bits from APV_LOCKER (40MHz domain) +apv_adcok_x <= not adc_status_in(7); -- '0' = good ADC, '1' = bad ADC +apv_locked_x <= adc_status_in(5); -- '0' = not locked, '1' = locked +apv_on_x <= not adc_status_in(1); -- '0' = "off" means "ignore", '1' = "on" means "look at me" + +THE_APV_ON_SYNC: state_sync +port map( STATE_A_IN => apv_on_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + STATE_B_OUT => apv_on + ); + +THE_APV_LOCKED_SYNC: state_sync +port map( STATE_A_IN => apv_locked_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + STATE_B_OUT => apv_locked + ); + +THE_APV_ADCOK_SYNC: state_sync +port map( STATE_A_IN => apv_adcok_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + STATE_B_OUT => apv_adcok + ); + +-- We deliver three status signals to the data handler: +-- BUF_GOOD_OUT : APV is switched on and alive, so data packets can be expected in case of triggers. +-- Timeouts should be handled on this particular APV. +-- BUF_BROKEN_OUT: APV is switched on and in trouble, so data packets will not come in here. +-- The data handler must take care of this situation. +-- Data frames already stored in the buffer may still be read out until LVL[4:0] = 0. +-- BUF_IGNORE_OUT: APV is switched off, no matter if it is attached or nor, we don't accept any data frames +-- here. + +-- CLOCK DOMAINS! +buf_good_x <= '1' when ((apv_on = '1') and (apv_adcok = '1') and (apv_locked = '1')) else '0'; +buf_broken_x <= '1' when ((apv_on = '1') and (apv_adcok = '0' or apv_locked = '0')) else '0'; +buf_ignore_x <= '1' when ( apv_on = '0' ) else '0'; + +THE_BUF_SYNCER_PROC: process( buf_clk_in ) +begin + if( rising_edge(buf_clk_in) ) then + buf_good <= buf_good_x; + buf_broken <= buf_broken_x; + buf_ignore <= buf_ignore_x; + -- not nicely done!!! + adc_status_qq <= adc_status_q; + adc_status_q <= adc_status_in; -- BUG: just a quick hack + end if; +end process THE_BUF_SYNCER_PROC; + +-- Transfer both start and stop signals to the other clock domain +adc_start_x <= (adc_start_in and buf_good_x); + +THE_ADC_START_SYNCER: pulse_sync +port map( CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_in, + PULSE_A_IN => adc_start_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + PULSE_B_OUT => adc_start + ); + +adc_last_x <= (adc_last_in and buf_good_x); + +THE_ADC_LAST_SYNCER: pulse_sync +port map( CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_in, + PULSE_A_IN => adc_last_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + PULSE_B_OUT => adc_last + ); + +-- The tickmark signal is also transfered from 40M to 100M clock domain +adc_tickmark <= adc_status_in(0); -- alias +THE_TICKMARK_SYNCER: pulse_sync +port map( CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_in, + PULSE_A_IN => adc_tickmark, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + PULSE_B_OUT => buf_tickmark + ); + + +-- Control signals for the write pointer counter +ce_wr_pointer <= adc_last_x; + +-- Write pointer counter +THE_WR_POINTER: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if ( reset_in = '1' ) then + wr_pointer <= (others => '0'); + elsif( ce_wr_pointer = '1' ) then + wr_pointer <= wr_pointer + 1; + end if; + end if; +end process THE_WR_POINTER; + +-- Control signals for the read pointer counter +ce_rd_pointer <= buf_done_in and apv_on; + +-- Read pointer counter +THE_RD_POINTER: process( buf_clk_in ) +begin + if( rising_edge(buf_clk_in) ) then + if ( buf_reset_in = '1' ) then + rd_pointer <= (others => '0'); + elsif( ce_rd_pointer = '1' ) then + rd_pointer <= rd_pointer + 1; + end if; + end if; +end process THE_RD_POINTER; + +-- We need a level counter for the EDS handler, anyhow +buf_level_up_x <= adc_last; +buf_level_down_x <= (buf_done_in and buf_good); + +THE_BUF_LEVEL_COUNTER_PROC: process( buf_clk_in ) +begin + if( rising_edge(buf_clk_in) ) then + if ( buf_reset_in = '1' ) then + buf_level <= (others => '0'); + elsif( (buf_level_up_x = '1') and (buf_level_down_x = '0') ) then + buf_level <= buf_level + 1; + elsif( (buf_level_up_x = '0') and (buf_level_down_x = '1') ) then + buf_level <= buf_level - 1; + end if; + end if; +end process THE_BUF_LEVEL_COUNTER_PROC; + +-- Control signals for the data EBRs +wr_data_ena <= adc_analog_in; +rd_data_ena <= '1'; +wr_data_addr <= wr_pointer & adc_channel_in; +rd_data_addr <= rd_pointer & buf_addr_in; +wr_data_d <= adc_raw_in; + +-- We have two EBRs to implement a 2kx18 ring buffer +THE_INPUT_BRAM: input_bram +port map( WRADDRESS => wr_data_addr, + RDADDRESS => rd_data_addr, + DATA => wr_data_d, + WE => wr_data_ena, + RDCLOCK => buf_clk_in, + RDCLOCKEN => rd_data_ena, + RESET => reset_in, + WRCLOCK => clk_apv_in, + WRCLOCKEN => '1', + Q => rd_data_d + ); + +-- We use a LUT based DPRAM for the 16x12b status memory +THE_FRAME_STATUS_MEM: frame_status_mem +port map( WRADDRESS => wr_pointer, + DATA => adc_frame_in, + WRCLOCK => clk_apv_in, + WE => ce_wr_pointer, -- we store the frame status with the last ADC word + WRCLOCKEN => '1', + RDADDRESS => rd_pointer, + RDCLOCK => buf_clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => buf_frame + ); + +------------------------------------------------------------------------------------------ +-- Buffer fill levels, busy generation +------------------------------------------------------------------------------------------ + +-- We need to keep track of the APV analog fifo fill level. +-- Two signals are used: +-- - an early "FRAME_REQD" to decrement to number of free entries, +-- - a late "FRAME_RCVD" to notify that a requested frame has been transfered +-- from APV to the raw buffer. + +apv_free_down <= frm_reqd_in; +apv_free_up <= adc_last; + +THE_APV_FREE_COUNTER_PROC: process( buf_clk_in ) +begin + if( rising_edge(buf_clk_in) ) then + if ( buf_reset_in = '1' ) then + apv_free_ctr <= "10000"; + elsif( apv_free_down = '1' and apv_free_up = '0' ) then + apv_free_ctr <= apv_free_ctr - 1; + elsif( apv_free_down = '0' and apv_free_up = '1' ) then + apv_free_ctr <= apv_free_ctr + 1; + end if; + end if; +end process THE_APV_FREE_COUNTER_PROC; + +-- The raw data buffer is also to be watched carefully. +-- An early signal reserved on raw buffer page, while a late one releases one +-- page to the buffer pool again. + +buf_free_down <= adc_start; +buf_free_up <= buf_done_in; + +THE_BUF_FREE_COUNTER_PROC: process( buf_clk_in ) +begin + if( rising_edge(buf_clk_in) ) then + if ( buf_reset_in = '1' ) then + buf_free_ctr <= "10000"; + elsif( buf_free_down = '1' and buf_free_up = '0' ) then + buf_free_ctr <= buf_free_ctr - 1; + elsif( buf_free_down = '0' and buf_free_up = '1' ) then + buf_free_ctr <= buf_free_ctr + 1; + end if; + end if; +end process THE_BUF_FREE_COUNTER_PROC; + +-- We need to sum up and check if there is always enough space in the buffers +-- (both APV and RAW_BUF) to store one full sized event, as given by MAX_TRG_NUM_IN. + +sum_apv <= '0' & apv_free_ctr; +sum_buf <= '0' & buf_free_ctr; + +-- Balance the frames requested from APV and already present in raw buffers +THE_APV_BUF_ADDER: adder_6bit +port map( DATAA => sum_apv, + DATAB => sum_buf, + CLOCK => buf_clk_in, + RESET => buf_reset_in, + CLOCKEN => '1', + RESULT => sum_apv_buf + ); + +-- We have a minimum number of buffer pages to keep: +-- this construct makes 16 + (max_trg_num) +trg_limit <= "01" & max_trg_num_in; + +apv_or_buf_full_x <= '1' when (sum_apv_buf < trg_limit) else '0'; + +THE_SYNC_PROC: process( buf_clk_in ) +begin + if( rising_edge(buf_clk_in) ) then + apv_or_buf_full <= apv_or_buf_full_x; + end if; +end process THE_SYNC_PROC; +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + + +-- Output signals +buf_data_out <= rd_data_d; +buf_start_out <= adc_start; +buf_ready_out <= adc_last; +buf_status_out <= adc_status_qq; +buf_frame_out <= buf_frame; + +buf_good_out <= buf_good; +buf_broken_out <= buf_broken; +buf_ignore_out <= buf_ignore; +buf_level_out <= buf_level; +buf_full_out <= apv_or_buf_full; + +buf_tickmark_out <= buf_tickmark; + +-- Debug signals +debug_out <= debug; + +end behavioral; + diff --git a/src/apv_sync_handler.vhd b/src/apv_sync_handler.vhd new file mode 100644 index 0000000..5360675 --- /dev/null +++ b/src/apv_sync_handler.vhd @@ -0,0 +1,148 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity apv_sync_handler is + port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished (100MHz) + APV_TRG_OUT : out std_logic; -- TRG line signal (40MHz APV) + APV_SYNC_OUT : out std_logic; -- signal for statemachines (40MHz APV) + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of apv_sync_handler is + + -- state machine signals + type STATES is (SLEEP,START,T2,T1,T0,DLY0,DLY1,DLY2,DLY3,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- normal signals + signal apv_trgdone : std_logic; + signal apv_trgstart : std_logic; + signal comb_apv_trgstart : std_logic; + -- state machine generated signals + signal next_apv_done : std_logic; + signal apv_done : std_logic; + signal next_apv_trg : std_logic; + signal apv_trg : std_logic; + signal next_apv_sync : std_logic; + signal apv_sync : std_logic; + + +begin + +-- APV_TRGSTART_IN crosses a clock domain (100M -> 40M). +comb_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; + +THE_APVTRGSTART_SYNC: pulse_sync +port map( CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => comb_apv_trgstart, + CLK_B_IN => clk_apv_in, + RESET_B_IN => reset_apv_in, + PULSE_B_OUT => apv_trgstart + ); + +-- A statemachine handles all actions for creating the trigger sequence +-- state registers +STATE_MEM: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_apv_in = '1' ) then + CURRENT_STATE <= SLEEP; + apv_done <= '0'; + apv_trg <= '0'; + apv_sync <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + apv_done <= next_apv_done; + apv_trg <= next_apv_trg; + apv_sync <= next_apv_sync; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, apv_trgstart ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + next_apv_done <= '0'; + next_apv_trg <= '0'; + next_apv_sync <= '0'; + case CURRENT_STATE is + when SLEEP => if( apv_trgstart = '1' ) then + NEXT_STATE <= START; + else + NEXT_STATE <= SLEEP; + end if; + when START => NEXT_STATE <= T2; + next_apv_trg <= '1'; + when T2 => NEXT_STATE <= T1; + when T1 => NEXT_STATE <= T0; + next_apv_trg <= '1'; + when T0 => NEXT_STATE <= DLY0; + next_apv_sync <= '1'; + when DLY0 => NEXT_STATE <= DLY1; + next_apv_sync <= '1'; + when DLY1 => NEXT_STATE <= DLY2; + next_apv_sync <= '1'; + when DLY2 => NEXT_STATE <= DLY3; + next_apv_sync <= '1'; + when DLY3 => NEXT_STATE <= DONE; + next_apv_done <= '1'; + next_apv_sync <= '1'; + when DONE => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; + end case; +end process STATE_TRANSFORM; + +-- state decoding +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SLEEP => bsm_out <= x"0"; + when START => bsm_out <= x"1"; + when T2 => bsm_out <= x"2"; + when T1 => bsm_out <= x"3"; + when T0 => bsm_out <= x"4"; + when DLY0 => bsm_out <= x"5"; + when DLY1 => bsm_out <= x"6"; + when DLY2 => bsm_out <= x"7"; + when DLY3 => bsm_out <= x"8"; + when DONE => bsm_out <= x"9"; + when others => bsm_out <= x"f"; + end case; +end process STATE_DECODE; + +-- APV_TRGDONE_OUT crosses a clock domain (40M -> 100M). +THE_APVTRGDONE_SYNC: pulse_sync +port map( CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_apv_in, + PULSE_A_IN => apv_done, + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + PULSE_B_OUT => apv_trgdone + ); + +-- output signals +apv_trgdone_out <= apv_trgdone; +apv_trg_out <= apv_trg; +apv_sync_out <= apv_sync; + +debug_out(15 downto 0) <= (others => '0'); + +end behavioral; + + + diff --git a/src/apv_trg_handler.vhd b/src/apv_trg_handler.vhd new file mode 100644 index 0000000..af130f0 --- /dev/null +++ b/src/apv_trg_handler.vhd @@ -0,0 +1,232 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity apv_trg_handler is + port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- synced reset signal (100MHz master clock) + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers + APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished + APV_TRG_OUT : out std_logic; + APV_TRGSENT_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of apv_trg_handler is + + -- state machine signals + type STATES is (SLEEP,START,T2,T1,T0,DEL,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- normal signals + signal apv_trgstart : std_logic; + signal next_apv_trgstart : std_logic; + signal todo_ctr : std_logic_vector(3 downto 0); + signal comb_todo_done : std_logic; + signal delay_ctr : std_logic_vector(3 downto 0); + signal comb_delay_done : std_logic; + signal apv_trgsent : std_logic; + signal apv_trgdone : std_logic; + + -- State machine generates signals + signal next_todo_ctr_ce : std_logic; + signal todo_ctr_ce : std_logic; + signal next_delay_ctr_ce : std_logic; + signal delay_ctr_ce : std_logic; + signal next_delay_ctr_ld : std_logic; + signal delay_ctr_ld : std_logic; + signal next_apv_done : std_logic; + signal apv_done : std_logic; + signal next_apv_trgcnt : std_logic; + signal apv_trgcnt : std_logic; + signal next_apv_trg : std_logic; + signal apv_trg : std_logic; + +begin + +-- APV_TRGSTART_IN crosses a clock domain (100M -> 40M). +next_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; + +THE_APVTRGSTART_SYNC: pulse_sync +port map( CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => next_apv_trgstart, + CLK_B_IN => clk_apv_in, + RESET_B_IN => reset_apv_in, + PULSE_B_OUT => apv_trgstart + ); + +-- A statemachine handles all actions for creating the trigger sequence (40MHz domain) +-- state registers +STATE_MEM: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if( reset_apv_in = '1' ) then + CURRENT_STATE <= SLEEP; + todo_ctr_ce <= '0'; + delay_ctr_ce <= '0'; + delay_ctr_ld <= '0'; + apv_done <= '0'; + apv_trgcnt <= '0'; + apv_trg <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + todo_ctr_ce <= next_todo_ctr_ce; + delay_ctr_ce <= next_delay_ctr_ce; + delay_ctr_ld <= next_delay_ctr_ld; + apv_done <= next_apv_done; + apv_trgcnt <= next_apv_trgcnt; + apv_trg <= next_apv_trg; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, apv_trgstart, comb_todo_done, comb_delay_done ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + next_todo_ctr_ce <= '0'; + next_delay_ctr_ce <= '0'; + next_delay_ctr_ld <= '0'; + next_apv_done <= '0'; + next_apv_trg <= '0'; + next_apv_trgcnt <= '0'; + case CURRENT_STATE is + when SLEEP => if( apv_trgstart = '1' ) then + NEXT_STATE <= START; + else + NEXT_STATE <= SLEEP; + end if; + when START => if( comb_todo_done = '1' ) then + NEXT_STATE <= DONE; + next_apv_done <= '1'; + else + NEXT_STATE <= T2; + next_delay_ctr_ld <= '1'; + next_apv_trg <= '1'; + end if; + when T2 => NEXT_STATE <= T1; + next_todo_ctr_ce <= '1'; + next_apv_trgcnt <= '1'; + when T1 => NEXT_STATE <= T0; + next_delay_ctr_ce <= '1'; + when T0 => if ( (comb_todo_done = '1') ) then + NEXT_STATE <= DONE; + next_apv_done <= '1'; + elsif( (comb_todo_done = '0') and (comb_delay_done = '0') ) then + NEXT_STATE <= DEL; + next_delay_ctr_ce <= '1'; + elsif( (comb_todo_done = '0') and (comb_delay_done = '1') ) then + NEXT_STATE <= T2; + next_delay_ctr_ld <= '1'; + next_apv_trg <= '1'; + end if; + when DEL => if( comb_delay_done = '1' ) then + NEXT_STATE <= T2; + next_delay_ctr_ld <= '1'; + next_apv_trg <= '1'; + else + NEXT_STATE <= DEL; + next_delay_ctr_ce <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; + end case; +end process STATE_TRANSFORM; + +-- state decoding +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SLEEP => bsm_out <= x"0"; + when START => bsm_out <= x"1"; + when T2 => bsm_out <= x"2"; + when T1 => bsm_out <= x"3"; + when T0 => bsm_out <= x"4"; + when DEL => bsm_out <= x"5"; + when DONE => bsm_out <= x"6"; + when others => bsm_out <= x"f"; + end case; +end process STATE_DECODE; + +-- ToDo counter +THE_TODO_CTR_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if ( reset_apv_in = '1' ) then + todo_ctr <= (others => '0'); + elsif( apv_trgstart = '1' ) then + todo_ctr <= apv_trg_todo_in; + elsif( todo_ctr_ce = '1' ) then + todo_ctr <= todo_ctr - 1; + end if; + end if; +end process THE_TODO_CTR_PROC; +comb_todo_done <= '1' when (todo_ctr = x"0") else '0'; + +-- Delay counter +THE_DELAY_CTR_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + if ( reset_apv_in = '1' ) then + delay_ctr <= (others => '0'); + elsif( delay_ctr_ld = '1' ) then + delay_ctr <= apv_trg_delay_in; + elsif( delay_ctr_ce = '1' ) then + delay_ctr <= delay_ctr - 1; + end if; + end if; +end process THE_DELAY_CTR_PROC; +comb_delay_done <= '1' when (delay_ctr = x"0") else '0'; + +-- APV_TRGSENT_OUT crosses a clock domain (40M -> 100M). +THE_APVTRGSENT_SYNC: pulse_sync +port map( CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_apv_in, + PULSE_A_IN => apv_trgcnt, + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + PULSE_B_OUT => apv_trgsent + ); + +-- APV_TRGDONE_OUT crosses a clock domain (40M -> 100M). +THE_APVTRGDONE_SYNC: pulse_sync +port map( CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_apv_in, + PULSE_A_IN => apv_done, + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + PULSE_B_OUT => apv_trgdone + ); + +-- output signals +apv_trgdone_out <= apv_trgdone; +apv_trg_out <= apv_trg; +apv_trgsent_out <= apv_trgsent; + +debug_out(15 downto 12) <= todo_ctr; +debug_out(11 downto 8) <= delay_ctr; +debug_out(7) <= delay_ctr_ld; +debug_out(6) <= '0'; +debug_out(5) <= comb_delay_done; +debug_out(4) <= delay_ctr_ce; +debug_out(3) <= apv_trgstart; +debug_out(2) <= '0'; +debug_out(1) <= comb_todo_done; +debug_out(0) <= todo_ctr_ce; + +end behavioral; + + + diff --git a/src/apv_trgctrl.vhd b/src/apv_trgctrl.vhd new file mode 100644 index 0000000..8b43a32 --- /dev/null +++ b/src/apv_trgctrl.vhd @@ -0,0 +1,382 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity apv_trgctrl is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- 100MHz clock domain reset + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + -- Triggers + SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow + TRG_FOUND_OUT : out std_logic; + -- slow control settings + TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + -- TRB LVL1 signals + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type + TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received + TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger + TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel + TRB_RST_COUNTER_IN : in std_logic; -- reset timing trigger counter + TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); -- timing trigger counter + -- EDS signals + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word + EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done + EDS_DONE_IN : in std_logic; -- release current EDS buffer + EDS_FULL_OUT : out std_logic; -- EDS buffer is full + EDS_LEVEL_OUT : out std_logic_vector(4 downto 0); + FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement) + -- APV signals + APV_TRG_OUT : out std_logic; + APV_SYNC_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); +end; + +architecture behavioral of apv_trgctrl is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of behavioral : architecture is "APV_TRG_CTRL_group"; + + -- normal signals + signal apv_trgsel : std_logic_vector(3 downto 0); + signal apv_trgstart : std_logic; + signal apv_trgdone : std_logic_vector(3 downto 0); + signal next_apv_trgdone_all : std_logic; + signal apv_trgdone_all : std_logic; + signal apv_trg : std_logic_vector(3 downto 0); + signal next_apv_trg_all : std_logic; + signal apv_trg_all : std_logic; + signal apv_clk_rst : std_logic; -- 40MHz sync'ed reset signal + + signal sc_trg_stretch : std_logic_vector(3 downto 0); + signal maximum_trg : std_logic_vector(3 downto 0); + + -- EDS fill signals + signal atc_eds_data : std_logic_vector(39 downto 0); + signal atc_eds_start : std_logic; + signal atc_eds_we : std_logic; + signal eds_data : std_logic_vector(39 downto 0); + signal eds_full : std_logic; + signal eds_avail : std_logic; + signal eds_level : std_logic_vector(4 downto 0); + signal trb_release : std_logic; + signal trb_missing : std_logic; + signal trg_found : std_logic; + + signal test_eds_data : std_logic_vector(39 downto 0); + + -- APV signals + signal apv_trgsent : std_logic_vector(3 downto 0); + signal next_apv_trgsent_all : std_logic; + signal apv_trgsent_all : std_logic; + signal apv_sync : std_logic; + signal apv_sync_signal : std_logic; + + signal trb_counter : std_logic_vector(15 downto 0); + signal busy_release : std_logic; + + signal debug : std_logic_vector(63 downto 0); + signal bsm : std_logic_vector(7 downto 0); + +begin + +--------------------------------------------------------------------------- +-- Debug +--------------------------------------------------------------------------- +debug(63 downto 40) <= (others => '0'); +debug(39 downto 0) <= test_eds_data; + + +--------------------------------------------------------------------------- +-- RESET signal clock domain crossing (100MHz sysclk -> 40MHz APV clock) +--------------------------------------------------------------------------- +THE_RESET_SYNC: state_sync +port map( STATE_A_IN => reset_in, + CLK_B_IN => clk_apv_in, + RESET_B_IN => '0', + STATE_B_OUT => apv_clk_rst + ); + +--------------------------------------------------------------------------- +-- TRB trigger (one clock pulse) stretchers +--------------------------------------------------------------------------- +SC_TRG0_STRECH: pulse_stretch +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => trb_trg_in(0), + PULSE_OUT => sc_trg_stretch(0), + DEBUG_OUT => open + ); +SC_TRG1_STRECH: pulse_stretch +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => trb_trg_in(1), + PULSE_OUT => sc_trg_stretch(1), + DEBUG_OUT => open + ); +SC_TRG2_STRECH: pulse_stretch +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => trb_trg_in(2), + PULSE_OUT => sc_trg_stretch(2), + DEBUG_OUT => open + ); +SC_TRG3_STRECH: pulse_stretch +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => trb_trg_in(3), + PULSE_OUT => sc_trg_stretch(3), + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Busy handling +--------------------------------------------------------------------------- +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + busy_release <= not still_busy_in and not eds_full; + end if; +end process THE_SYNC_PROC; + +--------------------------------------------------------------------------- +-- Triggers can either be sourced from hardware inputs (four LVDS signals), or by slow control accesses. +-- Each trigger input has its own settings (# triggers, delay inbetween), and can control an own state machine +-- for generation of APV TRG pulse sequences (like 1-0-0, or 1-0-1, etc.) +--------------------------------------------------------------------------- +THE_REAL_TRG_HANDLER: real_trg_handler +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + TIME_TRG_IN => time_trg_in, + TRB_TRG_IN => sc_trg_stretch, + APV_TRGDONE_IN => apv_trgdone_all, + TRG_3_TODO_IN => trg_3_todo_in, + TRG_2_TODO_IN => trg_2_todo_in, + TRG_1_TODO_IN => trg_1_todo_in, + TRG_0_TODO_IN => trg_0_todo_in, + TRG_SETUP_IN => trg_setup_in, + TRG_FOUND_OUT => trg_found, + TRB_TTAG_IN => trb_ttag_in, + TRB_TRND_IN => trb_trnd_in, + TRB_TTYPE_IN => trb_ttype_in, + TRB_TRGRCVD_IN => trb_trgrcvd_in, + TRB_MISSING_OUT => trb_missing, + BUSY_RELEASE_IN => busy_release, + RST_LVL1_COUNTER_IN => trb_rst_counter_in, + LVL1_COUNTER_OUT => trb_counter, + APV_TRGSEL_OUT => apv_trgsel, + APV_TRGSTART_OUT => apv_trgstart, + EDS_DATA_OUT => atc_eds_data, + EDS_START_OUT => atc_eds_start, -- just for debugging + EDS_WE_OUT => atc_eds_we, + EDS_READY_OUT => trb_release, + DBG_FRMCTR_OUT => open, + BSM_OUT => bsm, --open, + DEBUG_OUT => open --debug + ); + +-- automatically determine the maximum amount of APV frames per trigger +-- mind the delay in this block! +THE_MAX_TRG: max_data +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + TODO_3_IN => trg_3_todo_in, + TODO_2_IN => trg_2_todo_in, + TODO_1_IN => trg_1_todo_in, + TODO_0_IN => trg_0_todo_in, + TODO_MAX_OUT => maximum_trg, + DEBUG_OUT => open + ); + +-- Only for storing last EDS for debugging! +THE_TEST_EDS_DATA_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( atc_eds_we = '1' ) then + test_eds_data <= atc_eds_data; + end if; + end if; +end process THE_TEST_EDS_DATA_PROC; + +--------------------------------------------------------------------------- +-- EDS buffer with fill level information +--------------------------------------------------------------------------- +THE_EDS_BUF: eds_buf +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + EDS_DATA_IN => atc_eds_data, -- data from trigger handler + EDS_WE_IN => atc_eds_we, -- write enable from trigger handler + EDS_DONE_IN => eds_done_in, -- release current EDS page + EDS_DATA_OUT => eds_data, -- current EDS data out + EDS_AVAILABLE_OUT => eds_avail, -- current EDS is valid + BUF_FULL_OUT => eds_full, -- EDS buffer is full + BUF_LEVEL_OUT => eds_level, -- for debugging + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Trigger input 3: normal trigger +--------------------------------------------------------------------------- +THE_APV_TRG_HANDLER_3: apv_trg_handler +port map( CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => apv_trgstart, + APV_TRGSEL_IN => apv_trgsel(3), + APV_TRG_TODO_IN => trg_3_todo_in, + APV_TRG_DELAY_IN => trg_3_delay_in, + APV_TRGDONE_OUT => apv_trgdone(3), + APV_TRG_OUT => apv_trg(3), + APV_TRGSENT_OUT => apv_trgsent(3), + BSM_OUT => open, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Trigger input 2: normal trigger +--------------------------------------------------------------------------- +THE_APV_TRG_HANDLER_2: apv_trg_handler +port map( CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => apv_trgstart, + APV_TRGSEL_IN => apv_trgsel(2), + APV_TRG_TODO_IN => trg_2_todo_in, + APV_TRG_DELAY_IN => trg_2_delay_in, + APV_TRGDONE_OUT => apv_trgdone(2), + APV_TRG_OUT => apv_trg(2), + APV_TRGSENT_OUT => apv_trgsent(2), + BSM_OUT => open, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Trigger input 1: normal trigger +--------------------------------------------------------------------------- +THE_APV_TRG_HANDLER_1: apv_trg_handler +port map( CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => apv_trgstart, + APV_TRGSEL_IN => apv_trgsel(1), + APV_TRG_TODO_IN => trg_1_todo_in, + APV_TRG_DELAY_IN => trg_1_delay_in, + APV_TRGDONE_OUT => apv_trgdone(1), + APV_TRG_OUT => apv_trg(1), + APV_TRGSENT_OUT => apv_trgsent(1), + BSM_OUT => open, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Trigger input 0: normal trigger +--------------------------------------------------------------------------- +THE_APV_TRG_HANDLER_0: apv_trg_handler +port map( CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => apv_trgstart, + APV_TRGSEL_IN => apv_trgsel(0), + APV_TRG_TODO_IN => trg_0_todo_in, + APV_TRG_DELAY_IN => trg_0_delay_in, + APV_TRGDONE_OUT => apv_trgdone(0), + APV_TRG_OUT => apv_trg(0), + APV_TRGSENT_OUT => apv_trgsent(0), + BSM_OUT => open, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- APV SYNC trigger signal -- NOT CLEAN, outside trigger logic! +--------------------------------------------------------------------------- +THE_APV_SYNC_HANDLER: apv_sync_handler +port map( CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => sync_trg_in, + APV_TRGSEL_IN => '1', + APV_TRGDONE_OUT => open, + APV_TRG_OUT => apv_sync_signal, + APV_SYNC_OUT => apv_sync, + BSM_OUT => open, + DEBUG_OUT => open + ); + +-- combine all DONE and SENT signals for feedback +next_apv_trgdone_all <= apv_trgdone(3) or apv_trgdone(2) or apv_trgdone(1) or apv_trgdone(0); +next_apv_trgsent_all <= apv_trgsent(3) or apv_trgsent(2) or apv_trgsent(1) or apv_trgsent(0); + +THE_SYNC_AVP_HOUSEKEEPING_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + apv_trgdone_all <= next_apv_trgdone_all; + apv_trgsent_all <= next_apv_trgsent_all; + end if; +end process THE_SYNC_AVP_HOUSEKEEPING_PROC; + + +--------------------------------------------------------------------------- +-- APV triggering +--------------------------------------------------------------------------- +-- we combine all four trigger sources, and the sync source +next_apv_trg_all <= apv_trg(3) or apv_trg(2) or apv_trg(1) or apv_trg(0) or apv_sync_signal; + +THE_SYNC_AVP_TRG_PROC: process( clk_apv_in ) +begin + if( rising_edge(clk_apv_in) ) then + apv_trg_all <= next_apv_trg_all; + end if; +end process THE_SYNC_AVP_TRG_PROC; + + +--------------------------------------------------------------------------- +-- output signals +--------------------------------------------------------------------------- +eds_data_out <= eds_data; +eds_avail_out <= eds_avail; +eds_full_out <= eds_full; +eds_level_out <= eds_level; +frm_reqd_out <= apv_trgsent_all; +trb_release_out <= trb_release; +trb_missing_out <= trb_missing; +trb_counter_out <= trb_counter; + +apv_trg_out <= apv_trg_all; +apv_sync_out <= apv_sync; + +trg_found_out <= trg_found; +trg_max_out <= maximum_trg; + +--------------------------------------------------------------------------- +-- Debug signals +--------------------------------------------------------------------------- +debug_out <= debug; + +end behavioral; + + diff --git a/src/buf_toc.vhd b/src/buf_toc.vhd new file mode 100644 index 0000000..0cc2fc8 --- /dev/null +++ b/src/buf_toc.vhd @@ -0,0 +1,269 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +-- bugfixing: +-- ddmmyy - blafasel + +entity buf_toc is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUF_TICK_IN : in std_logic; -- tickmark from raw buffer + BUF_START_IN : in std_logic; -- start of frame from raw buffer + WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode + FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS + BUF_LVL_IN : in std_logic_vector(7 downto 0); + GOODDATA_OUT : out std_logic; -- APV is on, sent data, process it + BADDATA_OUT : out std_logic; -- APV is on, broken buffer, NO processing, only ERROR HDR + NODATA_OUT : out std_logic; -- APV is off, do not send anything! + READY_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of buf_toc is + + -- components + + -- state machine signals + type STATES is (SLEEP,CLEAR,RSTTOC,WATCH,COUNT,GDATA,BDATA,IDATA,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- normal signals + signal bsm_x : std_logic_vector(7 downto 0); + signal debug_x : std_logic_vector(15 downto 0); + + signal buf_lvl : std_logic_vector(4 downto 0); + signal buf_good : std_logic; + signal buf_broken : std_logic; + signal buf_ignore : std_logic; + + signal next_gooddata : std_logic; + signal gooddata : std_logic; + signal next_baddata : std_logic; + signal baddata : std_logic; + signal next_nodata : std_logic; + signal nodata : std_logic; + signal next_ready : std_logic; + signal ready : std_logic; + + signal frames_needed : std_logic_vector(4 downto 0); + + signal next_frames_avail : std_logic; + signal frames_avail : std_logic; + + signal toc_ctr : std_logic_vector(3 downto 0); + signal next_toc_rst : std_logic; + signal toc_rst : std_logic; + signal next_toc_ce : std_logic; + signal toc_ce : std_logic; + signal next_toc_hit : std_logic; + signal toc_hit : std_logic; + + signal next_stat_clr : std_logic; + signal stat_clr : std_logic; + + signal stat_good : std_logic; + signal stat_bad : std_logic; + signal stat_ignore : std_logic; + +begin + +-- Aliasing +buf_good <= buf_lvl_in(7); +buf_broken <= buf_lvl_in(6); +buf_ignore <= buf_lvl_in(5); +buf_lvl <= buf_lvl_in(4 downto 0); + +-- Timeout counter +THE_TIMEOUT_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (reset_in = '1') or (toc_rst = '1') ) then + toc_ctr <= (others => '0'); + elsif( toc_ce = '1' ) then + toc_ctr <= toc_ctr + 1; + end if; + end if; +end process THE_TIMEOUT_COUNTER_PROC; + +next_toc_hit <= '1' when (toc_ctr = x"f") else '0'; + +-- Check for the number of available frames +frames_needed <= '0' & frames_reqd_in; +next_frames_avail <= '1' when ( buf_lvl >= frames_needed ) else '0'; + +-- Synchronization process +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + toc_hit <= next_toc_hit; + frames_avail <= next_frames_avail; + end if; +end process THE_SYNC_PROC; + +-- state machine for handling synchronisation +-- state registers +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + gooddata <= '0'; + baddata <= '0'; + nodata <= '0'; + toc_ce <= '0'; + toc_rst <= '0'; + ready <= '0'; + stat_clr <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + gooddata <= next_gooddata; + baddata <= next_baddata; + nodata <= next_nodata; + toc_ce <= next_toc_ce; + toc_rst <= next_toc_rst; + ready <= next_ready; + stat_clr <= next_stat_clr; + end if; + end if; +end process STATE_MEM; + + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, waitframe_in, buf_good, buf_ignore, + buf_start_in, buf_tick_in, frames_avail, toc_hit ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + next_gooddata <= '0'; + next_baddata <= '0'; + next_nodata <= '0'; + next_toc_ce <= '0'; + next_toc_rst <= '0'; + next_ready <= '0'; + next_stat_clr <= '0'; + case CURRENT_STATE is + when SLEEP => if( waitframe_in = '1' ) then + NEXT_STATE <= CLEAR; + next_stat_clr <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when CLEAR => if ( buf_ignore = '1' ) then + NEXT_STATE <= IDATA; -- switched off buffer, ignore it + next_nodata <= '1'; + elsif( buf_good = '1' ) then + NEXT_STATE <= RSTTOC; -- good buffer, start of wait + next_toc_rst <= '1'; + else + NEXT_STATE <= BDATA; -- bad buffer, so we skip it immediatly + next_baddata <= '1'; + end if; + when RSTTOC => NEXT_STATE <= WATCH; + when WATCH => if ( frames_avail = '1' ) then + NEXT_STATE <= GDATA; -- all frames did arrive + next_gooddata <= '1'; + elsif( (toc_hit = '1') or (buf_good = '0') ) then + NEXT_STATE <= BDATA; -- timeout or broken buffer + next_baddata <= '1'; + elsif( (frames_avail = '0') and (buf_start_in = '1') ) then + NEXT_STATE <= RSTTOC; -- buffer arrived, reset TOC + next_toc_rst <= '1'; + elsif( (frames_avail = '0') and (buf_tick_in = '1') ) then + NEXT_STATE <= COUNT; + next_toc_ce <= '1'; + else + NEXT_STATE <= WATCH; + end if; + when COUNT => NEXT_STATE <= WATCH; + when GDATA => NEXT_STATE <= DONE; + next_ready <= '1'; + when BDATA => NEXT_STATE <= DONE; + next_ready <= '1'; + when IDATA => NEXT_STATE <= DONE; + next_ready <= '1'; + when DONE => if( waitframe_in = '1' ) then + NEXT_STATE <= DONE; + next_ready <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + + when others => NEXT_STATE <= SLEEP; + end case; +end process STATE_TRANSFORM; + +-- state decoding +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SLEEP => bsm_x <= x"00"; + when CLEAR => bsm_x <= x"01"; + when RSTTOC => bsm_x <= x"02"; + when WATCH => bsm_x <= x"03"; + when COUNT => bsm_x <= x"04"; + when GDATA => bsm_x <= x"05"; + when BDATA => bsm_x <= x"06"; + when IDATA => bsm_x <= x"07"; + when DONE => bsm_x <= x"08"; + when others => bsm_x <= x"ff"; + end case; +end process STATE_DECODE; + +-- We store the GOODDATA and BADDATA result for the following data transfer +-- stat_good and stat_bad are valid for the whole buffer processing phase! +THE_GOODDATA_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (reset_in = '1') or (stat_clr = '1') ) then + stat_good <= '0'; + elsif( gooddata = '1' ) then + stat_good <= '1'; + end if; + end if; +end process THE_GOODDATA_PROC; +THE_BADDATA_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (reset_in = '1') or (stat_clr = '1') ) then + stat_bad <= '0'; + elsif( baddata = '1' ) then + stat_bad <= '1'; + end if; + end if; +end process THE_BADDATA_PROC; +THE_IGNOREDATA_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (reset_in = '1') or (stat_clr = '1') ) then + stat_ignore <= '0'; + elsif( nodata = '1' ) then + stat_ignore <= '1'; + end if; + end if; +end process THE_IGNOREDATA_PROC; + +-- output signals +gooddata_out <= stat_good; +baddata_out <= stat_bad; +nodata_out <= stat_ignore; +ready_out <= ready; + +-- debug signals +debug_x(15 downto 9) <= (others => '0'); +debug_x(8) <= toc_hit; +debug_x(7) <= frames_avail; +debug_x(6) <= gooddata; +debug_x(5) <= baddata; +debug_x(4) <= ready; +debug_x(3 downto 0) <= toc_ctr; + +dbg_out <= debug_x; +bsm_out <= bsm_x; + +end behavioral; diff --git a/src/comp14bit.lpc b/src/comp14bit.lpc new file mode 100644 index 0000000..1e63ce1 --- /dev/null +++ b/src/comp14bit.lpc @@ -0,0 +1,35 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Comparator +CoreRevision=3.1 +ModuleName=comp14bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=02/26/2009 +Time=14:35:12 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +InputWidth=14 +FuncComparator= A >= B +ReprComparator=Unsigned +Lut=0 +OutReg=1 +Stage=0 diff --git a/src/comp14bit.vhd b/src/comp14bit.vhd new file mode 100644 index 0000000..64d5851 --- /dev/null +++ b/src/comp14bit.vhd @@ -0,0 +1,131 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 3.1 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp14bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 14 -unsigned -port ageb -output_reg -enable -pipeline 0 -e + +-- Thu Feb 26 14:35:13 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity comp14bit is + port ( + DataA: in std_logic_vector(13 downto 0); + DataB: in std_logic_vector(13 downto 0); + Clock: in std_logic; + ClockEn: in std_logic; + Aclr: in std_logic; + AGEB: out std_logic); +end comp14bit; + +architecture Structure of comp14bit is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal cmp_ci: std_logic; + signal co0: std_logic; + signal co1: std_logic; + signal co2: std_logic; + signal co3: std_logic; + signal co4: std_logic; + signal co5: std_logic; + signal ageb_out: std_logic; + signal ageb_out_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute GSR of FF_0 : label is "ENABLED"; + +begin + -- component instantiation statements + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ageb_out, SP=>ClockEn, CK=>Clock, CD=>Aclr, Q=>AGEB); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + cmp_0: AGEB2 + port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1), + CI=>cmp_ci, GE=>co0); + + cmp_1: AGEB2 + port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3), + CI=>co0, GE=>co1); + + cmp_2: AGEB2 + port map (A0=>DataA(4), A1=>DataA(5), B0=>DataB(4), B1=>DataB(5), + CI=>co1, GE=>co2); + + cmp_3: AGEB2 + port map (A0=>DataA(6), A1=>DataA(7), B0=>DataB(6), B1=>DataB(7), + CI=>co2, GE=>co3); + + cmp_4: AGEB2 + port map (A0=>DataA(8), A1=>DataA(9), B0=>DataB(8), B1=>DataB(9), + CI=>co3, GE=>co4); + + cmp_5: AGEB2 + port map (A0=>DataA(10), A1=>DataA(11), B0=>DataB(10), + B1=>DataB(11), CI=>co4, GE=>co5); + + cmp_6: AGEB2 + port map (A0=>DataA(12), A1=>DataA(13), B0=>DataB(12), + B1=>DataB(13), CI=>co5, GE=>ageb_out_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ageb_out_c, COUT=>open, S0=>ageb_out, + S1=>open); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of comp14bit is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/comp14bit_tmpl.vhd b/src/comp14bit_tmpl.vhd new file mode 100644 index 0000000..a4761de --- /dev/null +++ b/src/comp14bit_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 3.1 +-- Thu Feb 26 14:35:13 2009 + +-- parameterized module component declaration +component comp14bit + port (DataA: in std_logic_vector(13 downto 0); + DataB: in std_logic_vector(13 downto 0); Clock: in std_logic; + ClockEn: in std_logic; Aclr: in std_logic; + AGEB: out std_logic); +end component; + +-- parameterized module component instance +__ : comp14bit + port map (DataA(13 downto 0)=>__, DataB(13 downto 0)=>__, Clock=>__, + ClockEn=>__, Aclr=>__, AGEB=>__); diff --git a/src/comp4bit.lpc b/src/comp4bit.lpc new file mode 100644 index 0000000..f709952 --- /dev/null +++ b/src/comp4bit.lpc @@ -0,0 +1,35 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Comparator +CoreRevision=3.1 +ModuleName=comp4bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/09/2009 +Time=16:19:24 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +InputWidth=4 +FuncComparator= A > B +ReprComparator=Unsigned +Lut=0 +OutReg=0 +Stage=0 diff --git a/src/comp4bit.srp b/src/comp4bit.srp new file mode 100644 index 0000000..8a904b6 --- /dev/null +++ b/src/comp4bit.srp @@ -0,0 +1,32 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Fri Oct 09 16:19:24 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp4bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 4 -unsigned -port agtb -e + Circuit name : comp4bit + Module type : comp + Module Version : 3.1 + Width : 4 + Ports : + Inputs : DataA[3:0], DataB[3:0] + Outputs : AGTB + I/O buffer : not inserted + Representation : unsigned number + EDIF output : suppressed + VHDL output : comp4bit.vhd + VHDL template : comp4bit_tmpl.vhd + VHDL testbench : tb_comp4bit_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : comp4bit.srp + Element Usage : + ALEB2 : 2 + FADD2B : 2 + INV : 1 + Estimated Resource Usage: + LUT : 8 diff --git a/src/comp4bit.vhd b/src/comp4bit.vhd new file mode 100644 index 0000000..9d31e21 --- /dev/null +++ b/src/comp4bit.vhd @@ -0,0 +1,96 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 3.1 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp4bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 4 -unsigned -port agtb -e + +-- Fri Oct 09 16:19:24 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity comp4bit is + port ( + DataA: in std_logic_vector(3 downto 0); + DataB: in std_logic_vector(3 downto 0); + AGTB: out std_logic); +end comp4bit; + +architecture Structure of comp4bit is + + -- internal signal declarations + signal co1_inv: std_logic; + signal scuba_vhi: std_logic; + signal cmp_ci: std_logic; + signal co0: std_logic; + signal co1: std_logic; + signal agtb_out_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + INV_0: INV + port map (A=>co1, Z=>co1_inv); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + cmp_0: ALEB2 + port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1), + CI=>cmp_ci, LE=>co0); + + cmp_1: ALEB2 + port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3), + CI=>co0, LE=>agtb_out_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>agtb_out_c, COUT=>open, S0=>co1, S1=>open); + + AGTB <= co1_inv; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of comp4bit is + for Structure + for all:ALEB2 use entity ecp2m.ALEB2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/comp4bit_generate.log b/src/comp4bit_generate.log new file mode 100644 index 0000000..b68902a --- /dev/null +++ b/src/comp4bit_generate.log @@ -0,0 +1,46 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Fri Oct 09 16:19:24 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp4bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 4 -unsigned -port agtb -e + Circuit name : comp4bit + Module type : comp + Module Version : 3.1 + Width : 4 + Ports : + Inputs : DataA[3:0], DataB[3:0] + Outputs : AGTB + I/O buffer : not inserted + Representation : unsigned number + EDIF output : suppressed + VHDL output : comp4bit.vhd + VHDL template : comp4bit_tmpl.vhd + VHDL testbench : tb_comp4bit_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : comp4bit.srp + Estimated Resource Usage: + LUT : 8 + +END SCUBA Module Synthesis + +File: comp4bit.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/comp4bit_tmpl.vhd b/src/comp4bit_tmpl.vhd new file mode 100644 index 0000000..1e36d6e --- /dev/null +++ b/src/comp4bit_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 3.1 +-- Fri Oct 09 16:19:24 2009 + +-- parameterized module component declaration +component comp4bit + port (DataA: in std_logic_vector(3 downto 0); + DataB: in std_logic_vector(3 downto 0); AGTB: out std_logic); +end component; + +-- parameterized module component instance +__ : comp4bit + port map (DataA(3 downto 0)=>__, DataB(3 downto 0)=>__, AGTB=>__); diff --git a/src/crossover.lpc b/src/crossover.lpc new file mode 100644 index 0000000..49ca7f6 --- /dev/null +++ b/src/crossover.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.0 +ModuleName=crossover +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/20/2009 +Time=11:16:47 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=16 +Width=96 +RDepth=16 +RWidth=96 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Single Threshold +PeAssert=4 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Single Threshold +PfAssert=12 +PfDeassert=506 +RDataCount=1 +WDataCount=1 +EnECC=0 diff --git a/src/crossover.srp b/src/crossover.srp new file mode 100644 index 0000000..dd496d7 --- /dev/null +++ b/src/crossover.srp @@ -0,0 +1,43 @@ +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Nov 20 11:16:48 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e + Circuit name : crossover + Module type : ebfifo + Module Version : 5.0 + Ports : + Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : crossover.vhd + VHDL template : crossover_tmpl.vhd + VHDL testbench : tb_crossover_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : crossover.srp + Element Usage : + AGEB2 : 6 + AND2 : 2 + CU2 : 6 + FADD2B : 8 + FSUB2B : 6 + FD1P3BX : 2 + FD1P3DX : 124 + FD1S3BX : 1 + FD1S3DX : 31 + INV : 2 + OR2 : 1 + ROM16X1 : 13 + DPR16X4A : 24 + XOR2 : 10 + Estimated Resource Usage: + LUT : 78 + DRAM : 24 + Reg : 158 diff --git a/src/crossover.vhd b/src/crossover.vhd new file mode 100644 index 0000000..4342242 --- /dev/null +++ b/src/crossover.vhd @@ -0,0 +1,2049 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 5.0 +--F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 96 -depth 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e + +-- Fri Nov 20 11:16:48 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity crossover is + port ( + Data: in std_logic_vector(95 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(95 downto 0); + WCNT: out std_logic_vector(4 downto 0); + RCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic); +end crossover; + +architecture Structure of crossover is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal wptr_4: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal rptr_4: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal co2: std_logic; + signal wcount_4: std_logic; + signal co1: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal co2_1: std_logic; + signal rcount_4: std_logic; + signal co1_1: std_logic; + signal wfill_sub_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_2: std_logic; + signal wfill_sub_msb: std_logic; + signal co2_2d: std_logic; + signal co2_2: std_logic; + signal rfill_sub_0: std_logic; + signal scuba_vhi: std_logic; + signal rfill_sub_1: std_logic; + signal rfill_sub_2: std_logic; + signal co0_3: std_logic; + signal rfill_sub_3: std_logic; + signal rfill_sub_4: std_logic; + signal co1_3: std_logic; + signal rfill_sub_msb: std_logic; + signal co2_3d: std_logic; + signal co2_3: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_4: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_4: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_5: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_5: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + signal rdataout95: std_logic; + signal rdataout94: std_logic; + signal rdataout93: std_logic; + signal rdataout92: std_logic; + signal rdataout91: std_logic; + signal rdataout90: std_logic; + signal rdataout89: std_logic; + signal rdataout88: std_logic; + signal rdataout87: std_logic; + signal rdataout86: std_logic; + signal rdataout85: std_logic; + signal rdataout84: std_logic; + signal rdataout83: std_logic; + signal rdataout82: std_logic; + signal rdataout81: std_logic; + signal rdataout80: std_logic; + signal rdataout79: std_logic; + signal rdataout78: std_logic; + signal rdataout77: std_logic; + signal rdataout76: std_logic; + signal rdataout75: std_logic; + signal rdataout74: std_logic; + signal rdataout73: std_logic; + signal rdataout72: std_logic; + signal rdataout71: std_logic; + signal rdataout70: std_logic; + signal rdataout69: std_logic; + signal rdataout68: std_logic; + signal rdataout67: std_logic; + signal rdataout66: std_logic; + signal rdataout65: std_logic; + signal rdataout64: std_logic; + signal rdataout63: std_logic; + signal rdataout62: std_logic; + signal rdataout61: std_logic; + signal rdataout60: std_logic; + signal rdataout59: std_logic; + signal rdataout58: std_logic; + signal rdataout57: std_logic; + signal rdataout56: std_logic; + signal rdataout55: std_logic; + signal rdataout54: std_logic; + signal rdataout53: std_logic; + signal rdataout52: std_logic; + signal rdataout51: std_logic; + signal rdataout50: std_logic; + signal rdataout49: std_logic; + signal rdataout48: std_logic; + signal rdataout47: std_logic; + signal rdataout46: std_logic; + signal rdataout45: std_logic; + signal rdataout44: std_logic; + signal rdataout43: std_logic; + signal rdataout42: std_logic; + signal rdataout41: std_logic; + signal rdataout40: std_logic; + signal rdataout39: std_logic; + signal rdataout38: std_logic; + signal rdataout37: std_logic; + signal rdataout36: std_logic; + signal rdataout35: std_logic; + signal rdataout34: std_logic; + signal rdataout33: std_logic; + signal rdataout32: std_logic; + signal rdataout31: std_logic; + signal rdataout30: std_logic; + signal rdataout29: std_logic; + signal rdataout28: std_logic; + signal rdataout27: std_logic; + signal rdataout26: std_logic; + signal rdataout25: std_logic; + signal rdataout24: std_logic; + signal rdataout23: std_logic; + signal rdataout22: std_logic; + signal rdataout21: std_logic; + signal rdataout20: std_logic; + signal rdataout19: std_logic; + signal rdataout18: std_logic; + signal rdataout17: std_logic; + signal rdataout16: std_logic; + signal rdataout15: std_logic; + signal rdataout14: std_logic; + signal rdataout13: std_logic; + signal rdataout12: std_logic; + signal rdataout11: std_logic; + signal rdataout10: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rptr_3: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal rptr_0: std_logic; + signal dec0_wre3: std_logic; + signal wptr_3: std_logic; + signal wptr_2: std_logic; + signal wptr_1: std_logic; + signal wptr_0: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4A + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + attribute initval : string; + attribute GSR : string; + attribute initval of LUT4_12 : label is "0x8000"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t12: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t11: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t10: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t9: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t8: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t7: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t6: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t5: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t4: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t3: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t2: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8000") + -- synopsys translate_on + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_0); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_0); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); + + XOR2_t1: XOR2 + port map (A=>wptr_4, B=>r_gcount_w24, Z=>wfill_sub_msb); + + XOR2_t0: XOR2 + port map (A=>w_gcount_r24, B=>rptr_4, Z=>rfill_sub_msb); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + FF_157: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_156: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_155: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_154: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_153: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_152: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_151: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_150: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_149: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_148: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_147: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_146: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_145: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_144: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_143: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_142: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_141: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_140: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_139: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_138: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_137: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_136: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_135: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_134: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_133: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_132: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_131: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_130: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_129: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_128: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_127: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(0)); + + FF_126: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(1)); + + FF_125: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(2)); + + FF_124: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(3)); + + FF_123: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(4)); + + FF_122: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(5)); + + FF_121: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(6)); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(7)); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(8)); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(9)); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(10)); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(11)); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(12)); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(13)); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(14)); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(15)); + + FF_111: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(16)); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(17)); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout18, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(18)); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout19, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(19)); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout20, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(20)); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout21, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(21)); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout22, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(22)); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout23, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(23)); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout24, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(24)); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout25, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(25)); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout26, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(26)); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout27, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(27)); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout28, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(28)); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout29, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(29)); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout30, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(30)); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout31, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(31)); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout32, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(32)); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout33, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(33)); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout34, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(34)); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout35, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(35)); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout36, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(36)); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout37, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(37)); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout38, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(38)); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout39, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(39)); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout40, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(40)); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout41, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(41)); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout42, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(42)); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout43, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(43)); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout44, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(44)); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout45, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(45)); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout46, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(46)); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout47, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(47)); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout48, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(48)); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout49, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(49)); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout50, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(50)); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout51, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(51)); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout52, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(52)); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout53, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(53)); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout54, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(54)); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout55, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(55)); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout56, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(56)); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout57, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(57)); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout58, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(58)); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout59, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(59)); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout60, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(60)); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout61, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(61)); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout62, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(62)); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout63, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(63)); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout64, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(64)); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout65, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(65)); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout66, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(66)); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout67, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(67)); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout68, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(68)); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout69, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(69)); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout70, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(70)); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout71, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(71)); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout72, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(72)); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout73, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(73)); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout74, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(74)); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout75, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(75)); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout76, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(76)); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout77, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(77)); + + FF_49: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout78, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(78)); + + FF_48: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout79, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(79)); + + FF_47: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout80, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(80)); + + FF_46: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout81, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(81)); + + FF_45: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout82, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(82)); + + FF_44: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout83, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(83)); + + FF_43: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout84, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(84)); + + FF_42: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout85, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(85)); + + FF_41: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout86, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(86)); + + FF_40: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout87, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(87)); + + FF_39: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout88, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(88)); + + FF_38: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout89, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(89)); + + FF_37: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout90, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(90)); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout91, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(91)); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout92, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(92)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout93, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(93)); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout94, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(94)); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout95, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(95)); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2, + NC0=>iwcount_4, NC1=>open); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>ircount_4, NC1=>open); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w2, BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, + S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wfill_sub_msb, B0=>rcount_w3, + B1=>scuba_vlo, BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, + S1=>wfill_sub_4); + + wfilld: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_2, COUT=>open, S0=>co2_2d, S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + rfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, + B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, + S1=>rfill_sub_0); + + rfill_1: FSUB2B + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r2, B0=>rptr_1, + B1=>rptr_2, BI=>co0_3, BOUT=>co1_3, S0=>rfill_sub_1, + S1=>rfill_sub_2); + + rfill_2: FSUB2B + port map (A0=>wcount_r3, A1=>rfill_sub_msb, B0=>rptr_3, + B1=>scuba_vlo, BI=>co1_3, BOUT=>co2_3, S0=>rfill_sub_3, + S1=>rfill_sub_4); + + rfilld: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_3, COUT=>open, S0=>co2_3d, S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_4); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_4, GE=>co1_4); + + empty_cmp_2: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co1_4, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_1, GE=>co0_5); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + full_cmp_2: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co1_5, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + fifo_pfu_0_0: DPR16X4A + port map (DI0=>Data(92), DI1=>Data(93), DI2=>Data(94), + DI3=>Data(95), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout92, + DO1=>rdataout93, DO2=>rdataout94, DO3=>rdataout95); + + fifo_pfu_0_1: DPR16X4A + port map (DI0=>Data(88), DI1=>Data(89), DI2=>Data(90), + DI3=>Data(91), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout88, + DO1=>rdataout89, DO2=>rdataout90, DO3=>rdataout91); + + fifo_pfu_0_2: DPR16X4A + port map (DI0=>Data(84), DI1=>Data(85), DI2=>Data(86), + DI3=>Data(87), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout84, + DO1=>rdataout85, DO2=>rdataout86, DO3=>rdataout87); + + fifo_pfu_0_3: DPR16X4A + port map (DI0=>Data(80), DI1=>Data(81), DI2=>Data(82), + DI3=>Data(83), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout80, + DO1=>rdataout81, DO2=>rdataout82, DO3=>rdataout83); + + fifo_pfu_0_4: DPR16X4A + port map (DI0=>Data(76), DI1=>Data(77), DI2=>Data(78), + DI3=>Data(79), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout76, + DO1=>rdataout77, DO2=>rdataout78, DO3=>rdataout79); + + fifo_pfu_0_5: DPR16X4A + port map (DI0=>Data(72), DI1=>Data(73), DI2=>Data(74), + DI3=>Data(75), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout72, + DO1=>rdataout73, DO2=>rdataout74, DO3=>rdataout75); + + fifo_pfu_0_6: DPR16X4A + port map (DI0=>Data(68), DI1=>Data(69), DI2=>Data(70), + DI3=>Data(71), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout68, + DO1=>rdataout69, DO2=>rdataout70, DO3=>rdataout71); + + fifo_pfu_0_7: DPR16X4A + port map (DI0=>Data(64), DI1=>Data(65), DI2=>Data(66), + DI3=>Data(67), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout64, + DO1=>rdataout65, DO2=>rdataout66, DO3=>rdataout67); + + fifo_pfu_0_8: DPR16X4A + port map (DI0=>Data(60), DI1=>Data(61), DI2=>Data(62), + DI3=>Data(63), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout60, + DO1=>rdataout61, DO2=>rdataout62, DO3=>rdataout63); + + fifo_pfu_0_9: DPR16X4A + port map (DI0=>Data(56), DI1=>Data(57), DI2=>Data(58), + DI3=>Data(59), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout56, + DO1=>rdataout57, DO2=>rdataout58, DO3=>rdataout59); + + fifo_pfu_0_10: DPR16X4A + port map (DI0=>Data(52), DI1=>Data(53), DI2=>Data(54), + DI3=>Data(55), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout52, + DO1=>rdataout53, DO2=>rdataout54, DO3=>rdataout55); + + fifo_pfu_0_11: DPR16X4A + port map (DI0=>Data(48), DI1=>Data(49), DI2=>Data(50), + DI3=>Data(51), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout48, + DO1=>rdataout49, DO2=>rdataout50, DO3=>rdataout51); + + fifo_pfu_0_12: DPR16X4A + port map (DI0=>Data(44), DI1=>Data(45), DI2=>Data(46), + DI3=>Data(47), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout44, + DO1=>rdataout45, DO2=>rdataout46, DO3=>rdataout47); + + fifo_pfu_0_13: DPR16X4A + port map (DI0=>Data(40), DI1=>Data(41), DI2=>Data(42), + DI3=>Data(43), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout40, + DO1=>rdataout41, DO2=>rdataout42, DO3=>rdataout43); + + fifo_pfu_0_14: DPR16X4A + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout36, + DO1=>rdataout37, DO2=>rdataout38, DO3=>rdataout39); + + fifo_pfu_0_15: DPR16X4A + port map (DI0=>Data(32), DI1=>Data(33), DI2=>Data(34), + DI3=>Data(35), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout32, + DO1=>rdataout33, DO2=>rdataout34, DO3=>rdataout35); + + fifo_pfu_0_16: DPR16X4A + port map (DI0=>Data(28), DI1=>Data(29), DI2=>Data(30), + DI3=>Data(31), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout28, + DO1=>rdataout29, DO2=>rdataout30, DO3=>rdataout31); + + fifo_pfu_0_17: DPR16X4A + port map (DI0=>Data(24), DI1=>Data(25), DI2=>Data(26), + DI3=>Data(27), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout24, + DO1=>rdataout25, DO2=>rdataout26, DO3=>rdataout27); + + fifo_pfu_0_18: DPR16X4A + port map (DI0=>Data(20), DI1=>Data(21), DI2=>Data(22), + DI3=>Data(23), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout20, + DO1=>rdataout21, DO2=>rdataout22, DO3=>rdataout23); + + fifo_pfu_0_19: DPR16X4A + port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18), + DI3=>Data(19), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout16, + DO1=>rdataout17, DO2=>rdataout18, DO3=>rdataout19); + + fifo_pfu_0_20: DPR16X4A + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12, + DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15); + + fifo_pfu_0_21: DPR16X4A + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8, + DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11); + + fifo_pfu_0_22: DPR16X4A + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5, + DO2=>rdataout6, DO3=>rdataout7); + + fifo_pfu_0_23: DPR16X4A + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1, + DO2=>rdataout2, DO3=>rdataout3); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of crossover is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/crossover_generate.log b/src/crossover_generate.log new file mode 100644 index 0000000..4a2c3aa --- /dev/null +++ b/src/crossover_generate.log @@ -0,0 +1,46 @@ +Starting process: + +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Nov 20 11:16:48 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e + Circuit name : crossover + Module type : ebfifo + Module Version : 5.0 + Ports : + Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : crossover.vhd + VHDL template : crossover_tmpl.vhd + VHDL testbench : tb_crossover_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : crossover.srp + Estimated Resource Usage: + LUT : 78 + DRAM : 24 + Reg : 158 + +END SCUBA Module Synthesis + +File: ..\src\crossover.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/crossover_tmpl.vhd b/src/crossover_tmpl.vhd new file mode 100644 index 0000000..bbdc80d --- /dev/null +++ b/src/crossover_tmpl.vhd @@ -0,0 +1,20 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 5.0 +-- Fri Nov 20 11:16:48 2009 + +-- parameterized module component declaration +component crossover + port (Data: in std_logic_vector(95 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(95 downto 0); + WCNT: out std_logic_vector(4 downto 0); + RCNT: out std_logic_vector(4 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : crossover + port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, WCNT(4 downto 0)=>__, + RCNT(4 downto 0)=>__, Empty=>__, Full=>__); diff --git a/src/decoder_8bit.lpc b/src/decoder_8bit.lpc new file mode 100644 index 0000000..4a28d48 --- /dev/null +++ b/src/decoder_8bit.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_ROM +CoreRevision=2.4 +ModuleName=decoder_8bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/03/2009 +Time=09:38:59 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=256 +Data=4 +LUT=0 +MemFile=z:/vhdl_pro/adcm_v2/decoder_8bit.mem +MemFormat=orca diff --git a/src/decoder_8bit.mem b/src/decoder_8bit.mem new file mode 100644 index 0000000..55fdbdf --- /dev/null +++ b/src/decoder_8bit.mem @@ -0,0 +1,38 @@ +#Format=AddrHex +#Depth=256 +#Width=4 +#AddrRadix=3 +#DataRadix=3 +#Data +00: 0 1 1 2 1 2 2 3 +08: 1 2 2 3 2 3 3 4 +10: 1 2 2 3 2 3 3 4 +18: 2 3 3 4 3 4 4 5 +20: 1 2 2 3 2 3 3 4 +28: 2 3 3 4 3 4 4 5 +30: 2 3 3 4 3 4 4 5 +38: 3 4 4 5 4 5 5 6 +40: 1 2 2 3 2 3 3 4 +48: 2 3 3 4 3 4 4 5 +50: 2 3 3 4 3 4 4 5 +58: 3 4 4 5 4 5 5 6 +60: 2 3 3 4 3 4 4 5 +68: 3 4 4 5 4 5 5 6 +70: 3 4 4 5 4 5 5 6 +78: 4 5 5 6 5 6 6 7 +80: 1 2 2 3 2 3 3 4 +88: 2 3 3 4 3 4 4 5 +90: 2 3 3 4 3 4 4 5 +98: 3 4 4 5 4 5 5 6 +a0: 2 3 3 4 3 4 4 5 +a8: 3 4 4 5 4 5 5 6 +b0: 3 4 4 5 4 5 5 6 +b8: 4 5 5 6 5 6 6 7 +c0: 2 3 3 4 3 4 4 5 +c8: 3 4 4 5 4 5 5 6 +d0: 3 4 4 5 4 5 5 6 +d8: 4 5 5 6 5 6 6 7 +e0: 3 4 4 5 4 5 5 6 +e8: 4 5 5 6 5 6 6 7 +f0: 4 5 5 6 5 6 6 7 +f8: 5 6 6 7 6 7 7 8 \ No newline at end of file diff --git a/src/decoder_8bit.vhd b/src/decoder_8bit.vhd new file mode 100644 index 0000000..bff958b --- /dev/null +++ b/src/decoder_8bit.vhd @@ -0,0 +1,81 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 2.4 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 8 -num_rows 256 -data_width 4 -outdata UNREGISTERED -memfile z:/vhdl_pro/adcm_v2/decoder_8bit.mem -memformat orca -e + +-- Tue Mar 03 09:38:59 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity decoder_8bit is + port ( + Address: in std_logic_vector(7 downto 0); + Q: out std_logic_vector(3 downto 0)); +end decoder_8bit; + +architecture Structure of decoder_8bit is + + -- local component declarations + component ROM256X1 + -- synopsys translate_off + generic (INITVAL : in String); + -- synopsys translate_on + port (AD7: in std_logic; AD6: in std_logic; AD5: in std_logic; + AD4: in std_logic; AD3: in std_logic; AD2: in std_logic; + AD1: in std_logic; AD0: in std_logic; DO0: out std_logic); + end component; + attribute initval : string; + attribute initval of mem_0_3 : label is "0x8000000000000000000000000000000000000000000000000000000000000000"; + attribute initval of mem_0_2 : label is "0x7FFFFFFEFFFEFEE8FFFEFEE8FEE8E880FFFEFEE8FEE8E880FEE8E880E8808000"; + attribute initval of mem_0_1 : label is "0x7EE8E881E8818117E88181178117177EE88181178117177E8117177E177E7EE8"; + attribute initval of mem_0_0 : label is "0x6996966996696996966969966996966996696996699696696996966996696996"; + +begin + -- component instantiation statements + mem_0_3: ROM256X1 + -- synopsys translate_off + generic map (initval=> "0x8000000000000000000000000000000000000000000000000000000000000000") + -- synopsys translate_on + port map (AD7=>Address(7), AD6=>Address(6), AD5=>Address(5), + AD4=>Address(4), AD3=>Address(3), AD2=>Address(2), + AD1=>Address(1), AD0=>Address(0), DO0=>Q(3)); + + mem_0_2: ROM256X1 + -- synopsys translate_off + generic map (initval=> "0x7FFFFFFEFFFEFEE8FFFEFEE8FEE8E880FFFEFEE8FEE8E880FEE8E880E8808000") + -- synopsys translate_on + port map (AD7=>Address(7), AD6=>Address(6), AD5=>Address(5), + AD4=>Address(4), AD3=>Address(3), AD2=>Address(2), + AD1=>Address(1), AD0=>Address(0), DO0=>Q(2)); + + mem_0_1: ROM256X1 + -- synopsys translate_off + generic map (initval=> "0x7EE8E881E8818117E88181178117177EE88181178117177E8117177E177E7EE8") + -- synopsys translate_on + port map (AD7=>Address(7), AD6=>Address(6), AD5=>Address(5), + AD4=>Address(4), AD3=>Address(3), AD2=>Address(2), + AD1=>Address(1), AD0=>Address(0), DO0=>Q(1)); + + mem_0_0: ROM256X1 + -- synopsys translate_off + generic map (initval=> "0x6996966996696996966969966996966996696996699696696996966996696996") + -- synopsys translate_on + port map (AD7=>Address(7), AD6=>Address(6), AD5=>Address(5), + AD4=>Address(4), AD3=>Address(3), AD2=>Address(2), + AD1=>Address(1), AD0=>Address(0), DO0=>Q(0)); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of decoder_8bit is + for Structure + for all:ROM256X1 use entity ecp2m.ROM256X1(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/decoder_8bit_tmpl.vhd b/src/decoder_8bit_tmpl.vhd new file mode 100644 index 0000000..fb3c041 --- /dev/null +++ b/src/decoder_8bit_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 2.4 +-- Tue Mar 03 09:38:59 2009 + +-- parameterized module component declaration +component decoder_8bit + port (Address: in std_logic_vector(7 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : decoder_8bit + port map (Address(7 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/src/dhdr_buf.vhd b/src/dhdr_buf.vhd new file mode 100644 index 0000000..8a18c7e --- /dev/null +++ b/src/dhdr_buf.vhd @@ -0,0 +1,130 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity dhdr_buf is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + -- DHDR information block + DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input + DHDR_WE_IN : in std_logic; -- EDS write enable + DHDR_DONE_IN : in std_logic; -- release EDS + DHDR_DATA_OUT : out std_logic_vector(47 downto 0); + DHDR_AVAILABLE_OUT : out std_logic; + -- trigger busy information + BUF_FULL_OUT : out std_logic; + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of dhdr_buf is + + -- normal signals + signal debug : std_logic_vector(15 downto 0); + + -- Signals for controlling the DHDR buffer memory + signal dhdr_data : std_logic_vector(47 downto 0); + signal dhdr_rd_addr : std_logic_vector(3 downto 0); + signal dhdr_wr_addr : std_logic_vector(3 downto 0); + signal dhdr_wr : std_logic; + signal dhdr_rd : std_logic; + signal dhdr_free_ctr : std_logic_vector(4 downto 0); -- fill level counter + signal dhdr_free_up : std_logic; + signal dhdr_free_down : std_logic; + signal dhdr_available_x : std_logic; + signal dhdr_available : std_logic; -- at least one valid EDS entry is available + signal dhdr_full_x : std_logic; + signal dhdr_full : std_logic; + +begin + +-- General process for syncing combinatorial signals +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + dhdr_available <= dhdr_available_x; + dhdr_full <= dhdr_full_x; + end if; +end process THE_SYNC_PROC; + +-- Write address pointer for EDS buffer +dhdr_wr <= dhdr_we_in; + +THE_WR_ADDR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + dhdr_wr_addr <= (others => '0'); + elsif( dhdr_wr = '1' ) then + dhdr_wr_addr <= dhdr_wr_addr + 1; + end if; + end if; +end process THE_WR_ADDR_PROC; + +-- Read address pointer for EDS buffer +dhdr_rd <= dhdr_done_in; + +THE_RD_ADDR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + dhdr_rd_addr <= (others => '0'); + elsif( dhdr_rd = '1' ) then + dhdr_rd_addr <= dhdr_rd_addr + 1; + end if; + end if; +end process THE_RD_ADDR_PROC; + +-- Buffer fill level counter +dhdr_free_down <= dhdr_we_in; +dhdr_free_up <= dhdr_done_in; + +THE_DHDR_FREE_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + dhdr_free_ctr <= "10000"; + elsif( (dhdr_free_down = '1') and (dhdr_free_up = '0') ) then + dhdr_free_ctr <= dhdr_free_ctr - 1; + elsif( (dhdr_free_down = '0') and (dhdr_free_up = '1') ) then + dhdr_free_ctr <= dhdr_free_ctr + 1; + end if; + end if; +end process THE_DHDR_FREE_COUNTER_PROC; + +dhdr_full_x <= '1' when (dhdr_free_ctr = "00000") else '0'; + +-- A 16x32b DPRAM is used for buffering the DataHeaDeR (DHDR) +THE_DHDR_BUFFER: dhdr_buffer_dpram +port map( WRADDRESS => dhdr_wr_addr, + DATA => dhdr_data_in, + WRCLOCK => clk_in, + WE => dhdr_we_in, + WRCLOCKEN => '1', + RDADDRESS => dhdr_rd_addr, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => dhdr_data + ); + +-- Are there any EDS to work on? +dhdr_available_x <= '1' when (dhdr_wr_addr /= dhdr_rd_addr) else '0'; + +-- Debug signals +debug(15 downto 0) <= (others => '0'); + +-- Output signals +dhdr_data_out <= dhdr_data; +dhdr_available_out <= dhdr_available; +buf_full_out <= dhdr_full; +buf_level_out <= dhdr_free_ctr; +debug_out <= debug; + +end behavioral; diff --git a/src/dhdr_buffer_dpram.lpc b/src/dhdr_buffer_dpram.lpc new file mode 100644 index 0000000..705d305 --- /dev/null +++ b/src/dhdr_buffer_dpram.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_DPRAM +CoreRevision=3.4 +ModuleName=dhdr_buffer_dpram +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/03/2009 +Time=16:49:44 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=16 +Data=48 +LUT=1 +MemFile= +MemFormat=orca diff --git a/src/dhdr_buffer_dpram.vhd b/src/dhdr_buffer_dpram.vhd new file mode 100644 index 0000000..42c5e0f --- /dev/null +++ b/src/dhdr_buffer_dpram.vhd @@ -0,0 +1,636 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 3.4 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sdpram -rdata_width 48 -data_width 48 -num_rows 16 -outData REGISTERED -e + +-- Tue Mar 03 16:49:44 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity dhdr_buffer_dpram is + port ( + WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(47 downto 0); + WrClock: in std_logic; + WE: in std_logic; + WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(47 downto 0)); +end dhdr_buffer_dpram; + +architecture Structure of dhdr_buffer_dpram is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal dataout47_ffin: std_logic; + signal dataout46_ffin: std_logic; + signal dataout45_ffin: std_logic; + signal dataout44_ffin: std_logic; + signal dataout43_ffin: std_logic; + signal dataout42_ffin: std_logic; + signal dataout41_ffin: std_logic; + signal dataout40_ffin: std_logic; + signal dataout39_ffin: std_logic; + signal dataout38_ffin: std_logic; + signal dataout37_ffin: std_logic; + signal dataout36_ffin: std_logic; + signal dataout35_ffin: std_logic; + signal dataout34_ffin: std_logic; + signal dataout33_ffin: std_logic; + signal dataout32_ffin: std_logic; + signal dataout31_ffin: std_logic; + signal dataout30_ffin: std_logic; + signal dataout29_ffin: std_logic; + signal dataout28_ffin: std_logic; + signal dataout27_ffin: std_logic; + signal dataout26_ffin: std_logic; + signal dataout25_ffin: std_logic; + signal dataout24_ffin: std_logic; + signal dataout23_ffin: std_logic; + signal dataout22_ffin: std_logic; + signal dataout21_ffin: std_logic; + signal dataout20_ffin: std_logic; + signal dataout19_ffin: std_logic; + signal dataout18_ffin: std_logic; + signal dataout17_ffin: std_logic; + signal dataout16_ffin: std_logic; + signal dataout15_ffin: std_logic; + signal dataout14_ffin: std_logic; + signal dataout13_ffin: std_logic; + signal dataout12_ffin: std_logic; + signal dataout11_ffin: std_logic; + signal dataout10_ffin: std_logic; + signal dataout9_ffin: std_logic; + signal dataout8_ffin: std_logic; + signal dataout7_ffin: std_logic; + signal dataout6_ffin: std_logic; + signal dataout5_ffin: std_logic; + signal dataout4_ffin: std_logic; + signal dataout3_ffin: std_logic; + signal dataout2_ffin: std_logic; + signal dataout1_ffin: std_logic; + signal dataout0_ffin: std_logic; + signal dec0_wre3: std_logic; + + -- local component declarations + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4A + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute initval : string; + attribute GSR : string; + attribute initval of LUT4_0 : label is "0x8000"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8000") + -- synopsys translate_on + port map (AD3=>WE, AD2=>WrClockEn, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + FF_47: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout47_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(47)); + + FF_46: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout46_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(46)); + + FF_45: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout45_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(45)); + + FF_44: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout44_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(44)); + + FF_43: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout43_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(43)); + + FF_42: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout42_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(42)); + + FF_41: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout41_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(41)); + + FF_40: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout40_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(40)); + + FF_39: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout39_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(39)); + + FF_38: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout38_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(38)); + + FF_37: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout37_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(37)); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout36_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(36)); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout35_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(35)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout34_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(34)); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout33_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(33)); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout32_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(32)); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout31_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(31)); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout30_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(30)); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout29_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(29)); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout28_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(28)); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout27_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(27)); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout26_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(26)); + + FF_25: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout25_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(25)); + + FF_24: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout24_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(24)); + + FF_23: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout23_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(23)); + + FF_22: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout22_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(22)); + + FF_21: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout21_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(21)); + + FF_20: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout20_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(20)); + + FF_19: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout19_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(19)); + + FF_18: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout18_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(18)); + + FF_17: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout17_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(17)); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout16_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(16)); + + FF_15: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout15_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(15)); + + FF_14: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout14_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(14)); + + FF_13: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout13_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(13)); + + FF_12: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout12_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(12)); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout11_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(11)); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout10_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(10)); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout9_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(9)); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout8_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(8)); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout7_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(7)); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout6_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(6)); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout5_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(5)); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout4_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(4)); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout3_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(3)); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout2_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(2)); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout1_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(1)); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout0_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(0)); + + mem_0_0: DPR16X4A + port map (DI0=>Data(44), DI1=>Data(45), DI2=>Data(46), + DI3=>Data(47), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout44_ffin, + DO1=>dataout45_ffin, DO2=>dataout46_ffin, + DO3=>dataout47_ffin); + + mem_0_1: DPR16X4A + port map (DI0=>Data(40), DI1=>Data(41), DI2=>Data(42), + DI3=>Data(43), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout40_ffin, + DO1=>dataout41_ffin, DO2=>dataout42_ffin, + DO3=>dataout43_ffin); + + mem_0_2: DPR16X4A + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout36_ffin, + DO1=>dataout37_ffin, DO2=>dataout38_ffin, + DO3=>dataout39_ffin); + + mem_0_3: DPR16X4A + port map (DI0=>Data(32), DI1=>Data(33), DI2=>Data(34), + DI3=>Data(35), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout32_ffin, + DO1=>dataout33_ffin, DO2=>dataout34_ffin, + DO3=>dataout35_ffin); + + mem_0_4: DPR16X4A + port map (DI0=>Data(28), DI1=>Data(29), DI2=>Data(30), + DI3=>Data(31), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout28_ffin, + DO1=>dataout29_ffin, DO2=>dataout30_ffin, + DO3=>dataout31_ffin); + + mem_0_5: DPR16X4A + port map (DI0=>Data(24), DI1=>Data(25), DI2=>Data(26), + DI3=>Data(27), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout24_ffin, + DO1=>dataout25_ffin, DO2=>dataout26_ffin, + DO3=>dataout27_ffin); + + mem_0_6: DPR16X4A + port map (DI0=>Data(20), DI1=>Data(21), DI2=>Data(22), + DI3=>Data(23), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout20_ffin, + DO1=>dataout21_ffin, DO2=>dataout22_ffin, + DO3=>dataout23_ffin); + + mem_0_7: DPR16X4A + port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18), + DI3=>Data(19), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout16_ffin, + DO1=>dataout17_ffin, DO2=>dataout18_ffin, + DO3=>dataout19_ffin); + + mem_0_8: DPR16X4A + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout12_ffin, + DO1=>dataout13_ffin, DO2=>dataout14_ffin, + DO3=>dataout15_ffin); + + mem_0_9: DPR16X4A + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout8_ffin, + DO1=>dataout9_ffin, DO2=>dataout10_ffin, DO3=>dataout11_ffin); + + mem_0_10: DPR16X4A + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0), + RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3), + WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2), + WAD3=>WrAddress(3), DO0=>dataout4_ffin, DO1=>dataout5_ffin, + DO2=>dataout6_ffin, DO3=>dataout7_ffin); + + mem_0_11: DPR16X4A + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0), + RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3), + WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2), + WAD3=>WrAddress(3), DO0=>dataout0_ffin, DO1=>dataout1_ffin, + DO2=>dataout2_ffin, DO3=>dataout3_ffin); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of dhdr_buffer_dpram is + for Structure + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/dhdr_buffer_dpram_tmpl.vhd b/src/dhdr_buffer_dpram_tmpl.vhd new file mode 100644 index 0000000..a3ac36e --- /dev/null +++ b/src/dhdr_buffer_dpram_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 3.4 +-- Tue Mar 03 16:49:44 2009 + +-- parameterized module component declaration +component dhdr_buffer_dpram + port (WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(47 downto 0); WrClock: in std_logic; + WE: in std_logic; WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; Q: out std_logic_vector(47 downto 0)); +end component; + +-- parameterized module component instance +__ : dhdr_buffer_dpram + port map (WrAddress(3 downto 0)=>__, Data(47 downto 0)=>__, WrClock=>__, + WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__, + RdClockEn=>__, Reset=>__, Q(47 downto 0)=>__); diff --git a/src/dll_100m.lpc b/src/dll_100m.lpc new file mode 100644 index 0000000..4467a81 --- /dev/null +++ b/src/dll_100m.lpc @@ -0,0 +1,39 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DLL +CoreRevision=3.2 +ModuleName=dll_100m +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/29/2009 +Time=18:49:16 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +dlltype=Clock Injection Delay Removal +fin=100 +clkos_div=1 +clkos_ph=0 +Mode=CLKOP +Freq=CLKI +Smiports=0 +RSTNport=1 +reset_en=0 +DCNTL=0 diff --git a/src/dll_100m.vhd b/src/dll_100m.vhd new file mode 100644 index 0000000..079cd32 --- /dev/null +++ b/src/dll_100m.vhd @@ -0,0 +1,126 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 3.2 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n dll_100m -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dll -dll_type cid -fin 100 -clkos_div 1 -fb_mode 0 -use_rstn -e + +-- Thu Jan 29 18:49:16 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity dll_100m is + port ( + clk: in std_logic; + resetn: in std_logic; + aluhold: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic); + attribute dont_touch : string; + attribute dont_touch of dll_100m : entity is "true"; +end dll_100m; + +architecture Structure of dll_100m is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal clkos_t: std_logic; + signal clkop_t: std_logic; + signal clk_t: std_logic; + + -- local component declarations + component CIDDLLA + -- synopsys translate_off + generic (ALU_INIT_CNTVAL : in Integer; + ALU_UNLOCK_CNT : in Integer; ALU_LOCK_CNT : in Integer; + GSR : in String; CLKOS_DIV : in Integer; + CLKI_DIV : in Integer; CLKOS_FPHASE : in Integer; + CLKOS_PHASE : in Integer; CLKOP_PHASE : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; + RSTN: in std_logic; ALUHOLD: in std_logic; + SMIADDR9: in std_logic; SMIADDR8: in std_logic; + SMIADDR7: in std_logic; SMIADDR6: in std_logic; + SMIADDR5: in std_logic; SMIADDR4: in std_logic; + SMIADDR3: in std_logic; SMIADDR2: in std_logic; + SMIADDR1: in std_logic; SMIADDR0: in std_logic; + SMIRD: in std_logic; SMIWR: in std_logic; + SMICLK: in std_logic; SMIWDATA: in std_logic; + SMIRSTN: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; LOCK: out std_logic; + SMIRDATA: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute GSR : string; + attribute CLKFB_PDEL : string; + attribute CLKI_PDEL : string; + attribute ALU_INIT_CNTVAL : string; + attribute ALU_UNLOCK_CNT : string; + attribute ALU_LOCK_CNT : string; + attribute CLKI_DIV : string; + attribute CLKOS_DIV : string; + attribute CLKOS_FPHASE : string; + attribute CLKOS_PHASE : string; + attribute CLKOP_PHASE : string; + attribute FREQUENCY_PIN_CLKOS of dll_100m_0_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKOP of dll_100m_0_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKI of dll_100m_0_0 : label is "100.000000"; + attribute GSR of dll_100m_0_0 : label is "DISABLED"; + attribute CLKFB_PDEL of dll_100m_0_0 : label is "DEL0"; + attribute CLKI_PDEL of dll_100m_0_0 : label is "DEL0"; + attribute ALU_INIT_CNTVAL of dll_100m_0_0 : label is "0"; + attribute ALU_UNLOCK_CNT of dll_100m_0_0 : label is "3"; + attribute ALU_LOCK_CNT of dll_100m_0_0 : label is "3"; + attribute CLKI_DIV of dll_100m_0_0 : label is "1"; + attribute CLKOS_DIV of dll_100m_0_0 : label is "1"; + attribute CLKOS_FPHASE of dll_100m_0_0 : label is "0"; + attribute CLKOS_PHASE of dll_100m_0_0 : label is "270"; + attribute CLKOP_PHASE of dll_100m_0_0 : label is "270"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + dll_100m_0_0: CIDDLLA + -- synopsys translate_off + generic map (GSR=> "DISABLED", ALU_INIT_CNTVAL=> 0, + ALU_UNLOCK_CNT=> 3, ALU_LOCK_CNT=> 3, CLKI_DIV=> 1, CLKOS_DIV=> 1, + CLKOS_FPHASE=> 0, CLKOS_PHASE=> 270, CLKOP_PHASE=> 270) + -- synopsys translate_on + port map (CLKI=>clk_t, CLKFB=>clkop_t, RSTN=>resetn, + ALUHOLD=>aluhold, SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, + SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, + SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, + SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, + SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, + SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, + SMIRSTN=>scuba_vlo, CLKOP=>clkop_t, CLKOS=>clkos_t, + LOCK=>lock, SMIRDATA=>open); + + clkos <= clkos_t; + clkop <= clkop_t; + clk_t <= clk; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of dll_100m is + for Structure + for all:CIDDLLA use entity ecp2m.CIDDLLA(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/dll_100m_tmpl.vhd b/src/dll_100m_tmpl.vhd new file mode 100644 index 0000000..dfc2502 --- /dev/null +++ b/src/dll_100m_tmpl.vhd @@ -0,0 +1,15 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 3.2 +-- Thu Jan 29 18:49:16 2009 + +-- parameterized module component declaration +component dll_100m + port (clk: in std_logic; resetn: in std_logic; + aluhold: in std_logic; clkop: out std_logic; + clkos: out std_logic; lock: out std_logic); +end component; + +-- parameterized module component instance +__ : dll_100m + port map (clk=>__, resetn=>__, aluhold=>__, clkop=>__, clkos=>__, + lock=>__); diff --git a/src/dpram_8x19.lpc b/src/dpram_8x19.lpc new file mode 100644 index 0000000..b215053 --- /dev/null +++ b/src/dpram_8x19.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_DPRAM +CoreRevision=3.4 +ModuleName=dpram_8x19 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/20/2009 +Time=19:14:27 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=16 +Data=19 +LUT=0 +MemFile= +MemFormat=orca diff --git a/src/dpram_8x19.srp b/src/dpram_8x19.srp new file mode 100644 index 0000000..ded8bac --- /dev/null +++ b/src/dpram_8x19.srp @@ -0,0 +1,32 @@ +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Nov 20 19:14:28 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e + Circuit name : dpram_8x19 + Module type : sdpram + Module Version : 3.4 + Address width : 4 + Ports : + Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0] + Outputs : Q[18:0] + I/O buffer : not inserted + Clock edge : rising edge + EDIF output : suppressed + VHDL output : dpram_8x19.vhd + VHDL template : dpram_8x19_tmpl.vhd + VHDL testbench : tb_dpram_8x19_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : dpram_8x19.srp + Element Usage : + ROM16X1 : 1 + DPR16X4A : 5 + Estimated Resource Usage: + LUT : 1 + DRAM : 5 diff --git a/src/dpram_8x19.vhd b/src/dpram_8x19.vhd new file mode 100644 index 0000000..771e6ca --- /dev/null +++ b/src/dpram_8x19.vhd @@ -0,0 +1,127 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 3.4 +--F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sdpram -rdata_width 19 -data_width 19 -num_rows 16 -outData UNREGISTERED -e + +-- Fri Nov 20 19:14:28 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity dpram_8x19 is + port ( + WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(18 downto 0); + WrClock: in std_logic; + WE: in std_logic; + WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + Q: out std_logic_vector(18 downto 0)); +end dpram_8x19; + +architecture Structure of dpram_8x19 is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal dec0_wre3: std_logic; + + -- local component declarations + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4A + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute initval : string; + attribute initval of LUT4_0 : label is "0x8000"; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8000") + -- synopsys translate_on + port map (AD3=>WE, AD2=>WrClockEn, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + mem_0_0: DPR16X4A + port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18), + DI3=>scuba_vlo, WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>Q(16), + DO1=>Q(17), DO2=>Q(18), DO3=>open); + + mem_0_1: DPR16X4A + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>Q(12), + DO1=>Q(13), DO2=>Q(14), DO3=>Q(15)); + + mem_0_2: DPR16X4A + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>Q(8), DO1=>Q(9), + DO2=>Q(10), DO3=>Q(11)); + + mem_0_3: DPR16X4A + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0), + RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3), + WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2), + WAD3=>WrAddress(3), DO0=>Q(4), DO1=>Q(5), DO2=>Q(6), + DO3=>Q(7)); + + mem_0_4: DPR16X4A + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0), + RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3), + WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2), + WAD3=>WrAddress(3), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), + DO3=>Q(3)); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of dpram_8x19 is + for Structure + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/dpram_8x19_generate.log b/src/dpram_8x19_generate.log new file mode 100644 index 0000000..f50d5d2 --- /dev/null +++ b/src/dpram_8x19_generate.log @@ -0,0 +1,48 @@ +Starting process: + +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Nov 20 19:14:28 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e + Circuit name : dpram_8x19 + Module type : sdpram + Module Version : 3.4 + Address width : 4 + Data width : 19 + Ports : + Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0] + Outputs : Q[18:0] + I/O buffer : not inserted + Clock edge : rising edge + EDIF output : suppressed + VHDL output : dpram_8x19.vhd + VHDL template : dpram_8x19_tmpl.vhd + VHDL testbench : tb_dpram_8x19_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : dpram_8x19.srp + Estimated Resource Usage: + LUT : 1 + DRAM : 5 + +END SCUBA Module Synthesis + +File: ..\src\dpram_8x19.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/dpram_8x19_tmpl.vhd b/src/dpram_8x19_tmpl.vhd new file mode 100644 index 0000000..9985f90 --- /dev/null +++ b/src/dpram_8x19_tmpl.vhd @@ -0,0 +1,17 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 3.4 +-- Fri Nov 20 19:14:28 2009 + +-- parameterized module component declaration +component dpram_8x19 + port (WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(18 downto 0); WrClock: in std_logic; + WE: in std_logic; WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + Q: out std_logic_vector(18 downto 0)); +end component; + +-- parameterized module component instance +__ : dpram_8x19 + port map (WrAddress(3 downto 0)=>__, Data(18 downto 0)=>__, WrClock=>__, + WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, Q(18 downto 0)=>__); diff --git a/src/eds_buf.vhd b/src/eds_buf.vhd new file mode 100644 index 0000000..446ffbb --- /dev/null +++ b/src/eds_buf.vhd @@ -0,0 +1,130 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity eds_buf is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + -- EDS input, all synced to CLK_IN + EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input + EDS_WE_IN : in std_logic; -- EDS write enable + EDS_DONE_IN : in std_logic; -- release EDS + EDS_DATA_OUT : out std_logic_vector(39 downto 0); + EDS_AVAILABLE_OUT : out std_logic; + -- trigger busy information + BUF_FULL_OUT : out std_logic; + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of eds_buf is + + -- normal signals + signal debug : std_logic_vector(15 downto 0); + + -- Signals for controlling the EDS buffer memory + signal eds_data : std_logic_vector(39 downto 0); + signal eds_rd_addr : std_logic_vector(3 downto 0); + signal eds_wr_addr : std_logic_vector(3 downto 0); + signal eds_wr : std_logic; + signal eds_rd : std_logic; + signal eds_free_ctr : std_logic_vector(4 downto 0); -- fill level counter + signal eds_free_up : std_logic; + signal eds_free_down : std_logic; + signal eds_available_x : std_logic; + signal eds_available : std_logic; -- at least one valid EDS entry is available + signal eds_full_x : std_logic; + signal eds_full : std_logic; + +begin + +-- General process for syncing combinatorial signals +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + eds_available <= eds_available_x; + eds_full <= eds_full_x; + end if; +end process THE_SYNC_PROC; + +-- Write address pointer for EDS buffer +eds_wr <= eds_we_in; + +THE_WR_ADDR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + eds_wr_addr <= (others => '0'); + elsif( eds_wr = '1' ) then + eds_wr_addr <= eds_wr_addr + 1; + end if; + end if; +end process THE_WR_ADDR_PROC; + +-- Read address pointer for EDS buffer +eds_rd <= eds_done_in; + +THE_RD_ADDR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + eds_rd_addr <= (others => '0'); + elsif( eds_rd = '1' ) then + eds_rd_addr <= eds_rd_addr + 1; + end if; + end if; +end process THE_RD_ADDR_PROC; + +-- Buffer fill level counter +eds_free_down <= eds_we_in; +eds_free_up <= eds_done_in; + +THE_EDS_FREE_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + eds_free_ctr <= "10000"; + elsif( eds_free_down = '1' and eds_free_up = '0' ) then + eds_free_ctr <= eds_free_ctr - 1; + elsif( eds_free_down = '0' and eds_free_up = '1' ) then + eds_free_ctr <= eds_free_ctr + 1; + end if; + end if; +end process THE_EDS_FREE_COUNTER_PROC; + +eds_full_x <= '1' when (eds_free_ctr = "00000") else '0'; + +-- A 16x40b DPRAM is used for buffering the EventDataSheets (EDS) +THE_EDS_BUFFER: eds_buffer_dpram +port map( WRADDRESS => eds_wr_addr, + DATA => eds_data_in, + WRCLOCK => clk_in, + WE => eds_we_in, + WRCLOCKEN => '1', + RDADDRESS => eds_rd_addr, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => eds_data + ); + +-- Are there any EDS to work on? +eds_available_x <= '1' when (eds_wr_addr /= eds_rd_addr) else '0'; + +-- Debug signals +debug(15 downto 0) <= (others => '0'); + +-- Output signals +eds_data_out <= eds_data; +eds_available_out <= eds_available; +buf_full_out <= eds_full; +buf_level_out <= eds_free_ctr; +debug_out <= debug; + +end behavioral; diff --git a/src/eds_buffer_dpram.lpc b/src/eds_buffer_dpram.lpc new file mode 100644 index 0000000..604c395 --- /dev/null +++ b/src/eds_buffer_dpram.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M35E +PartName=LFE2M35E-6F672C +SpeedGrade=-6 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_DPRAM +CoreRevision=3.3 +ModuleName=eds_buffer_dpram +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/29/2008 +Time=14:24:36 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=16 +Data=40 +LUT=1 +MemFile= +MemFormat=orca diff --git a/src/eds_buffer_dpram.vhd b/src/eds_buffer_dpram.vhd new file mode 100644 index 0000000..2b3d495 --- /dev/null +++ b/src/eds_buffer_dpram.vhd @@ -0,0 +1,546 @@ +-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58) +-- Module Version: 3.3 +--X:\Programme\ispTOOLS_71\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sdpram -rdata_width 40 -data_width 40 -num_rows 16 -outData REGISTERED -e + +-- Fri Aug 29 14:24:36 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity eds_buffer_dpram is + port ( + WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(39 downto 0); + WrClock: in std_logic; + WE: in std_logic; + WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(39 downto 0)); +end eds_buffer_dpram; + +architecture Structure of eds_buffer_dpram is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal dataout39_ffin: std_logic; + signal dataout38_ffin: std_logic; + signal dataout37_ffin: std_logic; + signal dataout36_ffin: std_logic; + signal dataout35_ffin: std_logic; + signal dataout34_ffin: std_logic; + signal dataout33_ffin: std_logic; + signal dataout32_ffin: std_logic; + signal dataout31_ffin: std_logic; + signal dataout30_ffin: std_logic; + signal dataout29_ffin: std_logic; + signal dataout28_ffin: std_logic; + signal dataout27_ffin: std_logic; + signal dataout26_ffin: std_logic; + signal dataout25_ffin: std_logic; + signal dataout24_ffin: std_logic; + signal dataout23_ffin: std_logic; + signal dataout22_ffin: std_logic; + signal dataout21_ffin: std_logic; + signal dataout20_ffin: std_logic; + signal dataout19_ffin: std_logic; + signal dataout18_ffin: std_logic; + signal dataout17_ffin: std_logic; + signal dataout16_ffin: std_logic; + signal dataout15_ffin: std_logic; + signal dataout14_ffin: std_logic; + signal dataout13_ffin: std_logic; + signal dataout12_ffin: std_logic; + signal dataout11_ffin: std_logic; + signal dataout10_ffin: std_logic; + signal dataout9_ffin: std_logic; + signal dataout8_ffin: std_logic; + signal dataout7_ffin: std_logic; + signal dataout6_ffin: std_logic; + signal dataout5_ffin: std_logic; + signal dataout4_ffin: std_logic; + signal dataout3_ffin: std_logic; + signal dataout2_ffin: std_logic; + signal dataout1_ffin: std_logic; + signal dataout0_ffin: std_logic; + signal dec_wre3: std_logic; + + -- local component declarations + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4A + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute initval : string; + attribute GSR : string; + attribute initval of LUT4_0 : label is "0x8000"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8000") + -- synopsys translate_on + port map (AD3=>WE, AD2=>WrClockEn, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec_wre3); + + FF_39: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout39_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(39)); + + FF_38: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout38_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(38)); + + FF_37: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout37_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(37)); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout36_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(36)); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout35_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(35)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout34_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(34)); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout33_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(33)); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout32_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(32)); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout31_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(31)); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout30_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(30)); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout29_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(29)); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout28_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(28)); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout27_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(27)); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout26_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(26)); + + FF_25: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout25_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(25)); + + FF_24: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout24_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(24)); + + FF_23: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout23_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(23)); + + FF_22: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout22_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(22)); + + FF_21: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout21_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(21)); + + FF_20: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout20_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(20)); + + FF_19: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout19_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(19)); + + FF_18: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout18_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(18)); + + FF_17: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout17_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(17)); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout16_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(16)); + + FF_15: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout15_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(15)); + + FF_14: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout14_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(14)); + + FF_13: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout13_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(13)); + + FF_12: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout12_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(12)); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout11_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(11)); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout10_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(10)); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout9_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(9)); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout8_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(8)); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout7_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(7)); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout6_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(6)); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout5_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(5)); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout4_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(4)); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout3_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(3)); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout2_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(2)); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout1_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(1)); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout0_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(0)); + + mem_0_0: DPR16X4A + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), WCK=>WrClock, WRE=>dec_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout36_ffin, + DO1=>dataout37_ffin, DO2=>dataout38_ffin, + DO3=>dataout39_ffin); + + mem_0_1: DPR16X4A + port map (DI0=>Data(32), DI1=>Data(33), DI2=>Data(34), + DI3=>Data(35), WCK=>WrClock, WRE=>dec_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout32_ffin, + DO1=>dataout33_ffin, DO2=>dataout34_ffin, + DO3=>dataout35_ffin); + + mem_0_2: DPR16X4A + port map (DI0=>Data(28), DI1=>Data(29), DI2=>Data(30), + DI3=>Data(31), WCK=>WrClock, WRE=>dec_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout28_ffin, + DO1=>dataout29_ffin, DO2=>dataout30_ffin, + DO3=>dataout31_ffin); + + mem_0_3: DPR16X4A + port map (DI0=>Data(24), DI1=>Data(25), DI2=>Data(26), + DI3=>Data(27), WCK=>WrClock, WRE=>dec_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout24_ffin, + DO1=>dataout25_ffin, DO2=>dataout26_ffin, + DO3=>dataout27_ffin); + + mem_0_4: DPR16X4A + port map (DI0=>Data(20), DI1=>Data(21), DI2=>Data(22), + DI3=>Data(23), WCK=>WrClock, WRE=>dec_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout20_ffin, + DO1=>dataout21_ffin, DO2=>dataout22_ffin, + DO3=>dataout23_ffin); + + mem_0_5: DPR16X4A + port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18), + DI3=>Data(19), WCK=>WrClock, WRE=>dec_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout16_ffin, + DO1=>dataout17_ffin, DO2=>dataout18_ffin, + DO3=>dataout19_ffin); + + mem_0_6: DPR16X4A + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>WrClock, WRE=>dec_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout12_ffin, + DO1=>dataout13_ffin, DO2=>dataout14_ffin, + DO3=>dataout15_ffin); + + mem_0_7: DPR16X4A + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>WrClock, WRE=>dec_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout8_ffin, + DO1=>dataout9_ffin, DO2=>dataout10_ffin, DO3=>dataout11_ffin); + + mem_0_8: DPR16X4A + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>WrClock, WRE=>dec_wre3, RAD0=>RdAddress(0), + RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3), + WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2), + WAD3=>WrAddress(3), DO0=>dataout4_ffin, DO1=>dataout5_ffin, + DO2=>dataout6_ffin, DO3=>dataout7_ffin); + + mem_0_9: DPR16X4A + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>WrClock, WRE=>dec_wre3, RAD0=>RdAddress(0), + RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3), + WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2), + WAD3=>WrAddress(3), DO0=>dataout0_ffin, DO1=>dataout1_ffin, + DO2=>dataout2_ffin, DO3=>dataout3_ffin); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of eds_buffer_dpram is + for Structure + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/eds_buffer_dpram_tmpl.vhd b/src/eds_buffer_dpram_tmpl.vhd new file mode 100644 index 0000000..95c9ae0 --- /dev/null +++ b/src/eds_buffer_dpram_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58) +-- Module Version: 3.3 +-- Fri Aug 29 14:24:36 2008 + +-- parameterized module component declaration +component eds_buffer_dpram + port (WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(39 downto 0); WrClock: in std_logic; + WE: in std_logic; WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; Q: out std_logic_vector(39 downto 0)); +end component; + +-- parameterized module component instance +__ : eds_buffer_dpram + port map (WrAddress(3 downto 0)=>__, Data(39 downto 0)=>__, WrClock=>__, + WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__, + RdClockEn=>__, Reset=>__, Q(39 downto 0)=>__); diff --git a/src/fifo_16x11.lpc b/src/fifo_16x11.lpc new file mode 100644 index 0000000..49a7243 --- /dev/null +++ b/src/fifo_16x11.lpc @@ -0,0 +1,44 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.5 +ModuleName=fifo_16x11 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/03/2009 +Time=16:26:00 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=16 +Width=11 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Single Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=1 +EnECC=0 diff --git a/src/fifo_16x11.vhd b/src/fifo_16x11.vhd new file mode 100644 index 0000000..6214fe8 --- /dev/null +++ b/src/fifo_16x11.vhd @@ -0,0 +1,616 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 4.5 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 11 -depth 16 -no_enable -pe -1 -pf -1 -fill -e + +-- Tue Mar 03 16:26:00 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_16x11 is + port ( + Data: in std_logic_vector(10 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(10 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_16x11; + +architecture Structure of fifo_16x11 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal co2: std_logic; + signal cnt_con: std_logic; + signal co1: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal wren_i: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_4: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal co2_1: std_logic; + signal wcount_4: std_logic; + signal co1_3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal co2_2: std_logic; + signal rcount_4: std_logic; + signal co1_4: std_logic; + signal rdataout10: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal scuba_vlo: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rcount_3: std_logic; + signal rcount_2: std_logic; + signal rcount_1: std_logic; + signal rcount_0: std_logic; + signal dec0_wre3: std_logic; + signal wcount_3: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal wcount_0: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4A + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + attribute initval : string; + attribute GSR : string; + attribute initval of LUT4_2 : label is "0x3232"; + attribute initval of LUT4_1 : label is "0x3232"; + attribute initval of LUT4_0 : label is "0x8000"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8000") + -- synopsys translate_on + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_25: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_24: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_23: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_22: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_20: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_19: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_18: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_17: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_15: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_14: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_13: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_12: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(0)); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(1)); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(2)); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(3)); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(4)); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(5)); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(6)); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(7)); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(8)); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(9)); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(10)); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>open); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co1_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>iwcount_4, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_2, + NC0=>ircount_4, NC1=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_pfu_0_0: DPR16X4A + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, + RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>rcount_3, + WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, + WAD3=>wcount_3, DO0=>rdataout8, DO1=>rdataout9, + DO2=>rdataout10, DO3=>open); + + fifo_pfu_0_1: DPR16X4A + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout4, DO1=>rdataout5, DO2=>rdataout6, + DO3=>rdataout7); + + fifo_pfu_0_2: DPR16X4A + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout0, DO1=>rdataout1, DO2=>rdataout2, + DO3=>rdataout3); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_16x11 is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:ALEB2 use entity ecp2m.ALEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:CB2 use entity ecp2m.CB2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/fifo_16x11_tmpl.vhd b/src/fifo_16x11_tmpl.vhd new file mode 100644 index 0000000..5e157c8 --- /dev/null +++ b/src/fifo_16x11_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 4.5 +-- Tue Mar 03 16:26:00 2009 + +-- parameterized module component declaration +component fifo_16x11 + port (Data: in std_logic_vector(10 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(10 downto 0); + WCNT: out std_logic_vector(4 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_16x11 + port map (Data(10 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(10 downto 0)=>__, WCNT(4 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/src/fifo_2kx27.lpc b/src/fifo_2kx27.lpc new file mode 100644 index 0000000..77bc0d4 --- /dev/null +++ b/src/fifo_2kx27.lpc @@ -0,0 +1,44 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.5 +ModuleName=fifo_2kx27 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=02/27/2009 +Time=12:01:58 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=27 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Single Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=1 +EnECC=0 diff --git a/src/fifo_2kx27.vhd b/src/fifo_2kx27.vhd new file mode 100644 index 0000000..e2011a1 --- /dev/null +++ b/src/fifo_2kx27.vhd @@ -0,0 +1,1004 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 4.5 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 27 -depth 2048 -no_enable -pe -1 -pf -1 -fill -e + +-- Fri Feb 27 12:01:58 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_2kx27 is + port ( + Data: in std_logic_vector(26 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(26 downto 0); + WCNT: out std_logic_vector(11 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_2kx27; + +architecture Structure of fifo_2kx27 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal ifcount_11: std_logic; + signal co5: std_logic; + signal cnt_con: std_logic; + signal co4: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal fcount_10: std_logic; + signal fcount_11: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co3_3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5_1: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co4_3: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co1_4: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co2_4: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co3_4: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co5_2: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co4_4: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_1 : label is "0x3232"; + attribute initval of LUT4_0 : label is "0x3232"; + attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "fifo_2kx27.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_2 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_2 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_2 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_2 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_2 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_2 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_2 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_2 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_2 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_2 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_0_2 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "fifo_2kx27.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_1 : label is ""; + attribute CSDECODE_B of pdp_ram_0_1_1 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_1_1 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_1_1 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_1_1 : label is "NORMAL"; + attribute GSR of pdp_ram_0_1_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_1_1 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_1_1 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_1_1 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_1_1 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_1_1 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "fifo_2kx27.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is ""; + attribute CSDECODE_B of pdp_ram_0_2_0 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_2_0 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_2_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_2_0 : label is "NORMAL"; + attribute GSR of pdp_ram_0_2_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_2_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_2_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_2_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_2_0 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_2_0 : label is "9"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_2: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wcount_0, + ADA4=>wcount_1, ADA5=>wcount_2, ADA6=>wcount_3, + ADA7=>wcount_4, ADA8=>wcount_5, ADA9=>wcount_6, + ADA10=>wcount_7, ADA11=>wcount_8, ADA12=>wcount_9, + ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rcount_0, ADB4=>rcount_1, + ADB5=>rcount_2, ADB6=>rcount_3, ADB7=>rcount_4, + ADB8=>rcount_5, ADB9=>rcount_6, ADB10=>rcount_7, + ADB11=>rcount_8, ADB12=>rcount_9, ADB13=>rcount_10, + CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), + DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_1_1: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wcount_0, ADA4=>wcount_1, ADA5=>wcount_2, + ADA6=>wcount_3, ADA7=>wcount_4, ADA8=>wcount_5, + ADA9=>wcount_6, ADA10=>wcount_7, ADA11=>wcount_8, + ADA12=>wcount_9, ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rcount_0, + ADB4=>rcount_1, ADB5=>rcount_2, ADB6=>rcount_3, + ADB7=>rcount_4, ADB8=>rcount_5, ADB9=>rcount_6, + ADB10=>rcount_7, ADB11=>rcount_8, ADB12=>rcount_9, + ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(9), DOB1=>Q(10), DOB2=>Q(11), + DOB3=>Q(12), DOB4=>Q(13), DOB5=>Q(14), DOB6=>Q(15), + DOB7=>Q(16), DOB8=>Q(17), DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_2_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), + DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), + DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wcount_0, ADA4=>wcount_1, ADA5=>wcount_2, + ADA6=>wcount_3, ADA7=>wcount_4, ADA8=>wcount_5, + ADA9=>wcount_6, ADA10=>wcount_7, ADA11=>wcount_8, + ADA12=>wcount_9, ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rcount_0, + ADB4=>rcount_1, ADB5=>rcount_2, ADB6=>rcount_3, + ADB7=>rcount_4, ADB8=>rcount_5, ADB9=>rcount_6, + ADB10=>rcount_7, ADB11=>rcount_8, ADB12=>rcount_9, + ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(18), DOB1=>Q(19), DOB2=>Q(20), + DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23), DOB6=>Q(24), + DOB7=>Q(25), DOB8=>Q(26), DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + FF_37: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_25: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_23: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_22: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_21: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_20: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_19: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_18: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_17: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_15: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_14: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_13: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_12: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + bdcnt_bctr_5: CB2 + port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con, + CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>co4_1); + + e_cmp_5: ALEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + CI=>co3_2, GE=>co4_2); + + g_cmp_5: AGEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, + B1=>wren_i_inv, CI=>co4_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_ctr_5: CU2 + port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_1, + NC0=>iwcount_10, NC1=>iwcount_11); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4, + NC0=>ircount_8, NC1=>ircount_9); + + r_ctr_5: CU2 + port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_2, + NC0=>ircount_10, NC1=>ircount_11); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + WCNT(11) <= fcount_11; + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_2kx27 is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:ALEB2 use entity ecp2m.ALEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:CB2 use entity ecp2m.CB2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/fifo_2kx27_tmpl.vhd b/src/fifo_2kx27_tmpl.vhd new file mode 100644 index 0000000..7e0698c --- /dev/null +++ b/src/fifo_2kx27_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 4.5 +-- Fri Feb 27 12:01:58 2009 + +-- parameterized module component declaration +component fifo_2kx27 + port (Data: in std_logic_vector(26 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(26 downto 0); + WCNT: out std_logic_vector(11 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_2kx27 + port map (Data(26 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(26 downto 0)=>__, WCNT(11 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/src/frame_status_mem.lpc b/src/frame_status_mem.lpc new file mode 100644 index 0000000..7761bd4 --- /dev/null +++ b/src/frame_status_mem.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_DPRAM +CoreRevision=3.5 +ModuleName=frame_status_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/14/2009 +Time=13:08:21 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=16 +Data=12 +LUT=1 +MemFile= +MemFormat=orca diff --git a/src/frame_status_mem.srp b/src/frame_status_mem.srp new file mode 100644 index 0000000..cf54009 --- /dev/null +++ b/src/frame_status_mem.srp @@ -0,0 +1,34 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 13:08:21 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e + Circuit name : frame_status_mem + Module type : sdpram + Module Version : 3.5 + Address width : 4 + Ports : + Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset + Outputs : Q[11:0] + I/O buffer : not inserted + Clock edge : rising edge + EDIF output : suppressed + VHDL output : frame_status_mem.vhd + VHDL template : frame_status_mem_tmpl.vhd + VHDL testbench : tb_frame_status_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : frame_status_mem.srp + Element Usage : + FD1P3DX : 12 + ROM16X1 : 1 + DPR16X4A : 3 + Estimated Resource Usage: + LUT : 1 + DRAM : 3 + Reg : 12 diff --git a/src/frame_status_mem.vhd b/src/frame_status_mem.vhd new file mode 100644 index 0000000..9400698 --- /dev/null +++ b/src/frame_status_mem.vhd @@ -0,0 +1,231 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 3.5 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sdpram -rdata_width 12 -data_width 12 -num_rows 16 -outData REGISTERED -e + +-- Mon Sep 14 13:08:21 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity frame_status_mem is + port ( + WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(11 downto 0); + WrClock: in std_logic; + WE: in std_logic; + WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(11 downto 0)); +end frame_status_mem; + +architecture Structure of frame_status_mem is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal dataout11_ffin: std_logic; + signal dataout10_ffin: std_logic; + signal dataout9_ffin: std_logic; + signal dataout8_ffin: std_logic; + signal dataout7_ffin: std_logic; + signal dataout6_ffin: std_logic; + signal dataout5_ffin: std_logic; + signal dataout4_ffin: std_logic; + signal dataout3_ffin: std_logic; + signal dataout2_ffin: std_logic; + signal dataout1_ffin: std_logic; + signal dataout0_ffin: std_logic; + signal dec0_wre3: std_logic; + + -- local component declarations + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4A + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute initval : string; + attribute GSR : string; + attribute initval of LUT4_0 : label is "0x8000"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8000") + -- synopsys translate_on + port map (AD3=>WE, AD2=>WrClockEn, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout11_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(11)); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout10_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(10)); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout9_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(9)); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout8_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(8)); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout7_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(7)); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout6_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(6)); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout5_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(5)); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout4_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(4)); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout3_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(3)); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout2_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(2)); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout1_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(1)); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>dataout0_ffin, SP=>RdClockEn, CK=>RdClock, + CD=>Reset, Q=>Q(0)); + + mem_0_0: DPR16X4A + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, + RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2), + RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1), + WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout8_ffin, + DO1=>dataout9_ffin, DO2=>dataout10_ffin, DO3=>dataout11_ffin); + + mem_0_1: DPR16X4A + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0), + RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3), + WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2), + WAD3=>WrAddress(3), DO0=>dataout4_ffin, DO1=>dataout5_ffin, + DO2=>dataout6_ffin, DO3=>dataout7_ffin); + + mem_0_2: DPR16X4A + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0), + RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3), + WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2), + WAD3=>WrAddress(3), DO0=>dataout0_ffin, DO1=>dataout1_ffin, + DO2=>dataout2_ffin, DO3=>dataout3_ffin); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of frame_status_mem is + for Structure + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/frame_status_mem_generate.log b/src/frame_status_mem_generate.log new file mode 100644 index 0000000..c0b628b --- /dev/null +++ b/src/frame_status_mem_generate.log @@ -0,0 +1,49 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 13:08:21 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e + Circuit name : frame_status_mem + Module type : sdpram + Module Version : 3.5 + Address width : 4 + Data width : 12 + Ports : + Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset + Outputs : Q[11:0] + I/O buffer : not inserted + Clock edge : rising edge + EDIF output : suppressed + VHDL output : frame_status_mem.vhd + VHDL template : frame_status_mem_tmpl.vhd + VHDL testbench : tb_frame_status_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : frame_status_mem.srp + Estimated Resource Usage: + LUT : 1 + DRAM : 3 + Reg : 12 + +END SCUBA Module Synthesis + +File: frame_status_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/frame_status_mem_tmpl.vhd b/src/frame_status_mem_tmpl.vhd new file mode 100644 index 0000000..9bb11c2 --- /dev/null +++ b/src/frame_status_mem_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 3.5 +-- Mon Sep 14 13:08:21 2009 + +-- parameterized module component declaration +component frame_status_mem + port (WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(11 downto 0); WrClock: in std_logic; + WE: in std_logic; WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; Q: out std_logic_vector(11 downto 0)); +end component; + +-- parameterized module component instance +__ : frame_status_mem + port map (WrAddress(3 downto 0)=>__, Data(11 downto 0)=>__, WrClock=>__, + WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__, + RdClockEn=>__, Reset=>__, Q(11 downto 0)=>__); diff --git a/src/frmctr_check.vhd b/src/frmctr_check.vhd new file mode 100755 index 0000000..7eaae72 --- /dev/null +++ b/src/frmctr_check.vhd @@ -0,0 +1,89 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +-- This module checks the framecounter setting embedded inside the APV raw data. +-- Only channels with GOODDATA are taken into account. + +entity frmctr_check is + port( CLK_IN : in std_logic; + GOODDATA_IN : in std_logic_vector(15 downto 0); + FRAMECOUNTER_IN : in std_logic_vector(3 downto 0); + FRM_NR_0_IN : in std_logic_vector(3 downto 0); + FRM_NR_1_IN : in std_logic_vector(3 downto 0); + FRM_NR_2_IN : in std_logic_vector(3 downto 0); + FRM_NR_3_IN : in std_logic_vector(3 downto 0); + FRM_NR_4_IN : in std_logic_vector(3 downto 0); + FRM_NR_5_IN : in std_logic_vector(3 downto 0); + FRM_NR_6_IN : in std_logic_vector(3 downto 0); + FRM_NR_7_IN : in std_logic_vector(3 downto 0); + FRM_NR_8_IN : in std_logic_vector(3 downto 0); + FRM_NR_9_IN : in std_logic_vector(3 downto 0); + FRM_NR_10_IN : in std_logic_vector(3 downto 0); + FRM_NR_11_IN : in std_logic_vector(3 downto 0); + FRM_NR_12_IN : in std_logic_vector(3 downto 0); + FRM_NR_13_IN : in std_logic_vector(3 downto 0); + FRM_NR_14_IN : in std_logic_vector(3 downto 0); + FRM_NR_15_IN : in std_logic_vector(3 downto 0); + FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong + DBG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of frmctr_check is + + -- normal signals + signal debug_x : std_logic_vector(15 downto 0); + + signal next_frc_match : std_logic_vector(15 downto 0); + signal frc_match : std_logic_vector(15 downto 0); + signal next_frc_error : std_logic; + signal frc_error : std_logic; + +begin + +-- Sync process +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + frc_match <= next_frc_match; + frc_error <= next_frc_error; + end if; +end process THE_SYNC_PROC; + +-- Check the individual buffers +-- If an APV is "not good" (i.e. broken or switched off) we assume a match. +-- In case all APVs are switched off we get a match, this situation should be reconsidered... +next_frc_match(0) <= '1' when ( (frm_nr_0_in = framecounter_in) or (gooddata_in(0) = '0') ) else '0'; +next_frc_match(1) <= '1' when ( (frm_nr_1_in = framecounter_in) or (gooddata_in(1) = '0') ) else '0'; +next_frc_match(2) <= '1' when ( (frm_nr_2_in = framecounter_in) or (gooddata_in(2) = '0') ) else '0'; +next_frc_match(3) <= '1' when ( (frm_nr_3_in = framecounter_in) or (gooddata_in(3) = '0') ) else '0'; +next_frc_match(4) <= '1' when ( (frm_nr_4_in = framecounter_in) or (gooddata_in(4) = '0') ) else '0'; +next_frc_match(5) <= '1' when ( (frm_nr_5_in = framecounter_in) or (gooddata_in(5) = '0') ) else '0'; +next_frc_match(6) <= '1' when ( (frm_nr_6_in = framecounter_in) or (gooddata_in(6) = '0') ) else '0'; +next_frc_match(7) <= '1' when ( (frm_nr_7_in = framecounter_in) or (gooddata_in(7) = '0') ) else '0'; +next_frc_match(8) <= '1' when ( (frm_nr_8_in = framecounter_in) or (gooddata_in(8) = '0') ) else '0'; +next_frc_match(9) <= '1' when ( (frm_nr_9_in = framecounter_in) or (gooddata_in(9) = '0') ) else '0'; +next_frc_match(10) <= '1' when ( (frm_nr_10_in = framecounter_in) or (gooddata_in(10) = '0') ) else '0'; +next_frc_match(11) <= '1' when ( (frm_nr_11_in = framecounter_in) or (gooddata_in(11) = '0') ) else '0'; +next_frc_match(12) <= '1' when ( (frm_nr_12_in = framecounter_in) or (gooddata_in(12) = '0') ) else '0'; +next_frc_match(13) <= '1' when ( (frm_nr_13_in = framecounter_in) or (gooddata_in(13) = '0') ) else '0'; +next_frc_match(14) <= '1' when ( (frm_nr_14_in = framecounter_in) or (gooddata_in(14) = '0') ) else '0'; +next_frc_match(15) <= '1' when ( (frm_nr_15_in = framecounter_in) or (gooddata_in(15) = '0') ) else '0'; + +-- Combine all signals +next_frc_error <= '1' when ( frc_match /= x"ffff" ) else '0'; + +-- output signals +frc_error_out <= frc_error; + +-- debug signals +debug_x(15 downto 0) <= (others => '0'); + +dbg_out <= debug_x; + +end behavioral; diff --git a/src/i2c_gstart.vhd b/src/i2c_gstart.vhd new file mode 100644 index 0000000..ec4d696 --- /dev/null +++ b/src/i2c_gstart.vhd @@ -0,0 +1,227 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +entity I2C_GSTART is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + DOSTART_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector(7 downto 0); + SDONE_OUT : out std_logic; + SOK_OUT : out std_logic; + SDA_IN : in std_logic; + SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0) + ); +end entity; + +architecture Behavioral of I2C_GSTART is + +-- Signals + type STATES is (SLEEP,P_SCL,WCTR0,P_SDA,WCTR1,P_CHK,S_CHK0,RS_SDA,S_CHK1,ERROR,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + signal bsm : std_logic_vector(3 downto 0); + signal cctr : std_logic_vector(7 downto 0); -- counter for bit length + + signal cycdone_x : std_logic; + signal cycdone : std_logic; -- one counter period done + + signal load_cyc_x : std_logic; + signal load_cyc : std_logic; + signal dec_cyc_x : std_logic; + signal dec_cyc : std_logic; + signal sdone_x : std_logic; + signal sdone : std_logic; -- Start/Stop done + signal sok_x : std_logic; + signal sok : std_logic; -- Start/Stop OK + + signal r_scl : std_logic; + signal s_scl : std_logic; + signal r_sda : std_logic; + signal s_sda : std_logic; + +-- Moduls + +begin + +-- Countdown for one half of SCL (adjustable clock width) +THE_CYC_CTR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + cctr <= (others => '0'); + elsif( load_cyc = '1' ) then + cctr <= i2c_speed_in; + elsif( dec_cyc = '1' ) then + cctr <= cctr - 1; + end if; + end if; +end process THE_CYC_CTR_PROC; + +-- end of cycle recognition +cycdone_x <= '1' when (cctr = x"00") else '0'; + +-- The main state machine +-- State memory process +STATE_MEM: process( clk_in ) +begin + if ( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + load_cyc <= '0'; + dec_cyc <= '0'; + sdone <= '0'; + sok <= '0'; + cycdone <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + load_cyc <= load_cyc_x; + dec_cyc <= dec_cyc_x; + sdone <= sdone_x; + sok <= sok_x; + cycdone <= cycdone_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, dostart_in, start_in, sda_in, scl_in, cycdone) +begin + NEXT_STATE <= SLEEP; + load_cyc_x <= '0'; + dec_cyc_x <= '0'; + sdone_x <= '0'; + sok_x <= '1'; + case CURRENT_STATE is + when SLEEP => if ( (dostart_in = '1') and (start_in = '1') ) then + NEXT_STATE <= S_CHK0; -- generate a start condition + load_cyc_x <= '1'; + elsif( (dostart_in = '1') and (start_in = '0') ) then + NEXT_STATE <= P_SCL; -- generate a stop condition + load_cyc_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when P_SCL => NEXT_STATE <= WCTR0; + dec_cyc_x <= '1'; + when S_CHK0 => if( (sda_in = '1') and (scl_in = '1') ) then + NEXT_STATE <= RS_SDA; + else + NEXT_STATE <= ERROR; + sok_x <= '0'; + end if; + when RS_SDA => NEXT_STATE <= WCTR0; + dec_cyc_x <= '1'; + when WCTR0 => if ( (cycdone = '1') and (start_in = '1') ) then + NEXT_STATE <= S_CHK1; + elsif( (cycdone = '1') and (start_in = '0') ) then + NEXT_STATE <= P_SDA; + load_cyc_x <= '1'; + else + NEXT_STATE <= WCTR0; + dec_cyc_x <= '1'; + end if; + when S_CHK1 => if( (sda_in = '0') and (scl_in = '1') ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= ERROR; + sok_x <= '0'; + end if; + when P_SDA => NEXT_STATE <= WCTR1; + dec_cyc_x <= '1'; + when WCTR1 => if( (cycdone = '1') ) then + NEXT_STATE <= P_CHK; + else + NEXT_STATE <= WCTR1; + dec_cyc_x <= '1'; + end if; + when P_CHK => if( (sda_in = '1') and (scl_in = '1') ) then + NEXT_STATE <= DONE; + sdone_x <= '1'; + else + NEXT_STATE <= ERROR; + sok_x <= '0'; + end if; + when ERROR => if( dostart_in = '0' ) then + NEXT_STATE <= SLEEP; + else + NEXT_STATE <= ERROR; + sdone_x <= '1'; + sok_x <= '0'; + end if; + when DONE => if( dostart_in = '0' ) then + NEXT_STATE <= SLEEP; + else + NEXT_STATE <= DONE; + sdone_x <= '1'; + end if; + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +-- Output decoding +DECODE: process(CURRENT_STATE) +begin + case CURRENT_STATE is + when SLEEP => bsm <= x"0"; + when S_CHK0 => bsm <= x"1"; + when RS_SDA => bsm <= x"2"; + when P_SCL => bsm <= x"3"; + when WCTR0 => bsm <= x"4"; + when S_CHK1 => bsm <= x"5"; + when P_SDA => bsm <= x"6"; + when WCTR1 => bsm <= x"7"; + when P_CHK => bsm <= x"8"; + when DONE => bsm <= x"9"; + when ERROR => bsm <= x"e"; + when others => bsm <= x"f"; + end case; +end process DECODE; + +S_R_GEN: process(CURRENT_STATE) +begin + if ( CURRENT_STATE = P_SCL ) then + r_scl <= '0'; + s_scl <= '1'; + r_sda <= '0'; + s_sda <= '0'; + elsif( CURRENT_STATE = RS_SDA ) then + r_scl <= '0'; + s_scl <= '0'; + r_sda <= '1'; + s_sda <= '0'; + elsif( CURRENT_STATE = P_SDA ) then + r_scl <= '0'; + s_scl <= '0'; + r_sda <= '0'; + s_sda <= '1'; + else + r_scl <= '0'; + s_scl <= '0'; + r_sda <= '0'; + s_sda <= '0'; + end if; +end process S_R_GEN; + +-- Outputs +r_scl_out <= r_scl; +s_scl_out <= s_scl; +r_sda_out <= r_sda; +s_sda_out <= s_sda; +sdone_out <= sdone; +sok_out <= sok; + +-- Debug +bsm_out <= bsm; + +end Behavioral; diff --git a/src/i2c_master.vhd b/src/i2c_master.vhd new file mode 100644 index 0000000..e843b62 --- /dev/null +++ b/src/i2c_master.vhd @@ -0,0 +1,201 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +entity i2c_master is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of i2c_master is + +-- Signals + type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- slave bus signals + signal slv_busy_x : std_logic; + signal slv_busy : std_logic; + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input + signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data + signal reg_busy : std_logic; + + signal status_data : std_logic_vector(31 downto 0); + signal i2c_debug : std_logic_vector(31 downto 0); + +begin + +--------------------------------------------------------- +-- I2C master -- +--------------------------------------------------------- + +THE_I2C_SLIM: i2c_slim +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- I2C command / setup + I2C_GO_IN => reg_slv_data_in(31), + ACTION_IN => reg_slv_data_in(30), + I2C_SPEED_IN => reg_slv_data_in(29 downto 24), + I2C_ADR_IN => reg_slv_data_in(23 downto 16), + I2C_CMD_IN => reg_slv_data_in(15 downto 8), + I2C_DW_IN => reg_slv_data_in(7 downto 0), + I2C_DR_OUT => status_data(7 downto 0), + STATUS_OUT => status_data(31 downto 24), + I2C_BUSY_OUT => reg_busy, + -- I2C connections + SDA_IN => sda_in, + SDA_OUT => sda_out, + SCL_IN => scl_in, + SCL_OUT => scl_out, + -- Debug + STAT => i2c_debug + ); + +status_data(23 downto 21) <= (others => '0'); +status_data(20 downto 16) <= i2c_debug(4 downto 0); +status_data(15 downto 8) <= (others => '0'); + +-- Fake +stat <= i2c_debug; + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_busy <= '0'; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_busy <= slv_busy_x; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) +begin + NEXT_STATE <= SLEEP; + slv_busy_x <= '0'; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( (reg_busy = '0') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + elsif( (reg_busy = '1') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_BSY; + slv_busy_x <= '1'; + elsif( (reg_busy = '1') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_BSY; + slv_busy_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_RDY => NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + when WR_RDY => NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when RD_BSY => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_BSY; + slv_busy_x <= '1'; + end if; + when WR_BSY => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_BSY; + slv_busy_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +-- register write +THE_WRITE_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + reg_slv_data_in <= (others => '0'); + elsif( store_wr = '1' ) then + reg_slv_data_in <= slv_data_in; + end if; + end if; +end process THE_WRITE_REG_PROC; + +-- register read +THE_READ_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + reg_slv_data_out <= (others => '0'); + elsif( store_rd = '1' ) then + reg_slv_data_out <= status_data; + end if; + end if; +end process THE_READ_REG_PROC; + +-- output signals +slv_ack_out <= slv_ack; +slv_busy_out <= slv_busy; +slv_data_out <= reg_slv_data_out; + +end Behavioral; diff --git a/src/i2c_sendb.vhd b/src/i2c_sendb.vhd new file mode 100644 index 0000000..42d8187 --- /dev/null +++ b/src/i2c_sendb.vhd @@ -0,0 +1,299 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +entity I2C_SENDB is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + DOBYTE_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector( 7 downto 0 ); + I2C_BYTE_IN : in std_logic_vector( 8 downto 0 ); + I2C_BACK_OUT : out std_logic_vector( 8 downto 0 ); + SDA_IN : in std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; +-- SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + BDONE_OUT : out std_logic; + BOK_OUT : out std_logic; + BSM_OUT : out std_logic_vector( 3 downto 0 ) + ); +end entity; + +architecture Behavioral of I2C_SENDB is + +-- Signals + type STATES is (SLEEP,LCL,WCL,LCH,WCH,FREE,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + signal bsm : std_logic_vector( 3 downto 0 ); + + signal inc_bit_x : std_logic; + signal inc_bit : std_logic; -- increment bit counter for byte to send + signal rst_bit_x : std_logic; + signal rst_bit : std_logic; -- reset bit counter for byte to send + signal load_cyc_x : std_logic; + signal load_cyc : std_logic; -- load cycle counter (SCL length) + signal dec_cyc_x : std_logic; + signal dec_cyc : std_logic; -- decrement cycle counter (SCL length) + signal load_sr_x : std_logic; + signal load_sr : std_logic; -- load output shift register + signal shift_o_x : std_logic; + signal shift_o : std_logic; -- output shift register control + signal shift_i_x : std_logic; + signal shift_i : std_logic; -- input shift register control + signal bdone_x : std_logic; + signal bdone : std_logic; + signal r_scl_x : std_logic; + signal r_scl : std_logic; -- output for SCL + signal s_scl_x : std_logic; + signal s_scl : std_logic; -- output for SCL + + signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9) + signal cctr : std_logic_vector( 7 downto 0 ); -- counter for bit length + signal bok : std_logic; + signal cycdone : std_logic; -- one counter period done + signal bytedone : std_logic; -- all bits sents + signal in_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte in + signal out_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte out + signal i2c_back : std_logic_vector( 8 downto 0 ); -- shift register for byte in + signal r_sda : std_logic; -- output for SDA + signal s_sda : std_logic; -- output for SDA + signal load : std_logic; -- delay register + signal i2c_d : std_logic; -- auxiliary register + +-- Moduls + +begin + +-- Bit counter (for byte to send) +THE_BIT_CTR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + bctr <= (others => '0'); + elsif( rst_bit = '1' ) then + bctr <= (others => '0'); + elsif( inc_bit = '1' ) then + bctr <= bctr + 1; + end if; + end if; +end process THE_BIT_CTR_PROC; + +-- end of byte recognition +bytedone <= '1' when (bctr = x"9") else '0'; + +-- Countdown for one half of SCL (adjustable clock width) +THE_CYC_CTR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + cctr <= (others => '0'); + elsif( load_cyc = '1' ) then + cctr <= i2c_speed_in; + elsif( dec_cyc = '1' ) then + cctr <= cctr - 1; + end if; + end if; +end process THE_CYC_CTR_PROC; + +-- end of cycle recognition +cycdone <= '1' when (cctr = x"00") else '0'; + +-- Bit output +THE_BIT_OUT_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + out_sr <= (others => '0'); + i2c_d <= '1'; + elsif( load_sr = '1' ) then + out_sr <= i2c_byte_in; + i2c_d <= '1'; + elsif( shift_o = '1' ) then + i2c_d <= out_sr(8); + out_sr(8 downto 0) <= out_sr(7 downto 0) & '0'; + end if; + end if; +end process THE_BIT_OUT_PROC; + +-- Bit input +THE_BIT_IN_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + in_sr <= (others => '1'); + elsif( shift_o = '1' ) then + in_sr(8 downto 1) <= in_sr(7 downto 0); + in_sr(0) <= sda_in; + end if; + end if; +end process THE_BIT_IN_PROC; + +-- Output register for readback data (could be reduced to SR_IN_INT) +THE_I2C_BACK_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + i2c_back <= (others => '1'); + elsif( shift_i = '1' ) then + i2c_back(8 downto 1) <= in_sr(7 downto 0); + i2c_back(0) <= sda_in; + end if; + end if; +end process THE_I2C_BACK_PROC; + +-- ByteOK is the inverted ACK bit from readback data. +bok <= not i2c_back(0); -- BUG + +-- The main state machine +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1') then + CURRENT_STATE <= SLEEP; + inc_bit <= '0'; + rst_bit <= '0'; + load_cyc <= '0'; + dec_cyc <= '0'; + load_sr <= '0'; + shift_o <= '0'; + shift_i <= '0'; + bdone <= '0'; + r_scl <= '0'; + s_scl <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + inc_bit <= inc_bit_x; + rst_bit <= rst_bit_x; + load_cyc <= load_cyc_x; + dec_cyc <= dec_cyc_x; + load_sr <= load_sr_x; + shift_o <= shift_o_x; + shift_i <= shift_i_x; + bdone <= bdone_x; + r_scl <= r_scl_x; + s_scl <= s_scl_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, dobyte_in, cycdone, bytedone) +begin + NEXT_STATE <= SLEEP; + inc_bit_x <= '0'; + rst_bit_x <= '0'; + load_cyc_x <= '0'; + dec_cyc_x <= '0'; + load_sr_x <= '0'; + shift_o_x <= '0'; + shift_i_x <= '0'; + bdone_x <= '0'; + r_scl_x <= '0'; + s_scl_x <= '0'; + case CURRENT_STATE is + when SLEEP => if( dobyte_in = '1' ) then + NEXT_STATE <= LCL; + inc_bit_x <= '1'; + load_cyc_x <= '1'; + shift_o_x <= '1'; + r_scl_x <= '1'; + else + NEXT_STATE <= SLEEP; + load_sr_x <= '1'; + end if; + when LCL => NEXT_STATE <= WCL; + dec_cyc_x <= '1'; + when WCL => if( cycdone = '1' ) then + NEXT_STATE <= LCH; + load_cyc_x <= '1'; + s_scl_x <= '1'; + else + NEXT_STATE <= WCL; + dec_cyc_x <= '1'; + end if; + when LCH => NEXT_STATE <= WCH; + dec_cyc_x <= '1'; + when WCH => if ( (cycdone = '1') and (bytedone = '0') ) then + NEXT_STATE <= LCL; + inc_bit_x <= '1'; + load_cyc_x <= '1'; + shift_o_x <= '1'; + r_scl_x <= '1'; + elsif( (cycdone = '1') and (bytedone = '1') ) then + NEXT_STATE <= FREE; + shift_o_x <= '1'; + shift_i_x <= '1'; + r_scl_x <= '1'; + else + NEXT_STATE <= WCH; + dec_cyc_x <= '1'; + end if; + when FREE => NEXT_STATE <= DONE; + rst_bit_x <= '1'; + bdone_x <= '1'; + when DONE => if( dobyte_in = '0' ) then + NEXT_STATE <= SLEEP; + else + NEXT_STATE <= DONE; + rst_bit_x <= '1'; + bdone_x <= '1'; + end if; + -- Just in case... + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +-- Output decoding +DECODE: process(CURRENT_STATE) +begin + case CURRENT_STATE is + when SLEEP => bsm <= x"0"; + when LCL => bsm <= x"1"; + when WCL => bsm <= x"2"; + when LCH => bsm <= x"3"; + when WCH => bsm <= x"4"; + when FREE => bsm <= x"5"; + when DONE => bsm <= x"6"; + when others => bsm <= x"f"; + end case; +end process DECODE; + +-- SCL and SDA output pulses +THE_SDA_OUT_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + load <= '0'; -- was a bug, found 081008 + r_sda <= '0'; + s_sda <= '0'; + else + load <= shift_o; + r_sda <= load and not i2c_d; + s_sda <= load and i2c_d; + end if; + end if; +end process THE_SDA_OUT_PROC; + +-- Outputs +r_scl_out <= r_scl; +s_scl_out <= s_scl; +r_sda_out <= r_sda; +s_sda_out <= s_sda; + +i2c_back_out <= i2c_back; + +bdone_out <= bdone; +bok_out <= bok; + +-- Debugging +bsm_out <= bsm; + +end Behavioral; diff --git a/src/i2c_slim.vhd b/src/i2c_slim.vhd new file mode 100644 index 0000000..5c347ea --- /dev/null +++ b/src/i2c_slim.vhd @@ -0,0 +1,447 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +-- BUG: does alway set bit 0 of address byte to zero !!!! +-- REMARK: this is not a bug, but a feature.... + +entity i2c_slim is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- I2C command / setup + I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions + ACTION_IN : in std_logic; -- '0' -> write, '1' -> read + I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined) + I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte) + I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command + I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command + STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits + I2C_BUSY_OUT : out std_logic; + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Debug + STAT : out std_logic_vector(31 downto 0) + ); +end i2c_slim; + +architecture Behavioral of i2c_slim is + +-- Signals + type STATES is (SLEEP,LOADA,GSTART,SENDA,LOADC,SENDC,LOADD,SENDD,GSTOP,INC, + E_START,E_ADDR,E_CMD,E_WD,E_RSTART,E_RADDR,DONE,FAILED,CLRERR); + signal CURRENT_STATE, NEXT_STATE: STATES; + + signal bsm : std_logic_vector( 4 downto 0 ); + signal phase : std_logic; -- '0' => first phase, '1' => second phase of read cycle + + signal start_x : std_logic; + signal start : std_logic; -- '0' => generate STOP, '1' => generate START + signal dostart_x : std_logic; + signal dostart : std_logic; -- trigger the GenStart module + signal dobyte_x : std_logic; + signal dobyte : std_logic; -- trigger the ByteSend module + signal i2c_done_x : std_logic; + signal i2c_done : std_logic; -- acknowledge signal to the outside world + signal running_x : std_logic; + signal running : std_logic; -- legacy + + signal load_a_x : std_logic; + signal load_a : std_logic; + signal load_c_x : std_logic; + signal load_c : std_logic; + signal load_d_x : std_logic; + signal load_d : std_logic; + + signal sdone : std_logic; -- acknowledge signal from GenStart module + signal sok : std_logic; -- status signal from GenStart module + signal bdone : std_logic; -- acknowledge signal from SendByte module + signal bok : std_logic; -- status signal from SendByte module + signal e_sf : std_logic; -- Start failed + signal e_anak : std_logic; -- Adress byte NAK + signal e_cnak : std_logic; -- Command byte NAK + signal e_dnak : std_logic; -- Data byte NAK + signal e_rsf : std_logic; -- Repeated Start failed + signal e_ranak : std_logic; -- Repeated Adress NAK + signal i2c_byte : std_logic_vector( 8 downto 0 ); + signal i2c_dr : std_logic_vector( 8 downto 0 ); + + signal s_scl : std_logic; + signal r_scl : std_logic; + signal s_sda : std_logic; + signal r_sda : std_logic; + signal r_scl_gs : std_logic; + signal s_scl_gs : std_logic; + signal r_sda_gs : std_logic; + signal s_sda_gs : std_logic; + signal r_scl_sb : std_logic; + signal s_scl_sb : std_logic; + signal r_sda_sb : std_logic; + signal s_sda_sb : std_logic; + + signal gs_debug : std_logic_vector(3 downto 0); + + signal i2c_speed : std_logic_vector(7 downto 0); + +begin + +i2c_speed <= i2c_speed_in & "00"; + +-- Read phase indicator +THE_PHASE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + phase <= '0'; + elsif( CURRENT_STATE = INC ) then + phase <= '1'; + elsif( (CURRENT_STATE = DONE) or (CURRENT_STATE = SLEEP) ) then + phase <= '0'; + end if; + end if; +end process THE_PHASE_PROC; + +-- The main state machine +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + start <= '0'; + dostart <= '0'; + dobyte <= '0'; + i2c_done <= '0'; + running <= '0'; + load_a <= '0'; + load_c <= '0'; + load_d <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + start <= start_x; + dostart <= dostart_x; + dobyte <= dobyte_x; + i2c_done <= i2c_done_x; + running <= running_x; + load_a <= load_a_x; + load_c <= load_c_x; + load_d <= load_d_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, i2c_go_in, sdone, sok, phase, bdone, bok, action_in) +begin + NEXT_STATE <= SLEEP; + start_x <= '0'; + dostart_x <= '0'; + dobyte_x <= '0'; + i2c_done_x <= '0'; + running_x <= '1'; + load_a_x <= '0'; + load_c_x <= '0'; + load_d_x <= '0'; + case CURRENT_STATE is + when SLEEP => if( i2c_go_in = '1' ) then + NEXT_STATE <= CLRERR; + else + NEXT_STATE <= SLEEP; + running_x <= '0'; + end if; + when CLRERR => NEXT_STATE <= LOADA; + load_a_x <= '1'; + when LOADA => NEXT_STATE <= GSTART; + start_x <= '1'; + dostart_x <= '1'; + when GSTART => if ( (sdone = '1') and (sok = '1') ) then + NEXT_STATE <= SENDA; + dobyte_x <= '1'; + elsif( (sdone = '1') and (sok = '0') and (phase = '0') ) then + NEXT_STATE <= E_START; -- first START condition failed + elsif( (sdone = '1') and (sok = '0') and (phase = '1') ) then + NEXT_STATE <= E_RSTART; -- second START condition failed + else + NEXT_STATE <= GSTART; + start_x <= '1'; + dostart_x <= '1'; + end if; + when E_START => NEXT_STATE <= FAILED; + dostart_x <= '1'; + when E_RSTART => NEXT_STATE <= FAILED; + dostart_x <= '1'; + when SENDA => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then + NEXT_STATE <= LOADC; -- I2C write + load_c_x <= '1'; + elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '0') ) then + NEXT_STATE <= LOADC; -- I2C read, send register address + load_c_x <= '1'; + elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '1') ) then + NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte + load_d_x <= '1'; + elsif( (bdone = '1') and (bok = '0') and (phase = '0') ) then + NEXT_STATE <= E_ADDR; -- first address phase failed + elsif( (bdone = '1') and (bok = '0') and (phase = '1') ) then + NEXT_STATE <= E_RADDR; -- second address phase failed + else + NEXT_STATE <= SENDA; + dobyte_x <= '1'; + end if; + when E_ADDR => NEXT_STATE <= FAILED; + dostart_x <= '1'; + when E_RADDR => NEXT_STATE <= FAILED; + dostart_x <= '1'; + when LOADC => NEXT_STATE <= SENDC; +-- dobyte_x <= '1'; + when SENDC => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then + NEXT_STATE <= LOADD; -- I2C write, prepare data + load_d_x <= '1'; + elsif( (bdone = '1') and (bok = '1') and (action_in = '1') ) then + NEXT_STATE <= GSTOP; -- I2C read, first phase ends + dostart_x <= '1'; + elsif( (bdone = '1') and (bok = '0') ) then + NEXT_STATE <= E_CMD; -- command phase failed + else + NEXT_STATE <= SENDC; + dobyte_x <= '1'; + end if; + when E_CMD => NEXT_STATE <= FAILED; + dostart_x <= '1'; + when LOADD => NEXT_STATE <= SENDD; + when SENDD => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then + NEXT_STATE <= GSTOP; -- I2C write, data phase failed + dostart_x <= '1'; + elsif( (bdone = '1') and (action_in = '1') ) then + NEXT_STATE <= GSTOP; -- I2C read, data phase + dostart_x <= '1'; + elsif( (bdone = '1') and (bok = '0') and (action_in = '0') ) then + NEXT_STATE <= E_WD; -- I2C write, data phase failed + else + NEXT_STATE <= SENDD; + dobyte_x <= '1'; + end if; + when E_WD => NEXT_STATE <= FAILED; + dostart_x <= '1'; + when GSTOP => if ( (sdone = '1') and (action_in = '0') ) then + NEXT_STATE <= DONE; + elsif( (sdone = '1') and (action_in = '1') and (phase = '1') ) then + NEXT_STATE <= DONE; + elsif( (sdone = '1') and (action_in = '1') and (phase = '0') ) then + NEXT_STATE <= INC; + else + NEXT_STATE <= GSTOP; + dostart_x <= '1'; + end if; + when INC => NEXT_STATE <= LOADA; + load_a_x <= '1'; + when FAILED => if( sdone = '1' ) then + NEXT_STATE <= DONE; + i2c_done_x <= '1'; + running_x <= '0'; + else + NEXT_STATE <= FAILED; + dostart_x <= '1'; + end if; + when DONE => if( i2c_go_in = '1' ) then + NEXT_STATE <= DONE; + i2c_done_x <= '1'; + running_x <= '0'; + else + NEXT_STATE <= SLEEP; + end if; + -- Just in case... + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +-- Output decoding +DECODE: process(CURRENT_STATE) +begin + case CURRENT_STATE is + when SLEEP => bsm <= b"00000"; -- 00 + when CLRERR => bsm <= b"01100"; -- 0c + when LOADA => bsm <= b"00001"; -- 01 + when GSTART => bsm <= b"00010"; -- 02 + when SENDA => bsm <= b"00011"; -- 03 + when LOADC => bsm <= b"00100"; -- 04 + when SENDC => bsm <= b"00101"; -- 05 + when LOADD => bsm <= b"00110"; -- 06 + when SENDD => bsm <= b"00111"; -- 07 + when GSTOP => bsm <= b"01000"; -- 08 + when INC => bsm <= b"01001"; -- 09 + when FAILED => bsm <= b"01010"; -- 0a + when DONE => bsm <= b"01011"; -- 0b + when E_START => bsm <= b"10000"; -- 10 + when E_RSTART => bsm <= b"10001"; -- 11 + when E_ADDR => bsm <= b"10010"; -- 12 + when E_RADDR => bsm <= b"10011"; -- 13 + when E_CMD => bsm <= b"10100"; -- 14 + when E_WD => bsm <= b"10101"; -- 15 + when others => bsm <= b"11111"; -- 1f + end case; +end process DECODE; + +-- We need to load different data sets +--LOAD_DATA_PROC: process( clk_in, reset_in, CURRENT_STATE, action_in, phase) +LOAD_DATA_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + i2c_byte <= (others => '1'); + elsif( (CURRENT_STATE = LOADA) and (phase = '0') ) then + i2c_byte <= i2c_adr_in(6 downto 0) & '0' & '1'; -- send write address, receive ACK + elsif( (CURRENT_STATE = LOADA) and (phase = '1') ) then + i2c_byte <= i2c_adr_in(6 downto 0) & '1' & '1'; -- send read address, receive ACK + elsif( (CURRENT_STATE = LOADC) and (action_in = '0') ) then + i2c_byte <= i2c_cmd_in(7 downto 1) & '0' & '1'; -- send command byte (WRITE), receive ACK + elsif( (CURRENT_STATE = LOADC) and (action_in = '1') ) then + i2c_byte <= i2c_cmd_in(7 downto 1) & '1' & '1'; -- send command byte (READ), receive ACK + elsif( (CURRENT_STATE = LOADD) and (action_in = '0') ) then + i2c_byte <= i2c_dw_in & '1'; -- send data byte, receive ACK + elsif( (CURRENT_STATE = LOADD) and (action_in = '1') ) then + i2c_byte <= x"ff" & '1'; -- send 0xff byte, send NACK + end if; + end if; +end process LOAD_DATA_PROC; + +-- The SendByte module +THE_I2C_SENDB: I2C_SENDB +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + DOBYTE_IN => dobyte, + I2C_SPEED_IN => i2c_speed, + I2C_BYTE_IN => i2c_byte, + I2C_BACK_OUT => i2c_dr, + SDA_IN => sda_in, + R_SDA_OUT => r_sda_sb, + S_SDA_OUT => s_sda_sb, +-- SCL_IN => scl_in, + R_SCL_OUT => r_scl_sb, + S_SCL_OUT => s_scl_sb, + BDONE_OUT => bdone, + BOK_OUT => bok, + BSM_OUT => open + ); + +-- The GenStart module +THE_I2C_GSTART: I2C_GSTART +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => start, + DOSTART_IN => dostart, + I2C_SPEED_IN => i2c_speed, + SDONE_OUT => sdone, + SOK_OUT => sok, + SDA_IN => sda_in, + SCL_IN => scl_in, + R_SCL_OUT => r_scl_gs, + S_SCL_OUT => s_scl_gs, + R_SDA_OUT => r_sda_gs, + S_SDA_OUT => s_sda_gs, + BSM_OUT => gs_debug --open + ); + +r_scl <= r_scl_gs or r_scl_sb; +s_scl <= s_scl_gs or s_scl_sb; +r_sda <= r_sda_gs or r_sda_sb; +s_sda <= s_sda_gs or s_sda_sb; + +-- Output flipflops for SCL and SDA lines +THE_SCL_SDA_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + scl_out <= '1'; + sda_out <= '1'; + elsif( (r_scl = '1') and (s_scl = '0') ) then + scl_out <= '0'; + elsif( (r_scl = '0') and (s_scl = '1') ) then + scl_out <= '1'; + elsif( (r_sda = '1') and (s_sda = '0') ) then + sda_out <= '0'; + elsif( (r_sda = '0') and (s_sda = '1') ) then + sda_out <= '1'; + end if; + end if; +end process THE_SCL_SDA_PROC; + +-- Error bits +THE_ERR_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + e_sf <= '0'; + e_anak <= '0'; + e_cnak <= '0'; + e_dnak <= '0'; + e_rsf <= '0'; + e_ranak <= '0'; + elsif( CURRENT_STATE = CLRERR ) then + e_sf <= '0'; + e_anak <= '0'; + e_cnak <= '0'; + e_dnak <= '0'; + e_rsf <= '0'; + e_ranak <= '0'; + elsif( CURRENT_STATE = E_START ) then + e_sf <= '1'; + elsif( CURRENT_STATE = E_RSTART ) then + e_rsf <= '1'; + elsif( CURRENT_STATE = E_ADDR ) then + e_anak <= '1'; + elsif( CURRENT_STATE = E_RADDR ) then + e_ranak <= '1'; + elsif( CURRENT_STATE = E_CMD ) then + e_cnak <= '1'; + elsif( CURRENT_STATE = E_WD ) then + e_dnak <= '1'; + end if; + end if; +end process THE_ERR_REG_PROC; + +status_out(7) <= running; +status_out(6) <= i2c_done; +status_out(5) <= e_ranak; +status_out(4) <= e_rsf; +status_out(3) <= e_dnak; +status_out(2) <= e_cnak; +status_out(1) <= e_anak; +status_out(0) <= e_sf; + +-- Outputs +i2c_dr_out <= i2c_dr(8 downto 1); +i2c_busy_out <= running; + +-- Debug stuff +stat(31 downto 28) <= (others => '0'); +stat(27) <= s_sda; +stat(26) <= r_sda; +stat(25) <= s_scl; +stat(24) <= r_scl; +stat(23) <= s_sda_sb; +stat(22) <= r_sda_sb; +stat(21) <= s_scl_sb; +stat(20) <= r_scl_sb; +stat(19) <= s_sda_gs; +stat(18) <= r_sda_gs; +stat(17) <= s_scl_gs; +stat(16) <= r_scl_gs; +stat(15 downto 12) <= gs_debug; +stat(11) <= bok; +stat(10) <= bdone; +stat(9) <= dobyte; +stat(8) <= sok; +stat(7) <= dobyte; +stat(6) <= s_sda_sb; +stat(5) <= r_sda_sb; +stat(4 downto 0) <= bsm; + + +end Behavioral; diff --git a/src/input_bram.lpc b/src/input_bram.lpc new file mode 100644 index 0000000..3c20b62 --- /dev/null +++ b/src/input_bram.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP +CoreRevision=6.1 +ModuleName=input_bram +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/14/2009 +Time=12:58:01 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +RAddress=2048 +RData=18 +WAddress=2048 +WData=18 +enByte=0 +ByteSize=9 +adPipeline=0 +inPipeline=0 +outPipeline=1 +MOR=0 +InData=Registered +AdControl=Registered +MemFile= +MemFormat=hex +Reset=Sync +GSR=Enabled +Pad=0 +EnECC=0 +Optimization=Speed +EnSleep=ENABLED +Pipeline=0 diff --git a/src/input_bram.srp b/src/input_bram.srp new file mode 100644 index 0000000..22a45ab --- /dev/null +++ b/src/input_bram.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 12:58:01 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + Circuit name : input_bram + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[17:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : input_bram.vhd + VHDL template : input_bram_tmpl.vhd + VHDL testbench : tb_input_bram_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : input_bram.srp + Element Usage : + DP16KB : 2 + Estimated Resource Usage: + EBR : 2 diff --git a/src/input_bram.vhd b/src/input_bram.vhd new file mode 100644 index 0000000..050f155 --- /dev/null +++ b/src/input_bram.vhd @@ -0,0 +1,249 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 6.1 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 10 -rp 0011 -rdata_width 18 -data_width 18 -num_rows 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + +-- Mon Sep 14 12:58:01 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity input_bram is + port ( + WrAddress: in std_logic_vector(10 downto 0); + RdAddress: in std_logic_vector(10 downto 0); + Data: in std_logic_vector(17 downto 0); + WE: in std_logic; + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + WrClock: in std_logic; + WrClockEn: in std_logic; + Q: out std_logic_vector(17 downto 0)); +end input_bram; + +architecture Structure of input_bram is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute GSR : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute MEM_LPC_FILE of input_bram_0_0_1 : label is "input_bram.lpc"; + attribute MEM_INIT_FILE of input_bram_0_0_1 : label is ""; + attribute CSDECODE_B of input_bram_0_0_1 : label is "0b000"; + attribute CSDECODE_A of input_bram_0_0_1 : label is "0b000"; + attribute WRITEMODE_B of input_bram_0_0_1 : label is "NORMAL"; + attribute WRITEMODE_A of input_bram_0_0_1 : label is "NORMAL"; + attribute GSR of input_bram_0_0_1 : label is "DISABLED"; + attribute RESETMODE of input_bram_0_0_1 : label is "SYNC"; + attribute REGMODE_B of input_bram_0_0_1 : label is "OUTREG"; + attribute REGMODE_A of input_bram_0_0_1 : label is "OUTREG"; + attribute DATA_WIDTH_B of input_bram_0_0_1 : label is "9"; + attribute DATA_WIDTH_A of input_bram_0_0_1 : label is "9"; + attribute MEM_LPC_FILE of input_bram_0_1_0 : label is "input_bram.lpc"; + attribute MEM_INIT_FILE of input_bram_0_1_0 : label is ""; + attribute CSDECODE_B of input_bram_0_1_0 : label is "0b000"; + attribute CSDECODE_A of input_bram_0_1_0 : label is "0b000"; + attribute WRITEMODE_B of input_bram_0_1_0 : label is "NORMAL"; + attribute WRITEMODE_A of input_bram_0_1_0 : label is "NORMAL"; + attribute GSR of input_bram_0_1_0 : label is "DISABLED"; + attribute RESETMODE of input_bram_0_1_0 : label is "SYNC"; + attribute REGMODE_B of input_bram_0_1_0 : label is "OUTREG"; + attribute REGMODE_A of input_bram_0_1_0 : label is "OUTREG"; + attribute DATA_WIDTH_B of input_bram_0_1_0 : label is "9"; + attribute DATA_WIDTH_A of input_bram_0_1_0 : label is "9"; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + input_bram_0_0_1: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>WrAddress(0), + ADA4=>WrAddress(1), ADA5=>WrAddress(2), ADA6=>WrAddress(3), + ADA7=>WrAddress(4), ADA8=>WrAddress(5), ADA9=>WrAddress(6), + ADA10=>WrAddress(7), ADA11=>WrAddress(8), + ADA12=>WrAddress(9), ADA13=>WrAddress(10), CEA=>WrClockEn, + CLKA=>WrClock, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>RdAddress(0), + ADB4=>RdAddress(1), ADB5=>RdAddress(2), ADB6=>RdAddress(3), + ADB7=>RdAddress(4), ADB8=>RdAddress(5), ADB9=>RdAddress(6), + ADB10=>RdAddress(7), ADB11=>RdAddress(8), + ADB12=>RdAddress(9), ADB13=>RdAddress(10), CEB=>RdClockEn, + CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), + DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + input_bram_0_1_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>WrAddress(0), ADA4=>WrAddress(1), ADA5=>WrAddress(2), + ADA6=>WrAddress(3), ADA7=>WrAddress(4), ADA8=>WrAddress(5), + ADA9=>WrAddress(6), ADA10=>WrAddress(7), ADA11=>WrAddress(8), + ADA12=>WrAddress(9), ADA13=>WrAddress(10), CEA=>WrClockEn, + CLKA=>WrClock, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>RdAddress(0), + ADB4=>RdAddress(1), ADB5=>RdAddress(2), ADB6=>RdAddress(3), + ADB7=>RdAddress(4), ADB8=>RdAddress(5), ADB9=>RdAddress(6), + ADB10=>RdAddress(7), ADB11=>RdAddress(8), + ADB12=>RdAddress(9), ADB13=>RdAddress(10), CEB=>RdClockEn, + CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(9), + DOB1=>Q(10), DOB2=>Q(11), DOB3=>Q(12), DOB4=>Q(13), + DOB5=>Q(14), DOB6=>Q(15), DOB7=>Q(16), DOB8=>Q(17), + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of input_bram is + for Structure + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/input_bram_generate.log b/src/input_bram_generate.log new file mode 100644 index 0000000..c01e233 --- /dev/null +++ b/src/input_bram_generate.log @@ -0,0 +1,44 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 12:58:01 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + Circuit name : input_bram + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[17:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : input_bram.vhd + VHDL template : input_bram_tmpl.vhd + VHDL testbench : tb_input_bram_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : input_bram.srp + Estimated Resource Usage: + EBR : 2 + +END SCUBA Module Synthesis + +File: ..\src\input_bram.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/input_bram_tmpl.vhd b/src/input_bram_tmpl.vhd new file mode 100644 index 0000000..7b37858 --- /dev/null +++ b/src/input_bram_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 6.1 +-- Mon Sep 14 12:58:01 2009 + +-- parameterized module component declaration +component input_bram + port (WrAddress: in std_logic_vector(10 downto 0); + RdAddress: in std_logic_vector(10 downto 0); + Data: in std_logic_vector(17 downto 0); WE: in std_logic; + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; WrClock: in std_logic; + WrClockEn: in std_logic; Q: out std_logic_vector(17 downto 0)); +end component; + +-- parameterized module component instance +__ : input_bram + port map (WrAddress(10 downto 0)=>__, RdAddress(10 downto 0)=>__, + Data(17 downto 0)=>__, WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, + WrClock=>__, WrClockEn=>__, Q(17 downto 0)=>__); diff --git a/src/ipu_fifo_stage.vhd b/src/ipu_fifo_stage.vhd new file mode 100644 index 0000000..1ef4bd4 --- /dev/null +++ b/src/ipu_fifo_stage.vhd @@ -0,0 +1,562 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +-- Missing: FIFO buffer handling, full / empty checks + +entity ipu_fifo_stage is + port( CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control signals + SECTOR_IN : in std_logic_vector(2 downto 0); + MODULE_IN : in std_logic_vector(2 downto 0); + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter + -- DHDR buffer input + DHDR_DATA_IN : in std_logic_vector(31 downto 0); + DHDR_LENGTH_IN : in std_logic_vector(15 downto 0); + DHDR_STORE_IN : in std_logic; + DHDR_BUF_FULL_OUT : out std_logic; + -- processed data input + FIFO_START_IN : in std_logic; + FIFO_0_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_1_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_2_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_3_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_4_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_5_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_6_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_7_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_8_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_9_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_10_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_11_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_12_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_13_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_14_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_15_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_WE_IN : in std_logic_vector(15 downto 0); + FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(63 downto 0) + ); +end; + +architecture behavioral of ipu_fifo_stage is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of behavioral : architecture is "IPU_FIFO_STAGE_group"; + + -- state machine definitions + type STATES is (SLEEP,RDLF,GETFD,DELH,WHDR,GETD,WAITD,WAITDL,DEL0,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- signals + signal debug : std_logic_vector(63 downto 0); + signal bsm_x : std_logic_vector(7 downto 0); + signal next_trgnum_match : std_logic; + signal trgnum_match : std_logic; + + signal dhdr_fifo_in : std_logic_vector(47 downto 0); + signal dhdr_fifo_out : std_logic_vector(47 downto 0); + signal dhdr_avail : std_logic; + signal next_todo_list : std_logic_vector(15 downto 0); + signal todo_list : std_logic_vector(15 downto 0); + signal next_fifo_sel : std_logic_vector(4 downto 0); + signal fifo_sel : std_logic_vector(4 downto 0); + signal next_sel_fifo : std_logic_vector(15 downto 0); + signal sel_fifo : std_logic_vector(15 downto 0); + + signal comb_rd_dfifo : std_logic_vector(15 downto 0); + signal comb_st_data : std_logic_vector(15 downto 0); + signal comb_ack_todo : std_logic; + + signal ipu_out_data : std_logic_vector(31 downto 0); + + -- state machine signals + signal next_rd_lfifo : std_logic; + signal rd_lfifo : std_logic; -- read current LENGTH_FIFO information (as well as LockAtMe bit) + signal next_dataready : std_logic; + signal dataready : std_logic; -- data word is available + signal next_set_hdr : std_logic; + signal set_hdr : std_logic; -- store DHDR in output register + signal next_set_data : std_logic; + signal set_data : std_logic; -- store DATA from current DATA FIFO in output register + signal next_ld_todo : std_logic; + signal ld_todo : std_logic; -- load initial TODO list + signal next_ack_todo : std_logic; + signal ack_todo : std_logic; -- remove current entry from TODO list + signal next_finished : std_logic; + signal finished : std_logic; -- readout is finished + + -- generate needs arrays... + type fifo_data_t is array (0 to 15) of std_logic_vector(26 downto 0); + signal fifo_in_data : fifo_data_t; + signal fifo_out_data : fifo_data_t; + type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0); + signal fifo_in_count : fifo_count_t; + type fifo_todo_t is array (0 to 15) of std_logic_vector(9 downto 0); + signal fifo_todo : fifo_todo_t; + type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0); + signal fifo_ldata : fifo_ldata_t; + type fifo_wcnt_t is array (0 to 15) of std_logic_vector(11 downto 0); + signal fifo_wcnt : fifo_wcnt_t; + signal fifo_data_free : fifo_wcnt_t; + + + signal next_fifo_done : std_logic_vector(15 downto 0); + signal fifo_done : std_logic_vector(15 downto 0); + signal next_fifo_last : std_logic; + signal fifo_last : std_logic; + + signal my_trg_number : std_logic_vector(31 downto 0); -- just for checking! + + signal old_apv_num : std_logic_vector(3 downto 0); + signal new_apv_num : std_logic_vector(3 downto 0); + + signal cyclectr : std_logic_vector(15 downto 0); -- cycle counter + + signal dhdr_buf_full : std_logic; + +begin +--------------------------------------------------------------------------- +-- Statemachine +--------------------------------------------------------------------------- + +-- state registers +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + rd_lfifo <= '0'; + dataready <= '0'; + set_hdr <= '0'; + set_data <= '0'; + ld_todo <= '0'; + ack_todo <= '0'; + finished <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + rd_lfifo <= next_rd_lfifo; + dataready <= next_dataready; + set_hdr <= next_set_hdr; + set_data <= next_set_data; + ld_todo <= next_ld_todo; + ack_todo <= next_ack_todo; + finished <= next_finished; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, dhdr_avail, ipu_start_readout_in, ipu_read_in, fifo_last, fifo_sel(4) ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + next_rd_lfifo <= '0'; + next_dataready <= '0'; + next_set_hdr <= '0'; + next_set_data <= '0'; + next_ld_todo <= '0'; + next_ack_todo <= '0'; + next_finished <= '0'; + case CURRENT_STATE is + when SLEEP => if( (dhdr_avail = '1') and (ipu_start_readout_in = '1') ) then + NEXT_STATE <= RDLF; + next_rd_lfifo <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RDLF => NEXT_STATE <= GETFD; + next_set_hdr <= '1'; + next_ld_todo <= '1'; + when GETFD => NEXT_STATE <= DELH; + when DELH => NEXT_STATE <= WHDR; + next_dataready <= '1'; + when WHDR => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then + NEXT_STATE <= GETD; -- there are datawords to send + next_set_data <= '1'; + next_ack_todo <= '1'; + elsif( (ipu_read_in = '1') and (fifo_sel(4) = '1') ) then + NEXT_STATE <= DONE; -- only DHDR, no data words + next_finished <= '1'; + else + NEXT_STATE <= WHDR; + next_dataready <= '1'; + end if; + when GETD => if( fifo_last = '1' ) then + NEXT_STATE <= DEL0; + else + NEXT_STATE <= WAITD; + next_dataready <= '1'; + end if; + when WAITD => if( ipu_read_in = '1' ) then + NEXT_STATE <= GETD; + next_set_data <= '1'; + else + NEXT_STATE <= WAITD; + next_dataready <= '1'; + end if; + when DEL0 => NEXT_STATE <= WAITDL; + next_dataready <= '1'; + when WAITDL => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then + NEXT_STATE <= GETD; + next_set_data <= '1'; + next_ack_todo <= '1'; + elsif( (ipu_read_in = '1') and (fifo_sel(4) = '1') ) then + NEXT_STATE <= DONE; + next_finished <= '1'; + else + NEXT_STATE <= WAITDL; + next_dataready <= '1'; + end if; + when DONE => if( ipu_start_readout_in = '0' ) then + NEXT_STATE <= SLEEP; + else + NEXT_STATE <= DONE; + end if; + + when others => NEXT_STATE <= SLEEP; + end case; +end process STATE_TRANSFORM; + +-- Handshaking to IPU data channel +ipu_dataready_out <= dataready; +ipu_readout_finished_out <= finished; + +-- length information can be simply copied +ipu_length_out <= dhdr_fifo_out(47 downto 32); + +-- IPU error pattern: [24] => trigger tag mismatch +ipu_error_pattern_out(31 downto 25) <= (others => '0'); +ipu_error_pattern_out(24) <= not trgnum_match; +ipu_error_pattern_out(23 downto 0) <= (others => '0'); + +-- state decoding (ONLY FOR DEBUGGING!) +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SLEEP => bsm_x <= x"00"; + when RDLF => bsm_x <= x"01"; + when GETFD => bsm_x <= x"02"; + when DELH => bsm_x <= x"03"; + when WHDR => bsm_x <= x"04"; + when GETD => bsm_x <= x"05"; + when WAITD => bsm_x <= x"06"; + when WAITDL => bsm_x <= x"07"; + when DEL0 => bsm_x <= x"08"; + when DONE => bsm_x <= x"09"; + when others => bsm_x <= x"ff"; + end case; +end process STATE_DECODE; + +--------------------------------------------------------------------------- +-- Aliasing the data streams +--------------------------------------------------------------------------- +fifo_in_data(0) <= fifo_0_data_in(26 downto 0); fifo_in_count(0) <= fifo_0_data_in(37 downto 27); +fifo_in_data(1) <= fifo_1_data_in(26 downto 0); fifo_in_count(1) <= fifo_1_data_in(37 downto 27); +fifo_in_data(2) <= fifo_2_data_in(26 downto 0); fifo_in_count(2) <= fifo_2_data_in(37 downto 27); +fifo_in_data(3) <= fifo_3_data_in(26 downto 0); fifo_in_count(3) <= fifo_3_data_in(37 downto 27); +fifo_in_data(4) <= fifo_4_data_in(26 downto 0); fifo_in_count(4) <= fifo_4_data_in(37 downto 27); +fifo_in_data(5) <= fifo_5_data_in(26 downto 0); fifo_in_count(5) <= fifo_5_data_in(37 downto 27); +fifo_in_data(6) <= fifo_6_data_in(26 downto 0); fifo_in_count(6) <= fifo_6_data_in(37 downto 27); +fifo_in_data(7) <= fifo_7_data_in(26 downto 0); fifo_in_count(7) <= fifo_7_data_in(37 downto 27); +fifo_in_data(8) <= fifo_8_data_in(26 downto 0); fifo_in_count(8) <= fifo_8_data_in(37 downto 27); +fifo_in_data(9) <= fifo_9_data_in(26 downto 0); fifo_in_count(9) <= fifo_9_data_in(37 downto 27); +fifo_in_data(10) <= fifo_10_data_in(26 downto 0); fifo_in_count(10) <= fifo_10_data_in(37 downto 27); +fifo_in_data(11) <= fifo_11_data_in(26 downto 0); fifo_in_count(11) <= fifo_11_data_in(37 downto 27); +fifo_in_data(12) <= fifo_12_data_in(26 downto 0); fifo_in_count(12) <= fifo_12_data_in(37 downto 27); +fifo_in_data(13) <= fifo_13_data_in(26 downto 0); fifo_in_count(13) <= fifo_13_data_in(37 downto 27); +fifo_in_data(14) <= fifo_14_data_in(26 downto 0); fifo_in_count(14) <= fifo_14_data_in(37 downto 27); +fifo_in_data(15) <= fifo_15_data_in(26 downto 0); fifo_in_count(15) <= fifo_15_data_in(37 downto 27); + +--------------------------------------------------------------------------- +-- DATA and LENGTH FIFO for the APV data streams +--------------------------------------------------------------------------- + +GEN_FIFO: for i in 0 to 15 generate + THE_DFIFO: fifo_2kx27 + port map( DATA => fifo_in_data(i), + CLOCK => clk_in, + WREN => fifo_we_in(i), + RDEN => comb_rd_dfifo(i), -- BUG + RESET => reset_in, + Q => fifo_out_data(i), -- BUG + WCNT => fifo_wcnt(i), -- BUG + EMPTY => open, -- BUG + FULL => open -- BUG + ); + + -- Combinatorial read pulse for FIFOs + comb_rd_dfifo(i) <= (not fifo_done(i) and sel_fifo(i) and ipu_read_in and dataready) or (ld_todo and fifo_ldata(i)(10)); + + -- Combinatorial store pulse for data (last data word need to be transfered also!) + comb_st_data(i) <= (sel_fifo(i) and ipu_read_in and dataready); + -- BUGBUGBUG: one clock cycle too late when changing FIFOs.... + + -- getting the number of free entries in the data fifo by subtracting [size] - [used entries] + THE_SUBTRACTOR: suber_12bit + port map( DATAA => x"800", + DATAB => fifo_wcnt(i), + CLOCK => clk_in, + RESET => reset_in, + CLOCKEN => '1', + RESULT => fifo_data_free(i) + ); + + -- length fifo - stores the number of words to fetch from dfifo + THE_LFIFO: fifo_16x11 + port map( DATA => fifo_in_count(i), + CLOCK => clk_in, + WREN => fifo_done_in, + RDEN => rd_lfifo, + RESET => reset_in, + Q => fifo_ldata(i), + WCNT => open, -- BUG + EMPTY => open, -- BUG + FULL => open -- BUG + ); + next_todo_list(i) <= fifo_ldata(i)(10); + + THE_TODO_CTR_PROC: process( clk_in ) + begin + if( rising_edge(clk_in) ) then + if( (reset_in = '1') or (rd_lfifo = '1') ) then + fifo_todo(i) <= (others => '0'); + elsif( ld_todo = '1' ) then + fifo_todo(i) <= fifo_ldata(i)(9 downto 0); + elsif( comb_rd_dfifo(i) = '1' ) then + fifo_todo(i) <= fifo_todo(i) - 1; + end if; + end if; + end process THE_TODO_CTR_PROC; + + next_fifo_done(i) <= '1' when ( fifo_todo(i) = b"00_0000_0000" ) else '0'; + +end generate GEN_FIFO; + +comb_ack_todo <= fifo_last and set_data; + + +--------------------------------------------------------------------------- +-- DHDR buffer - delivers all information +--------------------------------------------------------------------------- +dhdr_fifo_in <= dhdr_length_in & dhdr_data_in; + +THE_DHDR_BUF: dhdr_buf +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + DHDR_DATA_IN => dhdr_fifo_in, + DHDR_WE_IN => dhdr_store_in, + DHDR_DONE_IN => finished, + DHDR_DATA_OUT => dhdr_fifo_out, + DHDR_AVAILABLE_OUT => dhdr_avail, + BUF_FULL_OUT => dhdr_buf_full, + BUF_LEVEL_OUT => open, + DEBUG_OUT => open + ); + +-- compare incoming trigger number with stored DHDR information +next_trgnum_match <= '1' when ( ipu_number_in = dhdr_fifo_out(15 downto 0) ) else '0'; + +THE_TRGNUM_MATCH_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + trgnum_match <= '0'; + my_trg_number <= (others => '0'); + elsif( set_hdr = '1' ) then + trgnum_match <= next_trgnum_match; + my_trg_number <= ipu_number_in & dhdr_fifo_out(15 downto 0); + end if; + end if; +end process THE_TRGNUM_MATCH_PROC; + + +--------------------------------------------------------------------------- +-- priority encoding is used to select the next buffer for readout +--------------------------------------------------------------------------- +--THE_PRI_ENCODER_PROC: process( todo_list, fifo_sel, fifo_done ) +THE_PRI_ENCODER_PROC: process( todo_list, fifo_done ) +begin + if ( todo_list(15 downto 15) = "1" ) then + next_fifo_sel <= "01111"; next_sel_fifo <= b"1000_0000_0000_0000"; next_fifo_last <= fifo_done(15); + elsif( todo_list(15 downto 14) = "01" ) then + next_fifo_sel <= "01110"; next_sel_fifo <= b"0100_0000_0000_0000"; next_fifo_last <= fifo_done(14); + elsif( todo_list(15 downto 13) = "001" ) then + next_fifo_sel <= "01101"; next_sel_fifo <= b"0010_0000_0000_0000"; next_fifo_last <= fifo_done(13); + elsif( todo_list(15 downto 12) = "0001" ) then + next_fifo_sel <= "01100"; next_sel_fifo <= b"0001_0000_0000_0000"; next_fifo_last <= fifo_done(12); + elsif( todo_list(15 downto 11) = "00001" ) then + next_fifo_sel <= "01011"; next_sel_fifo <= b"0000_1000_0000_0000"; next_fifo_last <= fifo_done(11); + elsif( todo_list(15 downto 10) = "000001" ) then + next_fifo_sel <= "01010"; next_sel_fifo <= b"0000_0100_0000_0000"; next_fifo_last <= fifo_done(10); + elsif( todo_list(15 downto 9) = "0000001" ) then + next_fifo_sel <= "01001"; next_sel_fifo <= b"0000_0010_0000_0000"; next_fifo_last <= fifo_done(9); + elsif( todo_list(15 downto 8) = "00000001" ) then + next_fifo_sel <= "01000"; next_sel_fifo <= b"0000_0001_0000_0000"; next_fifo_last <= fifo_done(8); + elsif( todo_list(15 downto 7) = "000000001" ) then + next_fifo_sel <= "00111"; next_sel_fifo <= b"0000_0000_1000_0000"; next_fifo_last <= fifo_done(7); + elsif( todo_list(15 downto 6) = "0000000001" ) then + next_fifo_sel <= "00110"; next_sel_fifo <= b"0000_0000_0100_0000"; next_fifo_last <= fifo_done(6); + elsif( todo_list(15 downto 5) = "00000000001" ) then + next_fifo_sel <= "00101"; next_sel_fifo <= b"0000_0000_0010_0000"; next_fifo_last <= fifo_done(5); + elsif( todo_list(15 downto 4) = "000000000001" ) then + next_fifo_sel <= "00100"; next_sel_fifo <= b"0000_0000_0001_0000"; next_fifo_last <= fifo_done(4); + elsif( todo_list(15 downto 3) = "0000000000001" ) then + next_fifo_sel <= "00011"; next_sel_fifo <= b"0000_0000_0000_1000"; next_fifo_last <= fifo_done(3); + elsif( todo_list(15 downto 2) = "00000000000001" ) then + next_fifo_sel <= "00010"; next_sel_fifo <= b"0000_0000_0000_0100"; next_fifo_last <= fifo_done(2); + elsif( todo_list(15 downto 1) = "000000000000001" ) then + next_fifo_sel <= "00001"; next_sel_fifo <= b"0000_0000_0000_0010"; next_fifo_last <= fifo_done(1); + elsif( todo_list(15 downto 0) = "0000000000000001" ) then + next_fifo_sel <= "00000"; next_sel_fifo <= b"0000_0000_0000_0001"; next_fifo_last <= fifo_done(0); + else + next_fifo_sel <= "10000"; next_sel_fifo <= b"0000_0000_0000_0000"; next_fifo_last <= '0'; + end if; +end process THE_PRI_ENCODER_PROC; + +-- We need to clear single bits during readout here!!! +THE_TODO_LIST_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + todo_list <= (others => '0'); + elsif( ld_todo = '1' ) then + todo_list <= next_todo_list; -- store initial todo list + elsif( comb_ack_todo = '1' ) then + todo_list <= todo_list and not sel_fifo; -- does this work?!? + end if; + end if; +end process THE_TODO_LIST_PROC; + + + +--------------------------------------------------------------------------- +-- synchronizing process +--------------------------------------------------------------------------- +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + fifo_sel <= next_fifo_sel; + sel_fifo <= next_sel_fifo; + fifo_done <= next_fifo_done; + fifo_last <= next_fifo_last; + end if; +end process THE_SYNC_PROC; + + +--------------------------------------------------------------------------- +-- backplane wise APV mapping +--------------------------------------------------------------------------- +old_apv_num <= fifo_sel(3 downto 0); + +THE_ADC_APV_MAP_MEM: adc_apv_map_mem +port map( ADDRESS(6 downto 4) => module_in(2 downto 0), + ADDRESS(3 downto 0) => old_apv_num, + Q => new_apv_num + ); + +--------------------------------------------------------------------------- +-- Data multiplexer +--------------------------------------------------------------------------- +THE_DATA_MUX_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( set_hdr = '1' ) then + ipu_out_data <= dhdr_fifo_out(31 downto 0); + elsif( comb_st_data(0) = '1' ) then + ipu_out_data <= fifo_out_data(0)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(0)(20 downto 0); + elsif( comb_st_data(1) = '1' ) then + ipu_out_data <= fifo_out_data(1)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(1)(20 downto 0); + elsif( comb_st_data(2) = '1' ) then + ipu_out_data <= fifo_out_data(2)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(2)(20 downto 0); + elsif( comb_st_data(3) = '1' ) then + ipu_out_data <= fifo_out_data(3)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(3)(20 downto 0); + elsif( comb_st_data(4) = '1' ) then + ipu_out_data <= fifo_out_data(4)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(4)(20 downto 0); + elsif( comb_st_data(5) = '1' ) then + ipu_out_data <= fifo_out_data(5)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(5)(20 downto 0); + elsif( comb_st_data(6) = '1' ) then + ipu_out_data <= fifo_out_data(6)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(6)(20 downto 0); + elsif( comb_st_data(7) = '1' ) then + ipu_out_data <= fifo_out_data(7)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(7)(20 downto 0); + elsif( comb_st_data(8) = '1' ) then + ipu_out_data <= fifo_out_data(8)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(8)(20 downto 0); + elsif( comb_st_data(9) = '1' ) then + ipu_out_data <= fifo_out_data(9)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(9)(20 downto 0); + elsif( comb_st_data(10) = '1' ) then + ipu_out_data <= fifo_out_data(10)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(10)(20 downto 0); + elsif( comb_st_data(11) = '1' ) then + ipu_out_data <= fifo_out_data(11)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(11)(20 downto 0); + elsif( comb_st_data(12) = '1' ) then + ipu_out_data <= fifo_out_data(12)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(12)(20 downto 0); + elsif( comb_st_data(13) = '1' ) then + ipu_out_data <= fifo_out_data(13)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(13)(20 downto 0); + elsif( comb_st_data(14) = '1' ) then + ipu_out_data <= fifo_out_data(14)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(14)(20 downto 0); + elsif( comb_st_data(15) = '1' ) then + ipu_out_data <= fifo_out_data(15)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(15)(20 downto 0); + end if; + end if; +end process THE_DATA_MUX_PROC; + + +--------------------------------------------------------------------------- +-- IPU cycle counter... just to be sure +--------------------------------------------------------------------------- +THE_CYCLE_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + cyclectr <= (others => '0'); + elsif( finished = '1' ) then + cyclectr <= cyclectr + 1; + end if; + end if; +end process THE_CYCLE_COUNTER_PROC; + +--------------------------------------------------------------------------- +-- debug information +--------------------------------------------------------------------------- +debug(63 downto 28) <= (others => '0'); +debug(27 downto 16) <= fifo_data_free(13); +debug(15 downto 12) <= (others => '0'); +debug(11 downto 0) <= fifo_wcnt(13); + + +--------------------------------------------------------------------------- +-- Output signals +--------------------------------------------------------------------------- +ipu_data_out <= ipu_out_data; +lvl2_counter_out <= cyclectr; +dhdr_buf_full_out <= dhdr_buf_full; + +--------------------------------------------------------------------------- +-- DEBUG signals +--------------------------------------------------------------------------- +dbg_bsm_out <= bsm_x; +dbg_out <= debug; + +end behavioral; + + + + + diff --git a/src/logic_analyzer.vhd b/src/logic_analyzer.vhd new file mode 100644 index 0000000..245f894 --- /dev/null +++ b/src/logic_analyzer.vhd @@ -0,0 +1,225 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +entity logic_analyzer is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- control signals + ARM_IN : in std_logic; -- arm the machine + TRG_IN : in std_logic; -- trigger the data acquisition + MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); + -- status signals + SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses + SM_CE_OUT : out std_logic; + SM_WE_OUT : out std_logic; -- write enable for sample RAM + CLEAR_OUT : out std_logic; -- sample memory is being cleared + RUN_OUT : out std_logic; -- ready for trigger + SAMPLE_OUT : out std_logic; -- data acquisition running + READY_OUT : out std_logic; -- data acquisition is finished + LAST_OUT : out std_logic; -- last data word of sampling + -- Status lines + BSM_OUT : out std_logic_vector(3 downto 0); + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of logic_analyzer is + +-- Signals + + type STATES is (SM_SLEEP,SM_CLEAR,SM_RUN,SM_SAMPLE,SM_READY); + signal CURRENT_STATE, NEXT_STATE: STATES; + + signal sm_addr : std_logic_vector(9 downto 0); + signal sm_counter : std_logic_vector(9 downto 0); + + signal sm_we_x : std_logic; + signal sm_we : std_logic; + signal sm_ce_x : std_logic; + signal sm_ce : std_logic; + signal sm_rst_x : std_logic; + signal sm_rst : std_logic; + signal sm_acq_x : std_logic; + signal sm_acq : std_logic; + signal sm_done_x : std_logic; + signal sm_done : std_logic; + + signal sm_clear_done_x : std_logic; + signal sm_clear_done : std_logic; + signal sm_sample_done_x : std_logic; + signal sm_sample_done : std_logic; + + signal data_available : std_logic; + +-- signal debug : std_logic_vector(31 downto 0); + +begin + +-- Fake +stat(31 downto 17) <= (others => '0'); +stat(16) <= sm_sample_done; +stat(15 downto 10) <= (others => '0'); +stat(9 downto 0) <= sm_counter; + +-- address counter +THE_ADDR_CTR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (reset_in = '1') or (sm_rst = '1') ) then + sm_addr <= (others => '0'); + elsif( sm_ce = '1' ) then + sm_addr <= sm_addr + 1; + end if; + end if; +end process THE_ADDR_CTR_PROC; + +sm_clear_done_x <= '1' when (sm_addr = b"11_1111_1110") else '0'; + +THE_SAMPLE_CTR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (reset_in = '1') or (sm_rst = '1') ) then + sm_counter <= (others => '0'); + elsif( sm_acq = '1' ) then + sm_counter <= sm_counter + 1; + end if; + end if; +end process THE_SAMPLE_CTR_PROC; + +sm_sample_done_x <= '1' when (sm_counter = max_sample_in) else '0'; + +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + sm_clear_done <= sm_clear_done_x; + sm_sample_done <= sm_sample_done_x; + end if; +end process THE_SYNC_PROC; + +THE_READY_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( (reset_in = '1') or (sm_rst = '1') ) then + data_available <= '0'; + elsif( sm_sample_done = '1' ) then + data_available <= '1'; + end if; + end if; +end process THE_READY_PROC; + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SM_SLEEP; + sm_rst <= '0'; + sm_ce <= '0'; + sm_we <= '0'; + sm_acq <= '0'; + sm_done <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + sm_rst <= sm_rst_x; + sm_ce <= sm_ce_x; + sm_we <= sm_we_x; + sm_acq <= sm_acq_x; + sm_done <= sm_done_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process( CURRENT_STATE, arm_in, trg_in, sm_clear_done, sm_sample_done ) +begin + NEXT_STATE <= SM_SLEEP; + sm_rst_x <= '0'; + sm_ce_x <= '0'; + sm_we_x <= '0'; + sm_acq_x <= '0'; + sm_done_x <= '0'; + case CURRENT_STATE is + when SM_SLEEP => if( arm_in = '1' ) then + NEXT_STATE <= SM_CLEAR; + sm_rst_x <= '1'; + else + NEXT_STATE <= SM_SLEEP; + end if; + when SM_CLEAR => if( sm_clear_done = '1' ) then + NEXT_STATE <= SM_RUN; + sm_ce_x <= '1'; + sm_we_x <= '1'; + else + NEXT_STATE <= SM_CLEAR; + sm_ce_x <= '1'; + sm_we_x <= '1'; + end if; + when SM_RUN => if( trg_in = '1' ) then + NEXT_STATE <= SM_SAMPLE; + sm_ce_x <= '1'; + sm_we_x <= '1'; + sm_acq_x <= '1'; + else + NEXT_STATE <= SM_RUN; + sm_ce_x <= '1'; + sm_we_x <= '1'; + end if; + when SM_SAMPLE => if( sm_sample_done = '1' ) then + NEXT_STATE <= SM_READY; + sm_done_x <= '1'; + else + NEXT_STATE <= SM_SAMPLE; + sm_ce_x <= '1'; + sm_we_x <= '1'; + sm_acq_x <= '1'; + end if; + when SM_READY => NEXT_STATE <= SM_SLEEP; + + when others => NEXT_STATE <= SM_SLEEP; + end case; +end process TRANSFORM; + +-- state decoding +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SM_SLEEP => bsm_out <= x"0"; + clear_out <= '0'; + run_out <= '0'; + when SM_CLEAR => bsm_out <= x"1"; + clear_out <= '1'; + run_out <= '0'; + when SM_RUN => bsm_out <= x"2"; + clear_out <= '0'; + run_out <= '1'; + when SM_SAMPLE => bsm_out <= x"3"; + clear_out <= '0'; + run_out <= '0'; + when SM_READY => bsm_out <= x"4"; + clear_out <= '0'; + run_out <= '0'; + when others => bsm_out <= x"f"; + clear_out <= '0'; + run_out <= '0'; + end case; +end process STATE_DECODE; + +--------------------------------------------------------- +-- output signals -- +--------------------------------------------------------- +sm_addr_out <= sm_addr; +sm_we_out <= sm_we; +sm_ce_out <= sm_ce; +ready_out <= data_available; +sample_out <= sm_acq; +last_out <= sm_sample_done; + +end Behavioral; diff --git a/src/max_data.vhd b/src/max_data.vhd new file mode 100644 index 0000000..01cc2ee --- /dev/null +++ b/src/max_data.vhd @@ -0,0 +1,178 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity max_data is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + TODO_3_IN : in std_logic_vector(3 downto 0); + TODO_2_IN : in std_logic_vector(3 downto 0); + TODO_1_IN : in std_logic_vector(3 downto 0); + TODO_0_IN : in std_logic_vector(3 downto 0); + TODO_MAX_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of max_data is + + -- Placer Directives + + -- normal signals + -- first comparatopr step + signal max_32_data : std_logic_vector(3 downto 0); + signal max_21_data : std_logic_vector(3 downto 0); + signal max_10_data : std_logic_vector(3 downto 0); + signal comb_3_gt_2 : std_logic; + signal comb_2_gt_1 : std_logic; + signal comb_1_gt_0 : std_logic; + -- second comparator step + signal max_321_data : std_logic_vector(3 downto 0); + signal max_210_data : std_logic_vector(3 downto 0); + signal comb_32_gt_21 : std_logic; + signal comb_21_gt_10 : std_logic; + -- third comparator step + signal max_final_data : std_logic_vector(3 downto 0); + signal comb_final : std_logic; + + signal debug : std_logic_vector(15 downto 0); + +begin + +-- FIRST COMPARATOR STEP +-- compare MAX_3 against MAX_2, store the bigger one +THE_COMP_3_2: comp4bit +port map( DATAA => todo_3_in, + DATAB => todo_2_in, + AGTB => comb_3_gt_2 + ); + +THE_3_2_STORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + max_32_data <= (others => '0'); + elsif( comb_3_gt_2 = '1' ) then + max_32_data <= todo_3_in; + else + max_32_data <= todo_2_in; + end if; + end if; +end process THE_3_2_STORE_PROC; + + +-- compare MAX_2 against MAX_1, store the bigger one +THE_COMP_2_1: comp4bit +port map( DATAA => todo_2_in, + DATAB => todo_1_in, + AGTB => comb_2_gt_1 + ); + +THE_2_1_STORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + max_21_data <= (others => '0'); + elsif( comb_2_gt_1 = '1' ) then + max_21_data <= todo_2_in; + else + max_21_data <= todo_1_in; + end if; + end if; +end process THE_2_1_STORE_PROC; + +-- compare MAX_1 against MAX_0, store the bigger one +THE_COMP_1_0: comp4bit +port map( DATAA => todo_1_in, + DATAB => todo_0_in, + AGTB => comb_1_gt_0 + ); + +THE_1_0_STORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + max_10_data <= (others => '0'); + elsif( comb_1_gt_0 = '1' ) then + max_10_data <= todo_1_in; + else + max_10_data <= todo_0_in; + end if; + end if; +end process THE_1_0_STORE_PROC; + + +-- SECOND COMPARATOR STEP +-- compare MAX_32 against MAX_21, store the bigger one +THE_COMP_32_21: comp4bit +port map( DATAA => max_32_data, + DATAB => max_21_data, + AGTB => comb_32_gt_21 + ); + +THE_32_21_STORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + max_321_data <= (others => '0'); + elsif( comb_32_gt_21 = '1' ) then + max_321_data <= max_32_data; + else + max_321_data <= max_21_data; + end if; + end if; +end process THE_32_21_STORE_PROC; + +-- compare MAX_21 against MAX_10, store the bigger one +THE_COMP_21_10: comp4bit +port map( DATAA => max_21_data, + DATAB => max_10_data, + AGTB => comb_21_gt_10 + ); + +THE_21_10_STORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + max_210_data <= (others => '0'); + elsif( comb_21_gt_10 = '1' ) then + max_210_data <= max_21_data; + else + max_210_data <= max_10_data; + end if; + end if; +end process THE_21_10_STORE_PROC; + +-- FINAL COMPARATOR STEP +THE_COMP_FINAL: comp4bit +port map( DATAA => max_321_data, + DATAB => max_210_data, + AGTB => comb_final + ); + +THE_FINAL_STORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + max_final_data <= (others => '0'); + elsif( comb_final = '1' ) then + max_final_data <= max_321_data; + else + max_final_data <= max_210_data; + end if; + end if; +end process THE_FINAL_STORE_PROC; + +-- debug signals +debug(15 downto 0) <= (others => '0'); + +-- output signals +todo_max_out <= max_final_data; +debug_out <= debug; + +end behavioral; + \ No newline at end of file diff --git a/src/msg_file.log b/src/msg_file.log new file mode 100644 index 0000000..079084d --- /dev/null +++ b/src/msg_file.log @@ -0,0 +1,35 @@ +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Nov 20 19:14:28 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e + Circuit name : dpram_8x19 + Module type : sdpram + Module Version : 3.4 + Address width : 4 + Data width : 19 + Ports : + Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0] + Outputs : Q[18:0] + I/O buffer : not inserted + Clock edge : rising edge + EDIF output : suppressed + VHDL output : dpram_8x19.vhd + VHDL template : dpram_8x19_tmpl.vhd + VHDL testbench : tb_dpram_8x19_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : dpram_8x19.srp + Estimated Resource Usage: + LUT : 1 + DRAM : 5 + +END SCUBA Module Synthesis + diff --git a/src/mult_3x8.lpc b/src/mult_3x8.lpc new file mode 100644 index 0000000..0ba594a --- /dev/null +++ b/src/mult_3x8.lpc @@ -0,0 +1,41 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Multiplier +CoreRevision=4.3 +ModuleName=mult_3x8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/29/2009 +Time=11:23:02 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +pmi_implemenntation=LUT +pmi_const_coeff=No +pmi_coeff_value=2 +pmi_ram_mult=No +pmi_dataa_width=3 +pmi_datab_width=8 +pmi_datap_width=11 +pmi_signa=Unsigned +pmi_signb=Unsigned +pmi_additional_pipeline=0 +pmi_input_reg=No +pmi_output_reg=Yes diff --git a/src/mult_3x8.srp b/src/mult_3x8.srp new file mode 100644 index 0000000..aa3ac4e --- /dev/null +++ b/src/mult_3x8.srp @@ -0,0 +1,32 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Oct 29 11:23:03 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e + Circuit name : mult_3x8 + Module type : dspmult_a + Module Version : 4.3 + Ports : + Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0] + Outputs : Result[10:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : mult_3x8.vhd + VHDL template : mult_3x8_tmpl.vhd + VHDL testbench : tb_mult_3x8_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : mult_3x8.srp + Element Usage : + AND2 : 9 + FADD2B : 6 + FD1P3DX : 11 + MULT2 : 4 + Estimated Resource Usage: + LUT : 29 + Reg : 11 diff --git a/src/mult_3x8.vhd b/src/mult_3x8.vhd new file mode 100644 index 0000000..4f31420 --- /dev/null +++ b/src/mult_3x8.vhd @@ -0,0 +1,295 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 4.3 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e + +-- Thu Oct 29 11:23:03 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity mult_3x8 is + port ( + Clock: in std_logic; + ClkEn: in std_logic; + Aclr: in std_logic; + DataA: in std_logic_vector(2 downto 0); + DataB: in std_logic_vector(7 downto 0); + Result: out std_logic_vector(10 downto 0)); +end mult_3x8; + +architecture Structure of mult_3x8 is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal mult_3x8_0_pp_0_0: std_logic; + signal rego_o_0: std_logic; + signal rego_o_1: std_logic; + signal rego_o_2: std_logic; + signal rego_o_3: std_logic; + signal mult_3x8_0_pp_1_2: std_logic; + signal mult_3x8_0_pp_1_3: std_logic; + signal rego_o_4: std_logic; + signal rego_o_5: std_logic; + signal co_t_mult_3x8_0_0_1: std_logic; + signal mult_3x8_0_pp_1_4: std_logic; + signal mult_3x8_0_pp_1_5: std_logic; + signal rego_o_6: std_logic; + signal rego_o_7: std_logic; + signal co_t_mult_3x8_0_0_2: std_logic; + signal mult_3x8_0_pp_1_6: std_logic; + signal mult_3x8_0_pp_1_7: std_logic; + signal rego_o_8: std_logic; + signal rego_o_9: std_logic; + signal co_t_mult_3x8_0_0_3: std_logic; + signal mult_3x8_0_pp_1_8: std_logic; + signal mult_3x8_0_pp_1_9: std_logic; + signal mult_3x8_0_pp_0_9: std_logic; + signal rego_o_10: std_logic; + signal co_t_mult_3x8_0_0_4: std_logic; + signal mult_3x8_0_pp_0_2: std_logic; + signal mult_3x8_0_pp_0_1: std_logic; + signal mult_3x8_0_pp_0_4: std_logic; + signal mult_3x8_0_pp_0_3: std_logic; + signal mco: std_logic; + signal mult_3x8_0_pp_0_6: std_logic; + signal mult_3x8_0_pp_0_5: std_logic; + signal mco_1: std_logic; + signal mfco: std_logic; + signal mult_3x8_0_pp_0_8: std_logic; + signal mult_3x8_0_pp_0_7: std_logic; + signal mco_2: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component MULT2 + port (A0: in std_logic; A1: in std_logic; A2: in std_logic; + A3: in std_logic; B0: in std_logic; B1: in std_logic; + B2: in std_logic; B3: in std_logic; CI: in std_logic; + P0: out std_logic; P1: out std_logic; CO: out std_logic); + end component; + attribute GSR : string; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + AND2_t8: AND2 + port map (A=>DataB(0), B=>DataA(0), Z=>mult_3x8_0_pp_0_0); + + AND2_t7: AND2 + port map (A=>DataB(0), B=>DataA(2), Z=>mult_3x8_0_pp_1_2); + + AND2_t6: AND2 + port map (A=>DataB(1), B=>DataA(2), Z=>mult_3x8_0_pp_1_3); + + AND2_t5: AND2 + port map (A=>DataB(2), B=>DataA(2), Z=>mult_3x8_0_pp_1_4); + + AND2_t4: AND2 + port map (A=>DataB(3), B=>DataA(2), Z=>mult_3x8_0_pp_1_5); + + AND2_t3: AND2 + port map (A=>DataB(4), B=>DataA(2), Z=>mult_3x8_0_pp_1_6); + + AND2_t2: AND2 + port map (A=>DataB(5), B=>DataA(2), Z=>mult_3x8_0_pp_1_7); + + AND2_t1: AND2 + port map (A=>DataB(6), B=>DataA(2), Z=>mult_3x8_0_pp_1_8); + + AND2_t0: AND2 + port map (A=>DataB(7), B=>DataA(2), Z=>mult_3x8_0_pp_1_9); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_0, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(0)); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_1, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(1)); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_2, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(2)); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_3, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(3)); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_4, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(4)); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_5, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(5)); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_6, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(6)); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_7, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(7)); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_8, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(8)); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_9, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(9)); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rego_o_10, SP=>ClkEn, CK=>Clock, CD=>Aclr, + Q=>Result(10)); + + mult_3x8_0_Cadd_0_4: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>mfco, COUT=>open, S0=>mult_3x8_0_pp_0_9, + S1=>open); + + t_mult_3x8_0_add_0_1: FADD2B + port map (A0=>mult_3x8_0_pp_0_2, A1=>mult_3x8_0_pp_0_3, + B0=>mult_3x8_0_pp_1_2, B1=>mult_3x8_0_pp_1_3, CI=>scuba_vlo, + COUT=>co_t_mult_3x8_0_0_1, S0=>rego_o_2, S1=>rego_o_3); + + t_mult_3x8_0_add_0_2: FADD2B + port map (A0=>mult_3x8_0_pp_0_4, A1=>mult_3x8_0_pp_0_5, + B0=>mult_3x8_0_pp_1_4, B1=>mult_3x8_0_pp_1_5, + CI=>co_t_mult_3x8_0_0_1, COUT=>co_t_mult_3x8_0_0_2, + S0=>rego_o_4, S1=>rego_o_5); + + t_mult_3x8_0_add_0_3: FADD2B + port map (A0=>mult_3x8_0_pp_0_6, A1=>mult_3x8_0_pp_0_7, + B0=>mult_3x8_0_pp_1_6, B1=>mult_3x8_0_pp_1_7, + CI=>co_t_mult_3x8_0_0_2, COUT=>co_t_mult_3x8_0_0_3, + S0=>rego_o_6, S1=>rego_o_7); + + t_mult_3x8_0_add_0_4: FADD2B + port map (A0=>mult_3x8_0_pp_0_8, A1=>mult_3x8_0_pp_0_9, + B0=>mult_3x8_0_pp_1_8, B1=>mult_3x8_0_pp_1_9, + CI=>co_t_mult_3x8_0_0_3, COUT=>co_t_mult_3x8_0_0_4, + S0=>rego_o_8, S1=>rego_o_9); + + Cadd_t_mult_3x8_0_0_5: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co_t_mult_3x8_0_0_4, COUT=>open, + S0=>rego_o_10, S1=>open); + + mult_3x8_0_mult_0_0: MULT2 + port map (A0=>DataB(0), A1=>DataB(1), A2=>DataB(1), A3=>DataB(2), + B0=>DataA(1), B1=>DataA(0), B2=>DataA(1), B3=>DataA(0), + CI=>scuba_vlo, P0=>mult_3x8_0_pp_0_1, P1=>mult_3x8_0_pp_0_2, + CO=>mco); + + mult_3x8_0_mult_0_1: MULT2 + port map (A0=>DataB(2), A1=>DataB(3), A2=>DataB(3), A3=>DataB(4), + B0=>DataA(1), B1=>DataA(0), B2=>DataA(1), B3=>DataA(0), + CI=>mco, P0=>mult_3x8_0_pp_0_3, P1=>mult_3x8_0_pp_0_4, + CO=>mco_1); + + mult_3x8_0_mult_0_2: MULT2 + port map (A0=>DataB(4), A1=>DataB(5), A2=>DataB(5), A3=>DataB(6), + B0=>DataA(1), B1=>DataA(0), B2=>DataA(1), B3=>DataA(0), + CI=>mco_1, P0=>mult_3x8_0_pp_0_5, P1=>mult_3x8_0_pp_0_6, + CO=>mco_2); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + mult_3x8_0_mult_0_3: MULT2 + port map (A0=>DataB(6), A1=>DataB(7), A2=>DataB(7), + A3=>scuba_vlo, B0=>DataA(1), B1=>DataA(0), B2=>DataA(1), + B3=>DataA(0), CI=>mco_2, P0=>mult_3x8_0_pp_0_7, + P1=>mult_3x8_0_pp_0_8, CO=>mfco); + + rego_o_0 <= mult_3x8_0_pp_0_0; + rego_o_1 <= mult_3x8_0_pp_0_1; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of mult_3x8 is + for Structure + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:MULT2 use entity ecp2m.MULT2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/mult_3x8_generate.log b/src/mult_3x8_generate.log new file mode 100644 index 0000000..a8615eb --- /dev/null +++ b/src/mult_3x8_generate.log @@ -0,0 +1,45 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Oct 29 11:23:03 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e + Circuit name : mult_3x8 + Module type : dspmult_a + Module Version : 4.3 + Ports : + Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0] + Outputs : Result[10:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : mult_3x8.vhd + VHDL template : mult_3x8_tmpl.vhd + VHDL testbench : tb_mult_3x8_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : mult_3x8.srp + Estimated Resource Usage: + LUT : 29 + Reg : 11 + +END SCUBA Module Synthesis + +File: ..\src\mult_3x8.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/mult_3x8_tmpl.vhd b/src/mult_3x8_tmpl.vhd new file mode 100644 index 0000000..9c5c888 --- /dev/null +++ b/src/mult_3x8_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 4.3 +-- Thu Oct 29 11:23:03 2009 + +-- parameterized module component declaration +component mult_3x8 + port (Clock: in std_logic; ClkEn: in std_logic; + Aclr: in std_logic; DataA: in std_logic_vector(2 downto 0); + DataB: in std_logic_vector(7 downto 0); + Result: out std_logic_vector(10 downto 0)); +end component; + +-- parameterized module component instance +__ : mult_3x8 + port map (Clock=>__, ClkEn=>__, Aclr=>__, DataA(2 downto 0)=>__, + DataB(7 downto 0)=>__, Result(10 downto 0)=>__); diff --git a/src/my_sbuf.vhd b/src/my_sbuf.vhd new file mode 100644 index 0000000..8fa6801 --- /dev/null +++ b/src/my_sbuf.vhd @@ -0,0 +1,165 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity my_sbuf is + port( CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- connections to data source A + COMB_DATAREADY_IN : in std_logic; + COMB_NEXT_READ_OUT : out std_logic; + COMB_READ_IN : in std_logic; + COMB_DATA_IN : in std_logic_vector (18 downto 0); + -- connections to data sink B + SYN_DATAREADY_OUT : out std_logic; + SYN_DATA_OUT : out std_logic_vector (18 downto 0); + SYN_READ_IN : in std_logic; + -- status signals + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_BUFFER : out std_logic + ); +end my_sbuf; + +architecture my_sbuf_arch of my_sbuf is + +-- small DPRAM LUT based +component dpram_8x19 is +port( WRADDRESS : in std_logic_vector(3 downto 0); + DATA : in std_logic_vector(18 downto 0); + WRCLOCK : in std_logic; + WE : in std_logic; + WRCLOCKEN : in std_logic; + RDADDRESS : in std_logic_vector(3 downto 0); +-- RDCLOCK : in std_logic; +-- RDCLOCKEN : in std_logic; +-- RESET : in std_logic; + Q : out std_logic_vector(18 downto 0) + ); +end component dpram_8x19; + +-- signals +signal fifo_wr_data : std_logic_vector(18 downto 0); +signal fifo_rd_data : std_logic_vector(18 downto 0); +signal fifo_we : std_logic; +signal fifo_rd : std_logic; +signal wr_pointer : std_logic_vector(3 downto 0); +signal comb_ce_wr_pointer : std_logic; +signal rd_pointer : std_logic_vector(3 downto 0); +signal comb_ce_rd_pointer : std_logic; +signal lvl_counter : std_logic_vector(4 downto 0); +signal free_counter : std_logic_vector(4 downto 0); +signal comb_inc_free_counter : std_logic; +signal comb_dec_free_counter : std_logic; + +signal debug : std_logic_vector(31 downto 0); + +begin + +------------------------------------------------------------- +-- debug signals +------------------------------------------------------------- +debug(31 downto 24) <= (others => '0'); + +debug(23 downto 21) <= (others => '0'); +debug(20 downto 16) <= lvl_counter; +debug(15 downto 13) <= (others => '0'); +debug(12 downto 8) <= free_counter; +debug(7 downto 4) <= rd_pointer; +debug(3 downto 0) <= wr_pointer; +------------------------------------------------------------- +-- write pointer +------------------------------------------------------------- +comb_ce_wr_pointer <= fifo_we; -- BUG + +THE_WR_POINTER_PROC: process( clk ) +begin + if( rising_edge(clk) ) then + if ( reset = '1' ) then + wr_pointer <= (others => '0'); + elsif( comb_ce_wr_pointer = '1' ) then + wr_pointer <= wr_pointer + 1; + end if; + end if; +end process THE_WR_POINTER_PROC; + + +------------------------------------------------------------- +-- read pointer +------------------------------------------------------------- +comb_ce_rd_pointer <= fifo_rd; -- BUG + +THE_RD_POINTER_PROC: process( clk ) +begin + if( rising_edge(clk) ) then + if ( reset = '1' ) then + rd_pointer <= (others => '0'); + elsif( comb_ce_rd_pointer = '1' ) then + rd_pointer <= rd_pointer + 1; + end if; + end if; +end process THE_RD_POINTER_PROC; + +------------------------------------------------------------- +-- free counter +------------------------------------------------------------- +comb_inc_free_counter <= fifo_rd; -- BUG +comb_dec_free_counter <= fifo_we; -- BUG + +THE_FREE_COUNTER_PROC: process( clk ) +begin + if( rising_edge(clk) ) then + if ( reset = '1' ) then + free_counter <= b"1_0000"; + elsif( (comb_inc_free_counter = '1') and (comb_dec_free_counter = '0') ) then + free_counter <= free_counter + 1; + elsif( (comb_inc_free_counter = '0') and (comb_dec_free_counter = '1') ) then + free_counter <= free_counter - 1; + end if; + end if; +end process THE_FREE_COUNTER_PROC; + +THE_LVL_COUNTER_PROC: process( clk ) +begin + if( rising_edge(clk) ) then + if ( reset = '1' ) then + lvl_counter <= (others => '0'); + elsif( (comb_inc_free_counter = '1') and (comb_dec_free_counter = '0') ) then + lvl_counter <= lvl_counter - 1; + elsif( (comb_inc_free_counter = '0') and (comb_dec_free_counter = '1') ) then + lvl_counter <= lvl_counter + 1; + end if; + end if; +end process THE_LVL_COUNTER_PROC; + +------------------------------------------------------------- +-- the buffer memory +------------------------------------------------------------- +fifo_we <= comb_dataready_in and comb_read_in; -- BUG +fifo_rd <= syn_read_in; -- BUG +fifo_wr_data <= comb_data_in; + +THE_BUFFER_DPRAM: dpram_8x19 +port map( WRADDRESS => wr_pointer, + DATA => fifo_wr_data, + WRCLOCK => clk, + WE => fifo_we, + WRCLOCKEN => '1', + RDADDRESS => rd_pointer, +-- RDCLOCK => clk, +-- RDCLOCKEN => '1', +-- RESET => reset, + Q => fifo_rd_data + ); + +------------------------------------------------------------- +-- output signals +------------------------------------------------------------- +debug_out <= debug; +comb_next_read_out <= '0'; +syn_dataready_out <= '0'; +stat_buffer <= '0'; +syn_data_out <= fifo_rd_data; + +end architecture; \ No newline at end of file diff --git a/src/onewire_master.vhd b/src/onewire_master.vhd new file mode 100644 index 0000000..5f1628b --- /dev/null +++ b/src/onewire_master.vhd @@ -0,0 +1,549 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +-- stolen from Jan Michel, was trb_net_onewire.vhd + +entity onewire_master is + generic( CLK_PERIOD : integer := 10 ); -- clock perion in nanoseconds + port( CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic; + -- connection to 1-wire interface (16 APV FEs) + ONEWIRE : inout std_logic_vector(15 downto 0); + BP_ONEWIRE : inout std_logic; + -- connection to external DPRAM for slow control readout + BP_DATA_OUT : out std_logic_vector(15 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(6 downto 0); + WRITE_OUT : out std_logic; + BUSY_OUT : out std_logic; + -- debug + BSM_OUT : out std_logic_vector(7 downto 0); + STAT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture onewire_master_arch of onewire_master is + + constant MAX_COUNTER : integer := 2**28-1; + type state_t is (START, IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT, + WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP, + READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP, CHECK_PULSE); + signal STATE : state_t; + signal NEXT_STATE : state_t; + signal bsm : std_logic_vector(7 downto 0); + signal timecounter : integer range 0 to MAX_COUNTER; + signal bitcounter : integer range 0 to 127; + signal bitcounter_vector : std_logic_vector(6 downto 0); + signal inc_bitcounter : std_logic; + signal reset_bitcounter : std_logic; + signal reset_timecounter : std_logic; + signal send_bit : std_logic; + signal next_send_bit : std_logic; + signal recv_bit_ready : std_logic; + signal next_recv_bit_ready : std_logic; + signal ext_ram_addr : std_logic_vector(3 downto 0); + signal ram_addr : std_logic_vector(2 downto 0); + signal ram_wr : std_logic; + + -- state machine auxiliary signals + signal wait_pulse : std_logic; + signal next_wait_pulse : std_logic; + signal strong_pullup : std_logic; + signal next_strong_pullup : std_logic; + signal presence_reset : std_logic; + signal next_presence_reset : std_logic; + signal send_rom : std_logic; -- read UniqueID + signal next_send_rom : std_logic; + signal conv_temp : std_logic; -- send CONV_TEMP + signal next_conv_temp : std_logic; + signal reading_temp : std_logic; -- readback of temperature + signal next_reading_temp : std_logic; + signal skip_rom : std_logic; -- send SKIP_ROM + signal next_skip_rom : std_logic; + signal output_tmp : std_logic; -- 1W output signal + signal next_output_tmp : std_logic; + signal output : std_logic; + signal next_output : std_logic; + + -- presence pulse detection + signal neg_edge : std_logic_vector(16 downto 0); -- presence pulse edge detection + signal presence_found : std_logic_vector(16 downto 0); -- set signal for presence bits + signal presence : std_logic_vector(16 downto 0); -- presence bits + + type input_t is array (0 to 16) of std_logic_vector(7 downto 0); + signal input : input_t; + + type word_t is array (0 to 16) of std_logic_vector(15 downto 0); + signal word : word_t; + + signal recv_bit : std_logic_vector(16 downto 0); + signal next_recv_bit : std_logic_vector(16 downto 0); + + signal comb_ext_addr_go : std_logic; + + -- output signals, delayed by one cycle + signal mux_data : std_logic_vector(15 downto 0); + signal mux_addr : std_logic_vector(6 downto 0); + signal mux_wr : std_logic; + + signal onewire_tmp : std_logic_vector(16 downto 0); + + signal comb_busy : std_logic; + signal busy : std_logic; + +begin + +-- bidirectional connection +IO_GEN: for i in 0 to 15 generate + onewire(i) <= '0' when (output = '0') else '1' when (strong_pullup = '1') else 'Z'; + onewire_tmp(i) <= '0' when onewire(i) = '0' else '1'; -- BUGBUGBUG +end generate IO_GEN; + +-- We have one "special" connection for the backplane 1Wire ID +bp_onewire <= '0' when (output = '0') else '1' when (strong_pullup = '1') else 'Z'; +onewire_tmp(16) <= '0' when bp_onewire = '0' else '1'; -- BUGBUGBUG + +-- shift and sync register +THE_SHIFT_PROC : process(clk) +begin + if( rising_edge(clk) ) then + for i in 0 to 16 loop + -- Shift registers + input(i)(7 downto 1) <= input(i)(6 downto 0); + input(i)(0) <= onewire_tmp(i); -- BUGBUGBUG + -- Edge detection + neg_edge(i) <= input(i)(7) and not input(i)(6) and not input(i)(5) and not input(i)(4) and not input(i)(3) and not input(i)(2); + presence_found(i) <= wait_pulse and neg_edge(i); + -- presence registers + if ( presence_reset = '1') then + presence(i) <= '0'; + elsif( presence_found(i) = '1' ) then + presence(i) <= '1'; + end if; + end loop; + -- Synchronize signals + end if; +end process THE_SHIFT_PROC; + +bitcounter_vector <= conv_std_logic_vector(bitcounter,7); + +-------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------- +-- State machine registers +THE_STATE_REGS_PROC: process(clk) +begin + if( rising_edge(clk) ) then + if( reset = '1' ) then + STATE <= START; + send_bit <= '0'; + output_tmp <= '0'; + recv_bit <= (others => '0'); + strong_pullup <= '0'; + wait_pulse <= '0'; + presence_reset <= '0'; + send_rom <= '1'; + conv_temp <= '0'; + reading_temp <= '0'; + skip_rom <= '0'; + busy <= '0'; + else + recv_bit_ready <= next_recv_bit_ready; + state <= next_state; + send_bit <= next_send_bit; + output <= next_output; + output_tmp <= next_output_tmp; + recv_bit <= next_recv_bit; + strong_pullup <= next_strong_pullup; + wait_pulse <= next_wait_pulse; + presence_reset <= next_presence_reset; + send_rom <= next_send_rom; + conv_temp <= next_conv_temp; + reading_temp <= next_reading_temp; + skip_rom <= next_skip_rom; + busy <= comb_busy; + end if; + end if; +end process THE_STATE_REGS_PROC; + +comb_busy <= '0' when (STATE = START) else '1'; + +-- State machine transitions +THE_STATE_MACHINE: process( STATE, timecounter, bitcounter_vector, input, send_bit, output_tmp, + skip_rom, recv_bit, conv_temp, reading_temp, send_rom, readout_enable_in ) +begin + NEXT_STATE <= STATE; + next_output <= '1'; + reset_timecounter <= '0'; + reset_bitcounter <= '0'; + next_output_tmp <= output_tmp; + inc_bitcounter <= '0'; + next_send_bit <= send_bit; + next_recv_bit <= (others => '0'); + next_recv_bit_ready <= '0'; + next_send_rom <= send_rom; + next_conv_temp <= conv_temp; + next_reading_temp <= reading_temp; + next_recv_bit <= recv_bit; + next_skip_rom <= skip_rom; + next_strong_pullup <= '0'; + next_wait_pulse <= '0'; + next_presence_reset <= '0'; + + case STATE is + -- + when START => + if( readout_enable_in = '1' ) then + NEXT_STATE <= IDLE; + reset_timecounter <= '1'; + end if; + + -- idle state for the DS1822 + when IDLE => + if( is_time_reached(timecounter,640000,CLK_PERIOD) = '1' ) then + NEXT_STATE <= SEND_RESET; + reset_timecounter <= '1'; + end if; + + -- send the reset pulse + when SEND_RESET => + next_output <= '0'; + if( is_time_reached(timecounter,640000,CLK_PERIOD) = '1' ) then + reset_timecounter <= '1'; + next_presence_reset <= '1'; + NEXT_STATE <= WAIT_AFTER_RESET; + end if; + + -- delay after RESET pulse (earliest presence pulse @15us) + when WAIT_AFTER_RESET => + if( is_time_reached(timecounter,10000,CLK_PERIOD) = '1' ) then + reset_timecounter <= '1'; + NEXT_STATE <= CHECK_PULSE; + end if; + + -- check if the is a pulse + when CHECK_PULSE => + next_wait_pulse <= '1'; + if( is_time_reached(timecounter,320000,CLK_PERIOD) = '1' ) then + next_wait_pulse <= '0'; + reset_timecounter <= '1'; + NEXT_STATE <= SEND_ROM_COMMAND; + end if; + + -- sending rom commands + when SEND_ROM_COMMAND => + next_skip_rom <= not send_rom and not bitcounter_vector(3); + inc_bitcounter <= '1'; + NEXT_STATE <= WRITE_START; + + if( send_rom = '1' ) then + next_send_bit <= not bitcounter_vector(1); -- this is x33 (READ_ROM_COMMAND), lsb first + else + next_send_bit <= bitcounter_vector(1); -- this is xCC (SKIP_ROM_COMMAND), lsb first + end if; + + if( bitcounter_vector(3) = '1' ) then --send 8 bit + if ( send_rom = '1' ) then + NEXT_STATE <= READ_READ_ROM; + elsif( conv_temp = '1' ) then + NEXT_STATE <= SEND_CONV_TEMP; + else + NEXT_STATE <= SEND_READ_TEMP; + end if; + reset_bitcounter <= '1'; + end if; + + --sending sensor commands + when SEND_CONV_TEMP => + next_send_bit <= bitcounter_vector(1) and not bitcounter_vector(0); + --this is x44, lsb first + inc_bitcounter <= '1'; + if( bitcounter_vector(3) = '1' ) then --send 8 bit + NEXT_STATE <= READ_CONV_TEMP; + reset_bitcounter <= '1'; + reset_timecounter <= '1'; + next_recv_bit <= (others => '0'); + else + NEXT_STATE <= WRITE_START; + end if; + + when SEND_READ_TEMP => + if( (bitcounter_vector(2 downto 0) = "000") or (bitcounter_vector(2 downto 0) = "110") ) then + next_send_bit <= '0'; --this is xBE, lsb first + else + next_send_bit <= '1'; + end if; + + inc_bitcounter <= '1'; + + if( bitcounter_vector(3) = '1' ) then --send 8 bit + NEXT_STATE <= READ_READ_TEMP; + reset_bitcounter <= '1'; + next_recv_bit <= (others => '0'); + else + NEXT_STATE <= WRITE_START; + end if; + + --reading rom answers + when READ_READ_ROM => + inc_bitcounter <= '1'; + if( bitcounter_vector(6) = '1' ) then --read 64 bit + NEXT_STATE <= IDLE; + next_send_rom <= '0'; + next_conv_temp <= '1'; + reset_bitcounter <= '1'; + else + NEXT_STATE <= READ_BIT; + end if; + + --reading sensor answers + when READ_CONV_TEMP => --waiting for end of conversion + next_strong_pullup <= '1'; + if( is_time_reached(timecounter,1300000000,CLK_PERIOD) = '1' ) then -- reality is 1.3s delay +-- if( is_time_reached(timecounter,3000000,CLK_PERIOD) = '1' ) then -- simulation is 3ms delay + NEXT_STATE <= IDLE; + reset_timecounter <= '1'; + next_conv_temp <= '0'; + next_reading_temp <= '1'; + end if; + + when READ_READ_TEMP => + inc_bitcounter <= '1'; + if( bitcounter_vector(3 downto 2) = "11" ) then --read 12 bit + NEXT_STATE <= START; + next_send_rom <= '1'; + next_reading_temp <= '0'; + reset_bitcounter <= '1'; + else + NEXT_STATE <= READ_BIT; + end if; + + --write cycle + when WRITE_START => + next_output <= output_tmp; + if( is_time_reached(timecounter,1200,CLK_PERIOD) = '1' ) then + next_output_tmp <= send_bit; + end if; + if( is_time_reached(timecounter,80000,CLK_PERIOD) = '1' ) then + NEXT_STATE <= WRITE_WAIT; + next_output_tmp <= '0'; + reset_timecounter <= '1'; + end if; + + when WRITE_WAIT => + if( is_time_reached(timecounter,1200,CLK_PERIOD) = '1' ) then + reset_timecounter <= '1'; + if( (send_rom = '1') or (skip_rom = '1') ) then + NEXT_STATE <= SEND_ROM_COMMAND; + elsif( conv_temp = '1' ) then + NEXT_STATE <= SEND_CONV_TEMP; + elsif( reading_temp = '1' ) then + NEXT_STATE <= SEND_READ_TEMP; + end if; + end if; + + --read cycle + when READ_BIT => + next_output <= output_tmp; + if( is_time_reached(timecounter,1200,CLK_PERIOD) = '1' ) then + next_output_tmp <= '1'; + end if; + if( is_time_reached(timecounter,10000,CLK_PERIOD) = '1' ) then + for i in 0 to 16 loop + next_recv_bit(i) <= input(i)(2); + end loop; + next_recv_bit_ready <= '1'; + NEXT_STATE <= READ_WAIT; + end if; + + when READ_WAIT => + if( is_time_reached(timecounter,80000,CLK_PERIOD) = '1' ) then + reset_timecounter <= '1'; + next_output_tmp <= '0'; + if ( send_rom = '1' ) then + NEXT_STATE <= READ_READ_ROM; + elsif( conv_temp = '1' ) then + NEXT_STATE <= READ_CONV_TEMP; + else + NEXT_STATE <= READ_READ_TEMP; + end if; + end if; + + when others => + NEXT_STATE <= START; + end case; +end process THE_STATE_MACHINE; + +-- State machine decoding +STATE_DECODE: process( STATE ) +begin + case STATE is + when START => bsm <= x"00"; + when IDLE => bsm <= x"01"; + when SEND_RESET => bsm <= x"02"; + when WAIT_AFTER_RESET => bsm <= x"03"; + when CHECK_PULSE => bsm <= x"0e"; + when SEND_ROM_COMMAND => bsm <= x"04"; + when READ_WAIT => bsm <= x"05"; + when WRITE_START => bsm <= x"06"; + when WRITE_WAIT => bsm <= x"07"; + when READ_BIT => bsm <= x"08"; + when READ_READ_ROM => bsm <= x"09"; + when SEND_CONV_TEMP => bsm <= x"0a"; + when READ_CONV_TEMP => bsm <= x"0b"; + when SEND_READ_TEMP => bsm <= x"0c"; + when READ_READ_TEMP => bsm <= x"0d"; + when others => bsm <= x"ff"; + end case; +end process STATE_DECODE; +-------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------- + +-- Time counter for 1Wire bus accesses +THE_TIME_COUNTER: process(clk) +begin + if( rising_edge(clk) ) then + if( reset_timecounter = '1' ) then + timecounter <= 0; + else + timecounter <= timecounter + 1; + end if; + end if; +end process THE_TIME_COUNTER; + +-- Bit counter +THE_BIT_COUNTER: process(clk) +begin + if( rising_edge(clk) ) then + if ( reset_bitcounter = '1' ) then + bitcounter <= 0; + elsif( inc_bitcounter = '1' ) then + bitcounter <= bitcounter + 1; + end if; + end if; +end process THE_BIT_COUNTER; + +-- Saving received data +THE_DATA_SAVE_PROC: process(clk) +begin + if( rising_edge(clk) ) then + if( reset = '1' ) then + ram_addr(1 downto 0) <= (others => '0'); + ram_wr <= '0'; +-- word(i) <= (others => '0'); + else + ram_wr <= '0'; + -- Shift process for serial / parallel data conversion + if( (recv_bit_ready = '1') and ((send_rom = '1') or (reading_temp = '1')) ) then + ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4)) - 1; + ram_addr(2) <= '0'; + for i in 0 to 16 loop + word(i)(14 downto 0) <= word(i)(15 downto 1); + word(i)(15) <= recv_bit(i); + end loop; + -- UniqueID write process + if( (bitcounter_vector(3 downto 0) = "0000") and (send_rom = '1') ) then + ram_wr <= '1'; + end if; + -- temperature value copy process + if( (bitcounter_vector(3 downto 0) = "1100") and (reading_temp = '1') ) then + ram_addr <= "100"; + ram_wr <= '1'; + for i in 0 to 16 loop + word(i)(11) <= recv_bit(i); + word(i)(10 downto 0) <= word(i)(15 downto 5); + word(i)(14 downto 12) <= (others => '0'); + word(i)(15) <= presence(i); + end loop; + + end if; + end if; + end if; + end if; +end process THE_DATA_SAVE_PROC; + +-- Data output multiplexer +THE_EXT_ADDR_PROC: process(clk) +begin + if( rising_edge(clk) ) then + if( reset = '1' ) then + ext_ram_addr <= (others => '0'); + elsif( (comb_ext_addr_go = '1') ) then + ext_ram_addr <= ext_ram_addr + 1; + end if; + end if; +end process THE_EXT_ADDR_PROC; + +comb_ext_addr_go <= '1' when ((ext_ram_addr /= "0000") or (ram_wr = '1')) else '0'; + +-- Data multiplexer +DATA_MUX_PROC: process(clk) +begin + if( rising_edge(clk) ) then + case ext_ram_addr is + when x"0" => mux_data <= word(0); + when x"1" => mux_data <= word(1); + when x"2" => mux_data <= word(2); + when x"3" => mux_data <= word(3); + when x"4" => mux_data <= word(4); + when x"5" => mux_data <= word(5); + when x"6" => mux_data <= word(6); + when x"7" => mux_data <= word(7); + when x"8" => mux_data <= word(8); + when x"9" => mux_data <= word(9); + when x"a" => mux_data <= word(10); + when x"b" => mux_data <= word(11); + when x"c" => mux_data <= word(12); + when x"d" => mux_data <= word(13); + when x"e" => mux_data <= word(14); + when x"f" => mux_data <= word(15); + when others => mux_data <= x"dead"; + end case; + mux_addr(2 downto 0) <= ram_addr; + mux_addr(6 downto 3) <= ext_ram_addr; + mux_wr <= comb_ext_addr_go; -- really? + end if; +end process DATA_MUX_PROC; + +-- Output signals +bp_data_out <= word(16); +addr_out <= mux_addr; +data_out <= mux_data; +write_out <= mux_wr; +busy_out <= busy; + +bsm_out <= bsm; + +-- Status signals +stat(0) <= '0' when ( input(0)(7) = '0' ) else '1'; +stat(1) <= ram_wr; +stat(2) <= send_rom; +stat(3) <= skip_rom; +stat(4) <= send_bit; +stat(5) <= recv_bit(0); +stat(6) <= recv_bit_ready; +stat(7) <= conv_temp; +stat(8) <= reading_temp; +stat(9) <= strong_pullup; +stat(10) <= reset_bitcounter; +stat(11) <= inc_bitcounter; +stat(15 downto 12) <= bitcounter_vector(3 downto 0); + + +end architecture; + + + + + + + + + diff --git a/src/onewire_spare_one.lpc b/src/onewire_spare_one.lpc new file mode 100644 index 0000000..0e9df8e --- /dev/null +++ b/src/onewire_spare_one.lpc @@ -0,0 +1,34 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Distributed_ROM +CoreRevision=2.4 +ModuleName=onewire_spare_one +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/05/2009 +Time=15:51:35 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Addresses=8 +Data=4 +LUT=0 +MemFile=\\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem +MemFormat=orca diff --git a/src/onewire_spare_one.srp b/src/onewire_spare_one.srp new file mode 100644 index 0000000..b0b1cc6 --- /dev/null +++ b/src/onewire_spare_one.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Nov 05 15:51:35 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e + Circuit name : onewire_spare_one + Module type : rom + Module Version : 2.4 + Address width : 3 + Ports : + Inputs : Address[2:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem + EDIF output : suppressed + VHDL output : onewire_spare_one.vhd + VHDL template : onewire_spare_one_tmpl.vhd + VHDL testbench : tb_onewire_spare_one_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : onewire_spare_one.srp + Element Usage : + ROM16X1 : 4 + Estimated Resource Usage: + LUT : 4 diff --git a/src/onewire_spare_one.vhd b/src/onewire_spare_one.vhd new file mode 100644 index 0000000..87f6e74 --- /dev/null +++ b/src/onewire_spare_one.vhd @@ -0,0 +1,86 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 3 -num_rows 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e + +-- Thu Nov 05 15:51:35 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity onewire_spare_one is + port ( + Address: in std_logic_vector(2 downto 0); + Q: out std_logic_vector(3 downto 0)); +end onewire_spare_one; + +architecture Structure of onewire_spare_one is + + -- internal signal declarations + signal scuba_vlo: std_logic; + + -- local component declarations + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute initval : string; + attribute initval of mem_0_3 : label is "0x00EA"; + attribute initval of mem_0_2 : label is "0x00E7"; + attribute initval of mem_0_1 : label is "0x00EC"; + attribute initval of mem_0_0 : label is "0x00E0"; + +begin + -- component instantiation statements + mem_0_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x00EA") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(3)); + + mem_0_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x00E7") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(2)); + + mem_0_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x00EC") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(1)); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + mem_0_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x00E0") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>Address(2), AD1=>Address(1), + AD0=>Address(0), DO0=>Q(0)); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of onewire_spare_one is + for Structure + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/onewire_spare_one_generate.log b/src/onewire_spare_one_generate.log new file mode 100644 index 0000000..ff8c064 --- /dev/null +++ b/src/onewire_spare_one_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Nov 05 15:51:35 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e + Circuit name : onewire_spare_one + Module type : rom + Module Version : 2.4 + Address width : 3 + Data width : 4 + Ports : + Inputs : Address[2:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem + EDIF output : suppressed + VHDL output : onewire_spare_one.vhd + VHDL template : onewire_spare_one_tmpl.vhd + VHDL testbench : tb_onewire_spare_one_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : onewire_spare_one.srp + Estimated Resource Usage: + LUT : 4 + +END SCUBA Module Synthesis + +File: onewire_spare_one.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/onewire_spare_one_tmpl.vhd b/src/onewire_spare_one_tmpl.vhd new file mode 100644 index 0000000..94ce4aa --- /dev/null +++ b/src/onewire_spare_one_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Thu Nov 05 15:51:35 2009 + +-- parameterized module component declaration +component onewire_spare_one + port (Address: in std_logic_vector(2 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : onewire_spare_one + port map (Address(2 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/src/ped_corr_ctrl.vhd b/src/ped_corr_ctrl.vhd new file mode 100755 index 0000000..4469014 --- /dev/null +++ b/src/ped_corr_ctrl.vhd @@ -0,0 +1,817 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +-- eds_data_in[35:32] = num_frames must be used for checking free space inside ipu_stage.vhd +-- max_space = (num_frames * 128 + num_frames) = num_frames * 129 + +entity ped_corr_ctrl is + port( CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control registers + -- EDS buffer -- back to previous source stage + EDS_DATA_IN : in std_logic_vector(39 downto 0); + EDS_AVAIL_IN : in std_logic; + EDS_DONE_OUT : out std_logic; + EVT_TYPE_IN : in std_logic_vector(2 downto 0); + -- DHDR information -- to next stage + DHDR_DATA_OUT : out std_logic_vector(31 downto 0); + DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0); + DHDR_STORE_OUT : out std_logic; + DHDR_BUF_FULL_IN : in std_logic; + -- data buffers -- from raw_buf_stage + BUF_ADDR_OUT : out std_logic_vector(6 downto 0); + BUF_DONE_OUT : out std_logic; + BUF_TICK_IN : in std_logic_vector(15 downto 0); + BUF_START_IN : in std_logic_vector(15 downto 0); + -- raw data + BUF_0_DATA_IN : in std_logic_vector(37 downto 0); + BUF_1_DATA_IN : in std_logic_vector(37 downto 0); + BUF_2_DATA_IN : in std_logic_vector(37 downto 0); + BUF_3_DATA_IN : in std_logic_vector(37 downto 0); + BUF_4_DATA_IN : in std_logic_vector(37 downto 0); + BUF_5_DATA_IN : in std_logic_vector(37 downto 0); + BUF_6_DATA_IN : in std_logic_vector(37 downto 0); + BUF_7_DATA_IN : in std_logic_vector(37 downto 0); + BUF_8_DATA_IN : in std_logic_vector(37 downto 0); + BUF_9_DATA_IN : in std_logic_vector(37 downto 0); + BUF_10_DATA_IN : in std_logic_vector(37 downto 0); + BUF_11_DATA_IN : in std_logic_vector(37 downto 0); + BUF_12_DATA_IN : in std_logic_vector(37 downto 0); + BUF_13_DATA_IN : in std_logic_vector(37 downto 0); + BUF_14_DATA_IN : in std_logic_vector(37 downto 0); + BUF_15_DATA_IN : in std_logic_vector(37 downto 0); + -- Pedestal data + PED_ADDR_OUT : out std_logic_vector(6 downto 0); + PED_0_DATA_IN : in std_logic_vector(17 downto 0); + PED_1_DATA_IN : in std_logic_vector(17 downto 0); + PED_2_DATA_IN : in std_logic_vector(17 downto 0); + PED_3_DATA_IN : in std_logic_vector(17 downto 0); + PED_4_DATA_IN : in std_logic_vector(17 downto 0); + PED_5_DATA_IN : in std_logic_vector(17 downto 0); + PED_6_DATA_IN : in std_logic_vector(17 downto 0); + PED_7_DATA_IN : in std_logic_vector(17 downto 0); + PED_8_DATA_IN : in std_logic_vector(17 downto 0); + PED_9_DATA_IN : in std_logic_vector(17 downto 0); + PED_10_DATA_IN : in std_logic_vector(17 downto 0); + PED_11_DATA_IN : in std_logic_vector(17 downto 0); + PED_12_DATA_IN : in std_logic_vector(17 downto 0); + PED_13_DATA_IN : in std_logic_vector(17 downto 0); + PED_14_DATA_IN : in std_logic_vector(17 downto 0); + PED_15_DATA_IN : in std_logic_vector(17 downto 0); + -- Threshold data + THR_ADDR_OUT : out std_logic_vector(6 downto 0); + THR_0_DATA_IN : in std_logic_vector(17 downto 0); + THR_1_DATA_IN : in std_logic_vector(17 downto 0); + THR_2_DATA_IN : in std_logic_vector(17 downto 0); + THR_3_DATA_IN : in std_logic_vector(17 downto 0); + THR_4_DATA_IN : in std_logic_vector(17 downto 0); + THR_5_DATA_IN : in std_logic_vector(17 downto 0); + THR_6_DATA_IN : in std_logic_vector(17 downto 0); + THR_7_DATA_IN : in std_logic_vector(17 downto 0); + THR_8_DATA_IN : in std_logic_vector(17 downto 0); + THR_9_DATA_IN : in std_logic_vector(17 downto 0); + THR_10_DATA_IN : in std_logic_vector(17 downto 0); + THR_11_DATA_IN : in std_logic_vector(17 downto 0); + THR_12_DATA_IN : in std_logic_vector(17 downto 0); + THR_13_DATA_IN : in std_logic_vector(17 downto 0); + THR_14_DATA_IN : in std_logic_vector(17 downto 0); + THR_15_DATA_IN : in std_logic_vector(17 downto 0); + -- processed data + FIFO_START_OUT : out std_logic; + FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_WE_OUT : out std_logic_vector(15 downto 0); + FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of ped_corr_ctrl is + + -- state machine definitions + type STATES is (SLEEP,LOADFC,DELFC,CHECK,FULL,DEL0,NBERR,EMPTY,CHKFC,FCERR,CHKRW,RWERR,CHKAE,AEERR, + FINIT,FLOAD,FZERO,FREAD,FDONE,FDEL,FDEC,WREDS,ACKEDS,WHDR,EHDR,CCNT,CDEL0,CDEL1,DEL1,DEL2); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- signals + signal debug : std_logic_vector(15 downto 0); + signal bsm_x : std_logic_vector(7 downto 0); + + -- status signals from TOCs + signal buf_gooddata : std_logic_vector(15 downto 0); + signal buf_baddata : std_logic_vector(15 downto 0); + signal buf_nodata : std_logic_vector(15 downto 0); + signal buf_ready : std_logic_vector(15 downto 0); + + -- local frame counter + signal to_do_ctr : std_logic_vector(3 downto 0); + signal done_ctr : std_logic_vector(3 downto 0); + signal loc_frm_ctr : std_logic_vector(3 downto 0); + signal next_ld_frm_ctr : std_logic; + signal ld_frm_ctr : std_logic; -- load frame counter with EDS start value + signal next_ce_frm_ctr : std_logic; + signal ce_frm_ctr : std_logic; -- increment frame counter + signal next_last_frame : std_logic; + signal last_frame : std_logic; -- all frame buffers have been copied + signal next_cleaned_up : std_logic; + signal cleaned_up : std_logic; -- only relevant in case of errors + signal next_multi_frame : std_logic; + signal multi_frame : std_logic; -- more than one frame requested + signal next_do_hdr : std_logic; + signal do_hdr : std_logic; -- insert debug header (in case of common errors, in case of multiframe) + signal next_do_error : std_logic; + signal do_error : std_logic; -- insert debug header (in case of broken buffer only) + signal next_do_start : std_logic; + signal do_start : std_logic; -- start signal for one event processing + + -- buffer status signals, error signals from checkers + signal buffers_ready : std_logic; -- all buffers are ready for data transport + signal buffers_valid : std_logic; -- at least one buffer has valid data + signal frame_row_error : std_logic; + signal frame_apv_error : std_logic; + signal frame_ctr_error : std_logic; + + signal frame_busy : std_logic; -- from ALU + + -- Buffer read address counter, control signals + signal buf_addr : std_logic_vector(5 downto 0); -- buffer / pedestal read address + signal buf_half : std_logic; + signal next_buf_addr_ce : std_logic; + signal buf_addr_ce : std_logic; + signal next_buf_addr_rst : std_logic; + signal buf_addr_rst : std_logic; + signal next_buf_addr_init : std_logic; -- needed for THR + signal buf_addr_init : std_logic; + signal next_buf_addr_done : std_logic; + signal buf_addr_done : std_logic; + signal next_buf_done : std_logic; + signal buf_done : std_logic; + signal next_frame_valid : std_logic; + signal frame_valid : std_logic; + signal buf_frame_valid : std_logic; + signal raw_addr : std_logic_vector(6 downto 0); + signal buf_raw_addr : std_logic_vector(6 downto 0); + + signal thr_addr : std_logic_vector(6 downto 0); -- threshold read address + signal thr_addr_ce : std_logic; + signal thr_addr_rst : std_logic; + signal dly_thr_addr_ce : std_logic_vector(7 downto 0); + signal dly_thr_addr_rst : std_logic_vector(7 downto 0); + +-- signal ped_addr : std_logic_vector(6 downto 0); -- pedestal read address + + -- statemachine signals + signal next_wait_frames : std_logic; + signal wait_frames : std_logic; -- we are in the waiting phase for incoming frames + signal next_eds_wr : std_logic; + signal eds_wr : std_logic; -- copy current EDS into new buffer + signal next_eds_done : std_logic; + signal eds_done : std_logic; -- acknowledge and release old EDS + + -- generate needs arrays... + type raw_data_t is array (0 to 15) of std_logic_vector(37 downto 0); + signal raw_data : raw_data_t; + type fifo_data_t is array (0 to 15) of std_logic_vector(39 downto 0); + signal fifo_data : fifo_data_t; + type sc_data_t is array (0 to 15) of std_logic_vector(17 downto 0); + signal ped_data : sc_data_t; + signal thr_data : sc_data_t; + + signal fifo_we : std_logic_vector(15 downto 0); + + signal errors : std_logic_vector(3 downto 0); + + -- for summing up + signal next_small_0_sum : std_logic_vector(4 downto 0); + signal small_0_sum : std_logic_vector(4 downto 0); + signal next_small_1_sum : std_logic_vector(4 downto 0); + signal small_1_sum : std_logic_vector(4 downto 0); + signal small_sum : std_logic_vector(15 downto 0); + signal total_sum : std_logic_vector(15 downto 0); + signal reset_sum : std_logic; + + +begin + +--------------------------------------------------------------------------- +-- Aliasing the data streams +--------------------------------------------------------------------------- +raw_data(0) <= buf_0_data_in; +raw_data(1) <= buf_1_data_in; +raw_data(2) <= buf_2_data_in; +raw_data(3) <= buf_3_data_in; +raw_data(4) <= buf_4_data_in; +raw_data(5) <= buf_5_data_in; +raw_data(6) <= buf_6_data_in; +raw_data(7) <= buf_7_data_in; +raw_data(8) <= buf_8_data_in; +raw_data(9) <= buf_9_data_in; +raw_data(10) <= buf_10_data_in; +raw_data(11) <= buf_11_data_in; +raw_data(12) <= buf_12_data_in; +raw_data(13) <= buf_13_data_in; +raw_data(14) <= buf_14_data_in; +raw_data(15) <= buf_15_data_in; + +ped_data(0) <= ped_0_data_in; +ped_data(1) <= ped_1_data_in; +ped_data(2) <= ped_2_data_in; +ped_data(3) <= ped_3_data_in; +ped_data(4) <= ped_4_data_in; +ped_data(5) <= ped_5_data_in; +ped_data(6) <= ped_6_data_in; +ped_data(7) <= ped_7_data_in; +ped_data(8) <= ped_8_data_in; +ped_data(9) <= ped_9_data_in; +ped_data(10) <= ped_10_data_in; +ped_data(11) <= ped_11_data_in; +ped_data(12) <= ped_12_data_in; +ped_data(13) <= ped_13_data_in; +ped_data(14) <= ped_14_data_in; +ped_data(15) <= ped_15_data_in; + +thr_data(0) <= thr_0_data_in; +thr_data(1) <= thr_1_data_in; +thr_data(2) <= thr_2_data_in; +thr_data(3) <= thr_3_data_in; +thr_data(4) <= thr_4_data_in; +thr_data(5) <= thr_5_data_in; +thr_data(6) <= thr_6_data_in; +thr_data(7) <= thr_7_data_in; +thr_data(8) <= thr_8_data_in; +thr_data(9) <= thr_9_data_in; +thr_data(10) <= thr_10_data_in; +thr_data(11) <= thr_11_data_in; +thr_data(12) <= thr_12_data_in; +thr_data(13) <= thr_13_data_in; +thr_data(14) <= thr_14_data_in; +thr_data(15) <= thr_15_data_in; + + +--------------------------------------------------------------------------- +-- framecounter check, must be done once per frame +--------------------------------------------------------------------------- +THE_FRMCTR_CHECK: frmctr_check +port map( CLK_IN => clk_in, + GOODDATA_IN => buf_gooddata, + FRAMECOUNTER_IN => loc_frm_ctr, + FRM_NR_0_IN => raw_data(0)(17 downto 14), + FRM_NR_1_IN => raw_data(1)(17 downto 14), + FRM_NR_2_IN => raw_data(2)(17 downto 14), + FRM_NR_3_IN => raw_data(3)(17 downto 14), + FRM_NR_4_IN => raw_data(4)(17 downto 14), + FRM_NR_5_IN => raw_data(5)(17 downto 14), + FRM_NR_6_IN => raw_data(6)(17 downto 14), + FRM_NR_7_IN => raw_data(7)(17 downto 14), + FRM_NR_8_IN => raw_data(8)(17 downto 14), + FRM_NR_9_IN => raw_data(9)(17 downto 14), + FRM_NR_10_IN => raw_data(10)(17 downto 14), + FRM_NR_11_IN => raw_data(11)(17 downto 14), + FRM_NR_12_IN => raw_data(12)(17 downto 14), + FRM_NR_13_IN => raw_data(13)(17 downto 14), + FRM_NR_14_IN => raw_data(14)(17 downto 14), + FRM_NR_15_IN => raw_data(15)(17 downto 14), + FRC_ERROR_OUT => frame_ctr_error, -- BUG + DBG_OUT => open + ); + +--------------------------------------------------------------------------- +-- framewise ROW and ERROR checker +--------------------------------------------------------------------------- +THE_REF_ROW_SEL: ref_row_sel +port map( CLK_IN => clk_in, + READY_IN => buf_ready, + GOODDATA_IN => buf_gooddata, + FRAME_0_IN => raw_data(0)(29 downto 18), + FRAME_1_IN => raw_data(1)(29 downto 18), + FRAME_2_IN => raw_data(2)(29 downto 18), + FRAME_3_IN => raw_data(3)(29 downto 18), + FRAME_4_IN => raw_data(4)(29 downto 18), + FRAME_5_IN => raw_data(5)(29 downto 18), + FRAME_6_IN => raw_data(6)(29 downto 18), + FRAME_7_IN => raw_data(7)(29 downto 18), + FRAME_8_IN => raw_data(8)(29 downto 18), + FRAME_9_IN => raw_data(9)(29 downto 18), + FRAME_10_IN => raw_data(10)(29 downto 18), + FRAME_11_IN => raw_data(11)(29 downto 18), + FRAME_12_IN => raw_data(12)(29 downto 18), + FRAME_13_IN => raw_data(13)(29 downto 18), + FRAME_14_IN => raw_data(14)(29 downto 18), + FRAME_15_IN => raw_data(15)(29 downto 18), + VALID_BUFS_OUT => buffers_valid, + READY_OUT => buffers_ready, + ROW_ERROR_OUT => frame_row_error, + APV_ERROR_OUT => frame_apv_error, + APV_ERROR_BITS_OUT => open, -- BUGBUGBUG + REF_ROW_OUT => open, -- selected reference row + DBG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Statemachine +--------------------------------------------------------------------------- + +-- state registers +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + wait_frames <= '0'; + ld_frm_ctr <= '0'; + ce_frm_ctr <= '0'; + eds_done <= '0'; + eds_wr <= '0'; + buf_addr_rst <= '0'; + buf_addr_init <= '0'; + buf_addr_ce <= '0'; + frame_valid <= '0'; + do_hdr <= '0'; + do_error <= '0'; + do_start <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + wait_frames <= next_wait_frames; + ld_frm_ctr <= next_ld_frm_ctr; + ce_frm_ctr <= next_ce_frm_ctr; + buf_done <= next_buf_done; + eds_done <= next_eds_done; + eds_wr <= next_eds_wr; + buf_addr_rst <= next_buf_addr_rst; + buf_addr_init <= next_buf_addr_init; + buf_addr_ce <= next_buf_addr_ce; + frame_valid <= next_frame_valid; + do_hdr <= next_do_hdr; + do_error <= next_do_error; + do_start <= next_do_start; + end if; + end if; +end process STATE_MEM; + +-- Error pattern +errors(3) <= not buffers_valid; +errors(2) <= frame_ctr_error; +errors(1) <= frame_row_error; +errors(0) <= frame_apv_error; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, eds_avail_in, dhdr_buf_full_in, last_frame, multi_frame, frame_busy, + buffers_ready, buffers_valid, frame_ctr_error, frame_row_error, frame_apv_error, + buf_addr_done, buf_half ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + next_wait_frames <= '0'; + next_ld_frm_ctr <= '0'; + next_ce_frm_ctr <= '0'; + next_buf_done <= '0'; + next_eds_done <= '0'; + next_eds_wr <= '0'; + next_buf_addr_rst <= '0'; + next_buf_addr_init <= '0'; + next_buf_addr_ce <= '0'; + next_frame_valid <= '0'; + next_do_hdr <= '0'; + next_do_error <= '0'; + next_do_start <= '0'; + case CURRENT_STATE is + when SLEEP => if( (eds_avail_in = '1') and (dhdr_buf_full_in = '0') ) then + NEXT_STATE <= LOADFC; + next_ld_frm_ctr <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when LOADFC => NEXT_STATE <= DELFC; + next_do_start <= '1'; + when DELFC => NEXT_STATE <= CHECK; + when CHECK => if( last_frame = '0' ) then + NEXT_STATE <= FULL; + next_wait_frames <= '1'; + else + NEXT_STATE <= EMPTY; + end if; + when EMPTY => NEXT_STATE <= WREDS; + next_eds_wr <= '1'; + when FULL => if( buffers_ready = '1' ) then + NEXT_STATE <= DEL0; + next_do_error <= '1'; -- here broken channels deliver a "I DON'T FEEL GOOD" word... + else + NEXT_STATE <= FULL; + next_wait_frames <= '1'; + end if; + when DEL0 => if ( buffers_valid = '1' ) then + NEXT_STATE <= CHKFC; + else + NEXT_STATE <= NBERR; + end if; + when CHKFC => if( frame_ctr_error = '0' ) then + NEXT_STATE <= CHKRW; + else + NEXT_STATE <= FCERR; + end if; + when CHKRW => if( frame_row_error = '0' ) then + NEXT_STATE <= CHKAE; + else + NEXT_STATE <= RWERR; + end if; + when CHKAE => if ( (frame_apv_error = '0') and (multi_frame = '1') ) then + NEXT_STATE <= WHDR; + next_do_hdr <= '1'; + elsif( (frame_apv_error = '0') and (multi_frame = '0') ) then + NEXT_STATE <= FINIT; + next_buf_addr_rst <= '1'; + else + NEXT_STATE <= AEERR; + end if; + when WHDR => NEXT_STATE <= FINIT; + next_buf_addr_rst <= '1'; + when FINIT => NEXT_STATE <= FLOAD; -- load address x"01"; + next_buf_addr_ce <= '1'; + when FLOAD => NEXT_STATE <= FZERO; -- load address x"00"; + next_buf_addr_rst <= '1'; + next_buf_addr_init <= not buf_half; + when FZERO => NEXT_STATE <= FREAD; + next_buf_addr_ce <= '1'; + when FREAD => if ( (buf_addr_done = '1') and (buf_half = '1') ) then + NEXT_STATE <= FDONE; + next_ce_frm_ctr <= '1'; + next_buf_done <= '1'; + next_frame_valid <= '1'; + elsif( (buf_addr_done = '1') and (buf_half = '0') ) then + NEXT_STATE <= FINIT; + next_frame_valid <= '1'; + else + NEXT_STATE <= FREAD; -- read buffer completely + next_buf_addr_ce <= '1'; + next_frame_valid <= '1'; + end if; + when FDONE => if( frame_busy = '1' ) then + NEXT_STATE <= FDONE; + else + NEXT_STATE <= FDEL; + end if; + when FDEL => NEXT_STATE <= FDEC; + when FDEC => if( last_frame = '1' ) then + NEXT_STATE <= WREDS; -- copy current EDS to new buffer + next_eds_wr <= '1'; + else + NEXT_STATE <= DEL0; -- only for multiframe readout, will not work (needs headers!!!) + end if; + when WREDS => NEXT_STATE <= ACKEDS; -- release old EDS + next_eds_done <= '1'; + when ACKEDS => NEXT_STATE <= DEL1; + when DEL1 => NEXT_STATE <= DEL2; + when DEL2 => NEXT_STATE <= SLEEP; + + when NBERR => NEXT_STATE <= EHDR; + next_do_hdr <= '1'; + when FCERR => NEXT_STATE <= EHDR; + next_do_hdr <= '1'; + when RWERR => NEXT_STATE <= EHDR; + next_do_hdr <= '1'; + when AEERR => NEXT_STATE <= EHDR; + next_do_hdr <= '1'; + when EHDR => if( last_frame = '1' ) then + NEXT_STATE <= WREDS; + next_eds_wr <= '1'; + else + NEXT_STATE <= CCNT; + next_ce_frm_ctr <= '1'; + next_buf_done <= '1'; + end if; + when CCNT => NEXT_STATE <= CDEL0; + when CDEL0 => NEXT_STATE <= CDEL1; + when CDEL1 => if( last_frame = '1' ) then + NEXT_STATE <= WREDS; + next_eds_wr <= '1'; + else + NEXT_STATE <= EHDR; + next_do_hdr <= '1'; + end if; + when others => NEXT_STATE <= SLEEP; + end case; +end process STATE_TRANSFORM; + +-- state decoding (ONLY FOR DEBUGGING!) +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SLEEP => bsm_x <= x"00"; + when LOADFC => bsm_x <= x"01"; + when DELFC => bsm_x <= x"02"; + when CHECK => bsm_x <= x"03"; + when FULL => bsm_x <= x"04"; + when EMPTY => bsm_x <= x"05"; + when NBERR => bsm_x <= x"06"; + when CHKFC => bsm_x <= x"07"; + when FCERR => bsm_x <= x"08"; + when CHKRW => bsm_x <= x"09"; + when RWERR => bsm_x <= x"0a"; + when CHKAE => bsm_x <= x"0b"; + when AEERR => bsm_x <= x"0c"; + when FINIT => bsm_x <= x"0d"; + when FLOAD => bsm_x <= x"0e"; + when FZERO => bsm_x <= x"0f"; + when FREAD => bsm_x <= x"10"; + when FDONE => bsm_x <= x"11"; + when FDEL => bsm_x <= x"12"; + when FDEC => bsm_x <= x"13"; + when WREDS => bsm_x <= x"14"; + when ACKEDS => bsm_x <= x"15"; + when EHDR => bsm_x <= x"16"; + when CDEL0 => bsm_x <= x"17"; + when CDEL1 => bsm_x <= x"18"; + when CCNT => bsm_x <= x"19"; + when DEL0 => bsm_x <= x"20"; + when DEL1 => bsm_x <= x"21"; + when DEL2 => bsm_x <= x"22"; + when WHDR => bsm_x <= x"23"; + when others => bsm_x <= x"ff"; + end case; +end process STATE_DECODE; + +--------------------------------------------------------------------------- +-- Buffer address counter, fetches raw data and pedestal values from EBRs +--------------------------------------------------------------------------- +THE_BUF_ADDR_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (buf_addr_rst = '1') or (reset_in = '1') ) then + buf_addr <= (others => '0'); + elsif( buf_addr_ce = '1' ) then + buf_addr <= buf_addr + 1; + end if; + end if; +end process THE_BUF_ADDR_COUNTER_PROC; + +next_buf_addr_done <= '1' when ( buf_addr = "111110" ) else '0'; + +THE_HALF_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (ld_frm_ctr = '1') or (reset_in = '1') ) then + buf_half <= '0'; + elsif( (buf_addr_done = '1') and (buf_half = '0') ) then + buf_half <= '1'; + elsif( (buf_addr_done = '1') and (buf_half = '1') ) then + buf_half <= '0'; + end if; + end if; +end process THE_HALF_PROC; + +raw_addr <= buf_half & buf_addr; + +--------------------------------------------------------------------------- +-- threshold address counter +--------------------------------------------------------------------------- +THE_THR_ADDR_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( (thr_addr_rst = '1') or (reset_in = '1') ) then + thr_addr <= (others => '0'); + elsif( thr_addr_ce = '1' ) then + thr_addr <= thr_addr + 1; + end if; + end if; +end process THE_THR_ADDR_COUNTER_PROC; + +-- was '3' +thr_addr_ce <= dly_thr_addr_ce(2); +thr_addr_rst <= dly_thr_addr_rst(2); + +--------------------------------------------------------------------------- +-- local frame counter, loaded / counted by SM for checking +--------------------------------------------------------------------------- +THE_LOC_FRAME_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + loc_frm_ctr <= (others => '0'); + to_do_ctr <= (others => '0'); + done_ctr <= (others => '0'); + elsif( ld_frm_ctr = '1' ) then + loc_frm_ctr <= eds_data_in(39 downto 36); + to_do_ctr <= eds_data_in(35 downto 32); + done_ctr <= (others => '0'); + elsif( ce_frm_ctr = '1' ) then + loc_frm_ctr <= loc_frm_ctr + 1; -- local frame counter + to_do_ctr <= to_do_ctr - 1; -- frames still to process + done_ctr <= done_ctr + 1; -- frames already processed + end if; + end if; +end process THE_LOC_FRAME_COUNTER_PROC; + +-- check if we have still buffers to copy +next_last_frame <= '1' when ( to_do_ctr = x"0" ) else '0'; + +-- check if we have clean up the mess in case of error +next_cleaned_up <= '1' when ( done_ctr = x"0" ) else '0'; + +-- insert administration words if more than one frame is requested (MULTIFRAME) +next_multi_frame <= '1' when ( eds_data_in(35 downto 32) > x"1" ) else '0'; + +--------------------------------------------------------------------------- +-- synchronizing process +--------------------------------------------------------------------------- +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + last_frame <= next_last_frame; + multi_frame <= next_multi_frame; + cleaned_up <= next_cleaned_up; + buf_addr_done <= next_buf_addr_done; + buf_frame_valid <= frame_valid; + buf_raw_addr <= raw_addr; + small_0_sum <= next_small_0_sum; + small_1_sum <= next_small_1_sum; + dly_thr_addr_ce(7 downto 0) <= dly_thr_addr_ce(6 downto 0) & buf_addr_ce; + dly_thr_addr_rst(7 downto 0) <= dly_thr_addr_rst(6 downto 0) & buf_addr_init; + end if; +end process THE_SYNC_PROC; + +--------------------------------------------------------------------------- +-- DHDR information assembly +--------------------------------------------------------------------------- +dhdr_data_out(31 downto 29) <= "000"; -- reserved bits +dhdr_data_out(28) <= '1'; -- packbit +dhdr_data_out(27 downto 24) <= eds_data_in(7 downto 4); +dhdr_data_out(23 downto 16) <= eds_data_in(15 downto 8); +dhdr_data_out(15 downto 0) <= eds_data_in(31 downto 16); + +dhdr_length_out <= total_sum; + +dhdr_store_out <= eds_wr; + +--########################################################################## +--########################################################################## + +-- generate TimeOutCounters for all 16 APVs +GEN_TOC: for i in 0 to 15 generate + THE_BUF_TOC: buf_toc + port map( CLK_IN => clk_in, + RESET_IN => reset_in, + BUF_TICK_IN => buf_tick_in(i), + BUF_START_IN => buf_start_in(i), + WAITFRAME_IN => wait_frames, + FRAMES_REQD_IN => eds_data_in(35 downto 32), -- always the same + BUF_LVL_IN => raw_data(i)(37 downto 30), + GOODDATA_OUT => buf_gooddata(i), + BADDATA_OUT => buf_baddata(i), + NODATA_OUT => buf_nodata(i), + READY_OUT => buf_ready(i), + BSM_OUT => open, + DBG_OUT => open + ); +end generate GEN_TOC; + +-- generate ALUs for all 16 APV data streams +GEN_ALU: for i in 0 to 15 generate + THE_ALU: apv_pc_nc_alu + port map( CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => ld_frm_ctr, + MAX_FRAMES_IN => eds_data_in(35 downto 32), + CURR_FRAME_IN => done_ctr, + LOC_FRM_CTR_IN => loc_frm_ctr, -- DEBUG + EDS_FRM_CTR_IN => eds_data_in(39 downto 36), -- DEBUG + BUF_GOOD_IN => buf_gooddata(i), + BUF_BAD_IN => buf_baddata(i), + BUF_IGNORE_IN => buf_nodata(i), + ERROR_IN => errors, + DO_HEADER_IN => do_hdr, + DO_ERROR_IN => do_error, + EVT_TYPE_IN => eds_data_in(6 downto 4), --evt_type_in, -- just a quick fix, does not work lateron! + RAW_ADDR_IN => buf_raw_addr, -- delayed by one cycle + RAW_DATA_IN => raw_data(i), + PED_DATA_IN => ped_data(i), + THR_DATA_IN => thr_data(i), + FRAME_IN => buf_frame_valid, -- delayed by one cycle + FIFO_DATA_OUT => fifo_data(i)(26 downto 0), + WE_OUT => fifo_we(i), + COUNT_OUT => fifo_data(i)(36 downto 27), + ANYDATA_OUT => fifo_data(i)(37), + DBG_OUT => open + ); + fifo_data(i)(39) <= '0'; + fifo_data(i)(38) <= '0'; +end generate GEN_ALU; + +frame_busy <= fifo_data(0)(26); -- WORKAROUND! + +--################################################################################## +--------------------------------------------------------------------------- +-- Sum up all data words of one event +--------------------------------------------------------------------------- +THE_DECODER_0: decoder_8bit +port map( ADDRESS => fifo_we(7 downto 0), + Q => next_small_0_sum(3 downto 0) + ); +next_small_0_sum(4) <= '0'; + +THE_DECODER_1: decoder_8bit +port map( ADDRESS => fifo_we(15 downto 8), + Q => next_small_1_sum(3 downto 0) + ); +next_small_1_sum(4) <= '0'; + +reset_sum <= reset_in or ld_frm_ctr; + +THE_FIRST_ADDER: adder_5bit +port map( DATAA => small_0_sum, + DATAB => small_1_sum, + CLOCK => clk_in, + RESET => reset_sum, -- BUG + CLOCKEN => '1', + RESULT => small_sum(4 downto 0) + ); +small_sum(15 downto 5) <= (others => '0'); + +THE_ACCUMULATOR: adder_16bit +port map( DATAA => small_sum, + DATAB => total_sum, + CLOCK => clk_in, + RESET => reset_sum, -- BUG + CLOCKEN => '1', + RESULT => total_sum + ); + +fifo_we_out <= fifo_we; +fifo_start_out <= do_start; +fifo_done_out <= eds_wr; +--################################################################################## + + +-- Aliasing the data output +fifo_0_data_out <= fifo_data(0); +fifo_1_data_out <= fifo_data(1); +fifo_2_data_out <= fifo_data(2); +fifo_3_data_out <= fifo_data(3); +fifo_4_data_out <= fifo_data(4); +fifo_5_data_out <= fifo_data(5); +fifo_6_data_out <= fifo_data(6); +fifo_7_data_out <= fifo_data(7); +fifo_8_data_out <= fifo_data(8); +fifo_9_data_out <= fifo_data(9); +fifo_10_data_out <= fifo_data(10); +fifo_11_data_out <= fifo_data(11); +fifo_12_data_out <= fifo_data(12); +fifo_13_data_out <= fifo_data(13); +fifo_14_data_out <= fifo_data(14); +fifo_15_data_out <= fifo_data(15); + +--------------------------------------------------------------------------- +--------------------------------------------------------------------------- +debug(15) <= frame_valid; +debug(14) <= buf_frame_valid; +debug(13 downto 0) <= (others => '0'); +--debug(15) <= last_frame; +--debug(14) <= cleaned_up; +--debug(13 downto 12) <= (others => '0'); +--debug(11 downto 8) <= loc_frm_ctr; +--debug(7 downto 4) <= to_do_ctr; +--debug(3 downto 0) <= done_ctr; +--------------------------------------------------------------------------- +--------------------------------------------------------------------------- + + +--------------------------------------------------------------------------- +-- Output signals +--------------------------------------------------------------------------- +eds_done_out <= eds_done; +buf_done_out <= buf_done; +buf_addr_out <= raw_addr; +ped_addr_out <= raw_addr; +thr_addr_out <= thr_addr; + +--------------------------------------------------------------------------- +-- DEBUG signals +--------------------------------------------------------------------------- +dbg_bsm_out <= bsm_x; +dbg_out <= debug; + +end behavioral; + + + + + diff --git a/src/ped_thr_mem.mem b/src/ped_thr_mem.mem new file mode 100644 index 0000000..68576c7 --- /dev/null +++ b/src/ped_thr_mem.mem @@ -0,0 +1,22 @@ +#Format=AddrHex +#Depth=1024 +#Width=18 +#AddrRadix=3 +#DataRadix=3 +#Data +000: 00000 00000 00000 00000 00000 00000 00000 00000 +008: 00000 00000 00000 00000 00000 00000 00000 00000 +010: 00000 00000 00000 00000 00000 00000 00000 00000 +018: 00000 00000 00000 00000 00000 00000 00000 00000 +020: 00000 00000 00000 00000 00000 00000 00000 00000 +028: 00000 00000 00000 00000 00000 00000 00000 00000 +030: 00000 00000 00000 00000 00000 00000 00000 00000 +038: 00000 00000 00000 00000 00000 00000 00000 00000 +040: 00000 00000 00000 00000 00000 00000 00000 00000 +048: 00000 00000 00000 00000 00000 00000 00000 00000 +050: 00000 00000 00000 00000 00000 00000 00000 00000 +058: 00000 00000 00000 00000 00000 00000 00000 00000 +060: 00000 00000 00000 00000 00000 00000 00000 00000 +068: 00000 00000 00000 00000 00000 00000 00000 00000 +070: 00000 00000 00000 00000 00000 00000 00000 00000 +078: 00000 00000 00000 00000 00000 00000 00000 00000 diff --git a/src/ped_thr_true.lpc b/src/ped_thr_true.lpc new file mode 100644 index 0000000..2464f40 --- /dev/null +++ b/src/ped_thr_true.lpc @@ -0,0 +1,57 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP_TRUE +CoreRevision=7.1 +ModuleName=ped_thr_true +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/14/2009 +Time=12:54:09 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +AAddress=128 +BAddress=128 +AData=18 +BData=18 +enByte=0 +ByteSize=9 +AadPipeline=0 +BadPipeline=0 +AinPipeline=0 +BinPipeline=0 +AoutPipeline=1 +BoutPipeline=1 +AMOR=0 +BMOR=0 +AInData=Registered +BInData=Registered +AAdControl=Registered +BAdControl=Registered +MemFile= +MemFormat=bin +Reset=Sync +GSR=Enabled +WriteA=Normal +WriteB=Normal +Pad=0 +EnECC=0 +Optimization=Speed +Pipeline=0 diff --git a/src/ped_thr_true.srp b/src/ped_thr_true.srp new file mode 100644 index 0000000..e67819a --- /dev/null +++ b/src/ped_thr_true.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 12:54:09 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n ped_thr_true -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 7 -widtha 18 -baddr_width 7 -widthb 18 -anum_words 128 -bnum_words 128 -outdataA REGISTERED -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e + Circuit name : ped_thr_true + Module type : RAM_DP_TRUE + Module Version : 7.1 + Ports : + Inputs : DataInA[17:0], DataInB[17:0], AddressA[6:0], AddressB[6:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB + Outputs : QA[17:0], QB[17:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : ped_thr_true.vhd + VHDL template : ped_thr_true_tmpl.vhd + VHDL testbench : tb_ped_thr_true_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : ped_thr_true.srp + Element Usage : + DP16KB : 1 + Estimated Resource Usage: + EBR : 1 diff --git a/src/ped_thr_true.vhd b/src/ped_thr_true.vhd new file mode 100644 index 0000000..7fa636b --- /dev/null +++ b/src/ped_thr_true.vhd @@ -0,0 +1,199 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 7.1 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 18 -rdata_width 18 -num_rows 128 -outdataA REGISTERED -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e + +-- Mon Sep 14 12:54:09 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity ped_thr_true is + port ( + DataInA: in std_logic_vector(17 downto 0); + DataInB: in std_logic_vector(17 downto 0); + AddressA: in std_logic_vector(6 downto 0); + AddressB: in std_logic_vector(6 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(17 downto 0); + QB: out std_logic_vector(17 downto 0)); +end ped_thr_true; + +architecture Structure of ped_thr_true is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute GSR : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute MEM_LPC_FILE of ped_thr_true_0_0_0 : label is "ped_thr_true.lpc"; + attribute MEM_INIT_FILE of ped_thr_true_0_0_0 : label is ""; + attribute CSDECODE_B of ped_thr_true_0_0_0 : label is "0b000"; + attribute CSDECODE_A of ped_thr_true_0_0_0 : label is "0b000"; + attribute WRITEMODE_B of ped_thr_true_0_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of ped_thr_true_0_0_0 : label is "NORMAL"; + attribute GSR of ped_thr_true_0_0_0 : label is "DISABLED"; + attribute RESETMODE of ped_thr_true_0_0_0 : label is "SYNC"; + attribute REGMODE_B of ped_thr_true_0_0_0 : label is "OUTREG"; + attribute REGMODE_A of ped_thr_true_0_0_0 : label is "OUTREG"; + attribute DATA_WIDTH_B of ped_thr_true_0_0_0 : label is "18"; + attribute DATA_WIDTH_A of ped_thr_true_0_0_0 : label is "18"; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + ped_thr_true_0_0_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), + DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5), + DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8), + DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11), + DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14), + DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17), + ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, + ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), + ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), + ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>scuba_vlo, + ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, + CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0), + DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3), + DIB4=>DataInB(4), DIB5=>DataInB(5), DIB6=>DataInB(6), + DIB7=>DataInB(7), DIB8=>DataInB(8), DIB9=>DataInB(9), + DIB10=>DataInB(10), DIB11=>DataInB(11), DIB12=>DataInB(12), + DIB13=>DataInB(13), DIB14=>DataInB(14), DIB15=>DataInB(15), + DIB16=>DataInB(16), DIB17=>DataInB(17), ADB0=>scuba_vhi, + ADB1=>scuba_vhi, ADB2=>scuba_vlo, ADB3=>scuba_vlo, + ADB4=>AddressB(0), ADB5=>AddressB(1), ADB6=>AddressB(2), + ADB7=>AddressB(3), ADB8=>AddressB(4), ADB9=>AddressB(5), + ADB10=>AddressB(6), ADB11=>scuba_vlo, ADB12=>scuba_vlo, + ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2), + DOA3=>QA(3), DOA4=>QA(4), DOA5=>QA(5), DOA6=>QA(6), + DOA7=>QA(7), DOA8=>QA(8), DOA9=>QA(9), DOA10=>QA(10), + DOA11=>QA(11), DOA12=>QA(12), DOA13=>QA(13), DOA14=>QA(14), + DOA15=>QA(15), DOA16=>QA(16), DOA17=>QA(17), DOB0=>QB(0), + DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>QB(4), + DOB5=>QB(5), DOB6=>QB(6), DOB7=>QB(7), DOB8=>QB(8), + DOB9=>QB(9), DOB10=>QB(10), DOB11=>QB(11), DOB12=>QB(12), + DOB13=>QB(13), DOB14=>QB(14), DOB15=>QB(15), DOB16=>QB(16), + DOB17=>QB(17)); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of ped_thr_true is + for Structure + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/ped_thr_true_tmpl.vhd b/src/ped_thr_true_tmpl.vhd new file mode 100644 index 0000000..53666ec --- /dev/null +++ b/src/ped_thr_true_tmpl.vhd @@ -0,0 +1,23 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 7.1 +-- Mon Sep 14 12:54:09 2009 + +-- parameterized module component declaration +component ped_thr_true + port (DataInA: in std_logic_vector(17 downto 0); + DataInB: in std_logic_vector(17 downto 0); + AddressA: in std_logic_vector(6 downto 0); + AddressB: in std_logic_vector(6 downto 0); + ClockA: in std_logic; ClockB: in std_logic; + ClockEnA: in std_logic; ClockEnB: in std_logic; + WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic; + ResetB: in std_logic; QA: out std_logic_vector(17 downto 0); + QB: out std_logic_vector(17 downto 0)); +end component; + +-- parameterized module component instance +__ : ped_thr_true + port map (DataInA(17 downto 0)=>__, DataInB(17 downto 0)=>__, + AddressA(6 downto 0)=>__, AddressB(6 downto 0)=>__, ClockA=>__, + ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__, + ResetB=>__, QA(17 downto 0)=>__, QB(17 downto 0)=>__); diff --git a/src/pll_40m.lpc b/src/pll_40m.lpc new file mode 100644 index 0000000..46760a8 --- /dev/null +++ b/src/pll_40m.lpc @@ -0,0 +1,56 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=4.2 +ModuleName=pll_40m +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/30/2009 +Time=10:01:30 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=100 +OFrq=40.000000 +KFrq=100.000000 +U_OFrq=40 +U_KFrq=50 +OP_Tol=0.0 +OK_Tol=0.0 +Div=5 +Mult=2 +Post=32 +SecD=2 +fb_mode=CLKOP +PhaseDuty=Dynamic +DelayControl=GPLL_NO_DELAY +External=DISABLED +PCDR=1 +ClkOPBp=0 +EnCLKOS=1 +ClkOSBp=0 +Phase=0.0 +Duty=8 +DPD=50% Duty +EnCLKOK=0 +ClkOKBp=0 +ClkRst=0 diff --git a/src/pll_40m.vhd b/src/pll_40m.vhd new file mode 100644 index 0000000..e8a3468 --- /dev/null +++ b/src/pll_40m.vhd @@ -0,0 +1,137 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 4.2 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n pll_40m -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl DYNAMIC -fclkop 40 -fclkop_tol 0.0 -delay_cntl GPLL_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -phaseadj 0.0 -duty 8 -duty50 -noclkok -use_rst -e + +-- Fri Jan 30 10:01:31 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity pll_40m is + port ( + CLK: in std_logic; + RESET: in std_logic; + DPAMODE: in std_logic; + DPHASE0: in std_logic; + DPHASE1: in std_logic; + DPHASE2: in std_logic; + DPHASE3: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + LOCK: out std_logic); + attribute dont_touch : string; + attribute dont_touch of pll_40m : entity is "true"; +end pll_40m; + +architecture Structure of pll_40m is + + -- internal signal declarations + signal DPHASE3_inv: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + signal CLK_t: std_logic; + + -- local component declarations + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component EPLLD + -- synopsys translate_off + generic (PLLCAP : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + DUTY : in Integer; PHASEADJ : in String; + PHASE_CNTL : in String; CLKOK_DIV : in Integer; + CLKFB_DIV : in Integer; CLKOP_DIV : in Integer; + CLKI_DIV : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; + CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + attribute PLLCAP : string; + attribute PLLTYPE : string; + attribute CLKOK_BYPASS : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute CLKOK_DIV : string; + attribute CLKOS_BYPASS : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute CLKOP_BYPASS : string; + attribute PHASE_CNTL : string; + attribute FDEL : string; + attribute DUTY : string; + attribute PHASEADJ : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute FIN : string; + attribute PLLCAP of PLLDInst_0 : label is "DISABLED"; + attribute PLLTYPE of PLLDInst_0 : label is "GPLL"; + attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000"; + attribute CLKOK_DIV of PLLDInst_0 : label is "2"; + attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOS of PLLDInst_0 : label is "40.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "40.000000"; + attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute PHASE_CNTL of PLLDInst_0 : label is "DYNAMIC"; + attribute FDEL of PLLDInst_0 : label is "0"; + attribute DUTY of PLLDInst_0 : label is "8"; + attribute PHASEADJ of PLLDInst_0 : label is "0.0"; + attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "100.000000"; + attribute CLKOP_DIV of PLLDInst_0 : label is "32"; + attribute CLKFB_DIV of PLLDInst_0 : label is "2"; + attribute CLKI_DIV of PLLDInst_0 : label is "5"; + attribute FIN of PLLDInst_0 : label is "100.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + INV_0: INV + port map (A=>DPHASE3, Z=>DPHASE3_inv); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLDInst_0: EPLLD + -- synopsys translate_off + generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED", + CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + PHASE_CNTL=> "DYNAMIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 32, + CLKFB_DIV=> 2, CLKI_DIV=> 5) + -- synopsys translate_on + port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>RESET, + RSTK=>scuba_vlo, DPAMODE=>DPAMODE, DRPAI3=>DPHASE3, + DRPAI2=>DPHASE2, DRPAI1=>DPHASE1, DRPAI0=>DPHASE0, + DFPAI3=>DPHASE3_inv, DFPAI2=>DPHASE2, DFPAI1=>DPHASE1, + DFPAI0=>DPHASE0, CLKOP=>CLKOP_t, CLKOS=>CLKOS, CLKOK=>open, + LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; + CLK_t <= CLK; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of pll_40m is + for Structure + for all:INV use entity ecp2m.INV(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:EPLLD use entity ecp2m.EPLLD(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/pll_40m_tmpl.vhd b/src/pll_40m_tmpl.vhd new file mode 100644 index 0000000..786a886 --- /dev/null +++ b/src/pll_40m_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 4.2 +-- Fri Jan 30 10:01:31 2009 + +-- parameterized module component declaration +component pll_40m + port (CLK: in std_logic; RESET: in std_logic; DPAMODE: in std_logic; + DPHASE0: in std_logic; DPHASE1: in std_logic; DPHASE2: in std_logic; + DPHASE3: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; + LOCK: out std_logic); +end component; + +-- parameterized module component instance +__ : pll_40m + port map (CLK=>__, RESET=>__, DPAMODE=>__, DPHASE0=>__, DPHASE1=>__, + DPHASE2=>__, DPHASE3=>__, CLKOP=>__, CLKOS=>__, LOCK=>__); diff --git a/src/pulse_stretch.vhd b/src/pulse_stretch.vhd new file mode 100644 index 0000000..df8b3a8 --- /dev/null +++ b/src/pulse_stretch.vhd @@ -0,0 +1,62 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity pulse_stretch is + port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + PULSE_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of pulse_stretch is + + -- normal signals + signal pulse_cnt : std_logic_vector(3 downto 0); + signal pulse_cnt_ce : std_logic; + signal pulse_x : std_logic; + signal pulse : std_logic; + +begin + +-- Pulse length counter +THE_PULSE_LENGTH_CTR: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + pulse_cnt <= (others => '0'); + elsif( pulse_cnt_ce = '1' ) then + pulse_cnt <= pulse_cnt + 1; + end if; + end if; +end process THE_PULSE_LENGTH_CTR; + +pulse_cnt_ce <= '1' when ( (start_in = '1') or (pulse_cnt /= x"0") ) else '0'; + +pulse_x <= '1' when ( (pulse_cnt(2) = '1') or (pulse_cnt(3) = '1') ) else '0'; + +-- Syanchronize it +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + pulse <= '0'; + else + pulse <= pulse_x; + end if; + end if; +end process THE_SYNC_PROC; + + +-- output signals +pulse_out <= pulse; +debug_out(15 downto 4) <= (others => '0'); +debug_out(3 downto 0) <= pulse_cnt; + +end behavioral; diff --git a/src/pulse_sync.vhd b/src/pulse_sync.vhd new file mode 100644 index 0000000..70164f6 --- /dev/null +++ b/src/pulse_sync.vhd @@ -0,0 +1,71 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity pulse_sync is + port( CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic + ); +end; + +architecture behavioral of pulse_sync is + + -- normal signals + signal toggle_ff : std_logic; + signal sync_q : std_logic; + signal sync_qq : std_logic; + signal sync_qqq : std_logic; + signal pulse_b : std_logic; + +begin + +-- toggle flip flop in clock domain A +THE_TOGGLE_FF_PROC: process( clk_a_in ) +begin + if( rising_edge(clk_a_in) ) then + if ( reset_a_in = '1' ) then + toggle_ff <= '0'; + elsif( pulse_a_in = '1' ) then + toggle_ff <= not toggle_ff; + end if; + end if; +end process THE_TOGGLE_FF_PROC; + +-- synchronizing stage for clock domain B +THE_SYNC_STAGE_PROC: process( clk_b_in ) +begin + if( rising_edge(clk_b_in) ) then + if( reset_b_in = '1' ) then + sync_q <= '0'; sync_qq <= '0'; sync_qqq <= '0'; + else + sync_qqq <= sync_qq; + sync_qq <= sync_q; + sync_q <= toggle_ff; + end if; + end if; +end process THE_SYNC_STAGE_PROC; + +-- output pulse registering +THE_OUTPUT_PULSE_PROC: process( clk_b_in ) +begin + if( rising_edge(clk_b_in) ) then + if( reset_b_in = '1' ) then + pulse_b <= '0'; + else + pulse_b <= sync_qqq xor sync_qq; + end if; + end if; +end process THE_OUTPUT_PULSE_PROC; + +-- output signals +pulse_b_out <= pulse_b; + +end behavioral; diff --git a/src/raw_buf_stage_new.vhd b/src/raw_buf_stage_new.vhd new file mode 100755 index 0000000..bef706b --- /dev/null +++ b/src/raw_buf_stage_new.vhd @@ -0,0 +1,410 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity raw_buf_stage_new is + port( CLK_IN : in std_logic; -- 100MHz local clock + CLK_APV_IN : in std_logic; -- 40MHz APV clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- trigger related signals + APV_RESET_IN : in std_logic; -- APV reset signal (100MHz) + APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz) + APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz) + -- ADC0 signals + ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0 + ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1 + ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2 + ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3 + ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4 + ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5 + ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6 + ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7 + -- ADC1 signals + ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0 + ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1 + ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2 + ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3 + ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4 + ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5 + ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6 + ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7 + -- Slow control registers + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold + FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold + APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control + -- 100MHZ synchronous interface + BUF_FULL_OUT : out std_logic; + BUF_ADDR_IN : in std_logic_vector(6 downto 0); + BUF_DONE_IN : in std_logic; + BUF_TICK_OUT : out std_logic_vector(15 downto 0); + BUF_START_OUT : out std_logic_vector(15 downto 0); + BUF_READY_OUT : out std_logic_vector(15 downto 0); + BUF_0_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_1_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_2_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_3_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_4_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_5_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_6_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_7_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_8_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_9_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_10_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_11_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_12_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_13_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_14_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_15_DATA_OUT : out std_logic_vector(37 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); +end; + +architecture behavioral of raw_buf_stage_new is + + -- Reset signals, combinatorial and registered + signal next_reset_all : std_logic; + signal reset_all : std_logic; -- 40MHz clock domain + signal next_reset : std_logic; + signal reset : std_logic; -- 100MHz clock domain + + -- APV locker signals (arrays / vectors) + type adc_data_t is array (0 to 15) of std_logic_vector(11 downto 0); + signal adc_data : adc_data_t; + type apv_status_t is array (0 to 15) of std_logic_vector(7 downto 0); + signal apv_status : apv_status_t; + type apv_frame_t is array (0 to 15) of std_logic_vector(11 downto 0); + signal apv_frame : apv_frame_t; + type apv_channel_t is array (0 to 15) of std_logic_vector(6 downto 0); + signal apv_channel : apv_channel_t; + type apv_data_t is array (0 to 15) of std_logic_vector(17 downto 0); + signal apv_data : apv_data_t; + + signal apv_analog : std_logic_vector(15 downto 0); + signal apv_start : std_logic_vector(15 downto 0); + signal apv_last : std_logic_vector(15 downto 0); + + -- Buffer signals (arrays / vectors) + type buf_data_t is array (0 to 15) of std_logic_vector(17 downto 0); + signal buf_data : buf_data_t; + type buf_status_t is array (0 to 15) of std_logic_vector(7 downto 0); + signal buf_status : buf_status_t; + type buf_frame_t is array (0 to 15) of std_logic_vector(11 downto 0); + signal buf_frame : buf_frame_t; + type buf_level_t is array (0 to 15) of std_logic_vector(7 downto 0); + signal buf_level : buf_level_t; + + signal buf_tick : std_logic_vector(15 downto 0); + signal buf_start : std_logic_vector(15 downto 0); + signal buf_ready : std_logic_vector(15 downto 0); + signal buf_full : std_logic_vector(15 downto 0); + + signal next_raw_buf_full : std_logic; + signal raw_buf_full : std_logic; + + -- Debug + signal debug : std_logic_vector(63 downto 0); + +begin + +--------------------------------------------------------------------------- +-- Debugging signals +--------------------------------------------------------------------------- +--debug(31 downto 0) <= (others => '0'); +debug(63 downto 60) <= apv_data(15)(17 downto 14); +debug(59 downto 56) <= apv_data(14)(17 downto 14); +debug(55 downto 52) <= apv_data(13)(17 downto 14); +debug(51 downto 48) <= apv_data(12)(17 downto 14); +debug(47 downto 44) <= apv_data(11)(17 downto 14); +debug(43 downto 40) <= apv_data(10)(17 downto 14); +debug(39 downto 36) <= apv_data(9)(17 downto 14); +debug(35 downto 32) <= apv_data(8)(17 downto 14); +debug(31 downto 28) <= apv_data(7)(17 downto 14); +debug(27 downto 24) <= apv_data(6)(17 downto 14); +debug(23 downto 20) <= apv_data(5)(17 downto 14); +debug(19 downto 16) <= apv_data(4)(17 downto 14); +debug(15 downto 12) <= apv_data(3)(17 downto 14); +debug(11 downto 8) <= apv_data(2)(17 downto 14); +debug(7 downto 4) <= apv_data(1)(17 downto 14); +debug(3 downto 0) <= apv_data(0)(17 downto 14); + +--------------------------------------------------------------------------- +-- Reset handling +--------------------------------------------------------------------------- +next_reset_all <= (reset_in or apv_reset_in); -- 40MHz clock domain +next_reset <= (reset_in or apv_reset_in); -- 100MHz clock domain + +THE_RESET_SYNC: state_sync +port map( STATE_A_IN => next_reset_all, + CLK_B_IN => clk_apv_in, + RESET_B_IN => '0', + STATE_B_OUT => reset_all + ); + + +--------------------------------------------------------------------------- +-- Busy and reset handling +--------------------------------------------------------------------------- +next_raw_buf_full <= '1' when ( buf_full /= x"0000" ) else '0'; + +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + raw_buf_full <= next_raw_buf_full; + reset <= next_reset_all; + end if; +end process THE_SYNC_PROC; + + +--------------------------------------------------------------------------- +-- ADC0: APV [7:0] lock handler, data separation, raw data buffer +--------------------------------------------------------------------------- + +-- Aliasing the inputs for the generator +adc_data(7) <= adc0_7_data_in; +adc_data(6) <= adc0_6_data_in; +adc_data(5) <= adc0_5_data_in; +adc_data(4) <= adc0_4_data_in; +adc_data(3) <= adc0_3_data_in; +adc_data(2) <= adc0_2_data_in; +adc_data(1) <= adc0_1_data_in; +adc_data(0) <= adc0_0_data_in; + +-- generate 8 identical blocks, one per APV connected to ADC0 +GEN_ADC0: for i in 0 to 7 generate + + -- APV locker, handles synchronisation and all the other stuff + THE_APV_LOCKER: apv_locker + port map( CLK_APV_IN => clk_apv_in, + RESET_IN => reset_all, + SYNC_IN => apv_sync_in, + ADC_RAW_IN => adc_data(i), + ADC_VALID_IN => adc0_valid_in, + APV_ON_IN => apv_on_in(i), + BIT_LOW_IN => bit_low_in, + BIT_HIGH_IN => bit_high_in, + FL_LOW_IN => fl_low_in, + FL_HIGH_IN => fl_high_in, + STATUS_IGNORE_OUT => apv_status(i)(1), + STATUS_UNKNOWN_OUT => apv_status(i)(6), + STATUS_BADADC_OUT => apv_status(i)(7), + STATUS_LOCKED_OUT => apv_status(i)(5), + STATUS_LOST_OUT => apv_status(i)(4), + STATUS_NOSYNC_OUT => apv_status(i)(3), + STATUS_MISSING_OUT => apv_status(i)(2), + STATUS_TICKMARK_OUT => apv_status(i)(0), + FRAME_ROW_OUT => apv_frame(i)(7 downto 0), + FRAME_ERROR_OUT => apv_frame(i)(8), + FRAME_OVF_OUT => apv_frame(i)(9), + FRAME_UDF_OUT => apv_frame(i)(10), + FRAME_FLAT_OUT => apv_frame(i)(11), + FRAME_CTR_OUT => apv_data(i)(17 downto 14), + APV_CHANNEL_OUT => apv_channel(i), + APV_OVERFLOW_OUT => apv_data(i)(13), + APV_UNDERFLOW_OUT => apv_data(i)(12), + APV_RAW_OUT => apv_data(i)(11 downto 0), + APV_ANALOG_OUT => apv_analog(i), + APV_START_OUT => apv_start(i), + APV_LAST_OUT => apv_last(i), + DEBUG_OUT => open + ); + + -- raw buffer, stores frame data, all outputs are 100MHz synchronized + THE_APV_RAW_BUFFER: apv_raw_buffer + port map( CLK_APV_IN => clk_apv_in, + RESET_IN => reset_all, + FRM_REQD_IN => apv_frame_reqd_in, + MAX_TRG_NUM_IN => max_trg_num_in, + ADC_ANALOG_IN => apv_analog(i), + ADC_START_IN => apv_start(i), + ADC_LAST_IN => apv_last(i), + ADC_CHANNEL_IN => apv_channel(i), + ADC_RAW_IN => apv_data(i), + ADC_STATUS_IN => apv_status(i), + ADC_FRAME_IN => apv_frame(i), + BUF_CLK_IN => clk_in, + BUF_RESET_IN => reset, + BUF_START_OUT => buf_start(i), + BUF_READY_OUT => buf_ready(i), + BUF_ADDR_IN => buf_addr_in, + BUF_DONE_IN => buf_done_in, + BUF_DATA_OUT => buf_data(i), + BUF_STATUS_OUT => buf_status(i), + BUF_FRAME_OUT => buf_frame(i), + BUF_GOOD_OUT => buf_level(i)(7), + BUF_BROKEN_OUT => buf_level(i)(6), + BUF_IGNORE_OUT => buf_level(i)(5), + BUF_LEVEL_OUT => buf_level(i)(4 downto 0), + BUF_TICKMARK_OUT => buf_tick(i), + BUF_FULL_OUT => buf_full(i), + DEBUG_OUT => open + ); + +end generate GEN_ADC0; + +--------------------------------------------------------------------------- +-- ADC1: APV [15:8] lock handler, data separation, raw data buffer +--------------------------------------------------------------------------- + +-- Aliasing the inputs for the generator +adc_data(15) <= adc1_7_data_in; +adc_data(14) <= adc1_6_data_in; +adc_data(13) <= adc1_5_data_in; +adc_data(12) <= adc1_4_data_in; +adc_data(11) <= adc1_3_data_in; +adc_data(10) <= adc1_2_data_in; +adc_data(9) <= adc1_1_data_in; +adc_data(8) <= adc1_0_data_in; + +-- generate 8 identical blocks, one per APV connected to ADC1 +GEN_ADC1: for i in 8 to 15 generate + + -- APV locker, handles synchronisation and all the other stuff + THE_APV_LOCKER: apv_locker + port map( CLK_APV_IN => clk_apv_in, + RESET_IN => reset_all, + SYNC_IN => apv_sync_in, + ADC_RAW_IN => adc_data(i), + ADC_VALID_IN => adc1_valid_in, + APV_ON_IN => apv_on_in(i), + BIT_LOW_IN => bit_low_in, + BIT_HIGH_IN => bit_high_in, + FL_LOW_IN => fl_low_in, + FL_HIGH_IN => fl_high_in, + STATUS_IGNORE_OUT => apv_status(i)(1), + STATUS_UNKNOWN_OUT => apv_status(i)(6), + STATUS_BADADC_OUT => apv_status(i)(7), + STATUS_LOCKED_OUT => apv_status(i)(5), + STATUS_LOST_OUT => apv_status(i)(4), + STATUS_NOSYNC_OUT => apv_status(i)(3), + STATUS_MISSING_OUT => apv_status(i)(2), + STATUS_TICKMARK_OUT => apv_status(i)(0), + FRAME_ROW_OUT => apv_frame(i)(7 downto 0), + FRAME_ERROR_OUT => apv_frame(i)(8), + FRAME_OVF_OUT => apv_frame(i)(9), + FRAME_UDF_OUT => apv_frame(i)(10), + FRAME_FLAT_OUT => apv_frame(i)(11), + FRAME_CTR_OUT => apv_data(i)(17 downto 14), + APV_CHANNEL_OUT => apv_channel(i), + APV_OVERFLOW_OUT => apv_data(i)(13), + APV_UNDERFLOW_OUT => apv_data(i)(12), + APV_RAW_OUT => apv_data(i)(11 downto 0), + APV_ANALOG_OUT => apv_analog(i), + APV_START_OUT => apv_start(i), + APV_LAST_OUT => apv_last(i), + DEBUG_OUT => open + ); + + -- raw buffer, stores frame data, all outputs are 100MHz synchronized + THE_APV_RAW_BUFFER: apv_raw_buffer + port map( CLK_APV_IN => clk_apv_in, + RESET_IN => reset_all, + FRM_REQD_IN => apv_frame_reqd_in, + MAX_TRG_NUM_IN => max_trg_num_in, + ADC_ANALOG_IN => apv_analog(i), + ADC_START_IN => apv_start(i), + ADC_LAST_IN => apv_last(i), + ADC_CHANNEL_IN => apv_channel(i), + ADC_RAW_IN => apv_data(i), + ADC_STATUS_IN => apv_status(i), + ADC_FRAME_IN => apv_frame(i), + BUF_CLK_IN => clk_in, + BUF_RESET_IN => reset, + BUF_START_OUT => buf_start(i), + BUF_READY_OUT => buf_ready(i), + BUF_ADDR_IN => buf_addr_in, + BUF_DONE_IN => buf_done_in, + BUF_DATA_OUT => buf_data(i), + BUF_STATUS_OUT => buf_status(i), + BUF_FRAME_OUT => buf_frame(i), + BUF_GOOD_OUT => buf_level(i)(7), + BUF_BROKEN_OUT => buf_level(i)(6), + BUF_IGNORE_OUT => buf_level(i)(5), + BUF_LEVEL_OUT => buf_level(i)(4 downto 0), + BUF_TICKMARK_OUT => buf_tick(i), + BUF_FULL_OUT => buf_full(i), + DEBUG_OUT => open + ); + +end generate GEN_ADC1; + + +--------------------------------------------------------------------------- +-- Output signals +--------------------------------------------------------------------------- + +buf_full_out <= raw_buf_full; +buf_tick_out <= buf_tick; -- needed for TOCs +buf_start_out <= buf_start; -- needed for TOCs +buf_ready_out <= buf_ready; -- debug signal + +-- Alias the outputs from generator +buf_0_data_out(17 downto 0) <= buf_data(0); +buf_0_data_out(29 downto 18) <= buf_frame(0); +buf_0_data_out(37 downto 30) <= buf_level(0); +buf_1_data_out(17 downto 0) <= buf_data(1); +buf_1_data_out(29 downto 18) <= buf_frame(1); +buf_1_data_out(37 downto 30) <= buf_level(1); +buf_2_data_out(17 downto 0) <= buf_data(2); +buf_2_data_out(29 downto 18) <= buf_frame(2); +buf_2_data_out(37 downto 30) <= buf_level(2); +buf_3_data_out(17 downto 0) <= buf_data(3); +buf_3_data_out(29 downto 18) <= buf_frame(3); +buf_3_data_out(37 downto 30) <= buf_level(3); +buf_4_data_out(17 downto 0) <= buf_data(4); +buf_4_data_out(29 downto 18) <= buf_frame(4); +buf_4_data_out(37 downto 30) <= buf_level(4); +buf_5_data_out(17 downto 0) <= buf_data(5); +buf_5_data_out(29 downto 18) <= buf_frame(5); +buf_5_data_out(37 downto 30) <= buf_level(5); +buf_6_data_out(17 downto 0) <= buf_data(6); +buf_6_data_out(29 downto 18) <= buf_frame(6); +buf_6_data_out(37 downto 30) <= buf_level(6); +buf_7_data_out(17 downto 0) <= buf_data(7); +buf_7_data_out(29 downto 18) <= buf_frame(7); +buf_7_data_out(37 downto 30) <= buf_level(7); +buf_8_data_out(17 downto 0) <= buf_data(8); +buf_8_data_out(29 downto 18) <= buf_frame(8); +buf_8_data_out(37 downto 30) <= buf_level(8); +buf_9_data_out(17 downto 0) <= buf_data(9); +buf_9_data_out(29 downto 18) <= buf_frame(9); +buf_9_data_out(37 downto 30) <= buf_level(9); +buf_10_data_out(17 downto 0) <= buf_data(10); +buf_10_data_out(29 downto 18) <= buf_frame(10); +buf_10_data_out(37 downto 30) <= buf_level(10); +buf_11_data_out(17 downto 0) <= buf_data(11); +buf_11_data_out(29 downto 18) <= buf_frame(11); +buf_11_data_out(37 downto 30) <= buf_level(11); +buf_12_data_out(17 downto 0) <= buf_data(12); +buf_12_data_out(29 downto 18) <= buf_frame(12); +buf_12_data_out(37 downto 30) <= buf_level(12); +buf_13_data_out(17 downto 0) <= buf_data(13); +buf_13_data_out(29 downto 18) <= buf_frame(13); +buf_13_data_out(37 downto 30) <= buf_level(13); +buf_14_data_out(17 downto 0) <= buf_data(14); +buf_14_data_out(29 downto 18) <= buf_frame(14); +buf_14_data_out(37 downto 30) <= buf_level(14); +buf_15_data_out(17 downto 0) <= buf_data(15); +buf_15_data_out(29 downto 18) <= buf_frame(15); +buf_15_data_out(37 downto 30) <= buf_level(15); + +--------------------------------------------------------------------------- +-- DEBUG signals +--------------------------------------------------------------------------- +debug_out <= debug; + +end behavioral; + + + + + diff --git a/src/real_trg_handler.vhd b/src/real_trg_handler.vhd new file mode 100755 index 0000000..bb7ed5c --- /dev/null +++ b/src/real_trg_handler.vhd @@ -0,0 +1,544 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +-- Comment: better than the first version, but still a lot of optimization possible. + +-- (1) no more compare tags here. some steps in the FSM can be taken out. +-- (2) no more rst_lvl1_counter signal anymore in the CCR. to be replaced! + +entity real_trg_handler is + port( CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse) + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint + -- TRB LVL1 channel signals + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type + TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB + TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger + RST_LVL1_COUNTER_IN : in std_logic; -- reset LVL1 counter + LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); + BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator + -- + APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine + APV_TRGSTART_OUT : out std_logic; -- start an APV trigger state machine + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data + EDS_WE_OUT : out std_logic; -- EDS write enable (general interface) + EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level + EDS_READY_OUT : out std_logic; -- APV trigger sequence done + DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); +end; + +architecture behavioral of real_trg_handler is + + -- state machine signals + type STATES is (SLEEP, STORE, START, COUNT, RELAX, CHECK, WAPV, WLVL1, TRBS, COMP, CTAG, STAG, + DTAG, WEDS, WDEL0, WDEL1, WBUSY, DONE, CNTEVT, BADTRG); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- normal signals + signal trg_comb : std_logic_vector(3 downto 0); -- TRB or hardware inputs + signal trg_q : std_logic_vector(3 downto 0); + signal trg_qq : std_logic_vector(3 downto 0); + signal trg_qqq : std_logic_vector(3 downto 0); + signal trg_qqqq : std_logic_vector(3 downto 0); + signal trg_edge : std_logic_vector(3 downto 0); + signal decoded_trg : std_logic_vector(3 downto 0); + signal todo_start : std_logic_vector(3 downto 0); + signal trg_found : std_logic; + signal trg_pattern : std_logic_vector(3 downto 0); + + signal evtctr : std_logic_vector(15 downto 0); -- event counter + signal ce_evtctr : std_logic; + signal ce_evtctr_x : std_logic; + signal frmctr : std_logic_vector(3 downto 0); -- frame counter + signal ce_frmctr : std_logic; + signal ce_frmctr_x : std_logic; + signal todo_ctr : std_logic_vector(3 downto 0); + signal todo_done_x : std_logic; + signal todo_done : std_logic; + signal apv_trgstart_x : std_logic; + signal apv_trgstart : std_logic; + signal eds_data : std_logic_vector(39 downto 0); + signal eds_start : std_logic; + signal eds_start_x : std_logic; + signal eds_we : std_logic; + signal eds_we_x : std_logic; + signal eds_ready_x : std_logic; + signal eds_ready : std_logic; -- end signal, release busy by sending TERM and clean up misc stuff + signal apv_trg_finished : std_logic; + signal accept_x : std_logic; -- we can accept a trigger + signal accept : std_logic; + signal missed_trg_x : std_logic; + signal missed_trg : std_logic; + signal missing_trg : std_logic; + signal rst_status_x : std_logic; + signal rst_status : std_logic; + + signal time_trg : std_logic_vector(3 downto 0); + + -- Information to be collected for the EDS + signal trb_ttag_reg : std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag (16bit) + signal trb_trnd_reg : std_logic_vector(7 downto 0); -- TRB LVL1 random byte (8bit) + signal trb_ttype_reg : std_logic_vector(3 downto 0); -- TRB LVL1 trigger type (4bit) + signal trg_pattern_reg : std_logic_vector(3 downto 0); -- timing trigger input pattern (4bit) + signal trg_dectrg_reg : std_logic_vector(3 downto 0); -- priority encoded timing trigger (4bit) + signal trg_frmctr_reg : std_logic_vector(3 downto 0); -- frame counter start value (4bit) + signal trg_frmnum_reg : std_logic_vector(3 downto 0); -- number of frames in this event (4bit) + + signal store_local_x : std_logic; + signal store_local : std_logic; + signal store_remote_x : std_logic; + signal store_remote : std_logic; + + signal time_trg_on : std_logic_vector(3 downto 0); + signal time_trg_inv : std_logic_vector(3 downto 0); + + signal bsm_x : std_logic_vector(7 downto 0); + +begin + +-- Aliasing the control bits +time_trg_on(3) <= trg_setup_in(7); +time_trg_inv(3) <= trg_setup_in(3); +time_trg_on(2) <= trg_setup_in(6); +time_trg_inv(2) <= trg_setup_in(2); +time_trg_on(1) <= trg_setup_in(5); +time_trg_inv(1) <= trg_setup_in(1); +time_trg_on(0) <= trg_setup_in(4); +time_trg_inv(0) <= trg_setup_in(0); + +------------------------------------------------------------ +-- Synchronize the external trigger inputs +THE_TIME_TRG_3_SYNC: state_sync +port map( STATE_A_IN => time_trg_in(3), + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + STATE_B_OUT => time_trg(3) + ); +THE_TIME_TRG_2_SYNC: state_sync +port map( STATE_A_IN => time_trg_in(2), + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + STATE_B_OUT => time_trg(2) + ); +THE_TIME_TRG_1_SYNC: state_sync +port map( STATE_A_IN => time_trg_in(1), + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + STATE_B_OUT => time_trg(1) + ); +THE_TIME_TRG_0_SYNC: state_sync +port map( STATE_A_IN => time_trg_in(0), + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + STATE_B_OUT => time_trg(0) + ); +------------------------------------------------------------ + +-- For all four possible hardware triggers we combine hardware and TRB inputs +-- TRB slow control trigger inputs are already synchronized to SYSCLK. +--trg_comb <= time_trg or trb_trg_in; + +trg_comb(3) <= ((time_trg(3) xor time_trg_inv(3)) and time_trg_on(3)) or trb_trg_in(3); +trg_comb(2) <= ((time_trg(2) xor time_trg_inv(2)) and time_trg_on(2)) or trb_trg_in(2); +trg_comb(1) <= ((time_trg(1) xor time_trg_inv(1)) and time_trg_on(1)) or trb_trg_in(1); +trg_comb(0) <= ((time_trg(0) xor time_trg_inv(0)) and time_trg_on(0)) or trb_trg_in(0); + +-- Now we shift the synced signals into shift registers with four FF in a row. +-- This gives us a 16bit pattern in total to decide which trigger input was active. +THE_TRG_LENGTH_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + trg_qqqq <= (others => '0'); + trg_qqq <= (others => '0'); + trg_qq <= (others => '0'); + trg_q <= (others => '0'); + else + trg_qqqq <= trg_qqq; + trg_qqq <= trg_qq; + trg_qq <= trg_q; + trg_q <= trg_comb; + end if; + end if; +end process THE_TRG_LENGTH_PROC; + +-- Check for rising edges in the signals, with a long steady state signal following. +-- We accept only signals of three clock cycles minimum length (as sent by the TRB_TRG). +THE_RISING_EDGES_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + trg_edge <= (others => '0'); + else + trg_edge(3) <= not trg_qqqq(3) and trg_qqq(3) and trg_qq(3) and trg_q(3); + trg_edge(2) <= not trg_qqqq(2) and trg_qqq(2) and trg_qq(2) and trg_q(2); + trg_edge(1) <= not trg_qqqq(1) and trg_qqq(1) and trg_qq(1) and trg_q(1); + trg_edge(0) <= not trg_qqqq(0) and trg_qqq(0) and trg_qq(0) and trg_q(0); + end if; + end if; +end process THE_RISING_EDGES_PROC; + +-- Now we are almost done. +-- The detected edges are priorized. +THE_TRG_PRIORITY_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + decoded_trg <= (others => '0'); + todo_start <= (others => '0'); + trg_found <= '0'; + else + if( trg_edge(3) = '1' ) then + decoded_trg <= "1000"; + todo_start <= trg_3_todo_in; + trg_found <= '1'; + elsif( trg_edge(3 downto 2) = "01" ) then + decoded_trg <= "0100"; + todo_start <= trg_2_todo_in; + trg_found <= '1'; + elsif( trg_edge(3 downto 1) = "001" ) then + decoded_trg <= "0010"; + todo_start <= trg_1_todo_in; + trg_found <= '1'; + elsif( trg_edge(3 downto 0) = "0001" ) then + decoded_trg <= "0001"; + todo_start <= trg_0_todo_in; + trg_found <= '1'; + else + decoded_trg <= "0000"; + todo_start <= "0000"; + trg_found <= '0'; + end if; + end if; + end if; +end process THE_TRG_PRIORITY_PROC; + +-- We need to store some information for the EDS... from local counters +-- NB: after one cycle this information set is reset to zero! +-- needed for missing timing trigger handling. +THE_LOCALSTORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( (reset_in = '1') or (eds_we = '1') ) then + trg_pattern_reg <= (others => '0'); + trg_frmctr_reg <= (others => '0'); + trg_frmnum_reg <= (others => '0'); + trg_dectrg_reg <= (others => '0'); + elsif( (accept = '1') and (trg_found = '1') ) then -- the clock cycle before local_store pulse + trg_pattern_reg <= trg_pattern; -- BUGBUGBUG + trg_frmctr_reg <= frmctr; + trg_frmnum_reg <= todo_start; + trg_dectrg_reg <= decoded_trg; + end if; + end if; +end process THE_LOCALSTORE_PROC; + +-- The ToDo counter: is loaded with the number of APV triggers, and counts down. +THE_TODO_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + todo_ctr <= (others => '0'); + elsif( store_local = '1' ) then + todo_ctr <= trg_frmnum_reg; --todo_start; + elsif( ce_frmctr = '1' ) then + todo_ctr <= todo_ctr - 1; + end if; + end if; +end process THE_TODO_COUNTER_PROC; +todo_done_x <= '1' when (todo_ctr = x"0") else '0'; + +-- We need to store some information for the EDS... from TRBnet LVL1 trigger endpoint +THE_REMOTESTORE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + trb_ttag_reg <= (others => '0'); + trb_trnd_reg <= (others => '0'); + trb_ttype_reg <= (others => '0'); + elsif( store_remote = '1' ) then + trb_ttag_reg <= trb_ttag_in; + trb_trnd_reg <= trb_trnd_in; + trb_ttype_reg <= trb_ttype_in; + end if; + end if; +end process THE_REMOTESTORE_PROC; + +------------------------------------------------- +------------------------------------------------- +------------------------------------------------- + +THE_TRG_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + trg_pattern <= (others => '0'); + todo_done <= '0'; + else + trg_pattern <= trg_edge; + todo_done <= todo_done_x; + end if; + end if; +end process THE_TRG_SYNC_PROC; + +-- We store the end pulse from the APV trigger handler, as we need to wait for +-- LVL1 in any case before we can take care of this signal. +THE_TRGDONE_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + apv_trg_finished <= '0'; + elsif( apv_trgdone_in = '1' ) then + apv_trg_finished <= '1'; + elsif( eds_ready = '1' ) then + apv_trg_finished <= '0'; + end if; + end if; +end process THE_TRGDONE_PROC; + +-- A statemachine handles all actions for filling out the trigger information sheet +-- state registers +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + ce_evtctr <= '0'; + ce_frmctr <= '0'; + eds_ready <= '0'; + eds_we <= '0'; + eds_start <= '0'; + store_local <= '0'; + store_remote <= '0'; + apv_trgstart <= '0'; + accept <= '1'; + missed_trg <= '0'; + rst_status <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + ce_evtctr <= ce_evtctr_x; + ce_frmctr <= ce_frmctr_x; + eds_ready <= eds_ready_x; + eds_we <= eds_we_x; + eds_start <= eds_start_x; + store_local <= store_local_x; + store_remote <= store_remote_x; + apv_trgstart <= apv_trgstart_x; + accept <= accept_x; + missed_trg <= missed_trg_x; + rst_status <= rst_status_x; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, trg_found, todo_done, trb_trgrcvd_in, apv_trg_finished, busy_release_in, missing_trg ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + ce_evtctr_x <= '0'; + ce_frmctr_x <= '0'; + eds_ready_x <= '0'; + eds_we_x <= '0'; + eds_start_x <= '0'; + store_local_x <= '0'; + store_remote_x <= '0'; + apv_trgstart_x <= '0'; + accept_x <= '0'; + missed_trg_x <= '0'; + rst_status_x <= '0'; + case CURRENT_STATE is + -- not good. if no timing trigger was received but a trb trigger arrives, we must do something! + when SLEEP => if ( trg_found = '1' ) then + -- normal way: timing trigger found + NEXT_STATE <= STORE; + store_local_x <= '1'; + eds_start_x <= '1'; + elsif( (trg_found = '0') and (trb_trgrcvd_in = '1') ) then + -- bad way: missing timing trigger + NEXT_STATE <= BADTRG; + missed_trg_x <= '1'; + else + NEXT_STATE <= SLEEP; + accept_x <= '1'; + end if; + when BADTRG => NEXT_STATE <= TRBS; + store_remote_x <= '1'; + when STORE => NEXT_STATE <= START; + apv_trgstart_x <= '1'; + when START => NEXT_STATE <= CHECK; + when CHECK => if( todo_done = '1' ) then + NEXT_STATE <= WAPV; + else + NEXT_STATE <= COUNT; + ce_frmctr_x <= '1'; + end if; + when COUNT => NEXT_STATE <= RELAX; + when RELAX => NEXT_STATE <= CHECK; + when WAPV => if( apv_trg_finished = '1' ) then + NEXT_STATE <= WLVL1; + else + NEXT_STATE <= WAPV; + end if; + when WLVL1 => if( trb_trgrcvd_in = '1' ) then + NEXT_STATE <= TRBS; + store_remote_x <= '1'; + else + NEXT_STATE <= WLVL1; + end if; + when TRBS => NEXT_STATE <= CTAG; + when CTAG => NEXT_STATE <= STAG; + when STAG => NEXT_STATE <= DTAG; + when DTAG => if( missing_trg = '0' ) then + -- everything is fine + NEXT_STATE <= WEDS; + eds_we_x <= '1'; + else + -- we missed a timing trigger, so no EDS was created + NEXT_STATE <= CNTEVT; + ce_evtctr_x <= '1'; + end if; + when WEDS => NEXT_STATE <= CNTEVT; + ce_evtctr_x <= '1'; + when CNTEVT => NEXT_STATE <= WDEL0; + when WDEL0 => NEXT_STATE <= WDEL1; + when WDEL1 => NEXT_STATE <= WBUSY; + when WBUSY => if( busy_release_in = '1' ) then + NEXT_STATE <= DONE; + eds_ready_x <= '1'; + else + NEXT_STATE <= WBUSY; + end if; + when DONE => if( trb_trgrcvd_in = '0' ) then -- mind the state synchronizer delay!!! + NEXT_STATE <= SLEEP; + accept_x <= '1'; + rst_status_x <= '1'; + else + NEXT_STATE <= DONE; + end if; + when others => NEXT_STATE <= SLEEP; + accept_x <= '1'; + end case; +end process STATE_TRANSFORM; + +-- state decoding +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SLEEP => bsm_x <= x"00"; + when STORE => bsm_x <= x"01"; + when START => bsm_x <= x"02"; + when CHECK => bsm_x <= x"03"; + when COUNT => bsm_x <= x"04"; + when RELAX => bsm_x <= x"14"; + when WAPV => bsm_x <= x"05"; + when WLVL1 => bsm_x <= x"06"; + when TRBS => bsm_x <= x"07"; + when CTAG => bsm_x <= x"08"; + when STAG => bsm_x <= x"09"; + when DTAG => bsm_x <= x"0a"; + when WEDS => bsm_x <= x"0b"; + when WDEL0 => bsm_x <= x"0c"; + when WDEL1 => bsm_x <= x"0d"; + when WBUSY => bsm_x <= x"0e"; + when DONE => bsm_x <= x"0f"; + when CNTEVT => bsm_x <= x"10"; + when BADTRG => bsm_x <= x"11"; + when others => bsm_x <= x"ff"; + end case; +end process STATE_DECODE; + + +-- The event counter: is incremented with each accepted trigger +THE_EVENT_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( (reset_in = '1') or (rst_lvl1_counter_in = '1') ) then + evtctr <= (others => '0'); + elsif( ce_evtctr = '1' ) then + evtctr <= evtctr + 1; + end if; + end if; +end process THE_EVENT_COUNTER_PROC; + +-- The frame counter: is incremented with each 1-0-0 trigger sent to APV +THE_FRAME_COUNTER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + frmctr <= (others => '0'); + elsif( ce_frmctr = '1' ) then + frmctr <= frmctr + 1; + end if; + end if; +end process THE_FRAME_COUNTER_PROC; + +-- If a timing trigger was missing, we simply ignore this LVL1 trigger +THE_MISSED_TRG_REG: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( (reset_in = '1') or (rst_status = '1') ) then + missing_trg <= '0'; + elsif( missed_trg = '1' ) then + missing_trg <= '1'; + end if; + end if; +end process THE_MISSED_TRG_REG; + +-- EDS bits: +eds_data(39 downto 36) <= trg_frmctr_reg; +eds_data(35 downto 32) <= trg_frmnum_reg; +eds_data(31 downto 16) <= trb_ttag_reg; +eds_data(15 downto 8) <= trb_trnd_reg; +eds_data(7 downto 4) <= trb_ttype_reg; +eds_data(3 downto 0) <= trg_pattern_reg; + +-- output signals +apv_trgstart_out <= apv_trgstart; +apv_trgsel_out <= trg_dectrg_reg; + +eds_data_out <= eds_data; +eds_start_out <= eds_start; +eds_we_out <= eds_we; +eds_ready_out <= eds_ready; +trb_missing_out <= missing_trg; +lvl1_counter_out <= evtctr; +trg_found_out <= trg_found; + +-- Debug signals +bsm_out <= bsm_x; + +debug_out(63 downto 32) <= (others => '0'); +debug_out(31 downto 24) <= evtctr(7 downto 0); +debug_out(23 downto 16) <= trb_ttag_reg(7 downto 0); +debug_out(15) <= ce_evtctr; +debug_out(14) <= '0'; +debug_out(13) <= missing_trg; +debug_out(12) <= accept; +debug_out(11) <= '0'; +debug_out(10) <= '0'; +debug_out(9) <= trb_trgrcvd_in; +debug_out(8) <= trg_found; +debug_out(7 downto 0) <= bsm_x; + +dbg_frmctr_out <= frmctr; + +end behavioral; + diff --git a/src/reboot_handler.vhd b/src/reboot_handler.vhd new file mode 100644 index 0000000..bfb7059 --- /dev/null +++ b/src/reboot_handler.vhd @@ -0,0 +1,61 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity reboot_handler is + port( RESET_IN : in std_logic; + CLK_IN : in std_logic; + START_IN : in std_logic; + REBOOT_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of reboot_handler is + + -- normal signals + signal reboot_counter : std_logic_vector(15 downto 0); + signal reboot_ce : std_logic; + signal reboot_x : std_logic; + signal reboot : std_logic; + +begin + +-- Latch the start pulse +THE_START_PULSE: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + reboot_ce <= '0'; + elsif( start_in = '1' ) then + reboot_ce <= '1'; + end if; + end if; +end process THE_START_PULSE; + +-- Reboot counter +THE_REBOOT_COUNTER: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + reboot_counter <= (others => '0'); + reboot <= '0'; + elsif( reboot_ce = '1' ) then + reboot_counter <= reboot_counter + 1; + end if; + reboot <= reboot_x; + end if; +end process THE_REBOOT_COUNTER; + +reboot_x <= reboot_counter(15) and reboot_counter(14) and reboot_counter(13); + +-- output signals +reboot_out <= reboot; + +debug_out(15 downto 0) <= reboot_counter; + +end behavioral; diff --git a/src/ref_row_sel.vhd b/src/ref_row_sel.vhd new file mode 100755 index 0000000..3cf165d --- /dev/null +++ b/src/ref_row_sel.vhd @@ -0,0 +1,252 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +-- This module takes ROW and ERROR information from all sixteen raw buffers, and +-- checks if the APVs with "good data" buffers are OK. +-- APV frame errors are sensed, as well as APV row errors. +-- The row error recognition is based somehow on the old RICH RC logic, as it takes +-- one APV as reference row by prioritiy encoding, and checks all other APVs against +-- this reference row. + +entity ref_row_sel is + port( CLK_IN : in std_logic; + READY_IN : in std_logic_vector(15 downto 0); -- buffer ready signals (data or timeout) + GOODDATA_IN : in std_logic_vector(15 downto 0); -- buffer data good signals + FRAME_0_IN : in std_logic_vector(11 downto 0); + FRAME_1_IN : in std_logic_vector(11 downto 0); + FRAME_2_IN : in std_logic_vector(11 downto 0); + FRAME_3_IN : in std_logic_vector(11 downto 0); + FRAME_4_IN : in std_logic_vector(11 downto 0); + FRAME_5_IN : in std_logic_vector(11 downto 0); + FRAME_6_IN : in std_logic_vector(11 downto 0); + FRAME_7_IN : in std_logic_vector(11 downto 0); + FRAME_8_IN : in std_logic_vector(11 downto 0); + FRAME_9_IN : in std_logic_vector(11 downto 0); + FRAME_10_IN : in std_logic_vector(11 downto 0); + FRAME_11_IN : in std_logic_vector(11 downto 0); + FRAME_12_IN : in std_logic_vector(11 downto 0); + FRAME_13_IN : in std_logic_vector(11 downto 0); + FRAME_14_IN : in std_logic_vector(11 downto 0); + FRAME_15_IN : in std_logic_vector(11 downto 0); + READY_OUT : out std_logic; -- all buffers reported being ready for data transport + VALID_BUFS_OUT : out std_logic; -- at least one APV raw buffer has data to fetch + ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong + APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit + APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0); + REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row + DBG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of ref_row_sel is + + -- normal signals + signal debug_x : std_logic_vector(15 downto 0); + + signal next_sel_ref_row : std_logic_vector(3 downto 0); + signal sel_ref_row : std_logic_vector(3 downto 0); + signal next_valid_bufs : std_logic; + signal valid_bufs : std_logic; + signal next_all_ready : std_logic; + signal all_ready : std_logic; + + signal ref_row : std_logic_vector(7 downto 0); -- selected reference row number + + signal next_row_match : std_logic_vector(15 downto 0); + signal row_match : std_logic_vector(15 downto 0); -- APV frame row matches reference number + + signal next_apv_error : std_logic_vector(15 downto 0); + signal apv_error : std_logic_vector(15 downto 0); -- APV frame error is set + + signal next_frame_row_err : std_logic; + signal frame_row_err : std_logic; + signal next_frame_apv_err : std_logic; + signal frame_apv_err : std_logic; + + +begin + +-- Sync process +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + sel_ref_row <= next_sel_ref_row; + valid_bufs <= next_valid_bufs; + apv_error <= next_apv_error; + row_match <= next_row_match; + frame_row_err <= next_frame_row_err; + frame_apv_err <= next_frame_apv_err; + all_ready <= next_all_ready; + end if; +end process THE_SYNC_PROC; + +-- All channels ready? +next_all_ready <= '1' when ( ready_in = x"ffff" ) else '0'; + +-- If no gooddata channel is available then we have no reference row +next_valid_bufs <= '1' when ( gooddata_in /= x"0000" ) else '0'; + +-- Do a priority encoding to select the reference row +THE_PRI_ENCODER_PROC: process( gooddata_in ) +begin + if ( gooddata_in(15 downto 15) = "1" ) then + next_sel_ref_row <= "1111"; + elsif( gooddata_in(15 downto 14) = "01" ) then + next_sel_ref_row <= "1110"; + elsif( gooddata_in(15 downto 13) = "001" ) then + next_sel_ref_row <= "1101"; + elsif( gooddata_in(15 downto 12) = "0001" ) then + next_sel_ref_row <= "1100"; + elsif( gooddata_in(15 downto 11) = "00001" ) then + next_sel_ref_row <= "1011"; + elsif( gooddata_in(15 downto 10) = "000001" ) then + next_sel_ref_row <= "1010"; + elsif( gooddata_in(15 downto 9) = "0000001" ) then + next_sel_ref_row <= "1001"; + elsif( gooddata_in(15 downto 8) = "00000001" ) then + next_sel_ref_row <= "1000"; + elsif( gooddata_in(15 downto 7) = "000000001" ) then + next_sel_ref_row <= "0111"; + elsif( gooddata_in(15 downto 6) = "0000000001" ) then + next_sel_ref_row <= "0110"; + elsif( gooddata_in(15 downto 5) = "00000000001" ) then + next_sel_ref_row <= "0101"; + elsif( gooddata_in(15 downto 4) = "000000000001" ) then + next_sel_ref_row <= "0100"; + elsif( gooddata_in(15 downto 3) = "0000000000001" ) then + next_sel_ref_row <= "0011"; + elsif( gooddata_in(15 downto 2) = "00000000000001" ) then + next_sel_ref_row <= "0010"; + elsif( gooddata_in(15 downto 1) = "000000000000001" ) then + next_sel_ref_row <= "0001"; + elsif( gooddata_in(15 downto 0) = "0000000000000001" ) then + next_sel_ref_row <= "0000"; + else + next_sel_ref_row <= "0000"; + end if; +end process THE_PRI_ENCODER_PROC; + +-- Select one reference row, and store it +THE_REF_ROW_SELECT_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + case sel_ref_row is + when "0000" => ref_row <= frame_0_in(7 downto 0); + when "0001" => ref_row <= frame_1_in(7 downto 0); + when "0010" => ref_row <= frame_2_in(7 downto 0); + when "0011" => ref_row <= frame_3_in(7 downto 0); + when "0100" => ref_row <= frame_4_in(7 downto 0); + when "0101" => ref_row <= frame_5_in(7 downto 0); + when "0110" => ref_row <= frame_6_in(7 downto 0); + when "0111" => ref_row <= frame_7_in(7 downto 0); + when "1000" => ref_row <= frame_8_in(7 downto 0); + when "1001" => ref_row <= frame_9_in(7 downto 0); + when "1010" => ref_row <= frame_10_in(7 downto 0); + when "1011" => ref_row <= frame_11_in(7 downto 0); + when "1100" => ref_row <= frame_12_in(7 downto 0); + when "1101" => ref_row <= frame_13_in(7 downto 0); + when "1110" => ref_row <= frame_14_in(7 downto 0); + when "1111" => ref_row <= frame_15_in(7 downto 0); + when others => ref_row <= x"ee"; -- will not be used... all cases are covered. + end case; + end if; +end process THE_REF_ROW_SELECT_PROC; + +-- Check all rows against the reference +-- Only channels with GOODDATA are to be taken into account; if the channel is invalid, we ignore it. + +next_row_match(0) <= '1' when ( (gooddata_in(0) = '0') or + ((gooddata_in(0) = '1') and (frame_0_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(1) <= '1' when ( (gooddata_in(1) = '0') or + ((gooddata_in(1) = '1') and (frame_1_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(2) <= '1' when ( (gooddata_in(2) = '0') or + ((gooddata_in(2) = '1') and (frame_2_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(3) <= '1' when ( (gooddata_in(3) = '0') or + ((gooddata_in(3) = '1') and (frame_3_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(4) <= '1' when ( (gooddata_in(4) = '0') or + ((gooddata_in(4) = '1') and (frame_4_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(5) <= '1' when ( (gooddata_in(5) = '0') or + ((gooddata_in(5) = '1') and (frame_5_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(6) <= '1' when ( (gooddata_in(6) = '0') or + ((gooddata_in(6) = '1') and (frame_6_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(7) <= '1' when ( (gooddata_in(7) = '0') or + ((gooddata_in(7) = '1') and (frame_7_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(8) <= '1' when ( (gooddata_in(8) = '0') or + ((gooddata_in(8) = '1') and (frame_8_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(9) <= '1' when ( (gooddata_in(9) = '0') or + ((gooddata_in(9) = '1') and (frame_9_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(10) <= '1' when ( (gooddata_in(10) = '0') or + ((gooddata_in(10) = '1') and (frame_10_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(11) <= '1' when ( (gooddata_in(11) = '0') or + ((gooddata_in(11) = '1') and (frame_11_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(12) <= '1' when ( (gooddata_in(12) = '0') or + ((gooddata_in(12) = '1') and (frame_12_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(13) <= '1' when ( (gooddata_in(13) = '0') or + ((gooddata_in(13) = '1') and (frame_13_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(14) <= '1' when ( (gooddata_in(14) = '0') or + ((gooddata_in(14) = '1') and (frame_14_in(7 downto 0) = ref_row) ) ) + else '0'; +next_row_match(15) <= '1' when ( (gooddata_in(15) = '0') or + ((gooddata_in(15) = '1') and (frame_15_in(7 downto 0) = ref_row) ) ) + else '0'; + +-- APV error recognition - same issue. +next_apv_error(0) <= '1' when ( (gooddata_in(0) = '1') and (frame_0_in(8) = '1') ) else '0'; +next_apv_error(1) <= '1' when ( (gooddata_in(1) = '1') and (frame_1_in(8) = '1') ) else '0'; +next_apv_error(2) <= '1' when ( (gooddata_in(2) = '1') and (frame_2_in(8) = '1') ) else '0'; +next_apv_error(3) <= '1' when ( (gooddata_in(3) = '1') and (frame_3_in(8) = '1') ) else '0'; +next_apv_error(4) <= '1' when ( (gooddata_in(4) = '1') and (frame_4_in(8) = '1') ) else '0'; +next_apv_error(5) <= '1' when ( (gooddata_in(5) = '1') and (frame_5_in(8) = '1') ) else '0'; +next_apv_error(6) <= '1' when ( (gooddata_in(6) = '1') and (frame_6_in(8) = '1') ) else '0'; +next_apv_error(7) <= '1' when ( (gooddata_in(7) = '1') and (frame_7_in(8) = '1') ) else '0'; +next_apv_error(8) <= '1' when ( (gooddata_in(8) = '1') and (frame_8_in(8) = '1') ) else '0'; +next_apv_error(9) <= '1' when ( (gooddata_in(9) = '1') and (frame_9_in(8) = '1') ) else '0'; +next_apv_error(10) <= '1' when ( (gooddata_in(10) = '1') and (frame_10_in(8) = '1') ) else '0'; +next_apv_error(11) <= '1' when ( (gooddata_in(11) = '1') and (frame_11_in(8) = '1') ) else '0'; +next_apv_error(12) <= '1' when ( (gooddata_in(12) = '1') and (frame_12_in(8) = '1') ) else '0'; +next_apv_error(13) <= '1' when ( (gooddata_in(13) = '1') and (frame_13_in(8) = '1') ) else '0'; +next_apv_error(14) <= '1' when ( (gooddata_in(14) = '1') and (frame_14_in(8) = '1') ) else '0'; +next_apv_error(15) <= '1' when ( (gooddata_in(15) = '1') and (frame_15_in(8) = '1') ) else '0'; + +-- Now we must "condense" the information +next_frame_row_err <= '1' when ( row_match /= x"ffff" ) else '0'; +next_frame_apv_err <= '1' when ( apv_error /= x"0000" ) else '0'; + +-- output signals +valid_bufs_out <= valid_bufs; +ready_out <= all_ready; +row_error_out <= frame_row_err; +apv_error_out <= frame_apv_err; +ref_row_out <= ref_row; +apv_error_bits_out <= apv_error; + +-- debug signals +debug_x(15) <= '0'; +debug_x(14) <= frame_apv_err; +debug_x(13) <= frame_row_err; +debug_x(12) <= valid_bufs; +debug_x(11 downto 8) <= sel_ref_row; +debug_x(7 downto 0) <= ref_row; + +dbg_out <= debug_x; + +end behavioral; diff --git a/src/replacement.vhd b/src/replacement.vhd new file mode 100755 index 0000000..cd899dd --- /dev/null +++ b/src/replacement.vhd @@ -0,0 +1,244 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; + +entity replacement is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of replacement is + +-- Signals + + type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- slave bus signals + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + signal arm_x : std_logic; + signal trg_x : std_logic; + + signal ctrl_reg : std_logic_vector(15 downto 0); + signal status_reg : std_logic_vector(31 downto 0); + + signal rd_data : std_logic_vector(15 downto 0); + + -- 40MHz clock domain!!! + signal wr_data : std_logic_vector(15 downto 0); + signal wr_addr : std_logic_vector(9 downto 0); + signal wr_we : std_logic; + signal reset_40mhz : std_logic; + signal arm_40mhz : std_logic; + signal trg_40mhz : std_logic; + + signal sm_clear : std_logic; + signal sm_run : std_logic; + signal sm_sample : std_logic; + signal sm_ready : std_logic; + signal sm_last : std_logic; + signal sm_bsm : std_logic_vector(3 downto 0); + +begin + +-- Fake +stat(31 downto 25) <= (others => '0'); +stat(24) <= sm_last; +stat(23) <= sm_ready; +stat(22) <= sm_sample; +stat(21) <= sm_run; +stat(20) <= sm_clear; +stat(19 downto 16) <= sm_bsm; +stat(15 downto 0) <= ctrl_reg; + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in ) +begin + NEXT_STATE <= SLEEP; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( slv_read_in = '1' ) then + NEXT_STATE <= RD_DEL0; + store_rd_x <= '1'; + elsif( slv_write_in = '1' ) then + NEXT_STATE <= WR_DEL0; + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_DEL0 => NEXT_STATE <= RD_DEL1; + when RD_DEL1 => NEXT_STATE <= RD_RDY; + when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_DEL0 => NEXT_STATE <= WR_DEL1; + when WR_DEL1 => NEXT_STATE <= WR_RDY; + when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +THE_RST_SYNC: state_sync +port map( STATE_A_IN => reset_in, + CLK_B_IN => adc_clk_in, + RESET_B_IN => '0', + STATE_B_OUT => reset_40mhz + ); + +arm_x <= slv_data_in(30) and store_wr; + +THE_ARM_PULSE_SYNC: pulse_sync +port map( CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => arm_x, + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset_40mhz, + PULSE_B_OUT => arm_40mhz + ); + +trg_x <= slv_data_in(31) and store_wr; + +THE_TRG_PULSE_SYNC: pulse_sync +port map( CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => trg_x, + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset_40mhz, + PULSE_B_OUT => trg_40mhz + ); + +THE_LOGIC_ANALYZER: logic_analyzer +port map( CLK_IN => adc_clk_in, + RESET_IN => reset_40mhz, + -- control signals + ARM_IN => arm_40mhz, -- BUGBUGBUG + TRG_IN => trg_40mhz, -- BUGBUGBUG + MAX_SAMPLE_IN => ctrl_reg(9 downto 0), + -- status signals + SM_ADDR_OUT => wr_addr, + SM_CE_OUT => open, + SM_WE_OUT => wr_we, + CLEAR_OUT => sm_clear, + RUN_OUT => sm_run, + SAMPLE_OUT => sm_sample, + READY_OUT => sm_ready, + LAST_OUT => sm_last, + -- Status lines + BSM_OUT => sm_bsm, + STAT => open + ); + +wr_data(15) <= sm_clear; +wr_data(14) <= sm_run; +wr_data(13) <= sm_sample; +wr_data(12) <= sm_last; +wr_data(11 downto 0) <= adc_data_in; + +THE_ADC0_SNOOP_MEM: adc_snoop_mem +port map( WRADDRESS => wr_addr, + DATA => wr_data, + WE => wr_we, + WRCLOCK => adc_clk_in, + WRCLOCKEN => '1', + RDADDRESS => slv_addr_in, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => rd_data + ); + +-- register write +THE_WRITE_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + ctrl_reg <= (others => '0'); + elsif( store_wr = '1' ) then + ctrl_reg <= slv_data_in(15 downto 0); + end if; + end if; +end process THE_WRITE_REG_PROC; + +-- register read +THE_READ_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + status_reg <= (others => '0'); + elsif( store_rd = '1' ) then + status_reg <= b"0000_00" & wr_addr & rd_data; + end if; + end if; +end process THE_READ_REG_PROC; + +-- output signals +slv_ack_out <= slv_ack; +slv_data_out <= status_reg; + +adc_sel_out <= ctrl_reg(14 downto 12); + +end Behavioral; diff --git a/src/reset_handler.vhd b/src/reset_handler.vhd new file mode 100644 index 0000000..8cc8bc5 --- /dev/null +++ b/src/reset_handler.vhd @@ -0,0 +1,75 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity reset_handler is + port( CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0') + RESET_IN : in std_logic; -- for testing, if not needed, set to '0' + CLK_IN : in std_logic; + TRB_RESET_IN : in std_logic; + RESET_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end; + +architecture behavioral of reset_handler is + +-- normal signals + signal async_sampler : std_logic_vector(7 downto 0); + signal async_pulse_x : std_logic; + signal async_pulse : std_logic; + signal reset_cnt : std_logic_vector(15 downto 0); + signal debug : std_logic_vector(15 downto 0); + signal reset : std_logic; + + attribute syn_preserve : boolean; + attribute syn_preserve of async_sampler : signal is true; + attribute syn_preserve of async_pulse : signal is true; + attribute syn_preserve of reset : signal is true; + attribute syn_preserve of reset_cnt : signal is true; + +begin + +-- sample the async reset line and react only on a long pulse +THE_ASYNC_SAMPLER_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + async_sampler(7 downto 0) <= async_sampler(6 downto 0) & clear_in; + async_pulse <= async_pulse_x; + end if; +end process THE_ASYNC_SAMPLER_PROC; + +async_pulse_x <= '1' when ( async_sampler = x"ff" ) else '0'; + +-- one global reset counter +THE_GLOBAL_RESET_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( (async_pulse = '1') or (reset_in = '1') or (trb_reset_in = '1') ) then + reset_cnt <= (others => '0'); + reset <= '1'; + else + reset_cnt <= reset_cnt + 1; + reset <= '1'; + if( reset_cnt = x"001F" ) then + reset <= '0'; + reset_cnt <= x"001F"; + end if; + end if; + end if; +end process THE_GLOBAL_RESET_PROC; + + +-- Debug signals +debug <= reset_cnt; + +-- Output signals +debug_out <= debug; +reset_out <= reset; + +end behavioral; + \ No newline at end of file diff --git a/src/rich_trb.vhd b/src/rich_trb.vhd new file mode 100755 index 0000000..c21020e --- /dev/null +++ b/src/rich_trb.vhd @@ -0,0 +1,305 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.ALL; +use IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.version.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.adcmv3_components.all; + +entity rich_trb is +port( CLK100M_IN : in std_logic; -- SerDes exclusive clock + SYSCLK_IN : in std_logic; -- fabric clock + RESET_IN : in std_logic; -- synchronous reset + -- SFP connections + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_PRESENT_IN : in std_logic; + SD_TXDIS_OUT : out std_logic; + SD_LOS_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic; + -- common regIO status / control registers + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI + -- status register input to regIO / control register output from regIO + CONTROL_OUT : out std_logic_vector(63 downto 0); + STATUS_IN : in std_logic_vector(127 downto 0); + -- LVL1 signals + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_OUT : out std_logic; + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_IN : in std_logic; + TIMING_TRG_FOUND_IN : in std_logic; + -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) + IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_OUT : out std_logic; -- gimme data! + IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_IN : in std_logic; -- data is valid + IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM + IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle + IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern + -- regIO bus + REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATAREADY_IN : in std_logic; + REGIO_NO_MORE_DATA_IN : in std_logic; + REGIO_WRITE_ACK_IN : in std_logic; + REGIO_UNKNOWN_ADDR_IN : in std_logic; + REGIO_TIMEOUT_OUT : out std_logic; + -- status LEDs + LED_LINK_STAT : out std_logic; + LED_LINK_TXD : out std_logic; + LED_LINK_RXD : out std_logic; + LINK_BSM_OUT : out std_logic_vector(3 downto 0); + RESET_OUT : out std_logic; + -- Debug + DEBUG : out std_logic_vector(63 downto 0) + ); +end entity; + +architecture rich_arch of rich_trb is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of rich_arch : architecture is "RICH_TRB_group"; + + -- Signals + signal clk_en : std_logic; + signal med_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_out : std_logic; + signal med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_in : std_logic; + signal med_stat_debug : std_logic_vector(63 downto 0); + signal med_ctrl_op : std_logic_vector(15 downto 0); + signal med_stat_op : std_logic_vector(15 downto 0); + + -- general purpose control and status registers in regIO + signal regio_ctrl_regs : std_logic_vector(32*2-1 downto 0); + signal regio_stat_regs : std_logic_vector(32*4-1 downto 0); + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); + + signal debug_x : std_logic_vector(63 downto 0); + + signal stat_debug_1 : std_logic_vector(31 downto 0); + +begin + +--####################################################################### + +--####################################################################### + +-- Debug +debug <= debug_x; + +-- Clock assignment. We don't use CLK_EN really in our designs. +clk_en <= '1'; + +------------------------------------------------------------- +-- Serdes +------------------------------------------------------------- +THE_MEDIA_INTERFACE : trb_net16_med_ecp_sfp_gbe +generic map( SERDES_NUM => 2 ) +port map( CLK => clk100m_in, + SYSCLK => sysclk_in, + RESET => reset_in, + CLK_EN => clk_en, + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => sd_rxd_p_in, + SD_RXD_N_IN => sd_rxd_n_in, + SD_TXD_P_OUT => sd_txd_p_out, + SD_TXD_N_OUT => sd_txd_n_out, + SD_REFCLK_P_IN => '1', + SD_REFCLK_N_IN => '0', + SD_PRSNT_N_IN => sd_present_in, + SD_LOS_IN => sd_los_in, + SD_TXDIS_OUT => sd_txdis_out, + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, -- input + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--debug_x <= med_stat_debug; + +debug_x(63 downto 42) <= (others => '0'); +debug_x(41) <= med_read_out; -- MED_READ_IN +debug_x(40) <= med_dataready_in; -- MED_DATAREADY_OUT +debug_x(39 downto 37) <= med_packet_num_in; -- MED_PACKET_NUM_OUT +debug_x(36 downto 21) <= med_data_in; -- MED_DATA_OUT +debug_x(20) <= med_read_in; -- MED_READ_OUT +debug_x(19) <= med_dataready_out; -- MED_DATAREADY_IN +debug_x(18 downto 16) <= med_packet_num_out; -- MED_PACKET_NUM_IN +debug_x(15 downto 0) <= med_data_out; -- MED_DATA_IN + +-- 16 MED_DATA_IN : in std_logic_vector(15 downto 0); +-- 3 MED_PACKET_NUM_IN : in std_logic_vector(2 downto 0); +-- 1 MED_DATAREADY_IN : in std_logic; +-- 1 MED_READ_OUT : out std_logic; +-- 16 MED_DATA_OUT : out std_logic_vector(15 downto 0); +-- 3 MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); +-- 1 MED_DATAREADY_OUT : out std_logic; +-- 1 MED_READ_IN : in std_logic; +-- 42 + + ------------------------------------------------------------ +-- Full featured HADES endpoint +------------------------------------------------------------- +THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full +generic map( USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES), + INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before? + REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES), + REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO), + BROADCAST_BITMASK => x"FB", -- RICH uses 0xfffb as subnet mask for broadcasts + REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] + REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] + --standard values for output registers + REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000", + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS => "00000001", + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", + REGIO_USE_DAT_PORT => c_YES, + REGIO_INIT_ADDRESS => x"fb00", + REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f", + REGIO_INIT_BOARD_INFO => x"5aa5_3cc3", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_COMPILE_TIME => VERSION_NUMBER_TIME, + REGIO_COMPILE_VERSION => x"0003", + REGIO_HARDWARE_VERSION => x"0002_0000", + REGIO_USE_1WIRE_INTERFACE => c_YES, + CLOCK_FREQUENCY => 100 + ) +port map( CLK => sysclk_in, + RESET => reset_in, + CLK_EN => clk_en, + -- Media direction port + MED_DATAREADY_OUT => med_dataready_out, + MED_DATA_OUT => med_data_out, + MED_PACKET_NUM_OUT => med_packet_num_out, + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + -- LVL1 trigger APL + LVL1_TRG_TYPE_OUT => lvl1_trg_type_out, + LVL1_TRG_RECEIVED_OUT => lvl1_trg_received_out, + LVL1_TRG_NUMBER_OUT => lvl1_trg_number_out, + LVL1_TRG_CODE_OUT => lvl1_trg_code_out, + LVL1_TRG_INFORMATION_OUT => lvl1_trg_information_out, + LVL1_ERROR_PATTERN_IN => lvl1_error_pattern_in, + LVL1_TRG_RELEASE_IN => lvl1_trg_release_in, + LVL1_INT_TRG_NUMBER_OUT => open, -- unknown!!! + -- IPU Port + IPU_NUMBER_OUT => ipu_number_out, + IPU_READOUT_TYPE_OUT => open, -- 4bit readout type + IPU_INFORMATION_OUT => ipu_information_out, + IPU_START_READOUT_OUT => ipu_start_readout_out, + IPU_DATA_IN => ipu_data_in, + IPU_DATAREADY_IN => ipu_dataready_in, + IPU_READOUT_FINISHED_IN => ipu_readout_finished_in, + IPU_READ_OUT => ipu_read_out, + IPU_LENGTH_IN => ipu_length_in, + IPU_ERROR_PATTERN_IN => ipu_error_pattern_in, + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, + REGIO_REGISTERS_IN => regio_stat_regs, + REGIO_REGISTERS_OUT => regio_ctrl_regs, + COMMON_STAT_REG_STROBE => open, --: out std_logic_vector(std_COMSTATREG-1 downto 0); + COMMON_CTRL_REG_STROBE => open, --: out std_logic_vector(std_COMCTRLREG-1 downto 0); + STAT_REG_STROBE => open, --: out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE => open, --: out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + --IDRAM is used if no 1-wire interface, onewire used otherwise + REGIO_IDRAM_DATA_IN => x"0000", -- not used + REGIO_IDRAM_DATA_OUT => open, -- not used + REGIO_IDRAM_ADDR_IN => "000", -- not used + REGIO_IDRAM_WR_IN => '0', -- not used + REGIO_ONEWIRE_INOUT => onewire_inout, + REGIO_ONEWIRE_MONITOR_IN => '1', -- not used + REGIO_ONEWIRE_MONITOR_OUT => open, -- not used + -- New stuff?!? + TRIGGER_MONITOR_IN => timing_trg_found_in, + GLOBAL_TIME_OUT => open, + LOCAL_TIME_OUT => open, + TIME_SINCE_LAST_TRG_OUT => open, + TIMER_US_TICK_OUT => open, + -- Status and debug + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => stat_debug_1, --open, + STAT_DEBUG_2 => open, + MED_STAT_OP => open, + CTRL_MPLEX => x"00000000", + IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000", + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open + ); + +-- Control register assignment + +-- Common status register +common_stat_reg(COMMON_STAT_REG'left downto 32) <= common_stat_reg_in(63 downto 32); --(others => '0'); +common_stat_reg(31 downto 20) <= (others => '0'); -- already taken by TEMP of 1WID +common_stat_reg(19 downto 0) <= common_stat_reg_in(19 downto 0); --(others => '0'); + +-- Common control register +common_ctrl_reg_out <= common_ctrl_reg; + +-- User status register +regio_stat_regs <= status_in; +control_out <= regio_ctrl_regs; + +-- FPGA LEDs +led_link_stat <= not med_stat_op(9); -- link status +led_link_rxd <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive +led_link_txd <= not med_stat_op(11); -- data transmit +link_bsm_out <= med_stat_op(7 downto 4); -- LSM state bits +reset_out <= med_stat_op(13); -- TRB generated reset + +end architecture; + \ No newline at end of file diff --git a/src/slave_bus.vhd b/src/slave_bus.vhd new file mode 100644 index 0000000..1560432 --- /dev/null +++ b/src/slave_bus.vhd @@ -0,0 +1,818 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.adcmv3_components.all; + + +entity slave_bus is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- RegIO signals + REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus + REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint + REGIO_READ_ENABLE_IN : in std_logic; -- read pulse + REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse + REGIO_TIMEOUT_IN : in std_logic; -- access timed out + REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested + REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted + REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now + REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- 1Wire connections + ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse) + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); + BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + -- ADC 0 SPI connections + SPI_ADC0_CS_OUT : out std_logic; + SPI_ADC0_SCK_OUT : out std_logic; + SPI_ADC0_SDO_OUT : out std_logic; + ADC0_PLL_LOCKED_IN : in std_logic; + ADC0_PD_OUT : out std_logic; + ADC0_RST_OUT : out std_logic; + ADC0_DEL_OUT : out std_logic_vector(3 downto 0); + ADC0_CLK_IN : in std_logic; + ADC0_DATA_IN : in std_logic_vector(11 downto 0); + ADC0_SEL_OUT : out std_logic_vector(2 downto 0); + APV0_RST_OUT : out std_logic; + -- ADC 1 SPI connections + SPI_ADC1_CS_OUT : out std_logic; + SPI_ADC1_SCK_OUT : out std_logic; + SPI_ADC1_SDO_OUT : out std_logic; + ADC1_PLL_LOCKED_IN : in std_logic; + ADC1_PD_OUT : out std_logic; + ADC1_RST_OUT : out std_logic; + ADC1_DEL_OUT : out std_logic_vector(3 downto 0); + ADC1_CLK_IN : in std_logic; + ADC1_DATA_IN : in std_logic_vector(11 downto 0); + ADC1_SEL_OUT : out std_logic_vector(2 downto 0); + APV1_RST_OUT : out std_logic; + -- User specific inputs / outputs + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- pedestal interface + PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers + PED_DATA_0_OUT : out std_logic_vector(17 downto 0); + PED_DATA_1_OUT : out std_logic_vector(17 downto 0); + PED_DATA_2_OUT : out std_logic_vector(17 downto 0); + PED_DATA_3_OUT : out std_logic_vector(17 downto 0); + PED_DATA_4_OUT : out std_logic_vector(17 downto 0); + PED_DATA_5_OUT : out std_logic_vector(17 downto 0); + PED_DATA_6_OUT : out std_logic_vector(17 downto 0); + PED_DATA_7_OUT : out std_logic_vector(17 downto 0); + PED_DATA_8_OUT : out std_logic_vector(17 downto 0); + PED_DATA_9_OUT : out std_logic_vector(17 downto 0); + PED_DATA_10_OUT : out std_logic_vector(17 downto 0); + PED_DATA_11_OUT : out std_logic_vector(17 downto 0); + PED_DATA_12_OUT : out std_logic_vector(17 downto 0); + PED_DATA_13_OUT : out std_logic_vector(17 downto 0); + PED_DATA_14_OUT : out std_logic_vector(17 downto 0); + PED_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- threshold interface + THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers + THR_DATA_0_OUT : out std_logic_vector(17 downto 0); + THR_DATA_1_OUT : out std_logic_vector(17 downto 0); + THR_DATA_2_OUT : out std_logic_vector(17 downto 0); + THR_DATA_3_OUT : out std_logic_vector(17 downto 0); + THR_DATA_4_OUT : out std_logic_vector(17 downto 0); + THR_DATA_5_OUT : out std_logic_vector(17 downto 0); + THR_DATA_6_OUT : out std_logic_vector(17 downto 0); + THR_DATA_7_OUT : out std_logic_vector(17 downto 0); + THR_DATA_8_OUT : out std_logic_vector(17 downto 0); + THR_DATA_9_OUT : out std_logic_vector(17 downto 0); + THR_DATA_10_OUT : out std_logic_vector(17 downto 0); + THR_DATA_11_OUT : out std_logic_vector(17 downto 0); + THR_DATA_12_OUT : out std_logic_vector(17 downto 0); + THR_DATA_13_OUT : out std_logic_vector(17 downto 0); + THR_DATA_14_OUT : out std_logic_vector(17 downto 0); + THR_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- APV control / status + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- some control signals + CTRL_LVL_OUT : out std_logic_vector(31 downto 0); + CTRL_TRG_OUT : out std_logic_vector(31 downto 0); + CTRL_PLL_OUT : out std_logic_vector(15 downto 0); + STATUS_PLL_IN : in std_logic_vector(15 downto 0); + -- temporary stuff + TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing! + TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing! + -- Debug + DEBUG_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture Behavioral of slave_bus is + + -- Signals + signal slv_read : std_logic_vector(15-1 downto 0); + signal slv_write : std_logic_vector(15-1 downto 0); + signal slv_busy : std_logic_vector(15-1 downto 0); + signal slv_ack : std_logic_vector(15-1 downto 0); + signal slv_addr : std_logic_vector(15*16-1 downto 0); + signal slv_data_rd : std_logic_vector(15*32-1 downto 0); + signal slv_data_wr : std_logic_vector(15*32-1 downto 0); + + -- SPI controller BRAM lines + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + signal spi_cs : std_logic; + signal spi_sck : std_logic; + signal spi_sdi : std_logic; + signal spi_sdo : std_logic; + signal spi_debug : std_logic_vector(31 downto 0); + + signal ctrl_lvl : std_logic_vector(31 downto 0); + signal ctrl_trg : std_logic_vector(31 downto 0); + signal ctrl_pll : std_logic_vector(15 downto 0); + + signal debug : std_logic_vector(63 downto 0); + signal onewire_debug : std_logic_vector(63 downto 0); + +begin + +-- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus +THE_BUS_HANDLER: trb_net16_regio_bus_handler +generic map( PORT_NUMBER => 15, + PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories + 1 => x"a800", -- threshold memories + 2 => x"8040", -- I2C master + 3 => x"c000", -- 1Wire master + memory + 4 => x"d000", -- SPI master + 5 => x"d100", -- SPI data memory + 6 => x"d010", -- ADC0 SPI + 7 => x"d020", -- ADC1 SPI + 8 => x"b000", -- APV control / status + 9 => x"b010", -- ADC level settings + 10 => x"b020", -- trigger settings + 11 => x"b030", -- PLL settings + 12 => x"f000", -- ADC 0 snooper + 13 => x"f800", -- ADC 1 snooper + 14 => x"8000", -- test register (busy) + others => x"0000"), + PORT_ADDR_MASK => ( 0 => 11, -- pedestal memories + 1 => 11, -- threshold memories + 2 => 0, -- I2C master + 3 => 6, -- 1Wire master + memory + 4 => 1, -- SPI master + 5 => 6, -- SPI data memory + 6 => 0, -- ADC0 SPI + 7 => 0, -- ADC1 SPI + 8 => 4, -- APV control / status + 9 => 0, -- ADC level settings + 10 => 0, -- trigger settings + 11 => 0, -- PLL settings + 12 => 10, -- ADC 0 snooper + 13 => 10, -- ADC 1 snooper + 14 => 0, -- test register (normal) + others => 0) + ) +port map( CLK => clk_in, + RESET => reset_in, + DAT_ADDR_IN => regio_addr_in, + DAT_DATA_IN => regio_data_in, + DAT_DATA_OUT => regio_data_out, + DAT_READ_ENABLE_IN => regio_read_enable_in, + DAT_WRITE_ENABLE_IN => regio_write_enable_in, + DAT_TIMEOUT_IN => regio_timeout_in, + DAT_DATAREADY_OUT => regio_dataready_out, + DAT_WRITE_ACK_OUT => regio_write_ack_out, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_out, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_out, + -- pedestal memories + BUS_READ_ENABLE_OUT(0) => slv_read(0), + BUS_WRITE_ENABLE_OUT(0) => slv_write(0), + BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32), + BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32), + BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16), + BUS_TIMEOUT_OUT(0) => open, + BUS_DATAREADY_IN(0) => slv_ack(0), + BUS_WRITE_ACK_IN(0) => slv_ack(0), + BUS_NO_MORE_DATA_IN(0) => slv_busy(0), + BUS_UNKNOWN_ADDR_IN(0) => '0', + -- threshold memories + BUS_READ_ENABLE_OUT(1) => slv_read(1), + BUS_WRITE_ENABLE_OUT(1) => slv_write(1), + BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32), + BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32), + BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16), + BUS_TIMEOUT_OUT(1) => open, + BUS_DATAREADY_IN(1) => slv_ack(1), + BUS_WRITE_ACK_IN(1) => slv_ack(1), + BUS_NO_MORE_DATA_IN(1) => slv_busy(1), + BUS_UNKNOWN_ADDR_IN(1) => '0', + -- I2C master + BUS_READ_ENABLE_OUT(2) => slv_read(2), + BUS_WRITE_ENABLE_OUT(2) => slv_write(2), + BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), + BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), + BUS_ADDR_OUT(2*16+15 downto 2*16) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATAREADY_IN(2) => slv_ack(2), + BUS_WRITE_ACK_IN(2) => slv_ack(2), + BUS_NO_MORE_DATA_IN(2) => slv_busy(2), + BUS_UNKNOWN_ADDR_IN(2) => '0', + -- OneWire master + BUS_READ_ENABLE_OUT(3) => slv_read(3), + BUS_WRITE_ENABLE_OUT(3) => slv_write(3), + BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32), + BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32), + BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16), + BUS_TIMEOUT_OUT(3) => open, + BUS_DATAREADY_IN(3) => slv_ack(3), + BUS_WRITE_ACK_IN(3) => slv_ack(3), + BUS_NO_MORE_DATA_IN(3) => slv_busy(3), + BUS_UNKNOWN_ADDR_IN(3) => '0', + -- SPI control registers + BUS_READ_ENABLE_OUT(4) => slv_read(4), + BUS_WRITE_ENABLE_OUT(4) => slv_write(4), + BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32), + BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), + BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16), + BUS_TIMEOUT_OUT(4) => open, + BUS_DATAREADY_IN(4) => slv_ack(4), + BUS_WRITE_ACK_IN(4) => slv_ack(4), + BUS_NO_MORE_DATA_IN(4) => slv_busy(4), + BUS_UNKNOWN_ADDR_IN(4) => '0', + -- SPI data memory + BUS_READ_ENABLE_OUT(5) => slv_read(5), + BUS_WRITE_ENABLE_OUT(5) => slv_write(5), + BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32), + BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32), + BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16), + BUS_TIMEOUT_OUT(5) => open, + BUS_DATAREADY_IN(5) => slv_ack(5), + BUS_WRITE_ACK_IN(5) => slv_ack(5), + BUS_NO_MORE_DATA_IN(5) => slv_busy(5), + BUS_UNKNOWN_ADDR_IN(5) => '0', + -- ADC 0 SPI control registers + BUS_READ_ENABLE_OUT(6) => slv_read(6), + BUS_WRITE_ENABLE_OUT(6) => slv_write(6), + BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32), + BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32), + BUS_ADDR_OUT(6*16+15 downto 6*16) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATAREADY_IN(6) => slv_ack(6), + BUS_WRITE_ACK_IN(6) => slv_ack(6), + BUS_NO_MORE_DATA_IN(6) => slv_busy(6), + BUS_UNKNOWN_ADDR_IN(6) => '0', + -- ADC 1 SPI control registers + BUS_READ_ENABLE_OUT(7) => slv_read(7), + BUS_WRITE_ENABLE_OUT(7) => slv_write(7), + BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32), + BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32), + BUS_ADDR_OUT(7*16+15 downto 7*16) => open, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATAREADY_IN(7) => slv_ack(7), + BUS_WRITE_ACK_IN(7) => slv_ack(7), + BUS_NO_MORE_DATA_IN(7) => slv_busy(7), + BUS_UNKNOWN_ADDR_IN(7) => '0', + -- APV control / status registers + BUS_READ_ENABLE_OUT(8) => slv_read(8), + BUS_WRITE_ENABLE_OUT(8) => slv_write(8), + BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32), + BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32), + BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16), + BUS_TIMEOUT_OUT(8) => open, + BUS_DATAREADY_IN(8) => slv_ack(8), + BUS_WRITE_ACK_IN(8) => slv_ack(8), + BUS_NO_MORE_DATA_IN(8) => slv_busy(8), + BUS_UNKNOWN_ADDR_IN(8) => '0', + -- ADC / PLL / trigger ctrl register + BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9), + BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9), + BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32), + BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32), + BUS_ADDR_OUT(11*16+15 downto 9*16) => open, + BUS_TIMEOUT_OUT(11 downto 9) => open, + BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9), + BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9), + BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9), + BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'), + -- ADC0 snooper + BUS_READ_ENABLE_OUT(12) => slv_read(12), + BUS_WRITE_ENABLE_OUT(12) => slv_write(12), + BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32), + BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32), + BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16), + BUS_TIMEOUT_OUT(12) => open, + BUS_DATAREADY_IN(12) => slv_ack(12), + BUS_WRITE_ACK_IN(12) => slv_ack(12), + BUS_NO_MORE_DATA_IN(12) => slv_busy(12), + BUS_UNKNOWN_ADDR_IN(12) => '0', + -- ADC1 snooper + BUS_READ_ENABLE_OUT(13) => slv_read(13), + BUS_WRITE_ENABLE_OUT(13) => slv_write(13), + BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32), + BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32), + BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16), + BUS_TIMEOUT_OUT(13) => open, + BUS_DATAREADY_IN(13) => slv_ack(13), + BUS_WRITE_ACK_IN(13) => slv_ack(13), + BUS_NO_MORE_DATA_IN(13) => slv_busy(13), + BUS_UNKNOWN_ADDR_IN(13) => '0', + -- Test register + BUS_READ_ENABLE_OUT(14) => slv_read(14), + BUS_WRITE_ENABLE_OUT(14) => slv_write(14), + BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32), + BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32), + BUS_ADDR_OUT(14*16+15 downto 14*16) => open, + BUS_TIMEOUT_OUT(14) => open, + BUS_DATAREADY_IN(14) => slv_ack(14), + BUS_WRITE_ACK_IN(14) => slv_ack(14), + BUS_NO_MORE_DATA_IN(14) => slv_busy(14), + BUS_UNKNOWN_ADDR_IN(14) => '0', + -- debug + STAT_DEBUG => stat + ); + + +------------------------------------------------------------------------------------ +-- pedestal memories (16x128 = 2048, 18bit) +------------------------------------------------------------------------------------ +THE_PED_MEM: slv_ped_thr_mem +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(0*16+10 downto 0*16), + SLV_READ_IN => slv_read(0), + SLV_WRITE_IN => slv_write(0), + SLV_ACK_OUT => slv_ack(0), + SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32), + SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), + -- backplane identifier + BACKPLANE_IN => backplane_in, + -- I/O to the backend + MEM_CLK_IN => clk_in, + MEM_ADDR_IN => ped_addr_in, + MEM_0_D_OUT => ped_data_0_out, + MEM_1_D_OUT => ped_data_1_out, + MEM_2_D_OUT => ped_data_2_out, + MEM_3_D_OUT => ped_data_3_out, + MEM_4_D_OUT => ped_data_4_out, + MEM_5_D_OUT => ped_data_5_out, + MEM_6_D_OUT => ped_data_6_out, + MEM_7_D_OUT => ped_data_7_out, + MEM_8_D_OUT => ped_data_8_out, + MEM_9_D_OUT => ped_data_9_out, + MEM_10_D_OUT => ped_data_10_out, + MEM_11_D_OUT => ped_data_11_out, + MEM_12_D_OUT => ped_data_12_out, + MEM_13_D_OUT => ped_data_13_out, + MEM_14_D_OUT => ped_data_14_out, + MEM_15_D_OUT => ped_data_15_out, + -- Status lines + STAT => open + ); +slv_busy(0) <= '0'; + +------------------------------------------------------------------------------------ +-- threshold memories (16x128 = 2048, 18bit) +------------------------------------------------------------------------------------ +THE_THR_MEM: slv_ped_thr_mem +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(1*16+10 downto 1*16), + SLV_READ_IN => slv_read(1), + SLV_WRITE_IN => slv_write(1), + SLV_ACK_OUT => slv_ack(1), + SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32), + SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32), + -- backplane identifier + BACKPLANE_IN => backplane_in, + -- I/O to the backend + MEM_CLK_IN => clk_in, + MEM_ADDR_IN => thr_addr_in, + MEM_0_D_OUT => thr_data_0_out, + MEM_1_D_OUT => thr_data_1_out, + MEM_2_D_OUT => thr_data_2_out, + MEM_3_D_OUT => thr_data_3_out, + MEM_4_D_OUT => thr_data_4_out, + MEM_5_D_OUT => thr_data_5_out, + MEM_6_D_OUT => thr_data_6_out, + MEM_7_D_OUT => thr_data_7_out, + MEM_8_D_OUT => thr_data_8_out, + MEM_9_D_OUT => thr_data_9_out, + MEM_10_D_OUT => thr_data_10_out, + MEM_11_D_OUT => thr_data_11_out, + MEM_12_D_OUT => thr_data_12_out, + MEM_13_D_OUT => thr_data_13_out, + MEM_14_D_OUT => thr_data_14_out, + MEM_15_D_OUT => thr_data_15_out, + -- Status lines + STAT => open + ); +slv_busy(1) <= '0'; + +------------------------------------------------------------------------------------ +-- I2C master block for accessing APVs +------------------------------------------------------------------------------------ +THE_I2C_MASTER: i2c_master +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_READ_IN => slv_read(2), + SLV_WRITE_IN => slv_write(2), + SLV_BUSY_OUT => slv_busy(2), + SLV_ACK_OUT => slv_ack(2), + SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32), + SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), + -- I2C connections + SDA_IN => sda_in, + SDA_OUT => sda_out, + SCL_IN => scl_in, + SCL_OUT => scl_out, + -- Status lines + STAT => open + ); + +------------------------------------------------------------------------------------ +-- 1Wire master including status memory +------------------------------------------------------------------------------------ +THE_ONEWIRE_MEMORY: slv_onewire_memory +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(3*16+5 downto 3*16), + SLV_READ_IN => slv_read(3), + SLV_WRITE_IN => slv_write(3), + SLV_ACK_OUT => slv_ack(3), + SLV_BUSY_OUT => open, + SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32), + -- backplane identifier + BACKPLANE_IN => backplane_in, + -- 1Wire lines + ONEWIRE_START_IN => onewire_start_in, -- not used yet + ONEWIRE_INOUT => onewire_inout, + BP_ONEWIRE_INOUT => bp_onewire_inout, + -- Status lines + STAT => onewire_debug --open + ); +slv_busy(3) <= '0'; + +------------------------------------------------------------------------------------ +-- SPI master +------------------------------------------------------------------------------------ +THE_SPI_MASTER: spi_master +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + BUS_READ_IN => slv_read(4), + BUS_WRITE_IN => slv_write(4), + BUS_BUSY_OUT => slv_busy(4), + BUS_ACK_OUT => slv_ack(4), + BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16), + BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32), + BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32), + -- SPI connections + SPI_CS_OUT => spi_cs, + SPI_SDI_IN => spi_sdi, + SPI_SDO_OUT => spi_sdo, + SPI_SCK_OUT => spi_sck, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => spi_debug --open + ); + +------------------------------------------------------------------------------------ +-- data memory for SPI accesses +------------------------------------------------------------------------------------ +THE_SPI_MEMORY: spi_databus_memory +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16), + BUS_READ_IN => slv_read(5), + BUS_WRITE_IN => slv_write(5), + BUS_ACK_OUT => slv_ack(5), + BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32), + BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32), + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); +slv_busy(5) <= '0'; + +------------------------------------------------------------------------------------ +-- ADC0 SPI master +------------------------------------------------------------------------------------ +THE_SPI_ADC0_MASTER: spi_adc_master +generic map( RESET_VALUE_CTRL => x"60" ) +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_READ_IN => slv_read(6), + SLV_WRITE_IN => slv_write(6), + SLV_BUSY_OUT => slv_busy(6), + SLV_ACK_OUT => slv_ack(6), + SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32), + SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32), + -- SPI connections + SPI_CS_OUT => spi_adc0_cs_out, + SPI_SDO_OUT => spi_adc0_sdo_out, + SPI_SCK_OUT => spi_adc0_sck_out, + -- ADC connections + ADC_LOCKED_IN => adc0_pll_locked_in, + ADC_PD_OUT => adc0_pd_out, + ADC_RST_OUT => adc0_rst_out, + ADC_DEL_OUT => adc0_del_out, + -- APV connections + APV_RST_OUT => apv0_rst_out, + -- Status lines + STAT => open + ); + +------------------------------------------------------------------------------------ +-- ADC1 SPI master +------------------------------------------------------------------------------------ +THE_SPI_ADC1_MASTER: spi_adc_master +generic map( RESET_VALUE_CTRL => x"60" ) +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_READ_IN => slv_read(7), + SLV_WRITE_IN => slv_write(7), + SLV_BUSY_OUT => slv_busy(7), + SLV_ACK_OUT => slv_ack(7), + SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32), + SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32), + -- SPI connections + SPI_CS_OUT => spi_adc1_cs_out, + SPI_SDO_OUT => spi_adc1_sdo_out, + SPI_SCK_OUT => spi_adc1_sck_out, + -- ADC connections + ADC_LOCKED_IN => adc1_pll_locked_in, + ADC_PD_OUT => adc1_pd_out, + ADC_RST_OUT => adc1_rst_out, + ADC_DEL_OUT => adc1_del_out, + -- APV connections + APV_RST_OUT => apv1_rst_out, + -- Status lines + STAT => open + ); + +------------------------------------------------------------------------------------ +-- APV control / status registers +------------------------------------------------------------------------------------ +THE_SLV_REGISTER_BANK: slv_register_bank +generic map( RESET_VALUE => x"0001" ) +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(8*16+3 downto 8*16), + SLV_READ_IN => slv_read(8), + SLV_WRITE_IN => slv_write(8), + SLV_ACK_OUT => slv_ack(8), + SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32), + SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32), + -- I/O to the backend + BACKPLANE_IN => backplane_in, + CTRL_0_OUT => ctrl_0_out, + CTRL_1_OUT => ctrl_1_out, + CTRL_2_OUT => ctrl_2_out, + CTRL_3_OUT => ctrl_3_out, + CTRL_4_OUT => ctrl_4_out, + CTRL_5_OUT => ctrl_5_out, + CTRL_6_OUT => ctrl_6_out, + CTRL_7_OUT => ctrl_7_out, + CTRL_8_OUT => ctrl_8_out, + CTRL_9_OUT => ctrl_9_out, + CTRL_10_OUT => ctrl_10_out, + CTRL_11_OUT => ctrl_11_out, + CTRL_12_OUT => ctrl_12_out, + CTRL_13_OUT => ctrl_13_out, + CTRL_14_OUT => ctrl_14_out, + CTRL_15_OUT => ctrl_15_out, + STAT_0_IN => stat_0_in, + STAT_1_IN => stat_1_in, + STAT_2_IN => stat_2_in, + STAT_3_IN => stat_3_in, + STAT_4_IN => stat_4_in, + STAT_5_IN => stat_5_in, + STAT_6_IN => stat_6_in, + STAT_7_IN => stat_7_in, + STAT_8_IN => stat_8_in, + STAT_9_IN => stat_9_in, + STAT_10_IN => stat_10_in, + STAT_11_IN => stat_11_in, + STAT_12_IN => stat_12_in, + STAT_13_IN => stat_13_in, + STAT_14_IN => stat_14_in, + STAT_15_IN => stat_15_in, + -- Status lines + STAT => open + ); +slv_busy(8) <= '0'; + +------------------------------------------------------------------------------------ +-- ADC level register +------------------------------------------------------------------------------------ +THE_ADC_LVL_REG: slv_register +generic map( RESET_VALUE => x"d0_20_78_88" ) +port map( CLK_IN => clk_in, + RESET_IN => reset_in, -- general reset + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => slv_read(9), + SLV_WRITE_IN => slv_write(9), + SLV_BUSY_OUT => slv_busy(9), + SLV_ACK_OUT => slv_ack(9), + SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32), + SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32), + -- I/O to the backend + REG_DATA_IN => ctrl_lvl, + REG_DATA_OUT => ctrl_lvl, + -- Status lines + STAT => open + ); + +------------------------------------------------------------------------------------ +-- trigger control register +------------------------------------------------------------------------------------ +THE_TRG_CTRL_REG: slv_register +generic map( RESET_VALUE => x"10_10_10_10" ) +port map( CLK_IN => clk_in, + RESET_IN => reset_in, -- general reset + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => slv_read(10), + SLV_WRITE_IN => slv_write(10), + SLV_BUSY_OUT => slv_busy(10), + SLV_ACK_OUT => slv_ack(10), + SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32), + SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32), + -- I/O to the backend + REG_DATA_IN => ctrl_trg, + REG_DATA_OUT => ctrl_trg, + -- Status lines + STAT => open + ); + +------------------------------------------------------------------------------------ +-- PLL control register +------------------------------------------------------------------------------------ +THE_PLL_CTRL_REG: slv_half_register +generic map( RESET_VALUE => x"00_02" ) +port map( CLK_IN => clk_in, + RESET_IN => reset_in, -- general reset + -- Slave bus + SLV_READ_IN => slv_read(11), + SLV_WRITE_IN => slv_write(11), + SLV_ACK_OUT => slv_ack(11), + SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32), + SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32), + -- I/O to the backend + STATUS_REG_IN => status_pll_in, + CTRL_REG_OUT => ctrl_pll, + -- Status lines + STAT => open + ); +slv_busy(11) <= '0'; + +------------------------------------------------------------------------------------ +-- ADC0 snooper +------------------------------------------------------------------------------------ +THE_ADC0_SNOOPER: slv_adc_snoop +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(12*16+9 downto 12*16), + SLV_READ_IN => slv_read(12), + SLV_WRITE_IN => slv_write(12), + SLV_ACK_OUT => slv_ack(12), + SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32), + SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32), + -- I/O to the backend + ADC_SEL_OUT => adc0_sel_out, + ADC_CLK_IN => adc0_clk_in, + ADC_DATA_IN => adc0_data_in, + -- Status lines + STAT => open + ); +slv_busy(12) <= '0'; + + +------------------------------------------------------------------------------------ +-- ADC1 snooper +------------------------------------------------------------------------------------ +THE_ADC1_SNOOPER: slv_adc_snoop +port map( CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(13*16+9 downto 13*16), + SLV_READ_IN => slv_read(13), + SLV_WRITE_IN => slv_write(13), + SLV_ACK_OUT => slv_ack(13), + SLV_DATA_IN => slv_data_wr(13*32+31 downto 13*32), + SLV_DATA_OUT => slv_data_rd(13*32+31 downto 13*32), + -- I/O to the backend + ADC_SEL_OUT => adc1_sel_out, + ADC_CLK_IN => adc1_clk_in, + ADC_DATA_IN => adc1_data_in, + -- Status lines + STAT => open + ); +slv_busy(13) <= '0'; + + +------------------------------------------------------------------------------------ +-- test register (normal) +------------------------------------------------------------------------------------ +THE_GOOD_TEST_REG: slv_register +generic map( RESET_VALUE => x"dead_beef" ) +port map( CLK_IN => clk_in, + RESET_IN => reset_in, -- general reset + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => slv_read(14), + SLV_WRITE_IN => slv_write(14), + SLV_BUSY_OUT => slv_busy(14), + SLV_ACK_OUT => slv_ack(14), + SLV_DATA_IN => slv_data_wr(14*32+31 downto 14*32), + SLV_DATA_OUT => slv_data_rd(14*32+31 downto 14*32), + -- I/O to the backend + REG_DATA_IN => test_reg_in, --x"5a3c_87e1", + REG_DATA_OUT => test_reg_out, + -- Status lines + STAT => open + ); + + + + +-- unusable pins +debug(63 downto 43) <= (others => '0'); +-- connected pins +debug(42 downto 0) <= (others => '0'); + +-- input signals +spi_sdi <= spi_sdi_in; + +-- Output signals +spi_cs_out <= spi_cs; +spi_sck_out <= spi_sck; +spi_sdo_out <= spi_sdo; + +ctrl_lvl_out <= ctrl_lvl; +ctrl_trg_out <= ctrl_trg; +ctrl_pll_out <= ctrl_pll; + +debug_out <= debug; + +end Behavioral; diff --git a/src/slv_adc_la.vhd b/src/slv_adc_la.vhd new file mode 100644 index 0000000..ba109d2 --- /dev/null +++ b/src/slv_adc_la.vhd @@ -0,0 +1,246 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + + +entity slv_adc_la is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of slv_adc_la is + +-- Signals + + type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- slave bus signals + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + signal arm_x : std_logic; + signal trg_x : std_logic; + + signal ctrl_reg : std_logic_vector(15 downto 0); + signal status_reg : std_logic_vector(31 downto 0); + + signal rd_data : std_logic_vector(15 downto 0); + + -- 40MHz clock domain!!! + signal wr_data : std_logic_vector(15 downto 0); + signal wr_addr : std_logic_vector(9 downto 0); + signal wr_we : std_logic; + signal reset_40mhz : std_logic; + signal arm_40mhz : std_logic; + signal trg_40mhz : std_logic; + + signal sm_clear : std_logic; + signal sm_run : std_logic; + signal sm_sample : std_logic; + signal sm_ready : std_logic; + signal sm_last : std_logic; + signal sm_bsm : std_logic_vector(3 downto 0); + +begin + +-- Fake +stat(31 downto 25) <= (others => '0'); +stat(24) <= sm_last; +stat(23) <= sm_ready; +stat(22) <= sm_sample; +stat(21) <= sm_run; +stat(20) <= sm_clear; +stat(19 downto 16) <= sm_bsm; +stat(15 downto 0) <= ctrl_reg; + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in ) +begin + NEXT_STATE <= SLEEP; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( slv_read_in = '1' ) then + NEXT_STATE <= RD_DEL0; + store_rd_x <= '1'; + elsif( slv_write_in = '1' ) then + NEXT_STATE <= WR_DEL0; + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_DEL0 => NEXT_STATE <= RD_DEL1; + when RD_DEL1 => NEXT_STATE <= RD_RDY; + when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_DEL0 => NEXT_STATE <= WR_DEL1; + when WR_DEL1 => NEXT_STATE <= WR_RDY; + when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +THE_RST_SYNC: state_sync +port map( STATE_A_IN => reset_in, + CLK_B_IN => adc_clk_in, + RESET_B_IN => '0', + STATE_B_OUT => reset_40mhz + ); + +arm_x <= slv_data_in(30) and store_wr; + +THE_ARM_PULSE_SYNC: pulse_sync +port map( CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => arm_x, + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset_40mhz, + PULSE_B_OUT => arm_40mhz + ); + +trg_x <= slv_data_in(31) and store_wr; + +THE_TRG_PULSE_SYNC: pulse_sync +port map( CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => trg_x, + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset_40mhz, + PULSE_B_OUT => trg_40mhz + ); + +THE_LOGIC_ANALYZER: logic_analyzer +port map( CLK_IN => adc_clk_in, + RESET_IN => reset_40mhz, + -- control signals + ARM_IN => arm_40mhz, -- BUGBUGBUG + TRG_IN => trg_40mhz, -- BUGBUGBUG + MAX_SAMPLE_IN => ctrl_reg(9 downto 0), + -- status signals + SM_ADDR_OUT => wr_addr, + SM_CE_OUT => open, + SM_WE_OUT => wr_we, + CLEAR_OUT => sm_clear, + RUN_OUT => sm_run, + SAMPLE_OUT => sm_sample, + READY_OUT => sm_ready, + LAST_OUT => sm_last, + -- Status lines + BSM_OUT => sm_bsm, + STAT => open + ); + +wr_data(15) <= sm_clear; +wr_data(14) <= sm_run; +wr_data(13) <= sm_sample; +wr_data(12) <= sm_last; +wr_data(11 downto 0) <= adc_data_in; + +THE_ADC0_SNOOP_MEM: adc_snoop_mem +port map( WRADDRESS => wr_addr, + DATA => wr_data, + WE => wr_we, + WRCLOCK => adc_clk_in, + WRCLOCKEN => '1', + RDADDRESS => slv_addr_in, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => rd_data + ); + +-- register write +THE_WRITE_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + ctrl_reg <= (others => '0'); + elsif( store_wr = '1' ) then + ctrl_reg <= slv_data_in(15 downto 0); + end if; + end if; +end process THE_WRITE_REG_PROC; + +-- register read +THE_READ_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + status_reg <= (others => '0'); + elsif( store_rd = '1' ) then + status_reg <= b"0000_00" & wr_addr & rd_data; + end if; + end if; +end process THE_READ_REG_PROC; + +-- output signals +slv_ack_out <= slv_ack; +slv_data_out <= status_reg; + +adc_sel_out <= ctrl_reg(14 downto 12); + +end Behavioral; diff --git a/src/slv_adc_snoop.vhd b/src/slv_adc_snoop.vhd new file mode 100644 index 0000000..d130d70 --- /dev/null +++ b/src/slv_adc_snoop.vhd @@ -0,0 +1,209 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + + +entity slv_adc_snoop is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of slv_adc_snoop is + +-- Signals + + type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- slave bus signals + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + signal ctrl_reg : std_logic_vector(15 downto 0); + signal status_reg : std_logic_vector(31 downto 0); + + signal rd_data : std_logic_vector(15 downto 0); + + -- 40MHz clock domain!!! + signal wr_data : std_logic_vector(15 downto 0); + signal wr_ctr : std_logic_vector(9 downto 0); + signal rst_wr_ctr : std_logic; + signal ce_wr_ctr : std_logic; + signal reset : std_logic; + +begin + +-- Fake +stat(31 downto 18) <= (others => '0'); +stat(17) <= rst_wr_ctr; +stat(16) <= ce_wr_ctr; +stat(15 downto 0) <= ctrl_reg; + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in ) +begin + NEXT_STATE <= SLEEP; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( slv_read_in = '1' ) then + NEXT_STATE <= RD_DEL0; + store_rd_x <= '1'; + elsif( slv_write_in = '1' ) then + NEXT_STATE <= WR_DEL0; + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_DEL0 => NEXT_STATE <= RD_DEL1; + when RD_DEL1 => NEXT_STATE <= RD_RDY; + when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_DEL0 => NEXT_STATE <= WR_DEL1; + when WR_DEL1 => NEXT_STATE <= WR_RDY; + when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +THE_RESET_SYNC: state_sync +port map( STATE_A_IN => reset_in, + CLK_B_IN => adc_clk_in, + RESET_B_IN => '0', + STATE_B_OUT => reset + ); + +THE_RST_SYNC: state_sync +port map( STATE_A_IN => ctrl_reg(15), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => rst_wr_ctr + ); + +THE_CE_SYNC: state_sync +port map( STATE_A_IN => ctrl_reg(14), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => ce_wr_ctr + ); + +THE_WR_CTR_PROC: process( adc_clk_in ) +begin + if( rising_edge(adc_clk_in) ) then + if ( (reset = '1') or (rst_wr_ctr = '1') ) then + wr_ctr <= (others => '0'); + elsif( ce_wr_ctr = '1' ) then + wr_ctr <= wr_ctr + 1; + end if; + end if; +end process THE_WR_CTR_PROC; + +wr_data <= x"0" & adc_data_in; + +THE_ADC0_SNOOP_MEM: adc_snoop_mem +port map( WRADDRESS => wr_ctr, + DATA => wr_data, + WE => ce_wr_ctr, + WRCLOCK => adc_clk_in, + WRCLOCKEN => '1', + RDADDRESS => slv_addr_in, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => rd_data + ); + +-- register write +THE_WRITE_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + ctrl_reg <= (others => '0'); + elsif( store_wr = '1' ) then + ctrl_reg <= slv_data_in(15 downto 0); + end if; + end if; +end process THE_WRITE_REG_PROC; + +-- register read +THE_READ_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + status_reg <= (others => '0'); + elsif( store_rd = '1' ) then + status_reg <= b"0000_00" & wr_ctr & rd_data; + end if; + end if; +end process THE_READ_REG_PROC; + +-- output signals +slv_ack_out <= slv_ack; +slv_data_out <= status_reg; + +adc_sel_out <= ctrl_reg(2 downto 0); + +end Behavioral; diff --git a/src/slv_half_register.vhd b/src/slv_half_register.vhd new file mode 100644 index 0000000..a4a1723 --- /dev/null +++ b/src/slv_half_register.vhd @@ -0,0 +1,150 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + + +entity slv_half_register is +generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" ); +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + STATUS_REG_IN : in std_logic_vector(15 downto 0); + CTRL_REG_OUT : out std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of slv_half_register is + +-- Signals + + type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- slave bus signals + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + signal ctrl_reg : std_logic_vector(15 downto 0); + + signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data + +begin + +-- Fake +stat <= (others => '0'); + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in ) +begin + NEXT_STATE <= SLEEP; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( slv_read_in = '1' ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( slv_write_in = '1' ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_RDY => NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + when WR_RDY => NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +-- register write +THE_WRITE_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + ctrl_reg <= (others => '0'); + elsif( store_wr = '1' ) then + ctrl_reg <= slv_data_in(15 downto 0); + end if; + end if; +end process THE_WRITE_REG_PROC; + +-- register read +THE_READ_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + reg_slv_data_out <= (others => '0'); + elsif( store_rd = '1' ) then + reg_slv_data_out <= status_reg_in & ctrl_reg; + end if; + end if; +end process THE_READ_REG_PROC; + +-- output signals +slv_ack_out <= slv_ack; +slv_data_out <= reg_slv_data_out; + +--------------------------------------------------------- +-- signals to backend -- +--------------------------------------------------------- + +ctrl_reg_out <= ctrl_reg; + +end Behavioral; diff --git a/src/slv_memory_true.vhd b/src/slv_memory_true.vhd new file mode 100644 index 0000000..2d4037b --- /dev/null +++ b/src/slv_memory_true.vhd @@ -0,0 +1,175 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +entity slv_memory_true is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(8 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(7 downto 0); + MEM_DATA_OUT : out std_logic_vector(17 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of slv_memory_true is + + +-- Signals + type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- slave bus signals + signal slv_busy_x : std_logic; + signal slv_busy : std_logic; + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + signal wr_addr : std_logic_vector(9 downto 0); -- some bits are masked + signal mem_data : std_logic_vector(17 downto 0); + signal rd_addr : std_logic_vector(9 downto 0); -- some bits are masked + signal readback_data : std_logic_vector(17 downto 0); + + signal reg_busy : std_logic; + +begin + +-- Fake +reg_busy <= busy_in; +stat <= (others => '0'); + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_busy <= '0'; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_busy <= slv_busy_x; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) +begin + NEXT_STATE <= SLEEP; + slv_busy_x <= '0'; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( (reg_busy = '0') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + elsif( (reg_busy = '1') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_BSY; + elsif( (reg_busy = '1') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_BSY; + else + NEXT_STATE <= SLEEP; + end if; + when RD_RDY => NEXT_STATE <= RD_ACK; + when WR_RDY => NEXT_STATE <= WR_ACK; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when RD_BSY => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_BSY; + slv_busy_x <= '1'; + end if; + when WR_BSY => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_BSY; + slv_busy_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +wr_addr <= b"00" & slv_addr_in(7 downto 0); +rd_addr <= b"00" & mem_addr_in(7 downto 0); + +-- one EBR used for one APV (A: TRBnet side, B: statemachines) +THE_PED_THR_MEM: ped_thr_mem_true +port map( DATAINA => slv_data_in(17 downto 0), + ADDRESSA => wr_addr, + CLOCKA => clk_in, + CLOCKENA => '1', + WRA => store_wr, + RESETA => reset_in, + QA => readback_data, + DATAINB => b"00_0000_0000_0000_0000", -- not used! + ADDRESSB => rd_addr, + CLOCKB => mem_clk_in, + CLOCKENB => '1', + WRB => '0', -- no write by statemachines! + RESETB => reset_in, + QB => mem_data + ); + +-- output signals +slv_ack_out <= slv_ack; +slv_busy_out <= slv_busy; +slv_data_out <= b"0000_0000_0000_00" & readback_data; + +--------------------------------------------------------- +-- signals to backend -- +--------------------------------------------------------- + +mem_data_out <= mem_data; + +end Behavioral; diff --git a/src/slv_onewire_dpram.lpc b/src/slv_onewire_dpram.lpc new file mode 100644 index 0000000..91cdd37 --- /dev/null +++ b/src/slv_onewire_dpram.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP +CoreRevision=6.1 +ModuleName=slv_onewire_dpram +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/11/2009 +Time=14:48:40 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +RAddress=64 +RData=32 +WAddress=128 +WData=16 +enByte=0 +ByteSize=9 +adPipeline=0 +inPipeline=0 +outPipeline=0 +MOR=0 +InData=Registered +AdControl=Registered +MemFile= +MemFormat=bin +Reset=Sync +GSR=Enabled +Pad=0 +EnECC=0 +Optimization=Speed +EnSleep=ENABLED +Pipeline=0 diff --git a/src/slv_onewire_dpram.srp b/src/slv_onewire_dpram.srp new file mode 100644 index 0000000..28e8aa5 --- /dev/null +++ b/src/slv_onewire_dpram.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Aug 11 14:48:40 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e + Circuit name : slv_onewire_dpram + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[31:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : slv_onewire_dpram.vhd + VHDL template : slv_onewire_dpram_tmpl.vhd + VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : slv_onewire_dpram.srp + Element Usage : + DP16KB : 1 + Estimated Resource Usage: + EBR : 1 diff --git a/src/slv_onewire_dpram.vhd b/src/slv_onewire_dpram.vhd new file mode 100644 index 0000000..b3f879c --- /dev/null +++ b/src/slv_onewire_dpram.vhd @@ -0,0 +1,194 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 6.1 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 16 -num_rows 128 -resetmode SYNC -cascade -1 -e + +-- Tue Aug 11 14:48:40 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity slv_onewire_dpram is + port ( + WrAddress: in std_logic_vector(6 downto 0); + RdAddress: in std_logic_vector(5 downto 0); + Data: in std_logic_vector(15 downto 0); + WE: in std_logic; + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + WrClock: in std_logic; + WrClockEn: in std_logic; + Q: out std_logic_vector(31 downto 0)); +end slv_onewire_dpram; + +architecture Structure of slv_onewire_dpram is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute GSR : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute MEM_LPC_FILE of slv_onewire_dpram_0_0_0 : label is "slv_onewire_dpram.lpc"; + attribute MEM_INIT_FILE of slv_onewire_dpram_0_0_0 : label is ""; + attribute CSDECODE_B of slv_onewire_dpram_0_0_0 : label is "0b000"; + attribute CSDECODE_A of slv_onewire_dpram_0_0_0 : label is "0b000"; + attribute WRITEMODE_B of slv_onewire_dpram_0_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of slv_onewire_dpram_0_0_0 : label is "NORMAL"; + attribute GSR of slv_onewire_dpram_0_0_0 : label is "DISABLED"; + attribute RESETMODE of slv_onewire_dpram_0_0_0 : label is "SYNC"; + attribute REGMODE_B of slv_onewire_dpram_0_0_0 : label is "NOREG"; + attribute REGMODE_A of slv_onewire_dpram_0_0_0 : label is "NOREG"; + attribute DATA_WIDTH_B of slv_onewire_dpram_0_0_0 : label is "36"; + attribute DATA_WIDTH_A of slv_onewire_dpram_0_0_0 : label is "18"; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + slv_onewire_dpram_0_0_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 36, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>scuba_vlo, + DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>WrAddress(0), + ADA5=>WrAddress(1), ADA6=>WrAddress(2), ADA7=>WrAddress(3), + ADA8=>WrAddress(4), ADA9=>WrAddress(5), ADA10=>WrAddress(6), + ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo, + CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>RdAddress(0), + ADB6=>RdAddress(1), ADB7=>RdAddress(2), ADB8=>RdAddress(3), + ADB9=>RdAddress(4), ADB10=>RdAddress(5), ADB11=>scuba_vlo, + ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>RdClockEn, + CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0), + DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), + DOA6=>Q(6), DOA7=>Q(7), DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10), + DOA11=>Q(11), DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14), + DOA15=>Q(15), DOA16=>open, DOA17=>open, DOB0=>Q(16), + DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>Q(20), + DOB5=>Q(21), DOB6=>Q(22), DOB7=>Q(23), DOB8=>Q(24), + DOB9=>Q(25), DOB10=>Q(26), DOB11=>Q(27), DOB12=>Q(28), + DOB13=>Q(29), DOB14=>Q(30), DOB15=>Q(31), DOB16=>open, + DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of slv_onewire_dpram is + for Structure + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/slv_onewire_dpram_generate.log b/src/slv_onewire_dpram_generate.log new file mode 100644 index 0000000..8173499 --- /dev/null +++ b/src/slv_onewire_dpram_generate.log @@ -0,0 +1,44 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Aug 11 14:48:40 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e + Circuit name : slv_onewire_dpram + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[31:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : slv_onewire_dpram.vhd + VHDL template : slv_onewire_dpram_tmpl.vhd + VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : slv_onewire_dpram.srp + Estimated Resource Usage: + EBR : 1 + +END SCUBA Module Synthesis + +File: slv_onewire_dpram.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/slv_onewire_dpram_tmpl.vhd b/src/slv_onewire_dpram_tmpl.vhd new file mode 100644 index 0000000..7abb4e2 --- /dev/null +++ b/src/slv_onewire_dpram_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 6.1 +-- Tue Aug 11 14:48:40 2009 + +-- parameterized module component declaration +component slv_onewire_dpram + port (WrAddress: in std_logic_vector(6 downto 0); + RdAddress: in std_logic_vector(5 downto 0); + Data: in std_logic_vector(15 downto 0); WE: in std_logic; + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; WrClock: in std_logic; + WrClockEn: in std_logic; Q: out std_logic_vector(31 downto 0)); +end component; + +-- parameterized module component instance +__ : slv_onewire_dpram + port map (WrAddress(6 downto 0)=>__, RdAddress(5 downto 0)=>__, Data(15 downto 0)=>__, + WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__, + WrClockEn=>__, Q(31 downto 0)=>__); diff --git a/src/slv_onewire_memory.vhd b/src/slv_onewire_memory.vhd new file mode 100644 index 0000000..2c23121 --- /dev/null +++ b/src/slv_onewire_memory.vhd @@ -0,0 +1,221 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +entity slv_onewire_memory is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(5 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- 1Wire lines + ONEWIRE_START_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); + BP_ONEWIRE_INOUT : inout std_logic; + -- Status lines + STAT : out std_logic_vector(63 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of slv_onewire_memory is + +-- Signals + type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- slave bus signals + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal slv_busy : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + -- for replacing the lost FE with BP data + signal wr_addr_q : std_logic_vector(6 downto 0); -- some bits are masked + signal wr_data_q : std_logic_vector(15 downto 0); + signal wr_we_q : std_logic; + + signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked + signal wr_bp_data : std_logic_vector(15 downto 0); + signal wr_data : std_logic_vector(15 downto 0); + signal wr_we : std_logic; + signal buf_slv_data_out : std_logic_vector(31 downto 0); + + signal read_address : std_logic_vector(5 downto 0); + signal missing_one : std_logic_vector(3 downto 0); -- missing APV FE <-> backplane + signal overlay : std_logic; + + signal onewire_bsm : std_logic_vector(7 downto 0); + +begin + +-- Fake +stat(63 downto 40) <= (others => '0'); + +stat(39 downto 32) <= buf_slv_data_out(7 downto 0); +stat(31 downto 26) <= slv_addr_in; +stat(25) <= slv_write_in; +stat(24) <= slv_read_in; +stat(23) <= store_wr; +stat(22) <= store_rd; +stat(21) <= slv_ack; +stat(20) <= slv_busy; +stat(19) <= wr_we; +stat(18 downto 12) <= wr_addr; +stat(11 downto 4) <= wr_data(7 downto 0); +stat(3 downto 0) <= onewire_bsm(3 downto 0); + +-- Remap the 1Wire chips to Luigi's world +THE_ADC_ONEWIRE_MAP_MEM: adc_onewire_map_mem +port map( ADDRESS(6 downto 4) => backplane_in, + ADDRESS(3 downto 0) => slv_addr_in(5 downto 2), + Q => read_address(5 downto 2) + ); +read_address(1 downto 0) <= slv_addr_in(1 downto 0); + +-- One APV FE connector is missing ("Roman's FE"), and replace the +-- 1Wire ID by the backplane +THE_ONEWIRE_SPARE_ONE: onewire_spare_one +port map( ADDRESS => backplane_in, + Q => missing_one + ); + +-- Check if we need to replace data +overlay <= '1' when (wr_addr(6 downto 3) = missing_one) else '0'; + + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in ) +begin + NEXT_STATE <= SLEEP; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( (slv_read_in = '1') ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( (slv_write_in = '1') ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_RDY => NEXT_STATE <= RD_ACK; + when WR_RDY => NEXT_STATE <= WR_ACK; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + + +--------------------------------------------------------- +-- 1 Wire master -- +--------------------------------------------------------- +THE_ONEWIRE_MASTER: onewire_master +generic map( CLK_PERIOD => 10 ) +port map( CLK => clk_in, + RESET => reset_in, + READOUT_ENABLE_IN => store_wr, + -- connection to 1-wire interface (16 APV FEs) + ONEWIRE => onewire_inout, + BP_ONEWIRE => bp_onewire_inout, + -- connection to external DPRAM for slow control readout + BP_DATA_OUT => wr_bp_data, + DATA_OUT => wr_data, + ADDR_OUT => wr_addr, + WRITE_OUT => wr_we, + BUSY_OUT => slv_busy, -- could be used... + -- debug + BSM_OUT => onewire_bsm, + STAT => open + ); + +--------------------------------------------------------- +-- data replacing -- +--------------------------------------------------------- +THE_DATA_REPLACE_PROC: process(clk_in) +begin + if( rising_edge(clk_in) ) then + wr_addr_q <= wr_addr; + wr_we_q <= wr_we; + if( overlay = '1' ) then + wr_data_q <= wr_bp_data; + else + wr_data_q <= wr_data; + end if; + end if; +end process THE_DATA_REPLACE_PROC; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- +THE_SLV_ONEWIRE_DPRAM: slv_onewire_dpram +port map( WRADDRESS => wr_addr_q, + RDADDRESS => read_address, + DATA => wr_data_q, + WE => wr_we_q, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + WRCLOCK => clk_in, + WRCLOCKEN => '1', + Q => buf_slv_data_out + ); + + + +-- output signals +slv_data_out <= buf_slv_data_out; +slv_ack_out <= slv_ack; +slv_busy_out <= slv_busy; + +end Behavioral; diff --git a/src/slv_ped_thr_mem.vhd b/src/slv_ped_thr_mem.vhd new file mode 100644 index 0000000..12c2e3c --- /dev/null +++ b/src/slv_ped_thr_mem.vhd @@ -0,0 +1,249 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +entity slv_ped_thr_mem is +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(10 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(6 downto 0); + MEM_0_D_OUT : out std_logic_vector(17 downto 0); + MEM_1_D_OUT : out std_logic_vector(17 downto 0); + MEM_2_D_OUT : out std_logic_vector(17 downto 0); + MEM_3_D_OUT : out std_logic_vector(17 downto 0); + MEM_4_D_OUT : out std_logic_vector(17 downto 0); + MEM_5_D_OUT : out std_logic_vector(17 downto 0); + MEM_6_D_OUT : out std_logic_vector(17 downto 0); + MEM_7_D_OUT : out std_logic_vector(17 downto 0); + MEM_8_D_OUT : out std_logic_vector(17 downto 0); + MEM_9_D_OUT : out std_logic_vector(17 downto 0); + MEM_10_D_OUT : out std_logic_vector(17 downto 0); + MEM_11_D_OUT : out std_logic_vector(17 downto 0); + MEM_12_D_OUT : out std_logic_vector(17 downto 0); + MEM_13_D_OUT : out std_logic_vector(17 downto 0); + MEM_14_D_OUT : out std_logic_vector(17 downto 0); + MEM_15_D_OUT : out std_logic_vector(17 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of slv_ped_thr_mem is + +-- Signals + type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- statemachine signals + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + signal block_addr : std_logic_vector(3 downto 0); + + type ped_data_t is array (0 to 15) of std_logic_vector(17 downto 0); + signal ped_data : ped_data_t; + signal mem_data : ped_data_t; + + signal mem_wr_x : std_logic_vector(15 downto 0); + signal mem_wr : std_logic_vector(15 downto 0); + signal mem_sel : std_logic_vector(15 downto 0); + + signal rdback_data : std_logic_vector(17 downto 0); + +begin + +--------------------------------------------------------- +-- Mapping of backplanes -- +--------------------------------------------------------- +THE_APV_ADC_MAP_MEM: apv_adc_map_mem +port map( ADDRESS(6 downto 4) => backplane_in, + ADDRESS(3 downto 0) => slv_addr_in(10 downto 7), + Q => block_addr + ); + +THE_MEM_SEL_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + case block_addr is + when x"0" => mem_sel <= b"0000_0000_0000_0001"; + rdback_data <= mem_data(0); + when x"1" => mem_sel <= b"0000_0000_0000_0010"; + rdback_data <= mem_data(1); + when x"2" => mem_sel <= b"0000_0000_0000_0100"; + rdback_data <= mem_data(2); + when x"3" => mem_sel <= b"0000_0000_0000_1000"; + rdback_data <= mem_data(3); + when x"4" => mem_sel <= b"0000_0000_0001_0000"; + rdback_data <= mem_data(4); + when x"5" => mem_sel <= b"0000_0000_0010_0000"; + rdback_data <= mem_data(5); + when x"6" => mem_sel <= b"0000_0000_0100_0000"; + rdback_data <= mem_data(6); + when x"7" => mem_sel <= b"0000_0000_1000_0000"; + rdback_data <= mem_data(7); + when x"8" => mem_sel <= b"0000_0001_0000_0000"; + rdback_data <= mem_data(8); + when x"9" => mem_sel <= b"0000_0010_0000_0000"; + rdback_data <= mem_data(9); + when x"a" => mem_sel <= b"0000_0100_0000_0000"; + rdback_data <= mem_data(10); + when x"b" => mem_sel <= b"0000_1000_0000_0000"; + rdback_data <= mem_data(11); + when x"c" => mem_sel <= b"0001_0000_0000_0000"; + rdback_data <= mem_data(12); + when x"d" => mem_sel <= b"0010_0000_0000_0000"; + rdback_data <= mem_data(13); + when x"e" => mem_sel <= b"0100_0000_0000_0000"; + rdback_data <= mem_data(14); + when x"f" => mem_sel <= b"1000_0000_0000_0000"; + rdback_data <= mem_data(15); + when others => mem_sel <= b"0000_0000_0000_0000"; -- never used + rdback_data <= (others => '0'); + end case; + end if; +end process THE_MEM_SEL_PROC; + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in ) +begin + NEXT_STATE <= SLEEP; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( slv_read_in = '1' ) then + NEXT_STATE <= RD_DEL0; + store_rd_x <= '1'; + elsif( slv_write_in = '1' ) then + NEXT_STATE <= WR_DEL0; + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_DEL0 => NEXT_STATE <= RD_DEL1; + when RD_DEL1 => NEXT_STATE <= RD_RDY; + when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_DEL0 => NEXT_STATE <= WR_DEL1; + when WR_DEL1 => NEXT_STATE <= WR_RDY; + when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- block memories -- +--------------------------------------------------------- +GEN_PED_MEM: for i in 0 to 15 generate + -- Port A: SLV_BUS + -- Port B: state machine + THE_PED_MEM: ped_thr_true + port map( DATAINA => slv_data_in(17 downto 0), + DATAINB => b"00_0000_0000_0000_0000", + ADDRESSA => slv_addr_in(6 downto 0), + ADDRESSB => mem_addr_in, + CLOCKA => clk_in, + CLOCKB => mem_clk_in, + CLOCKENA => '1', + CLOCKENB => '1', + WRA => mem_wr(i), -- BUGBUGBUG + WRB => '0', -- state machine never writes! + RESETA => reset_in, + RESETB => reset_in, + QA => mem_data(i), + QB => ped_data(i) + ); + -- Write signals + mem_wr_x(i) <= '1' when ( (mem_sel(i) = '1') and (store_wr = '1') ) else '0'; +end generate GEN_PED_MEM; + +-- Synchronize +THE_SYNC_PROC: process(clk_in) +begin + if( rising_edge(clk_in) ) then + mem_wr <= mem_wr_x; + end if; +end process THE_SYNC_PROC; + +--------------------------------------------------------- +-- output signals -- +--------------------------------------------------------- +slv_ack_out <= slv_ack; +slv_data_out <= b"0000_0000_0000_00" & rdback_data; + +mem_0_d_out <= ped_data(0); +mem_1_d_out <= ped_data(1); +mem_2_d_out <= ped_data(2); +mem_3_d_out <= ped_data(3); +mem_4_d_out <= ped_data(4); +mem_5_d_out <= ped_data(5); +mem_6_d_out <= ped_data(6); +mem_7_d_out <= ped_data(7); +mem_8_d_out <= ped_data(8); +mem_9_d_out <= ped_data(9); +mem_10_d_out <= ped_data(10); +mem_11_d_out <= ped_data(11); +mem_12_d_out <= ped_data(12); +mem_13_d_out <= ped_data(13); +mem_14_d_out <= ped_data(14); +mem_15_d_out <= ped_data(15); + +stat(31 downto 20) <= (others => '0'); +stat(19 downto 16) <= block_addr; +stat(15 downto 0) <= mem_sel; + +end Behavioral; diff --git a/src/slv_register.vhd b/src/slv_register.vhd new file mode 100644 index 0000000..f851ca7 --- /dev/null +++ b/src/slv_register.vhd @@ -0,0 +1,177 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + + +entity slv_register is +generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" ); +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + REG_DATA_IN : in std_logic_vector(31 downto 0); + REG_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of slv_register is + +-- Signals + + type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + -- slave bus signals + signal slv_busy_x : std_logic; + signal slv_busy : std_logic; + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input + signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data + signal reg_busy : std_logic; + +begin + +-- Fake +reg_busy <= busy_in; +stat <= (others => '0'); + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_busy <= '0'; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_busy <= slv_busy_x; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) +begin + NEXT_STATE <= SLEEP; + slv_busy_x <= '0'; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( (reg_busy = '0') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + elsif( (reg_busy = '1') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_BSY; + slv_busy_x <= '1'; -- added 23022009 + elsif( (reg_busy = '1') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_BSY; + slv_busy_x <= '1'; -- added 23022009 + else + NEXT_STATE <= SLEEP; + end if; + when RD_RDY => NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + when WR_RDY => NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when RD_BSY => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_BSY; + slv_busy_x <= '1'; + end if; + when WR_BSY => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_BSY; + slv_busy_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +-- register write +THE_WRITE_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + reg_slv_data_in <= RESET_VALUE; + elsif( store_wr = '1' ) then + reg_slv_data_in <= slv_data_in; + end if; + end if; +end process THE_WRITE_REG_PROC; + +-- register read +THE_READ_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + reg_slv_data_out <= (others => '0'); + elsif( store_rd = '1' ) then + reg_slv_data_out <= reg_data_in; + end if; + end if; +end process THE_READ_REG_PROC; + +-- output signals +slv_ack_out <= slv_ack; +slv_busy_out <= slv_busy; +slv_data_out <= reg_slv_data_out; + +--------------------------------------------------------- +-- signals to backend -- +--------------------------------------------------------- + +reg_data_out <= reg_slv_data_in; + +end Behavioral; diff --git a/src/slv_register_bank.vhd b/src/slv_register_bank.vhd new file mode 100644 index 0000000..5baa67d --- /dev/null +++ b/src/slv_register_bank.vhd @@ -0,0 +1,253 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +entity slv_register_bank is +generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" ); +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(3 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + BACKPLANE_IN : in std_logic_vector(2 downto 0); + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of slv_register_bank is + +-- Signals + type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + + signal adc_addr : std_logic_vector(3 downto 0); -- ADC address after mapping + signal reg_sel : std_logic_vector(15 downto 0); + signal reg_wr : std_logic_vector(15 downto 0); + signal reg_wr_x : std_logic_vector(15 downto 0); + + type ctrl_reg_t is array (0 to 15) of std_logic_vector(15 downto 0); + signal ctrl_reg : ctrl_reg_t; + + signal rdback_data : std_logic_vector(31 downto 0); + +begin + +-- Fake +stat <= (others => '0'); + +--------------------------------------------------------- +-- Mapping of backplanes -- +--------------------------------------------------------- +THE_APV_ADC_MAP_MEM: apv_adc_map_mem +port map( ADDRESS(6 downto 4) => backplane_in, + ADDRESS(3 downto 0) => slv_addr_in, + Q => adc_addr + ); + +THE_REG_SEL_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + case adc_addr is + when x"0" => reg_sel <= b"0000_0000_0000_0001"; + rdback_data <= stat_0_in & ctrl_reg(0); + when x"1" => reg_sel <= b"0000_0000_0000_0010"; + rdback_data <= stat_1_in & ctrl_reg(1); + when x"2" => reg_sel <= b"0000_0000_0000_0100"; + rdback_data <= stat_2_in & ctrl_reg(2); + when x"3" => reg_sel <= b"0000_0000_0000_1000"; + rdback_data <= stat_3_in & ctrl_reg(3); + when x"4" => reg_sel <= b"0000_0000_0001_0000"; + rdback_data <= stat_4_in & ctrl_reg(4); + when x"5" => reg_sel <= b"0000_0000_0010_0000"; + rdback_data <= stat_5_in & ctrl_reg(5); + when x"6" => reg_sel <= b"0000_0000_0100_0000"; + rdback_data <= stat_6_in & ctrl_reg(6); + when x"7" => reg_sel <= b"0000_0000_1000_0000"; + rdback_data <= stat_7_in & ctrl_reg(7); + when x"8" => reg_sel <= b"0000_0001_0000_0000"; + rdback_data <= stat_8_in & ctrl_reg(8); + when x"9" => reg_sel <= b"0000_0010_0000_0000"; + rdback_data <= stat_9_in & ctrl_reg(9); + when x"a" => reg_sel <= b"0000_0100_0000_0000"; + rdback_data <= stat_10_in & ctrl_reg(10); + when x"b" => reg_sel <= b"0000_1000_0000_0000"; + rdback_data <= stat_11_in & ctrl_reg(11); + when x"c" => reg_sel <= b"0001_0000_0000_0000"; + rdback_data <= stat_12_in & ctrl_reg(12); + when x"d" => reg_sel <= b"0010_0000_0000_0000"; + rdback_data <= stat_13_in & ctrl_reg(13); + when x"e" => reg_sel <= b"0100_0000_0000_0000"; + rdback_data <= stat_14_in & ctrl_reg(14); + when x"f" => reg_sel <= b"1000_0000_0000_0000"; + rdback_data <= stat_15_in & ctrl_reg(15); + when others => reg_sel <= b"0000_0000_0000_0000"; -- never used + rdback_data <= x"0000_0000"; + end case; + end if; +end process THE_REG_SEL_PROC; + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in ) +begin + NEXT_STATE <= SLEEP; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( slv_read_in = '1' ) then + NEXT_STATE <= RD_DEL0; + store_rd_x <= '1'; + elsif( slv_write_in = '1' ) then + NEXT_STATE <= WR_DEL0; + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_DEL0 => NEXT_STATE <= RD_DEL1; + when RD_DEL1 => NEXT_STATE <= RD_RDY; + when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_DEL0 => NEXT_STATE <= WR_DEL1; + when WR_DEL1 => NEXT_STATE <= WR_RDY; + when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +-- register write +GEN_CTRL_REG: for i in 0 to 15 generate + THE_WR_REG_PROC: process( clk_in ) + begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + ctrl_reg(i) <= RESET_VALUE; + elsif( reg_wr(i) = '1' ) then + ctrl_reg(i) <= slv_data_in(15 downto 0); + end if; + end if; + end process THE_WR_REG_PROC; + reg_wr_x(i) <= '1' when ( (reg_sel(i) = '1') and (store_wr = '1') ) else '0'; +end generate GEN_CTRL_REG; + +THE_SYNC_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + reg_wr <= reg_wr_x; + end if; +end process THE_SYNC_PROC; + +--------------------------------------------------------- +-- output signals -- +--------------------------------------------------------- +ctrl_0_out <= ctrl_reg(0); +ctrl_1_out <= ctrl_reg(1); +ctrl_2_out <= ctrl_reg(2); +ctrl_3_out <= ctrl_reg(3); +ctrl_4_out <= ctrl_reg(4); +ctrl_5_out <= ctrl_reg(5); +ctrl_6_out <= ctrl_reg(6); +ctrl_7_out <= ctrl_reg(7); +ctrl_8_out <= ctrl_reg(8); +ctrl_9_out <= ctrl_reg(9); +ctrl_10_out <= ctrl_reg(10); +ctrl_11_out <= ctrl_reg(11); +ctrl_12_out <= ctrl_reg(12); +ctrl_13_out <= ctrl_reg(13); +ctrl_14_out <= ctrl_reg(14); +ctrl_15_out <= ctrl_reg(15); + +slv_ack_out <= slv_ack; +slv_data_out <= rdback_data; + +stat <= (others => '0'); + +end Behavioral; diff --git a/src/spare_onewire_mapping.mem b/src/spare_onewire_mapping.mem new file mode 100644 index 0000000..830138b --- /dev/null +++ b/src/spare_onewire_mapping.mem @@ -0,0 +1,20 @@ +#Format=Address-Hex +#Depth=8 +#DataWidth=4 +#AddrRadix=3 +#DataRadix=3 + +# This mapping memory denotes the "spare" 1Wire port, which is connected to Roman's APV. +# This information can be used to replace the 1Wire ID of the non-existing APV-FE by the +# backplane 1Wire ID. + +# IMPORTANT: KEEP IN SYNC WITH adc_onewire_mapping.mem!!! + +00: 4 +01: c +02: 6 +03: a +04: 0 +05: f +06: f +07: f diff --git a/src/spi_adc_master.vhd b/src/spi_adc_master.vhd new file mode 100644 index 0000000..92ed5c9 --- /dev/null +++ b/src/spi_adc_master.vhd @@ -0,0 +1,215 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.adcmv3_components.all; + +entity spi_adc_master is +generic( RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" ); +port( CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + -- ADC connections + ADC_LOCKED_IN : in std_logic; + ADC_PD_OUT : out std_logic; + ADC_RST_OUT : out std_logic; + ADC_DEL_OUT : out std_logic_vector(3 downto 0); + -- APV connections + APV_RST_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end entity; + +architecture Behavioral of spi_adc_master is + +-- Signals + type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); + signal CURRENT_STATE, NEXT_STATE: STATES; + + signal status_data : std_logic_vector(31 downto 0); + signal spi_busy : std_logic; + + signal reg_ctrl_data : std_logic_vector(7 downto 0); + signal adc_ctrl_data : std_logic_vector(7 downto 0); + + signal reg_slv_data_out : std_logic_vector(31 downto 0); -- readback + + signal spi_start_x : std_logic; + signal spi_start : std_logic; + + -- State machine signals + signal slv_busy_x : std_logic; + signal slv_busy : std_logic; + signal slv_ack_x : std_logic; + signal slv_ack : std_logic; + signal store_wr_x : std_logic; + signal store_wr : std_logic; + signal store_rd_x : std_logic; + signal store_rd : std_logic; + +begin + +--------------------------------------------------------- +-- SPI master -- +--------------------------------------------------------- + +THE_SPI_REAL_SLIM: spi_real_slim +port map( SYSCLK => clk_in, + RESET => reset_in, + -- Command interface + START_IN => spi_start, + BUSY_OUT => spi_busy, + CMD_IN => reg_ctrl_data, + -- SPI interface + SPI_SCK_OUT => spi_sck_out, + SPI_CS_OUT => spi_cs_out, + SPI_SDO_OUT => spi_sdo_out, + -- DEBUG + CLK_EN_OUT => open, + BSM_OUT => open, + DEBUG_OUT => open + ); + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if( reset_in = '1' ) then + CURRENT_STATE <= SLEEP; + slv_busy <= '0'; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_busy <= slv_busy_x; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, spi_busy ) +begin + NEXT_STATE <= SLEEP; + slv_busy_x <= '0'; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( (spi_busy = '0') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( (spi_busy = '0') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + elsif( (spi_busy = '1') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_BSY; + slv_busy_x <= '1'; + elsif( (spi_busy = '1') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_BSY; + slv_busy_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RD_RDY => NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + when WR_RDY => NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when RD_BSY => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_BSY; + slv_busy_x <= '1'; + end if; + when WR_BSY => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_BSY; + slv_busy_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +-- register write +THE_WRITE_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + reg_ctrl_data <= (others => '0'); + adc_ctrl_data <= RESET_VALUE_CTRL; + spi_start <= '0'; + elsif( store_wr = '1' ) then + reg_ctrl_data <= slv_data_in(31 downto 24); + adc_ctrl_data <= slv_data_in(7 downto 0); + end if; + spi_start <= spi_start_x; + end if; +end process THE_WRITE_REG_PROC; + +spi_start_x <= '1' when ( (store_wr = '1') and (slv_data_in(3) = '1') ) else '0'; + +-- register read +THE_READ_REG_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + if ( reset_in = '1' ) then + reg_slv_data_out <= (others => '0'); + elsif( store_rd = '1' ) then + reg_slv_data_out <= reg_ctrl_data & x"000" & b"000" & adc_locked_in & adc_ctrl_data; + end if; + end if; +end process THE_READ_REG_PROC; + +-- debug signals +status_data(31 downto 0) <= (others => '0'); + +-- output signals +adc_del_out <= adc_ctrl_data(7 downto 4); +apv_rst_out <= adc_ctrl_data(2); +adc_pd_out <= adc_ctrl_data(1); +adc_rst_out <= not adc_ctrl_data(0); + +stat <= status_data; +slv_ack_out <= slv_ack; +slv_busy_out <= slv_busy; +slv_data_out <= reg_slv_data_out; + +end Behavioral; diff --git a/src/spi_real_slim.vhd b/src/spi_real_slim.vhd new file mode 100644 index 0000000..4b83c1e --- /dev/null +++ b/src/spi_real_slim.vhd @@ -0,0 +1,242 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + + +entity spi_real_slim is + port( SYSCLK : in std_logic; -- 100MHz sysclock + RESET : in std_logic; -- synchronous reset + -- Command interface + START_IN : in std_logic; -- one start pulse + BUSY_OUT : out std_logic; -- SPI transactions are ongoing + CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte + -- SPI interface + SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + -- DEBUG + CLK_EN_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end spi_real_slim; + +architecture Behavioral of spi_real_slim is + +-- new clock divider +signal div_counter : std_logic_vector(1 downto 0); +signal div_done_x : std_logic; +signal div_done : std_logic; -- same as clk_en +signal clk_en : std_logic; -- same as div_done + +-- Statemachine signals +type state_t is (IDLE,CSL,TXCMD,CSH); +signal STATE, NEXT_STATE : state_t; + +signal tx_ena_x : std_logic; +signal tx_ena : std_logic; +signal busy_x : std_logic; +signal busy : std_logic; +signal spi_cs_x : std_logic; -- SPI chip select (low active) +signal spi_cs : std_logic; +signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter) +signal spi_sck : std_logic; +signal tx_load_x : std_logic; -- load TX shift register +signal tx_load : std_logic; + +signal last_tx_bit_x : std_logic; +signal last_tx_bit : std_logic; + +-- debug signals +signal bsm_x : std_logic_vector(7 downto 0); +signal debug_x : std_logic_vector(31 downto 0); + +signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine +signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes + +-- transmitter +signal tx_sreg : std_logic_vector(7 downto 0); +signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer +signal tx_bit_cnt : std_logic_vector(3 downto 0); + +begin + +----------------------------------------------------------- +-- Debug signals +----------------------------------------------------------- +debug_x(31 downto 24) <= tx_sreg; --(others => '0'); +debug_x(23 downto 20) <= tx_bit_cnt; --(others => '0'); +debug_x(19 downto 16) <= (others => '0'); +debug_x(15) <= '0'; +debug_x(14) <= '0'; +debug_x(13) <= '0'; +debug_x(12) <= '0'; +debug_x(11) <= last_tx_bit; +debug_x(10) <= '0'; +debug_x(9) <= '0'; +debug_x(8) <= '0'; +debug_x(7) <= '0'; +debug_x(6) <= '0'; +debug_x(5) <= tx_load; +debug_x(4) <= tx_ena; +debug_x(3) <= '0'; +debug_x(2 downto 0) <= (others => '0'); + + +----------------------------------------------------------- +-- SPI clock generator +----------------------------------------------------------- +THE_CLOCK_DIVIDER: process( sysclk ) +begin + if( rising_edge(sysclk) ) then + if( reset = '1' ) then + div_counter <= (others => '0'); + div_done <= '0'; + spi_sck <= '0'; + else + div_counter <= div_counter + 1; + div_done <= div_done_x; + spi_sck <= spi_sck_x; + end if; + end if; +end process THE_CLOCK_DIVIDER; + +div_done_x <= '1' when ( div_counter = b"00" ) else '0'; + +spi_sck_x <= '1' when ( ((div_counter = b"11") or (div_counter = b"00")) and + (tx_ena = '1') ) else '0'; + +clk_en <= div_done; + +----------------------------------------------------------- +-- start signal and local register sets for CMD and ADR +----------------------------------------------------------- +THE_START_PROC: process( sysclk ) +begin + if( rising_edge(sysclk) ) then + if ( reset = '1' ) then + start <= '0'; + cmd_int <= (others => '0'); + elsif( (start_in = '1') and (busy = '0') ) then + start <= '1'; + cmd_int <= cmd_in; + elsif( busy = '1' ) then + start <= '0'; + end if; + end if; +end process THE_START_PROC; + +----------------------------------------------------------- +-- statemachine: clocked process +----------------------------------------------------------- +THE_STATEMACHINE: process( sysclk ) +begin + if( rising_edge(sysclk) ) then + if ( reset = '1' ) then + STATE <= IDLE; + tx_ena <= '0'; + busy <= '0'; + spi_cs <= '1'; + tx_load <= '0'; + elsif( clk_en = '1' ) then + STATE <= NEXT_STATE; + tx_ena <= tx_ena_x; + busy <= busy_x; + spi_cs <= spi_cs_x; + tx_load <= tx_load_x; + end if; + end if; +end process THE_STATEMACHINE; + +----------------------------------------------------------- +-- state machine transition table +----------------------------------------------------------- +THE_STATE_TRANSITIONS: process( STATE, start, tx_bit_cnt ) +begin + tx_ena_x <= '0'; + busy_x <= '1'; + spi_cs_x <= '1'; + tx_load_x <= '0'; + case STATE is + when IDLE => + if( start = '1' ) then + NEXT_STATE <= CSL; + spi_cs_x <= '0'; + tx_load_x <= '1'; + else + NEXT_STATE <= IDLE; + busy_x <= '0'; + end if; + + when CSL => + NEXT_STATE <= TXCMD; + tx_ena_x <= '1'; + spi_cs_x <= '0'; + + when TXCMD => + if( tx_bit_cnt < x"7" ) then + NEXT_STATE <= TXCMD; + tx_ena_x <= '1'; + spi_cs_x <= '0'; + else + NEXT_STATE <= CSH; + spi_cs_x <= '0'; + end if; + + when CSH => + NEXT_STATE <= IDLE; + busy_x <= '0'; + + when others => + NEXT_STATE <= IDLE; + + end case; +end process THE_STATE_TRANSITIONS; + +-- state machine output table +THE_STATEMACHINE_OUT: process( STATE ) +begin + case STATE is + when IDLE => bsm_x <= x"00"; + when CSL => bsm_x <= x"01"; + when TXCMD => bsm_x <= x"02"; + when CSH => bsm_x <= x"03"; + when others => bsm_x <= x"ff"; + end case; +end process THE_STATEMACHINE_OUT; + +-- We only use one CMD byte +tx_reg_comb <= cmd_int; + +-- TXData shift register and bit counter +THE_TX_SHIFT_AND_BITCOUNT: process( sysclk ) +begin + if( rising_edge(sysclk) ) then + if ( (clk_en = '1' ) and (tx_load = '1') ) then + tx_bit_cnt <= (others => '0'); + tx_sreg <= tx_reg_comb; + elsif( (clk_en = '1') and (tx_ena = '1') ) then + tx_bit_cnt <= tx_bit_cnt + 1; + tx_sreg <= tx_sreg (6 downto 0) & '0'; + end if; + last_tx_bit <= last_tx_bit_x; + end if; +end process THE_TX_SHIFT_AND_BITCOUNT; + +last_tx_bit_x <= '1' when ( tx_bit_cnt = x"7" ) else '0'; + +-- output signals +spi_cs_out <= spi_cs; +spi_sck_out <= spi_sck; +spi_sdo_out <= tx_sreg(7); +busy_out <= busy; + +clk_en_out <= clk_en; +bsm_out <= bsm_x; +debug_out <= debug_x; + + +end Behavioral; diff --git a/src/state_sync.vhd b/src/state_sync.vhd new file mode 100644 index 0000000..a00cd2f --- /dev/null +++ b/src/state_sync.vhd @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.adcmv3_components.all; + +entity state_sync is + port( STATE_A_IN : in std_logic; + RESET_B_IN : in std_logic; + CLK_B_IN : in std_logic; + STATE_B_OUT : out std_logic + ); +end; + +architecture behavioral of state_sync is + + -- normal signals + signal sync_q : std_logic; + signal sync_qq : std_logic; + +begin + +-- synchronizing stage for clock domain B +THE_SYNC_STAGE_PROC: process( clk_b_in ) +begin + if( rising_edge(clk_b_in) ) then + if( reset_b_in = '1' ) then + sync_q <= '0'; sync_qq <= '0'; + else + sync_qq <= sync_q; + sync_q <= state_a_in; + end if; + end if; +end process THE_SYNC_STAGE_PROC; + +-- output signals +state_b_out <= sync_qq; + +end behavioral; diff --git a/src/suber_12bit.lpc b/src/suber_12bit.lpc new file mode 100644 index 0000000..a7aa216 --- /dev/null +++ b/src/suber_12bit.lpc @@ -0,0 +1,36 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=Subtractor +CoreRevision=3.1 +ModuleName=suber_12bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/27/2009 +Time=16:54:01 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +InputWidth=12 +Representation=Unsigned +UseCIport=0 +COport=None +OutReg=1 +Complex=0 +Stage=0 diff --git a/src/suber_12bit.srp b/src/suber_12bit.srp new file mode 100644 index 0000000..657e061 --- /dev/null +++ b/src/suber_12bit.srp @@ -0,0 +1,32 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Oct 27 16:54:01 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n suber_12bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type mgaddsub -direction sub -width 12 -unsigned -output_reg -enable -pipeline 0 -e + Circuit name : suber_12bit + Module type : sub + Module Version : 3.1 + Width : 12 + Ports : + Inputs : DataA[11:0], DataB[11:0], Clock, Reset, ClockEn + Outputs : Result[11:0] + I/O buffer : not inserted + Representation : unsigned number + EDIF output : suppressed + VHDL output : suber_12bit.vhd + VHDL template : suber_12bit_tmpl.vhd + VHDL testbench : tb_suber_12bit_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : suber_12bit.srp + Element Usage : + FSUB2B : 7 + FD1P3DX : 12 + Estimated Resource Usage: + LUT : 14 + Reg : 12 diff --git a/src/suber_12bit.vhd b/src/suber_12bit.vhd new file mode 100644 index 0000000..c582ff2 --- /dev/null +++ b/src/suber_12bit.vhd @@ -0,0 +1,239 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 3.1 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sub -width 12 -unsigned -output_reg -enable -pipeline 0 -e + +-- Tue Oct 27 16:54:01 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity suber_12bit is + port ( + DataA: in std_logic_vector(11 downto 0); + DataB: in std_logic_vector(11 downto 0); + Clock: in std_logic; + Reset: in std_logic; + ClockEn: in std_logic; + Result: out std_logic_vector(11 downto 0)); +end suber_12bit; + +architecture Structure of suber_12bit is + + -- internal signal declarations + signal r0_diff11: std_logic; + signal r0_diff10: std_logic; + signal r0_diff9: std_logic; + signal r0_diff8: std_logic; + signal r0_diff7: std_logic; + signal r0_diff6: std_logic; + signal r0_diff5: std_logic; + signal r0_diff4: std_logic; + signal r0_diff3: std_logic; + signal r0_diff2: std_logic; + signal r0_diff1: std_logic; + signal r0_diff0: std_logic; + signal tdiff0: std_logic; + signal scuba_vhi: std_logic; + signal tdiff1: std_logic; + signal tdiff2: std_logic; + signal co0: std_logic; + signal tdiff3: std_logic; + signal tdiff4: std_logic; + signal co1: std_logic; + signal tdiff5: std_logic; + signal tdiff6: std_logic; + signal co2: std_logic; + signal tdiff7: std_logic; + signal tdiff8: std_logic; + signal co3: std_logic; + signal tdiff9: std_logic; + signal tdiff10: std_logic; + signal co4: std_logic; + signal tdiff11: std_logic; + signal co5: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff11, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff11); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff10, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff10); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff9, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff9); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff8, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff8); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff7, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff7); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff6, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff6); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff5, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff5); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff4, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff4); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff3, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff3); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff2, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff2); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff1, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff1); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>tdiff0, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>r0_diff0); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + addsub_0: FSUB2B + port map (A0=>scuba_vhi, A1=>DataA(0), B0=>scuba_vlo, + B1=>DataB(0), BI=>scuba_vlo, BOUT=>co0, S0=>open, S1=>tdiff0); + + addsub_1: FSUB2B + port map (A0=>DataA(1), A1=>DataA(2), B0=>DataB(1), B1=>DataB(2), + BI=>co0, BOUT=>co1, S0=>tdiff1, S1=>tdiff2); + + addsub_2: FSUB2B + port map (A0=>DataA(3), A1=>DataA(4), B0=>DataB(3), B1=>DataB(4), + BI=>co1, BOUT=>co2, S0=>tdiff3, S1=>tdiff4); + + addsub_3: FSUB2B + port map (A0=>DataA(5), A1=>DataA(6), B0=>DataB(5), B1=>DataB(6), + BI=>co2, BOUT=>co3, S0=>tdiff5, S1=>tdiff6); + + addsub_4: FSUB2B + port map (A0=>DataA(7), A1=>DataA(8), B0=>DataB(7), B1=>DataB(8), + BI=>co3, BOUT=>co4, S0=>tdiff7, S1=>tdiff8); + + addsub_5: FSUB2B + port map (A0=>DataA(9), A1=>DataA(10), B0=>DataB(9), + B1=>DataB(10), BI=>co4, BOUT=>co5, S0=>tdiff9, S1=>tdiff10); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + addsub_6: FSUB2B + port map (A0=>DataA(11), A1=>scuba_vlo, B0=>DataB(11), + B1=>scuba_vlo, BI=>co5, BOUT=>open, S0=>tdiff11, S1=>open); + + Result(11) <= r0_diff11; + Result(10) <= r0_diff10; + Result(9) <= r0_diff9; + Result(8) <= r0_diff8; + Result(7) <= r0_diff7; + Result(6) <= r0_diff6; + Result(5) <= r0_diff5; + Result(4) <= r0_diff4; + Result(3) <= r0_diff3; + Result(2) <= r0_diff2; + Result(1) <= r0_diff1; + Result(0) <= r0_diff0; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of suber_12bit is + for Structure + for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/suber_12bit_generate.log b/src/suber_12bit_generate.log new file mode 100644 index 0000000..dafc99f --- /dev/null +++ b/src/suber_12bit_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Oct 27 16:54:01 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n suber_12bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type mgaddsub -direction sub -width 12 -unsigned -output_reg -enable -pipeline 0 -e + Circuit name : suber_12bit + Module type : sub + Module Version : 3.1 + Width : 12 + Ports : + Inputs : DataA[11:0], DataB[11:0], Clock, Reset, ClockEn + Outputs : Result[11:0] + I/O buffer : not inserted + Representation : unsigned number + EDIF output : suppressed + VHDL output : suber_12bit.vhd + VHDL template : suber_12bit_tmpl.vhd + VHDL testbench : tb_suber_12bit_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : suber_12bit.srp + Estimated Resource Usage: + LUT : 14 + Reg : 12 + +END SCUBA Module Synthesis + +File: suber_12bit.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/src/suber_12bit_tmpl.vhd b/src/suber_12bit_tmpl.vhd new file mode 100644 index 0000000..6c4f816 --- /dev/null +++ b/src/suber_12bit_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 3.1 +-- Tue Oct 27 16:54:01 2009 + +-- parameterized module component declaration +component suber_12bit + port (DataA: in std_logic_vector(11 downto 0); + DataB: in std_logic_vector(11 downto 0); Clock: in std_logic; + Reset: in std_logic; ClockEn: in std_logic; + Result: out std_logic_vector(11 downto 0)); +end component; + +-- parameterized module component instance +__ : suber_12bit + port map (DataA(11 downto 0)=>__, DataB(11 downto 0)=>__, Clock=>__, + Reset=>__, ClockEn=>__, Result(11 downto 0)=>__); diff --git a/src/tb_adc_apv_map_mem_tmpl.vhd b/src/tb_adc_apv_map_mem_tmpl.vhd new file mode 100644 index 0000000..73cba33 --- /dev/null +++ b/src/tb_adc_apv_map_mem_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component adc_apv_map_mem + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : adc_apv_map_mem + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/src/tb_adc_cross.vhd b/src/tb_adc_cross.vhd new file mode 100644 index 0000000..fb24ad3 --- /dev/null +++ b/src/tb_adc_cross.vhd @@ -0,0 +1,231 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT adc_data_handler + PORT( + RESET_IN : IN std_logic; + RESET_PLL_IN : IN std_logic; + ADC_LCLK_IN : IN std_logic; + ADC_ADCLK_IN : IN std_logic; + ADC_CHNL_IN : IN std_logic_vector(7 downto 0); + PLL_CTRL_IN : IN std_logic_vector(3 downto 0); + PLL_LOCK_OUT : OUT std_logic; + CLK40M_OUT : OUT std_logic; + ADC_ADCLK_OUT : OUT std_logic; + ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA4_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA3_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0); + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + COMPONENT adc_crossover + PORT( + CLK_APV_IN : IN std_logic; + RESET_IN : IN std_logic; + ADC_CLK_IN : IN std_logic; + ADC_CE_IN : IN std_logic; + ADC_PLL_LOCKED_IN : IN std_logic; + ADC_DATA_0_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_1_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_2_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_3_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_4_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_5_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_6_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_7_IN : IN std_logic_vector(11 downto 0); + LEVEL_WR_OUT : OUT std_logic_vector(4 downto 0); + APV_DATA_0_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_1_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_2_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_3_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_4_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_5_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_6_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_7_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_VALID_OUT : OUT std_logic; + LEVEL_RD_OUT : OUT std_logic_vector(4 downto 0); + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_APV_IN : std_logic; + SIGNAL ADC_CE_IN : std_logic; + SIGNAL LEVEL_WR_OUT : std_logic_vector(4 downto 0); + SIGNAL LEVEL_RD_OUT : std_logic_vector(4 downto 0); + SIGNAL APV_DATA_0_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_1_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_2_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_3_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_4_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_5_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_6_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_7_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_VALID_OUT : std_logic; + SIGNAL DEBUG2_OUT : std_logic_vector(31 downto 0); + + SIGNAL CLK40M_INT : std_logic; + SIGNAL PLL_LOCK_INT : std_logic; + SIGNAL ADC_DATA_7_INT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_6_INT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_5_INT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_4_INT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_3_INT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_2_INT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_1_INT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_0_INT : std_logic_vector(11 downto 0); + + + SIGNAL RESET_IN : std_logic; + SIGNAL RESET_PLL_IN : std_logic; + SIGNAL ADC_LCLK_IN : std_logic; + SIGNAL ADC_ADCLK_IN : std_logic; + SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0); + SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0); +-- SIGNAL ADC_ADCLK_OUT : std_logic; + SIGNAL DEBUG1_OUT : std_logic_vector(15 downto 0); + + signal adc_0_real : std_logic_vector(11 downto 0); + signal adc_7_real : std_logic_vector(11 downto 0); + + +BEGIN + +-- Please check and add your generic clause manually + uut1: adc_data_handler PORT MAP( + RESET_IN => RESET_IN, + RESET_PLL_IN => RESET_PLL_IN, + ADC_LCLK_IN => ADC_LCLK_IN, + ADC_ADCLK_IN => ADC_ADCLK_IN, + ADC_CHNL_IN => ADC_CHNL_IN, + PLL_CTRL_IN => PLL_CTRL_IN, + PLL_LOCK_OUT => PLL_LOCK_INT, + CLK40M_OUT => CLK40M_INT, + ADC_ADCLK_OUT => ADC_CE_IN, --open, + ADC_DATA7_OUT => ADC_DATA_7_INT, + ADC_DATA6_OUT => ADC_DATA_6_INT, + ADC_DATA5_OUT => ADC_DATA_5_INT, + ADC_DATA4_OUT => ADC_DATA_4_INT, + ADC_DATA3_OUT => ADC_DATA_3_INT, + ADC_DATA2_OUT => ADC_DATA_2_INT, + ADC_DATA1_OUT => ADC_DATA_1_INT, + ADC_DATA0_OUT => ADC_DATA_0_INT, + DEBUG_OUT => DEBUG1_OUT + ); + + uut2: adc_crossover PORT MAP( + CLK_APV_IN => CLK_APV_IN, + RESET_IN => RESET_IN, + ADC_CLK_IN => ADC_LCLK_IN, --CLK40M_INT, + ADC_CE_IN => ADC_CE_IN, + ADC_PLL_LOCKED_IN => PLL_LOCK_INT, + ADC_DATA_0_IN => ADC_DATA_0_INT, + ADC_DATA_1_IN => ADC_DATA_1_INT, + ADC_DATA_2_IN => ADC_DATA_2_INT, + ADC_DATA_3_IN => ADC_DATA_3_INT, + ADC_DATA_4_IN => ADC_DATA_4_INT, + ADC_DATA_5_IN => ADC_DATA_5_INT, + ADC_DATA_6_IN => ADC_DATA_6_INT, + ADC_DATA_7_IN => ADC_DATA_7_INT, + LEVEL_WR_OUT => LEVEL_WR_OUT, + APV_DATA_0_OUT => APV_DATA_0_OUT, + APV_DATA_1_OUT => APV_DATA_1_OUT, + APV_DATA_2_OUT => APV_DATA_2_OUT, + APV_DATA_3_OUT => APV_DATA_3_OUT, + APV_DATA_4_OUT => APV_DATA_4_OUT, + APV_DATA_5_OUT => APV_DATA_5_OUT, + APV_DATA_6_OUT => APV_DATA_6_OUT, + APV_DATA_7_OUT => APV_DATA_7_OUT, + APV_DATA_VALID_OUT => APV_DATA_VALID_OUT, + LEVEL_RD_OUT => LEVEL_RD_OUT, + DEBUG_OUT => DEBUG2_OUT + ); + +APV_CLK_GEN: process +begin + clk_apv_in <= '1'; wait for 12.50 ns; + clk_apv_in <= '0'; wait for 12.50 ns; +end process APV_CLK_GEN; + +-- 240MHz DDR clock from ADC, aka bit clock +THE_CLOCK_GEN: process +begin + adc_lclk_in <= '1'; wait for 2.08 ns; + adc_lclk_in <= '0'; wait for 2.08 ns; +end process THE_CLOCK_GEN; + +-- test data generator +BLA: process +variable adc_0_data : unsigned(11 downto 0) := x"000"; +variable adc_7_data : unsigned(11 downto 0) := x"fff"; +variable my_bit : integer := 0; +begin + + my_bit := 0; + adc_0_real <= std_logic_vector(adc_0_data); + adc_7_real <= std_logic_vector(adc_7_data); + + BIT_LOOP: for I in 0 to 5 loop + + wait until rising_edge(adc_lclk_in); + wait for 1.04 ns; + if( I < 3 ) then + adc_adclk_in <= '1'; + else + adc_adclk_in <= '0'; -- second half + end if; + adc_chnl_in(7) <= adc_7_data(my_bit); + adc_chnl_in(6 downto 1) <= (others => '0'); + adc_chnl_in(0) <= adc_0_data(my_bit); + my_bit := my_bit + 1; + wait until falling_edge(adc_lclk_in); + wait for 1.04 ns; + adc_chnl_in(7) <= adc_7_data(my_bit); + adc_chnl_in(6 downto 1) <= (others => '0'); + adc_chnl_in(0) <= adc_0_data(my_bit); + my_bit := my_bit + 1; + + end loop BIT_LOOP; + + adc_7_data := adc_7_data - 1; + adc_0_data := adc_0_data + 1; + +end process BLA; + + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + reset_pll_in <= '0'; + pll_ctrl_in <= x"6"; +-- adc_ce_in <= '1'; + wait for 100 ns; + + -- Reset all + reset_in <= '1'; + wait for 100 ns; + reset_in <= '0'; + wait for 100 ns; + + -- Tests may start now + + + -- Stay a while, stay forever! + wait; + +end process THE_TEST_BENCH; + + +END; diff --git a/src/tb_adc_crossover.vhd b/src/tb_adc_crossover.vhd new file mode 100644 index 0000000..5bfa026 --- /dev/null +++ b/src/tb_adc_crossover.vhd @@ -0,0 +1,237 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT adc_crossover + PORT( + CLK_APV_IN : IN std_logic; + RESET_IN : IN std_logic; + ADC_CLK_IN : IN std_logic; + ADC_CE_IN : IN std_logic; + ADC_PLL_LOCKED_IN : IN std_logic; + ADC_DATA_0_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_1_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_2_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_3_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_4_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_5_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_6_IN : IN std_logic_vector(11 downto 0); + ADC_DATA_7_IN : IN std_logic_vector(11 downto 0); + LEVEL_WR_OUT : OUT std_logic_vector(4 downto 0); + APV_DATA_0_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_1_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_2_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_3_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_4_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_5_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_6_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_7_OUT : OUT std_logic_vector(11 downto 0); + APV_DATA_VALID_OUT : OUT std_logic; + LEVEL_RD_OUT : OUT std_logic_vector(4 downto 0); + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_APV_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL ADC_CLK_IN : std_logic; + SIGNAL ADC_CE_IN : std_logic; + SIGNAL ADC_PLL_LOCKED_IN : std_logic; + SIGNAL ADC_DATA_0_IN : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_1_IN : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_2_IN : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_3_IN : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_4_IN : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_5_IN : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_6_IN : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA_7_IN : std_logic_vector(11 downto 0); + SIGNAL LEVEL_WR_OUT : std_logic_vector(4 downto 0); + SIGNAL APV_DATA_0_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_1_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_2_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_3_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_4_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_5_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_6_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_7_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_DATA_VALID_OUT : std_logic; + SIGNAL LEVEL_RD_OUT : std_logic_vector(4 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: adc_crossover PORT MAP( + CLK_APV_IN => CLK_APV_IN, + RESET_IN => RESET_IN, + ADC_CLK_IN => ADC_CLK_IN, + ADC_CE_IN => ADC_CE_IN, + ADC_PLL_LOCKED_IN => ADC_PLL_LOCKED_IN, + ADC_DATA_0_IN => ADC_DATA_0_IN, + ADC_DATA_1_IN => ADC_DATA_1_IN, + ADC_DATA_2_IN => ADC_DATA_2_IN, + ADC_DATA_3_IN => ADC_DATA_3_IN, + ADC_DATA_4_IN => ADC_DATA_4_IN, + ADC_DATA_5_IN => ADC_DATA_5_IN, + ADC_DATA_6_IN => ADC_DATA_6_IN, + ADC_DATA_7_IN => ADC_DATA_7_IN, + LEVEL_WR_OUT => LEVEL_WR_OUT, + APV_DATA_0_OUT => APV_DATA_0_OUT, + APV_DATA_1_OUT => APV_DATA_1_OUT, + APV_DATA_2_OUT => APV_DATA_2_OUT, + APV_DATA_3_OUT => APV_DATA_3_OUT, + APV_DATA_4_OUT => APV_DATA_4_OUT, + APV_DATA_5_OUT => APV_DATA_5_OUT, + APV_DATA_6_OUT => APV_DATA_6_OUT, + APV_DATA_7_OUT => APV_DATA_7_OUT, + APV_DATA_VALID_OUT => APV_DATA_VALID_OUT, + LEVEL_RD_OUT => LEVEL_RD_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +RDCLOCK_GEN: process +begin + clk_apv_in <= '1'; wait for 12.50 ns; + clk_apv_in <= '0'; wait for 12.50 ns; +end process RDCLOCK_GEN; + +--WRCLOCK_GEN: process +--begin +-- adc_clk_in <= '1'; wait for 12.45 ns; +-- adc_clk_in <= '0'; wait for 12.45 ns; +--end process WRCLOCK_GEN; + +WRCLOCK_GEN: process +begin + wait until rising_edge(clk_apv_in); wait for 3.33 ns; adc_clk_in <= '1'; + wait until falling_edge(clk_apv_in); wait for 3.33 ns; adc_clk_in <= '0'; +end process WRCLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + adc_ce_in <= '1'; + adc_data_0_in <= x"000"; + adc_data_1_in <= x"000"; + adc_data_2_in <= x"000"; + adc_data_3_in <= x"000"; + adc_data_4_in <= x"000"; + adc_data_5_in <= x"000"; + adc_data_6_in <= x"000"; + adc_data_7_in <= x"000"; + adc_pll_locked_in <= '0'; + reset_in <= '0'; + + -- Reset all + reset_in <= '1'; wait for 50 ns; + reset_in <= '0'; wait for 50 ns; + + -- Tests may start here + wait for 101 ns; + adc_pll_locked_in <= '1'; + wait for 55 ns; + + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"ffe"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"001"; + + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"ffd"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"002"; + + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"ffc"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"003"; + + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"ffb"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + wait until rising_edge(adc_clk_in); + adc_data_0_in <= x"004"; + + + -- Stay a while, stay forever. + wait; + +end process THE_TEST_BENCH; + +END; diff --git a/src/tb_adc_handler.vhd b/src/tb_adc_handler.vhd new file mode 100644 index 0000000..dbeafa8 --- /dev/null +++ b/src/tb_adc_handler.vhd @@ -0,0 +1,149 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT adc_data_handler + PORT( + RESET_IN : IN std_logic; + RESET_PLL_IN : IN std_logic; + ADC_LCLK_IN : IN std_logic; + ADC_ADCLK_IN : IN std_logic; + ADC_CHNL_IN : IN std_logic_vector(7 downto 0); + PLL_CTRL_IN : IN std_logic_vector(3 downto 0); + PLL_LOCK_OUT : OUT std_logic; + CLK40M_OUT : OUT std_logic; + ADC_ADCLK_OUT : OUT std_logic; + ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA4_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA3_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0); + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL RESET_IN : std_logic; + SIGNAL RESET_PLL_IN : std_logic; + SIGNAL ADC_LCLK_IN : std_logic; + SIGNAL ADC_ADCLK_IN : std_logic; + SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0); + SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0); + SIGNAL PLL_LOCK_OUT : std_logic; + SIGNAL CLK40M_OUT : std_logic; + SIGNAL ADC_ADCLK_OUT : std_logic; + SIGNAL ADC_DATA7_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA6_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA5_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA4_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA3_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA2_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA1_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA0_OUT : std_logic_vector(11 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + + signal adc_0_real : std_logic_vector(11 downto 0); + signal adc_7_real : std_logic_vector(11 downto 0); + + +BEGIN + +-- Please check and add your generic clause manually + uut: adc_data_handler PORT MAP( + RESET_IN => RESET_IN, + RESET_PLL_IN => RESET_PLL_IN, + ADC_LCLK_IN => ADC_LCLK_IN, + ADC_ADCLK_IN => ADC_ADCLK_IN, + ADC_CHNL_IN => ADC_CHNL_IN, + PLL_CTRL_IN => PLL_CTRL_IN, + PLL_LOCK_OUT => PLL_LOCK_OUT, + CLK40M_OUT => CLK40M_OUT, + ADC_ADCLK_OUT => ADC_ADCLK_OUT, + ADC_DATA7_OUT => ADC_DATA7_OUT, + ADC_DATA6_OUT => ADC_DATA6_OUT, + ADC_DATA5_OUT => ADC_DATA5_OUT, + ADC_DATA4_OUT => ADC_DATA4_OUT, + ADC_DATA3_OUT => ADC_DATA3_OUT, + ADC_DATA2_OUT => ADC_DATA2_OUT, + ADC_DATA1_OUT => ADC_DATA1_OUT, + ADC_DATA0_OUT => ADC_DATA0_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +-- 240MHz DDR clock from ADC, aka bit clock +THE_CLOCK_GEN: process +begin + adc_lclk_in <= '1'; wait for 2.08 ns; + adc_lclk_in <= '0'; wait for 2.08 ns; +end process THE_CLOCK_GEN; + +-- test data generator +BLA: process +variable adc_0_data : unsigned(11 downto 0) := x"000"; +variable adc_7_data : unsigned(11 downto 0) := x"fff"; +variable my_bit : integer := 0; +begin + + my_bit := 0; + adc_0_real <= std_logic_vector(adc_0_data); + adc_7_real <= std_logic_vector(adc_7_data); + + BIT_LOOP: for I in 0 to 5 loop + + wait until rising_edge(adc_lclk_in); + wait for 1.04 ns; + if( I < 3 ) then + adc_adclk_in <= '1'; + else + adc_adclk_in <= '0'; -- second half + end if; + adc_chnl_in(7) <= adc_7_data(my_bit); + adc_chnl_in(6 downto 1) <= (others => '0'); + adc_chnl_in(0) <= adc_0_data(my_bit); + my_bit := my_bit + 1; + wait until falling_edge(adc_lclk_in); + wait for 1.04 ns; + adc_chnl_in(7) <= adc_7_data(my_bit); + adc_chnl_in(6 downto 1) <= (others => '0'); + adc_chnl_in(0) <= adc_0_data(my_bit); + my_bit := my_bit + 1; + + end loop BIT_LOOP; + + adc_7_data := adc_7_data - 1; + adc_0_data := adc_0_data + 1; + +end process BLA; + + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + reset_pll_in <= '0'; + pll_ctrl_in <= x"6"; + wait for 100 ns; + + -- Reset all + reset_in <= '1'; + wait for 100 ns; + reset_in <= '0'; + wait for 100 ns; + + -- Tests may start now + + + -- Stay a while, stay forever! + wait; + +end process THE_TEST_BENCH; + + +END; diff --git a/src/tb_adc_handler_OLD.vhd b/src/tb_adc_handler_OLD.vhd new file mode 100644 index 0000000..6bf34cb --- /dev/null +++ b/src/tb_adc_handler_OLD.vhd @@ -0,0 +1,187 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT adc_data_handler + PORT( + RESET_IN : IN std_logic; + RESET_PLL_IN : IN std_logic; + ADC_LCLK_IN : IN std_logic; + ADC_ADCLK_IN : IN std_logic; + ADC_CHNL_IN : IN std_logic_vector(7 downto 0); + PLL_CTRL_IN : IN std_logic_vector(3 downto 0); + PLL_LOCK_OUT : OUT std_logic; + CLK40M_OUT : OUT std_logic; + ADC_ADCLK_OUT : OUT std_logic; + ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA4_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA3_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0); + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL RESET_IN : std_logic; + SIGNAL RESET_PLL_IN : std_logic; + SIGNAL ADC_LCLK_IN : std_logic; + SIGNAL ADC_ADCLK_IN : std_logic; + SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0); + SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0); + SIGNAL PLL_LOCK_OUT : std_logic; + SIGNAL CLK40M_OUT : std_logic; + SIGNAL ADC_ADCLK_OUT : std_logic; + SIGNAL ADC_DATA7_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA6_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA5_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA4_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA3_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA2_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA1_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA0_OUT : std_logic_vector(11 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + + signal adc_0_real : std_logic_vector(11 downto 0); + signal adc_7_real : std_logic_vector(11 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: adc_data_handler PORT MAP( + RESET_IN => RESET_IN, + RESET_PLL_IN => RESET_PLL_IN, + ADC_LCLK_IN => ADC_LCLK_IN, + ADC_ADCLK_IN => ADC_ADCLK_IN, + ADC_CHNL_IN => ADC_CHNL_IN, + PLL_CTRL_IN => PLL_CTRL_IN, + PLL_LOCK_OUT => PLL_LOCK_OUT, + CLK40M_OUT => CLK40M_OUT, + ADC_ADCLK_OUT => ADC_ADCLK_OUT, + ADC_DATA7_OUT => ADC_DATA7_OUT, + ADC_DATA6_OUT => ADC_DATA6_OUT, + ADC_DATA5_OUT => ADC_DATA5_OUT, + ADC_DATA4_OUT => ADC_DATA4_OUT, + ADC_DATA3_OUT => ADC_DATA3_OUT, + ADC_DATA2_OUT => ADC_DATA2_OUT, + ADC_DATA1_OUT => ADC_DATA1_OUT, + ADC_DATA0_OUT => ADC_DATA0_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +THE_CLOCK_GEN: process +begin + adc_lclk_in <= '1'; wait for 4.16 ns; + adc_lclk_in <= '0'; wait for 4.16 ns; +end process THE_CLOCK_GEN; + +BLA: process +variable adc_0_data : unsigned(11 downto 0) := x"000"; +variable adc_7_data : unsigned(11 downto 0) := x"fff"; +variable my_bit : integer := 0; +begin + + my_bit := 0; + adc_0_real <= std_logic_vector(adc_0_data); + adc_7_real <= std_logic_vector(adc_7_data); + + BIT_LOOP: for I in 0 to 5 loop + + wait until rising_edge(adc_lclk_in); + wait for 2.08 ns; + if( I < 3 ) then + adc_adclk_in <= '1'; + else + adc_adclk_in <= '0'; -- second half + end if; + adc_chnl_in(7) <= adc_7_data(my_bit); + adc_chnl_in(6 downto 1) <= (others => '0'); + adc_chnl_in(0) <= adc_0_data(my_bit); + my_bit := my_bit + 1; + wait until falling_edge(adc_lclk_in); + wait for 2.08 ns; + adc_chnl_in(7) <= adc_7_data(my_bit); + adc_chnl_in(6 downto 1) <= (others => '0'); + adc_chnl_in(0) <= adc_0_data(my_bit); + my_bit := my_bit + 1; + + end loop BIT_LOOP; + + adc_7_data := adc_7_data - 1; + adc_0_data := adc_0_data + 1; + +end process BLA; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + reset_pll_in <= '0'; + pll_ctrl_in <= x"6"; + wait for 100 ns; + + -- Reset all + reset_in <= '1'; + wait for 100 ns; + reset_in <= '0'; + wait for 100 ns; + + -- Tests may start now + + + + + + -- Stay a while, stay forever! + wait; + +end process THE_TEST_BENCH; + +END; + + +-- -- ADCLK = '1' => first half of data word +-- wait until rising_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '1'; adc_chnl_in <= b"0000_0000"; -- Bit D0 +-- wait until falling_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '1'; adc_chnl_in <= b"1111_1111"; -- Bit D1 +-- wait until rising_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '1'; adc_chnl_in <= b"0000_0000"; -- Bit D2 +-- wait until falling_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '1'; adc_chnl_in <= b"1111_1111"; -- Bit D3 +-- wait until rising_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '1'; adc_chnl_in <= b"0000_0000"; -- Bit D4 +-- wait until falling_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '1'; adc_chnl_in <= b"1111_1111"; -- Bit D5 +-- -- ADCLK = '0' => second half of data word +-- wait until rising_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '0'; adc_chnl_in <= b"0000_0000"; -- Bit D6 +-- wait until falling_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '0'; adc_chnl_in <= b"1111_1111"; -- Bit D7 +-- wait until rising_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '0'; adc_chnl_in <= b"0000_0000"; -- Bit D8 +-- wait until falling_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '0'; adc_chnl_in <= b"1111_1111"; -- Bit D9 +-- wait until rising_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '0'; adc_chnl_in <= b"0000_0000"; -- Bit D10 +-- wait until falling_edge(adc_lclk_in); +-- wait for 2.08 ns; +-- adc_adclk_in <= '0'; adc_chnl_in <= b"1111_1111"; -- Bit D11 diff --git a/src/tb_adc_handler_new.vhd b/src/tb_adc_handler_new.vhd new file mode 100644 index 0000000..c585817 --- /dev/null +++ b/src/tb_adc_handler_new.vhd @@ -0,0 +1,142 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT adc_data_handler_new + PORT( + RESET_IN : IN std_logic; + ADC_LCLK_IN : IN std_logic; + ADC_ADCLK_IN : IN std_logic; + ADC_CHNL_IN : IN std_logic_vector(7 downto 0); + PLL_CTRL_IN : IN std_logic_vector(3 downto 0); + ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA4_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA3_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0); + ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0); + ADC_CE_OUT : OUT std_logic; + ADC_VALID_OUT : OUT std_logic; + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL RESET_IN : std_logic; + SIGNAL ADC_LCLK_IN : std_logic; + SIGNAL ADC_ADCLK_IN : std_logic; + SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0); + SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0); + SIGNAL ADC_DATA7_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA6_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA5_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA4_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA3_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA2_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA1_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_DATA0_OUT : std_logic_vector(11 downto 0); + SIGNAL ADC_CE_OUT : std_logic; + SIGNAL ADC_VALID_OUT : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + + signal adc_0_real : std_logic_vector(11 downto 0); + signal adc_7_real : std_logic_vector(11 downto 0); + + +BEGIN + +-- Please check and add your generic clause manually + uut: adc_data_handler_new PORT MAP( + RESET_IN => RESET_IN, + ADC_LCLK_IN => ADC_LCLK_IN, + ADC_ADCLK_IN => ADC_ADCLK_IN, + ADC_CHNL_IN => ADC_CHNL_IN, + PLL_CTRL_IN => PLL_CTRL_IN, + ADC_DATA7_OUT => ADC_DATA7_OUT, + ADC_DATA6_OUT => ADC_DATA6_OUT, + ADC_DATA5_OUT => ADC_DATA5_OUT, + ADC_DATA4_OUT => ADC_DATA4_OUT, + ADC_DATA3_OUT => ADC_DATA3_OUT, + ADC_DATA2_OUT => ADC_DATA2_OUT, + ADC_DATA1_OUT => ADC_DATA1_OUT, + ADC_DATA0_OUT => ADC_DATA0_OUT, + ADC_CE_OUT => ADC_CE_OUT, + ADC_VALID_OUT => ADC_VALID_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +-- 240MHz DDR clock from ADC, aka bit clock +THE_CLOCK_GEN: process +begin + adc_lclk_in <= '1'; wait for 2.08 ns; + adc_lclk_in <= '0'; wait for 2.08 ns; +end process THE_CLOCK_GEN; + +-- test data generator +BLA: process +variable adc_0_data : unsigned(11 downto 0) := x"000"; +variable adc_7_data : unsigned(11 downto 0) := x"fff"; +variable my_bit : integer := 0; +begin + + my_bit := 0; + adc_0_real <= std_logic_vector(adc_0_data); + adc_7_real <= std_logic_vector(adc_7_data); + + BIT_LOOP: for I in 0 to 5 loop + + wait until rising_edge(adc_lclk_in); + wait for 1.04 ns; + if( I < 3 ) then + adc_adclk_in <= '1'; + else + adc_adclk_in <= '0'; -- second half + end if; + adc_chnl_in(7) <= adc_7_data(my_bit); + adc_chnl_in(6 downto 1) <= (others => '0'); + adc_chnl_in(0) <= adc_0_data(my_bit); + my_bit := my_bit + 1; + wait until falling_edge(adc_lclk_in); + wait for 1.04 ns; + adc_chnl_in(7) <= adc_7_data(my_bit); + adc_chnl_in(6 downto 1) <= (others => '0'); + adc_chnl_in(0) <= adc_0_data(my_bit); + my_bit := my_bit + 1; + + end loop BIT_LOOP; + + adc_7_data := adc_7_data - 1; + adc_0_data := adc_0_data + 1; + +end process BLA; + + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + pll_ctrl_in <= x"6"; + wait for 100 ns; + + -- Reset all + reset_in <= '1'; + wait for 100 ns; + reset_in <= '0'; + wait for 100 ns; + + -- Tests may start now + + + -- Stay a while, stay forever! + wait; + +end process THE_TEST_BENCH; + + +END; diff --git a/src/tb_adc_onewire_map_mem_tmpl.vhd b/src/tb_adc_onewire_map_mem_tmpl.vhd new file mode 100644 index 0000000..c38f34b --- /dev/null +++ b/src/tb_adc_onewire_map_mem_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component adc_onewire_map_mem + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : adc_onewire_map_mem + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/src/tb_apv_adc_map_mem_tmpl.vhd b/src/tb_apv_adc_map_mem_tmpl.vhd new file mode 100644 index 0000000..d66043c --- /dev/null +++ b/src/tb_apv_adc_map_mem_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component apv_adc_map_mem + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : apv_adc_map_mem + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/src/tb_apv_locker.vhd b/src/tb_apv_locker.vhd new file mode 100755 index 0000000..81a88ba --- /dev/null +++ b/src/tb_apv_locker.vhd @@ -0,0 +1,193 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT apv_locker + PORT( + CLK_APV_IN : IN std_logic; + RESET_IN : IN std_logic; + SYNC_IN : IN std_logic; + ADC_RAW_IN : IN std_logic_vector(11 downto 0); + ADC_VALID_IN : IN std_logic; + APV_ON_IN : IN std_logic; + BIT_LOW_IN : IN std_logic_vector(11 downto 0); + BIT_HIGH_IN : IN std_logic_vector(11 downto 0); + FL_LOW_IN : IN std_logic_vector(11 downto 0); + FL_HIGH_IN : IN std_logic_vector(11 downto 0); + STATUS_IGNORE_OUT : OUT std_logic; + STATUS_UNKNOWN_OUT : OUT std_logic; + STATUS_BADADC_OUT : OUT std_logic; + STATUS_LOCKED_OUT : OUT std_logic; + STATUS_LOST_OUT : OUT std_logic; + STATUS_NOSYNC_OUT : OUT std_logic; + STATUS_MISSING_OUT : OUT std_logic; + STATUS_TICKMARK_OUT : OUT std_logic; + FRAME_ROW_OUT : OUT std_logic_vector(7 downto 0); + FRAME_ERROR_OUT : OUT std_logic; + FRAME_FLAT_OUT : OUT std_logic; + FRAME_OVF_OUT : OUT std_logic; + FRAME_UDF_OUT : OUT std_logic; + FRAME_CTR_OUT : OUT std_logic_vector(3 downto 0); + APV_CHANNEL_OUT : OUT std_logic_vector(6 downto 0); + APV_OVERFLOW_OUT : OUT std_logic; + APV_UNDERFLOW_OUT : OUT std_logic; + APV_RAW_OUT : OUT std_logic_vector(11 downto 0); + APV_ANALOG_OUT : OUT std_logic; + APV_START_OUT : OUT std_logic; + APV_LAST_OUT : OUT std_logic; + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_APV_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL SYNC_IN : std_logic; + SIGNAL ADC_RAW_IN : std_logic_vector(11 downto 0); + SIGNAL ADC_VALID_IN : std_logic; + SIGNAL APV_ON_IN : std_logic; + SIGNAL BIT_LOW_IN : std_logic_vector(11 downto 0); + SIGNAL BIT_HIGH_IN : std_logic_vector(11 downto 0); + SIGNAL FL_LOW_IN : std_logic_vector(11 downto 0); + SIGNAL FL_HIGH_IN : std_logic_vector(11 downto 0); + SIGNAL STATUS_IGNORE_OUT : std_logic; + SIGNAL STATUS_UNKNOWN_OUT : std_logic; + SIGNAL STATUS_BADADC_OUT : std_logic; + SIGNAL STATUS_LOCKED_OUT : std_logic; + SIGNAL STATUS_LOST_OUT : std_logic; + SIGNAL STATUS_NOSYNC_OUT : std_logic; + SIGNAL STATUS_MISSING_OUT : std_logic; + SIGNAL STATUS_TICKMARK_OUT : std_logic; + SIGNAL FRAME_ROW_OUT : std_logic_vector(7 downto 0); + SIGNAL FRAME_ERROR_OUT : std_logic; + SIGNAL FRAME_FLAT_OUT : std_logic; + SIGNAL FRAME_OVF_OUT : std_logic; + SIGNAL FRAME_UDF_OUT : std_logic; + SIGNAL FRAME_CTR_OUT : std_logic_vector(3 downto 0); + SIGNAL APV_CHANNEL_OUT : std_logic_vector(6 downto 0); + SIGNAL APV_OVERFLOW_OUT : std_logic; + SIGNAL APV_UNDERFLOW_OUT : std_logic; + SIGNAL APV_RAW_OUT : std_logic_vector(11 downto 0); + SIGNAL APV_ANALOG_OUT : std_logic; + SIGNAL APV_START_OUT : std_logic; + SIGNAL APV_LAST_OUT : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: apv_locker PORT MAP( + CLK_APV_IN => CLK_APV_IN, + RESET_IN => RESET_IN, + SYNC_IN => SYNC_IN, + ADC_RAW_IN => ADC_RAW_IN, + ADC_VALID_IN => ADC_VALID_IN, + APV_ON_IN => APV_ON_IN, + BIT_LOW_IN => BIT_LOW_IN, + BIT_HIGH_IN => BIT_HIGH_IN, + FL_LOW_IN => FL_LOW_IN, + FL_HIGH_IN => FL_HIGH_IN, + STATUS_IGNORE_OUT => STATUS_IGNORE_OUT, + STATUS_UNKNOWN_OUT => STATUS_UNKNOWN_OUT, + STATUS_BADADC_OUT => STATUS_BADADC_OUT, + STATUS_LOCKED_OUT => STATUS_LOCKED_OUT, + STATUS_LOST_OUT => STATUS_LOST_OUT, + STATUS_NOSYNC_OUT => STATUS_NOSYNC_OUT, + STATUS_MISSING_OUT => STATUS_MISSING_OUT, + STATUS_TICKMARK_OUT => STATUS_TICKMARK_OUT, + FRAME_ROW_OUT => FRAME_ROW_OUT, + FRAME_ERROR_OUT => FRAME_ERROR_OUT, + FRAME_FLAT_OUT => FRAME_FLAT_OUT, + FRAME_OVF_OUT => FRAME_OVF_OUT, + FRAME_UDF_OUT => FRAME_UDF_OUT, + FRAME_CTR_OUT => FRAME_CTR_OUT, + APV_CHANNEL_OUT => APV_CHANNEL_OUT, + APV_OVERFLOW_OUT => APV_OVERFLOW_OUT, + APV_UNDERFLOW_OUT => APV_UNDERFLOW_OUT, + APV_RAW_OUT => APV_RAW_OUT, + APV_ANALOG_OUT => APV_ANALOG_OUT, + APV_START_OUT => APV_START_OUT, + APV_LAST_OUT => APV_LAST_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +THE_ADC_CLOCK_GEN: process +begin + clk_apv_in <= '1'; wait for 12.5 ns; + clk_apv_in <= '0'; wait for 12.5 ns; +end process THE_ADC_CLOCK_GEN; + +THE_APV_SIM_PROC: process +begin + LOOP_IT: for J in 0 to 32 loop + wait until rising_edge(clk_apv_in); + adc_raw_in <= x"e00"; + wait until rising_edge(clk_apv_in); + adc_raw_in <= x"100"; + ONE_LOOP: for I in 0 to 32 loop + wait until rising_edge(clk_apv_in); + end loop ONE_LOOP; + end loop LOOP_IT; + + wait until rising_edge(clk_apv_in); + adc_raw_in <= x"fff"; + wait until rising_edge(clk_apv_in); + adc_raw_in <= x"fff"; + wait until rising_edge(clk_apv_in); + adc_raw_in <= x"fff"; + HEADER_LOOP: for L in 0 to 8 loop + wait until rising_edge(clk_apv_in); + adc_raw_in <= x"eee"; + end loop HEADER_LOOP; + DATA_LOOP: for L in 0 to 127 loop + wait until rising_edge(clk_apv_in); + adc_raw_in <= x"222"; + end loop DATA_LOOP; + +end process THE_APV_SIM_PROC; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + sync_in <= '0'; + adc_valid_in <= '0'; + apv_on_in <= '1'; + bit_low_in <= x"200"; + bit_high_in <= x"d00"; + fl_low_in <= x"780"; + fl_high_in <= x"880"; + wait for 100 ns; + + -- Reset all + reset_in <= '1'; + wait for 100 ns; + reset_in <= '0'; + wait for 100 ns; + adc_valid_in <= '1'; + wait for 100 ns; + + -- Tests may start now + -- send a SYNC sequence b"101" + wait until rising_edge(clk_apv_in); + sync_in <= '1'; + wait until rising_edge(clk_apv_in); + sync_in <= '0'; + + -- wait until sync'ed +-- wait until rising_edge(status_locked_out); +-- wait for 300 ns; + + + + + -- Stay a while, stay forever! + wait; + +end process THE_TEST_BENCH; + +END; diff --git a/src/tb_apv_map_mem_tmpl.vhd b/src/tb_apv_map_mem_tmpl.vhd new file mode 100644 index 0000000..9e06c81 --- /dev/null +++ b/src/tb_apv_map_mem_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component apv_map_mem + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : apv_map_mem + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/src/tb_apv_trgctrl.vhd b/src/tb_apv_trgctrl.vhd new file mode 100755 index 0000000..ec21ace --- /dev/null +++ b/src/tb_apv_trgctrl.vhd @@ -0,0 +1,257 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT apv_trgctrl + PORT( + CLK_APV_IN : IN std_logic; + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + SYNC_TRG_IN : IN std_logic; + TIME_TRG_IN : IN std_logic_vector(3 downto 0); + TRB_TRG_IN : IN std_logic_vector(3 downto 0); + STILL_BUSY_IN : IN std_logic; + TRG_3_TODO_IN : IN std_logic_vector(3 downto 0); + TRG_3_DELAY_IN : IN std_logic_vector(3 downto 0); + TRG_2_TODO_IN : IN std_logic_vector(3 downto 0); + TRG_2_DELAY_IN : IN std_logic_vector(3 downto 0); + TRG_1_TODO_IN : IN std_logic_vector(3 downto 0); + TRG_1_DELAY_IN : IN std_logic_vector(3 downto 0); + TRG_0_TODO_IN : IN std_logic_vector(3 downto 0); + TRG_0_DELAY_IN : IN std_logic_vector(3 downto 0); + TRG_SETUP_IN : IN std_logic_vector(7 downto 0); + TRB_TTAG_IN : IN std_logic_vector(15 downto 0); + TRB_TRND_IN : IN std_logic_vector(7 downto 0); + TRB_TTYPE_IN : IN std_logic_vector(3 downto 0); + TRB_TRGRCVD_IN : IN std_logic; + TRB_RST_COUNTER_IN : IN std_logic; + EDS_DONE_IN : IN std_logic; + TRG_FOUND_OUT : OUT std_logic; + TRB_MISSING_OUT : OUT std_logic; + TRB_RELEASE_OUT : OUT std_logic; + TRB_COUNTER_OUT : OUT std_logic_vector(15 downto 0); + EDS_DATA_OUT : OUT std_logic_vector(39 downto 0); + EDS_AVAIL_OUT : OUT std_logic; + EDS_FULL_OUT : OUT std_logic; + EDS_LEVEL_OUT : OUT std_logic_vector(4 downto 0); + FRM_REQD_OUT : OUT std_logic; + APV_TRG_OUT : OUT std_logic; + APV_SYNC_OUT : OUT std_logic; + DEBUG_OUT : OUT std_logic_vector(63 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_APV_IN : std_logic; + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL SYNC_TRG_IN : std_logic; + SIGNAL TIME_TRG_IN : std_logic_vector(3 downto 0); + SIGNAL TRB_TRG_IN : std_logic_vector(3 downto 0); + SIGNAL STILL_BUSY_IN : std_logic; + SIGNAL TRG_FOUND_OUT : std_logic; + SIGNAL TRG_3_TODO_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_3_DELAY_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_2_TODO_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_2_DELAY_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_1_TODO_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_1_DELAY_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_0_TODO_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_0_DELAY_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_SETUP_IN : std_logic_vector(7 downto 0); + SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0); + SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0); + SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0); + SIGNAL TRB_TRGRCVD_IN : std_logic; + SIGNAL TRB_MISSING_OUT : std_logic; + SIGNAL TRB_RELEASE_OUT : std_logic; + SIGNAL TRB_RST_COUNTER_IN : std_logic; + SIGNAL TRB_COUNTER_OUT : std_logic_vector(15 downto 0); + SIGNAL EDS_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL EDS_AVAIL_OUT : std_logic; + SIGNAL EDS_DONE_IN : std_logic; + SIGNAL EDS_FULL_OUT : std_logic; + SIGNAL EDS_LEVEL_OUT : std_logic_vector(4 downto 0); + SIGNAL FRM_REQD_OUT : std_logic; + SIGNAL APV_TRG_OUT : std_logic; + SIGNAL APV_SYNC_OUT : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(63 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: apv_trgctrl PORT MAP( + CLK_APV_IN => CLK_APV_IN, + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SYNC_TRG_IN => SYNC_TRG_IN, + TIME_TRG_IN => TIME_TRG_IN, + TRB_TRG_IN => TRB_TRG_IN, + STILL_BUSY_IN => STILL_BUSY_IN, + TRG_FOUND_OUT => TRG_FOUND_OUT, + TRG_3_TODO_IN => TRG_3_TODO_IN, + TRG_3_DELAY_IN => TRG_3_DELAY_IN, + TRG_2_TODO_IN => TRG_2_TODO_IN, + TRG_2_DELAY_IN => TRG_2_DELAY_IN, + TRG_1_TODO_IN => TRG_1_TODO_IN, + TRG_1_DELAY_IN => TRG_1_DELAY_IN, + TRG_0_TODO_IN => TRG_0_TODO_IN, + TRG_0_DELAY_IN => TRG_0_DELAY_IN, + TRG_SETUP_IN => TRG_SETUP_IN, + TRB_TTAG_IN => TRB_TTAG_IN, + TRB_TRND_IN => TRB_TRND_IN, + TRB_TTYPE_IN => TRB_TTYPE_IN, + TRB_TRGRCVD_IN => TRB_TRGRCVD_IN, + TRB_MISSING_OUT => TRB_MISSING_OUT, + TRB_RELEASE_OUT => TRB_RELEASE_OUT, + TRB_RST_COUNTER_IN => TRB_RST_COUNTER_IN, + TRB_COUNTER_OUT => TRB_COUNTER_OUT, + EDS_DATA_OUT => EDS_DATA_OUT, + EDS_AVAIL_OUT => EDS_AVAIL_OUT, + EDS_DONE_IN => EDS_DONE_IN, + EDS_FULL_OUT => EDS_FULL_OUT, + EDS_LEVEL_OUT => EDS_LEVEL_OUT, + FRM_REQD_OUT => FRM_REQD_OUT, + APV_TRG_OUT => APV_TRG_OUT, + APV_SYNC_OUT => APV_SYNC_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +-- Generate the clock +THE_CLOCK_GEN: process +begin + clk_in <= '0'; wait for 5 ns; + clk_in <= '1'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_APV_CLOCK_GEN: process +begin + clk_apv_in <= '0'; wait for 12.5 ns; + clk_apv_in <= '1'; wait for 12.5 ns; +end process THE_APV_CLOCK_GEN; + +-- The real testbench +THE_TESTBENCH_PROC: process +begin + -- Setup signals + reset_in <= '0'; + sync_trg_in <= '0'; + time_trg_in <= x"0"; + trb_trg_in <= x"0"; + still_busy_in <= '0'; + trg_3_todo_in <= x"1"; + trg_3_delay_in <= x"0"; + trg_2_todo_in <= x"1"; + trg_2_delay_in <= x"0"; + trg_1_todo_in <= x"1"; + trg_1_delay_in <= x"0"; + trg_0_todo_in <= x"1"; + trg_0_delay_in <= x"0"; + trg_setup_in <= x"10"; -- TRG0 is active, non-inverted + trb_ttag_in <= x"0000"; + trb_trnd_in <= x"00"; + trb_ttype_in <= x"0"; + trb_trgrcvd_in <= '0'; + trb_rst_counter_in <= '0'; + eds_done_in <= '0'; + + wait for 20 ns; + + -- Do a reset + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 100 ns; + + -- test may start here + + wait until rising_edge(clk_in); + sync_trg_in <= '1'; + wait until rising_edge(clk_in); + sync_trg_in <= '0'; + wait until rising_edge(clk_in); + + wait for 1 us; + + -- first trigger + -- send in one timing trigger + wait for 77.7 ns; + time_trg_in <= x"1"; + wait for 222.2 ns; + time_trg_in <= x"0"; + + -- send TRB trigger infos + wait for 2.3 us; + wait until rising_edge(clk_in); + trb_ttype_in <= x"1"; + trb_ttag_in <= x"abcd"; + trb_trnd_in <= x"ef"; + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; + + -- release trigger + wait until rising_edge(trb_release_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '0'; + wait until rising_edge(clk_in); + + wait for 1.22 us; + + -- next trigger + -- send in one timing trigger + wait for 77.7 ns; + time_trg_in <= x"1"; + wait for 222.2 ns; + time_trg_in <= x"0"; + + -- send TRB trigger infos + wait for 2.3 us; + wait until rising_edge(clk_in); + trb_ttype_in <= x"2"; + trb_ttag_in <= x"dead"; + trb_trnd_in <= x"42"; + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; + + -- release trigger + wait until rising_edge(trb_release_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '0'; + wait until rising_edge(clk_in); + + wait for 1.11 us; + + -- release one EDS + wait until rising_edge(clk_in); + eds_done_in <= '1'; + wait until rising_edge(clk_in); + eds_done_in <= '0'; + wait until rising_edge(clk_in); + + wait for 200 ns; + + -- release one EDS + wait until rising_edge(clk_in); + eds_done_in <= '1'; + wait until rising_edge(clk_in); + eds_done_in <= '0'; + wait until rising_edge(clk_in); + + + -- Stay a while, stay forever.... wuhahahahaha + wait; +end process THE_TESTBENCH_PROC; + + +END; diff --git a/src/tb_comp4bit_tmpl.vhd b/src/tb_comp4bit_tmpl.vhd new file mode 100644 index 0000000..69fe6ee --- /dev/null +++ b/src/tb_comp4bit_tmpl.vhd @@ -0,0 +1,48 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component comp4bit + port (DataA : in std_logic_vector(3 downto 0); + DataB : in std_logic_vector(3 downto 0); AGTB: out std_logic + ); + end component; + + signal DataA : std_logic_vector(3 downto 0) := (others => '0'); + signal DataB : std_logic_vector(3 downto 0) := (others => '0'); + signal AGTB: std_logic; +begin + u1 : comp4bit + port map (DataA => DataA, DataB => DataB, AGTB => AGTB + ); + + process + + begin + DataA <= (others => '0') ; + for i in 0 to 200 loop + wait for 10 ns; + DataA <= DataA + '1' ; + end loop; + wait; + end process; + + process + + begin + DataB <= (others => '0') ; + for i in 0 to 100 loop + wait for 10 ns; + DataB <= DataB + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/src/tb_crossfifo.vhd b/src/tb_crossfifo.vhd new file mode 100644 index 0000000..5dda828 --- /dev/null +++ b/src/tb_crossfifo.vhd @@ -0,0 +1,260 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + component crossfifo is + port( DATA : in std_logic_vector(95 downto 0); + WRCLOCK : in std_logic; + RDCLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + RPRESET : in std_logic; + Q : out std_logic_vector(95 downto 0); + EMPTY : out std_logic; + FULL : out std_logic; + ALMOSTEMPTY : out std_logic + ); + end component; + + signal DATA : std_logic_vector(95 downto 0); + signal WRCLOCK : std_logic; + signal RDCLOCK : std_logic; + signal WREN : std_logic; + signal RDEN : std_logic; + signal RESET : std_logic; + signal RPRESET : std_logic; + signal Q : std_logic_vector(95 downto 0); + signal EMPTY : std_logic; + signal FULL : std_logic; + signal ALMOSTEMPTY : std_logic; + +BEGIN + +-- Please check and add your generic clause manually + uut: crossfifo PORT MAP( + DATA => DATA, + WRCLOCK => WRCLOCK, + RDCLOCK => RDCLOCK, + WREN => WREN, + RDEN => RDEN, + RESET => RESET, + RPRESET => RPRESET, + Q => Q, + EMPTY => EMPTY, + FULL => FULL, + ALMOSTEMPTY => ALMOSTEMPTY + ); + +RDCLOCK_GEN: process +begin + rdclock <= '1'; wait for 12.5 ns; + rdclock <= '0'; wait for 12.5 ns; +end process RDCLOCK_GEN; + +WRCLOCK_GEN: process +begin + wait until rising_edge(rdclock); wait for 3.33 ns; wrclock <= '1'; + wait until falling_edge(rdclock); wait for 3.33 ns; wrclock <= '0'; +end process WRCLOCK_GEN; + +RDEN_GEN: process +begin + rden <= '0'; + wait until falling_edge(reset); + wait until falling_edge(almostempty); + rden <= '1'; +end process RDEN_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + data <= x"000_000_000_000_000_000_000_000"; + wren <= '0'; + --rden <= '0'; + reset <= '0'; + rpreset <= '0'; + + -- Reset all + reset <= '1'; wait for 50 ns; + reset <= '0'; wait for 50 ns; + + -- Tests may start here + + wait until rising_edge(wrclock); + wren <= '1'; + data(95 downto 84) <= x"001"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"002"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"003"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"004"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"005"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"006"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"007"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"008"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"009"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"00a"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"00b"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"00c"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"00d"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"00e"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"00e"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"00f"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"010"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"011"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"012"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"013"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"014"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"015"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"016"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"017"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"018"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"019"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"01a"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"01b"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"01c"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"01d"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"01e"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"01f"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"020"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"021"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"022"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"023"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"024"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"025"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"026"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"027"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"028"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"029"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"02a"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"02b"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"02c"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"02d"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"02e"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"02f"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"030"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"031"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"032"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"033"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"034"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"035"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"036"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"037"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"038"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"039"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"03a"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"03b"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"03c"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"03d"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"03e"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"03f"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"040"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"041"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"042"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"043"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"044"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"045"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"046"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"047"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"048"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"049"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"04a"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"04b"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"04c"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"04d"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"04e"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"04f"; + wait until rising_edge(wrclock); + + + -- Stay a while, stay forever. + wait; + +end process THE_TEST_BENCH; + + +END; + diff --git a/src/tb_crossfifo_tmpl.vhd b/src/tb_crossfifo_tmpl.vhd new file mode 100644 index 0000000..405d101 --- /dev/null +++ b/src/tb_crossfifo_tmpl.vhd @@ -0,0 +1,103 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component crossfifo + port (Data : in std_logic_vector(95 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(95 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostEmpty: out std_logic + ); + end component; + + signal Data : std_logic_vector(95 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(95 downto 0); + signal Empty: std_logic; + signal Full: std_logic; + signal AlmostEmpty: std_logic; +begin + u1 : crossfifo + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 259 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 259 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 259 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/src/tb_crossover.vhd b/src/tb_crossover.vhd new file mode 100644 index 0000000..87ec08e --- /dev/null +++ b/src/tb_crossover.vhd @@ -0,0 +1,161 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + component crossover is + port( DATA : in std_logic_vector(95 downto 0); + WRCLOCK : in std_logic; + RDCLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + RPRESET : in std_logic; + Q : out std_logic_vector(95 downto 0); + WCNT : out std_logic_vector(4 downto 0); + RCNT : out std_logic_vector(4 downto 0); + EMPTY : out std_logic; + FULL : out std_logic + ); + end component; + + signal DATA : std_logic_vector(95 downto 0); + signal WRCLOCK : std_logic; + signal RDCLOCK : std_logic; + signal WREN : std_logic; + signal RDEN : std_logic; + signal RESET : std_logic; + signal RPRESET : std_logic; + signal Q : std_logic_vector(95 downto 0); + signal WCNT : std_logic_vector(4 downto 0); + signal RCNT : std_logic_vector(4 downto 0); + signal EMPTY : std_logic; + signal FULL : std_logic; + +BEGIN + +-- Please check and add your generic clause manually + uut: crossover PORT MAP( + DATA => DATA, + WRCLOCK => WRCLOCK, + RDCLOCK => RDCLOCK, + WREN => WREN, + RDEN => RDEN, + RESET => RESET, + RPRESET => RPRESET, + Q => Q, + RCNT => RCNT, + WCNT => WCNT, + EMPTY => EMPTY, + FULL => FULL + ); + +RDCLOCK_GEN: process +begin + rdclock <= '1'; wait for 12.5 ns; + rdclock <= '0'; wait for 12.5 ns; +end process RDCLOCK_GEN; + +WRCLOCK_GEN: process +begin + wait until rising_edge(rdclock); wait for 3.33 ns; wrclock <= '1'; + wait until falling_edge(rdclock); wait for 3.33 ns; wrclock <= '0'; +end process WRCLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + data <= x"000_000_000_000_000_000_000_000"; + wren <= '0'; + rden <= '0'; + reset <= '0'; + rpreset <= '0'; + + -- Reset all + reset <= '1'; wait for 50 ns; + reset <= '0'; wait for 50 ns; + + -- Tests may start here + + wait until rising_edge(wrclock); + wren <= '1'; + data(95 downto 84) <= x"100"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"101"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"102"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"103"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"104"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"105"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"106"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"107"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"108"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"109"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"10a"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"10b"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"10c"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"10d"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"10e"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"10f"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"110"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"111"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"112"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"113"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"114"; + wait until rising_edge(wrclock); + data(95 downto 84) <= x"115"; + wait until rising_edge(wrclock); + wren <= '0'; + + wait until rising_edge(rdclock); + rden <= '1'; + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + + wait until rising_edge(rdclock); + wait until rising_edge(rdclock); + + -- Stay a while, stay forever. + wait; + +end process THE_TEST_BENCH; + + +END; + diff --git a/src/tb_crossover_tmpl.vhd b/src/tb_crossover_tmpl.vhd new file mode 100644 index 0000000..ca6cbbf --- /dev/null +++ b/src/tb_crossover_tmpl.vhd @@ -0,0 +1,106 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component crossover + port (Data : in std_logic_vector(95 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(95 downto 0); + WCNT : out std_logic_vector(4 downto 0); + RCNT : out std_logic_vector(4 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(95 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(95 downto 0); + signal WCNT : std_logic_vector(4 downto 0); + signal RCNT : std_logic_vector(4 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : crossover + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 19 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 19 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 19 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/src/tb_dpram_8x19_tmpl.vhd b/src/tb_dpram_8x19_tmpl.vhd new file mode 100644 index 0000000..08ccad6 --- /dev/null +++ b/src/tb_dpram_8x19_tmpl.vhd @@ -0,0 +1,98 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component dpram_8x19 + port (WrAddress : in std_logic_vector(3 downto 0); + Data : in std_logic_vector(18 downto 0); WrClock: in std_logic; + WE: in std_logic; WrClockEn: in std_logic; + RdAddress : in std_logic_vector(3 downto 0); + Q : out std_logic_vector(18 downto 0) + ); + end component; + + signal WrAddress : std_logic_vector(3 downto 0) := (others => '0'); + signal Data : std_logic_vector(18 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal WE: std_logic := '0'; + signal WrClockEn: std_logic := '0'; + signal RdAddress : std_logic_vector(3 downto 0) := (others => '0'); + signal Q : std_logic_vector(18 downto 0); +begin + u1 : dpram_8x19 + port map (WrAddress => WrAddress, Data => Data, WrClock => WrClock, + WE => WE, WrClockEn => WrClockEn, RdAddress => RdAddress, Q => Q + ); + + process + + begin + WrAddress <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 38 loop + wait until WrClock'event and WrClock = '1'; + WrAddress <= WrAddress + '1' after 1 ns; + end loop; + wait; + end process; + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 19 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + process + + begin + WE <= '0' ; + wait for 10 ns; + for i in 0 to 19 loop + wait until WrClock'event and WrClock = '1'; + WE <= '1' after 1 ns; + end loop; + WE <= '0' ; + wait; + end process; + + process + + begin + WrClockEn <= '0' ; + wait for 100 ns; + wait for 10 ns; + WrClockEn <= '1' ; + wait; + end process; + + process + + begin + RdAddress <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 38 loop + wait for 10 ns; + RdAddress <= RdAddress + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/src/tb_ipu_fifo_stage.vhd b/src/tb_ipu_fifo_stage.vhd new file mode 100644 index 0000000..c1d3d3a --- /dev/null +++ b/src/tb_ipu_fifo_stage.vhd @@ -0,0 +1,359 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +library work; +use work.adcmv3_components.all; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT ipu_fifo_stage + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + SECTOR_IN : IN std_logic_vector(2 downto 0); + MODULE_IN : IN std_logic_vector(2 downto 0); + IPU_NUMBER_IN : IN std_logic_vector(15 downto 0); + IPU_INFORMATION_IN : IN std_logic_vector(7 downto 0); + IPU_START_READOUT_IN : IN std_logic; + IPU_READ_IN : IN std_logic; + DHDR_DATA_IN : IN std_logic_vector(31 downto 0); + DHDR_LENGTH_IN : IN std_logic_vector(15 downto 0); + DHDR_STORE_IN : IN std_logic; + FIFO_START_IN : IN std_logic; + FIFO_0_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_1_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_2_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_3_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_4_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_5_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_6_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_7_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_8_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_9_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_10_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_11_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_12_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_13_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_14_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_15_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_WE_IN : IN std_logic_vector(15 downto 0); + FIFO_DONE_IN : IN std_logic; + IPU_DATA_OUT : OUT std_logic_vector(31 downto 0); + IPU_DATAREADY_OUT : OUT std_logic; + IPU_READOUT_FINISHED_OUT : OUT std_logic; + IPU_LENGTH_OUT : OUT std_logic_vector(15 downto 0); + IPU_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); + DBG_BSM_OUT : OUT std_logic_vector(7 downto 0); + DBG_OUT : OUT std_logic_vector(63 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL SECTOR_IN : std_logic_vector(2 downto 0); + SIGNAL MODULE_IN : std_logic_vector(2 downto 0); + SIGNAL IPU_NUMBER_IN : std_logic_vector(15 downto 0); + SIGNAL IPU_INFORMATION_IN : std_logic_vector(7 downto 0); + SIGNAL IPU_START_READOUT_IN : std_logic; + SIGNAL IPU_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL IPU_DATAREADY_OUT : std_logic; + SIGNAL IPU_READOUT_FINISHED_OUT : std_logic; + SIGNAL IPU_READ_IN : std_logic; + SIGNAL IPU_LENGTH_OUT : std_logic_vector(15 downto 0); + SIGNAL IPU_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); + SIGNAL DHDR_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL DHDR_LENGTH_IN : std_logic_vector(15 downto 0); + SIGNAL DHDR_STORE_IN : std_logic; + SIGNAL FIFO_START_IN : std_logic; + SIGNAL FIFO_0_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_1_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_2_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_3_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_4_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_5_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_6_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_7_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_8_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_9_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_10_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_11_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_12_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_13_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_14_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_15_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_WE_IN : std_logic_vector(15 downto 0); + SIGNAL FIFO_DONE_IN : std_logic; + SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0); + SIGNAL DBG_OUT : std_logic_vector(63 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: ipu_fifo_stage PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SECTOR_IN => SECTOR_IN, + MODULE_IN => MODULE_IN, + IPU_NUMBER_IN => IPU_NUMBER_IN, + IPU_INFORMATION_IN => IPU_INFORMATION_IN, + IPU_START_READOUT_IN => IPU_START_READOUT_IN, + IPU_DATA_OUT => IPU_DATA_OUT, + IPU_DATAREADY_OUT => IPU_DATAREADY_OUT, + IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_OUT, + IPU_READ_IN => IPU_READ_IN, + IPU_LENGTH_OUT => IPU_LENGTH_OUT, + IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT, + DHDR_DATA_IN => DHDR_DATA_IN, + DHDR_LENGTH_IN => DHDR_LENGTH_IN, + DHDR_STORE_IN => DHDR_STORE_IN, + FIFO_START_IN => FIFO_START_IN, + FIFO_0_DATA_IN => FIFO_0_DATA_IN, + FIFO_1_DATA_IN => FIFO_1_DATA_IN, + FIFO_2_DATA_IN => FIFO_2_DATA_IN, + FIFO_3_DATA_IN => FIFO_3_DATA_IN, + FIFO_4_DATA_IN => FIFO_4_DATA_IN, + FIFO_5_DATA_IN => FIFO_5_DATA_IN, + FIFO_6_DATA_IN => FIFO_6_DATA_IN, + FIFO_7_DATA_IN => FIFO_7_DATA_IN, + FIFO_8_DATA_IN => FIFO_8_DATA_IN, + FIFO_9_DATA_IN => FIFO_9_DATA_IN, + FIFO_10_DATA_IN => FIFO_10_DATA_IN, + FIFO_11_DATA_IN => FIFO_11_DATA_IN, + FIFO_12_DATA_IN => FIFO_12_DATA_IN, + FIFO_13_DATA_IN => FIFO_13_DATA_IN, + FIFO_14_DATA_IN => FIFO_14_DATA_IN, + FIFO_15_DATA_IN => FIFO_15_DATA_IN, + FIFO_WE_IN => FIFO_WE_IN, + FIFO_DONE_IN => FIFO_DONE_IN, + DBG_BSM_OUT => DBG_BSM_OUT, + DBG_OUT => DBG_OUT + ); + +-- Generate the clock +THE_CLOCK_GEN: process +begin + clk_in <= '0'; wait for 5 ns; + clk_in <= '1'; wait for 5 ns; +end process THE_CLOCK_GEN; + +-- The real testbench +THE_TESTBENCH_PROC: process +variable LOOP_I: integer; +begin + -- Setup signals + reset_in <= '0'; + module_in <= "000"; + sector_in <= "111"; + ipu_number_in <= x"0000"; + ipu_information_in <= x"00"; + ipu_start_readout_in <= '0'; + ipu_read_in <= '0'; + dhdr_data_in <= x"01234567"; + dhdr_length_in <= x"0000"; + dhdr_store_in <= '0'; + fifo_start_in <= '0'; + fifo_we_in <= x"0000"; + fifo_done_in <= '0'; + fifo_0_data_in <= (others => '0'); + fifo_1_data_in <= (others => '0'); + fifo_2_data_in <= (others => '0'); + fifo_3_data_in <= (others => '0'); + fifo_4_data_in <= (others => '0'); + fifo_5_data_in <= (others => '0'); + fifo_6_data_in <= (others => '0'); + fifo_7_data_in <= (others => '0'); + fifo_8_data_in <= (others => '0'); + fifo_9_data_in <= (others => '0'); + fifo_10_data_in <= (others => '0'); + fifo_11_data_in <= (others => '0'); + fifo_12_data_in <= (others => '0'); + fifo_13_data_in <= (others => '0'); + fifo_14_data_in <= (others => '0'); + fifo_15_data_in <= (others => '0'); + + wait for 20 ns; + + -- Do a reset + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- test may start here + + -- Data is coming from processing stage + -- Start of event + wait until rising_edge(clk_in); + fifo_start_in <= '1'; + wait until rising_edge(clk_in); + fifo_start_in <= '0'; + wait until rising_edge(clk_in); + + -- Fill data buffers + wait until rising_edge(clk_in); + fifo_we_in <= b"1111_1111_1111_1111"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_1111"; + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0001_1110"; + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0010_1101"; + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0011_1100"; + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0100_1011"; + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0101_1010"; + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0110_1001"; + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0111_1000"; + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1000_0111"; + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1111_0000"; + wait until rising_edge(clk_in); + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; + fifo_we_in(0) <= '0'; + wait until rising_edge(clk_in); + + wait until rising_edge(clk_in); + + -- Final stage, counter values setting + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + fifo_0_data_in(37 downto 27) <= "10000000001"; -- "10000000011"; -- 3 + fifo_1_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + fifo_2_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + fifo_3_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + fifo_4_data_in(37 downto 27) <= "10000000001"; -- "10000000101"; -- 5 + fifo_5_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + fifo_6_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + fifo_7_data_in(37 downto 27) <= "10000000001"; -- "10000000111"; -- 7 + fifo_8_data_in(37 downto 27) <= "10000000001"; -- "10000000001"; -- 1 + fifo_9_data_in(37 downto 27) <= "10000000001"; -- "10000000010"; -- 2 + fifo_10_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + fifo_11_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + fifo_12_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + fifo_13_data_in(37 downto 27) <= "10000000001"; -- "10000001000"; -- 8 + fifo_14_data_in(37 downto 27) <= "10000000001"; -- "10000000111"; -- 7 + fifo_15_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- Event (0) DHDR + wait until rising_edge(clk_in); + dhdr_data_in <= x"1abbcccc"; + dhdr_length_in <= x"0010"; + dhdr_store_in <= '1'; + fifo_done_in <= '1'; + wait until rising_edge(clk_in); + dhdr_store_in <= '0'; + fifo_done_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + + -- IPU request + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + ipu_number_in <= x"cccc"; + ipu_information_in <= x"ff"; + ipu_start_readout_in <= '1'; + wait until rising_edge(clk_in); + + + -- wait for statemachine to react + -- transfer DHDR + wait until rising_edge(ipu_dataready_out); + wait until rising_edge(clk_in); + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + ipu_read_in <= '1'; + wait until rising_edge(ipu_readout_finished_out); + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + ipu_start_readout_in <= '0'; + + wait; + + + + + + + + + + + ------------------------------------------------------------------------ + ------------------------------------------------------------------------ + + -- wait for statemachine to react + -- DHDR + wait until rising_edge(ipu_dataready_out); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + + DATA_LOOP: for LOOP_I in 34 downto 0 loop + -- one data word + wait until rising_edge(ipu_dataready_out); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + end loop DATA_LOOP; + + + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- Stay a while, stay forever.... wuhahahahaha + wait; +end process THE_TESTBENCH_PROC; + + +END; + diff --git a/src/tb_ipu_fifo_stage_OLD.vhd b/src/tb_ipu_fifo_stage_OLD.vhd new file mode 100644 index 0000000..3d3aa2e --- /dev/null +++ b/src/tb_ipu_fifo_stage_OLD.vhd @@ -0,0 +1,449 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +library work; +use work.adcmv3_components.all; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT ipu_fifo_stage + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + SECTOR_IN : IN std_logic_vector(2 downto 0); + MODULE_IN : IN std_logic_vector(2 downto 0); + IPU_NUMBER_IN : IN std_logic_vector(15 downto 0); + IPU_INFORMATION_IN : IN std_logic_vector(7 downto 0); + IPU_START_READOUT_IN : IN std_logic; + IPU_READ_IN : IN std_logic; + DHDR_DATA_IN : IN std_logic_vector(31 downto 0); + DHDR_LENGTH_IN : IN std_logic_vector(15 downto 0); + DHDR_STORE_IN : IN std_logic; + FIFO_START_IN : IN std_logic; + FIFO_0_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_1_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_2_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_3_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_4_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_5_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_6_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_7_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_8_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_9_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_10_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_11_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_12_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_13_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_14_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_15_DATA_IN : IN std_logic_vector(39 downto 0); + FIFO_WE_IN : IN std_logic_vector(15 downto 0); + FIFO_DONE_IN : IN std_logic; + IPU_DATA_OUT : OUT std_logic_vector(31 downto 0); + IPU_DATAREADY_OUT : OUT std_logic; + IPU_READOUT_FINISHED_OUT : OUT std_logic; + IPU_LENGTH_OUT : OUT std_logic_vector(15 downto 0); + IPU_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); + DBG_BSM_OUT : OUT std_logic_vector(7 downto 0); + DBG_OUT : OUT std_logic_vector(63 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL SECTOR_IN : std_logic_vector(2 downto 0); + SIGNAL MODULE_IN : std_logic_vector(2 downto 0); + SIGNAL IPU_NUMBER_IN : std_logic_vector(15 downto 0); + SIGNAL IPU_INFORMATION_IN : std_logic_vector(7 downto 0); + SIGNAL IPU_START_READOUT_IN : std_logic; + SIGNAL IPU_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL IPU_DATAREADY_OUT : std_logic; + SIGNAL IPU_READOUT_FINISHED_OUT : std_logic; + SIGNAL IPU_READ_IN : std_logic; + SIGNAL IPU_LENGTH_OUT : std_logic_vector(15 downto 0); + SIGNAL IPU_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); + SIGNAL DHDR_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL DHDR_LENGTH_IN : std_logic_vector(15 downto 0); + SIGNAL DHDR_STORE_IN : std_logic; + SIGNAL FIFO_START_IN : std_logic; + SIGNAL FIFO_0_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_1_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_2_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_3_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_4_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_5_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_6_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_7_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_8_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_9_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_10_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_11_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_12_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_13_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_14_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_15_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL FIFO_WE_IN : std_logic_vector(15 downto 0); + SIGNAL FIFO_DONE_IN : std_logic; + SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0); + SIGNAL DBG_OUT : std_logic_vector(63 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: ipu_fifo_stage PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SECTOR_IN => SECTOR_IN, + MODULE_IN => MODULE_IN, + IPU_NUMBER_IN => IPU_NUMBER_IN, + IPU_INFORMATION_IN => IPU_INFORMATION_IN, + IPU_START_READOUT_IN => IPU_START_READOUT_IN, + IPU_DATA_OUT => IPU_DATA_OUT, + IPU_DATAREADY_OUT => IPU_DATAREADY_OUT, + IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_OUT, + IPU_READ_IN => IPU_READ_IN, + IPU_LENGTH_OUT => IPU_LENGTH_OUT, + IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT, + DHDR_DATA_IN => DHDR_DATA_IN, + DHDR_LENGTH_IN => DHDR_LENGTH_IN, + DHDR_STORE_IN => DHDR_STORE_IN, + FIFO_START_IN => FIFO_START_IN, + FIFO_0_DATA_IN => FIFO_0_DATA_IN, + FIFO_1_DATA_IN => FIFO_1_DATA_IN, + FIFO_2_DATA_IN => FIFO_2_DATA_IN, + FIFO_3_DATA_IN => FIFO_3_DATA_IN, + FIFO_4_DATA_IN => FIFO_4_DATA_IN, + FIFO_5_DATA_IN => FIFO_5_DATA_IN, + FIFO_6_DATA_IN => FIFO_6_DATA_IN, + FIFO_7_DATA_IN => FIFO_7_DATA_IN, + FIFO_8_DATA_IN => FIFO_8_DATA_IN, + FIFO_9_DATA_IN => FIFO_9_DATA_IN, + FIFO_10_DATA_IN => FIFO_10_DATA_IN, + FIFO_11_DATA_IN => FIFO_11_DATA_IN, + FIFO_12_DATA_IN => FIFO_12_DATA_IN, + FIFO_13_DATA_IN => FIFO_13_DATA_IN, + FIFO_14_DATA_IN => FIFO_14_DATA_IN, + FIFO_15_DATA_IN => FIFO_15_DATA_IN, + FIFO_WE_IN => FIFO_WE_IN, + FIFO_DONE_IN => FIFO_DONE_IN, + DBG_BSM_OUT => DBG_BSM_OUT, + DBG_OUT => DBG_OUT + ); + +-- Generate the clock +THE_CLOCK_GEN: process +begin + clk_in <= '0'; wait for 5 ns; + clk_in <= '1'; wait for 5 ns; +end process THE_CLOCK_GEN; + +-- The real testbench +THE_TESTBENCH_PROC: process +variable LOOP_I: integer; +begin + -- Setup signals + reset_in <= '0'; + module_in <= "000"; + sector_in <= "111"; + ipu_number_in <= x"0000"; + ipu_information_in <= x"00"; + ipu_start_readout_in <= '0'; + ipu_read_in <= '0'; + dhdr_data_in <= x"01234567"; + dhdr_length_in <= x"0000"; + dhdr_store_in <= '0'; + fifo_start_in <= '0'; + fifo_we_in <= x"0000"; + fifo_done_in <= '0'; + fifo_0_data_in <= (others => '0'); + fifo_1_data_in <= (others => '0'); + fifo_2_data_in <= (others => '0'); + fifo_3_data_in <= (others => '0'); + fifo_4_data_in <= (others => '0'); + fifo_5_data_in <= (others => '0'); + fifo_6_data_in <= (others => '0'); + fifo_7_data_in <= (others => '0'); + fifo_8_data_in <= (others => '0'); + fifo_9_data_in <= (others => '0'); + fifo_10_data_in <= (others => '0'); + fifo_11_data_in <= (others => '0'); + fifo_12_data_in <= (others => '0'); + fifo_13_data_in <= (others => '0'); + fifo_14_data_in <= (others => '0'); + fifo_15_data_in <= (others => '0'); + + wait for 20 ns; + + -- Do a reset + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- test may start here + + -- Data is coming from processing stage + -- Start of event + wait until rising_edge(clk_in); + fifo_start_in <= '1'; + wait until rising_edge(clk_in); + fifo_start_in <= '0'; + wait until rising_edge(clk_in); + + -- Fill data buffers + -- FIFO 0 - 3 data words + wait until rising_edge(clk_in); + fifo_we_in(0) <= '1'; + fifo_0_data_in(26 downto 0) <= b"111_111_0000000_00_0000_0001_0001"; + wait until rising_edge(clk_in); + fifo_0_data_in(26 downto 0) <= b"111_111_0000001_00_0000_0010_0010"; + wait until rising_edge(clk_in); + fifo_0_data_in(26 downto 0) <= b"111_111_0000010_00_0000_0011_0011"; + wait until rising_edge(clk_in); + fifo_0_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000"; + fifo_we_in(0) <= '0'; + wait until rising_edge(clk_in); + + -- FIFO 4 - 5 data words + wait until rising_edge(clk_in); + fifo_we_in(4) <= '1'; + fifo_4_data_in(26 downto 0) <= b"111_111_0000000_00_0100_0001_0001"; + wait until rising_edge(clk_in); + fifo_4_data_in(26 downto 0) <= b"111_111_0000001_00_0100_0010_0010"; + wait until rising_edge(clk_in); + fifo_4_data_in(26 downto 0) <= b"111_111_0000010_00_0100_0011_0011"; + wait until rising_edge(clk_in); + fifo_4_data_in(26 downto 0) <= b"111_111_0000011_00_0100_0100_0100"; + wait until rising_edge(clk_in); + fifo_4_data_in(26 downto 0) <= b"111_111_0000100_00_0100_0101_0101"; + wait until rising_edge(clk_in); + fifo_4_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000"; + fifo_we_in(4) <= '0'; + wait until rising_edge(clk_in); + + -- FIFO 7 - 7 data words + wait until rising_edge(clk_in); + fifo_we_in(7) <= '1'; + fifo_7_data_in(26 downto 0) <= b"111_111_0000000_00_0111_0001_0001"; + wait until rising_edge(clk_in); + fifo_7_data_in(26 downto 0) <= b"111_111_0000001_00_0111_0010_0010"; + wait until rising_edge(clk_in); + fifo_7_data_in(26 downto 0) <= b"111_111_0000010_00_0111_0011_0011"; + wait until rising_edge(clk_in); + fifo_7_data_in(26 downto 0) <= b"111_111_0000011_00_0111_0100_0100"; + wait until rising_edge(clk_in); + fifo_7_data_in(26 downto 0) <= b"111_111_0000100_00_0111_0101_0101"; + wait until rising_edge(clk_in); + fifo_7_data_in(26 downto 0) <= b"111_111_0000101_00_0111_0110_0110"; + wait until rising_edge(clk_in); + fifo_7_data_in(26 downto 0) <= b"111_111_0000110_00_0111_0111_0111"; + wait until rising_edge(clk_in); + fifo_7_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000"; + fifo_we_in(7) <= '0'; + wait until rising_edge(clk_in); + + -- FIFO 8 - 1 data words + wait until rising_edge(clk_in); + fifo_we_in(8) <= '1'; + fifo_8_data_in(26 downto 0) <= b"111_111_0000000_00_1000_0001_0001"; + wait until rising_edge(clk_in); + fifo_8_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000"; + fifo_we_in(8) <= '0'; + wait until rising_edge(clk_in); + + -- FIFO 9 - 2 data words + wait until rising_edge(clk_in); + fifo_we_in(9) <= '1'; + fifo_9_data_in(26 downto 0) <= b"111_111_0000000_00_1001_0001_0001"; + wait until rising_edge(clk_in); + fifo_9_data_in(26 downto 0) <= b"111_111_0000001_00_1001_0010_0010"; + wait until rising_edge(clk_in); + fifo_9_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000"; + fifo_we_in(9) <= '0'; + wait until rising_edge(clk_in); + + -- FIFO 13 - 8 data words + wait until rising_edge(clk_in); + fifo_we_in(13) <= '1'; + fifo_13_data_in(26 downto 0) <= b"111_111_0000000_00_1101_0001_0001"; + wait until rising_edge(clk_in); + fifo_13_data_in(26 downto 0) <= b"111_111_0000001_00_1101_0010_0010"; + wait until rising_edge(clk_in); + fifo_13_data_in(26 downto 0) <= b"111_111_0000010_00_1101_0011_0011"; + wait until rising_edge(clk_in); + fifo_13_data_in(26 downto 0) <= b"111_111_0000011_00_1101_0100_0100"; + wait until rising_edge(clk_in); + fifo_13_data_in(26 downto 0) <= b"111_111_0000100_00_1101_0101_0101"; + wait until rising_edge(clk_in); + fifo_13_data_in(26 downto 0) <= b"111_111_0000101_00_1101_0110_0110"; + wait until rising_edge(clk_in); + fifo_13_data_in(26 downto 0) <= b"111_111_0000110_00_1101_0111_0111"; + wait until rising_edge(clk_in); + fifo_13_data_in(26 downto 0) <= b"111_111_0000111_00_1101_1000_1000"; + wait until rising_edge(clk_in); + fifo_13_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000"; + fifo_we_in(13) <= '0'; + wait until rising_edge(clk_in); + + -- FIFO 14 - 7 data words + wait until rising_edge(clk_in); + fifo_we_in(14) <= '1'; + fifo_14_data_in(26 downto 0) <= b"111_111_0000000_00_1110_0001_0001"; + wait until rising_edge(clk_in); + fifo_14_data_in(26 downto 0) <= b"111_111_0000001_00_1110_0010_0010"; + wait until rising_edge(clk_in); + fifo_14_data_in(26 downto 0) <= b"111_111_0000010_00_1110_0011_0011"; + wait until rising_edge(clk_in); + fifo_14_data_in(26 downto 0) <= b"111_111_0000011_00_1110_0100_0100"; + wait until rising_edge(clk_in); + fifo_14_data_in(26 downto 0) <= b"111_111_0000100_00_1110_0101_0101"; + wait until rising_edge(clk_in); + fifo_14_data_in(26 downto 0) <= b"111_111_0000101_00_1110_0110_0110"; + wait until rising_edge(clk_in); + fifo_14_data_in(26 downto 0) <= b"111_111_0000110_00_1110_0111_0111"; + wait until rising_edge(clk_in); + fifo_14_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000"; + fifo_we_in(14) <= '0'; + wait until rising_edge(clk_in); + + -- Final stage, counter values setting + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + fifo_0_data_in(37 downto 27) <= "10000000010"; -- "10000000011"; -- 3 + fifo_1_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid + fifo_2_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid + fifo_3_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid + fifo_4_data_in(37 downto 27) <= "10000000100"; -- "10000000101"; -- 5 + fifo_5_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid + fifo_6_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid + fifo_7_data_in(37 downto 27) <= "10000000110"; -- "10000000111"; -- 7 + fifo_8_data_in(37 downto 27) <= "10000000000"; -- "10000000001"; -- 1 + fifo_9_data_in(37 downto 27) <= "10000000001"; -- "10000000010"; -- 2 + fifo_10_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid + fifo_11_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid + fifo_12_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid + fifo_13_data_in(37 downto 27) <= "10000000111"; -- "10000001000"; -- 8 + fifo_14_data_in(37 downto 27) <= "10000000110"; -- "10000000111"; -- 7 + fifo_15_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- Event (0) DHDR + wait until rising_edge(clk_in); + dhdr_data_in <= x"1abbcccc"; + dhdr_length_in <= x"0021"; + dhdr_store_in <= '1'; + fifo_done_in <= '1'; + wait until rising_edge(clk_in); + dhdr_store_in <= '0'; + fifo_done_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + + -- IPU request + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + ipu_number_in <= x"cccc"; + ipu_information_in <= x"ff"; + ipu_start_readout_in <= '1'; + wait until rising_edge(clk_in); + + + -- wait for statemachine to react + -- transfer DHDR + wait until rising_edge(ipu_dataready_out); + wait until rising_edge(clk_in); + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + ipu_read_in <= '1'; + wait until rising_edge(ipu_readout_finished_out); + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + ipu_start_readout_in <= '0'; + + wait; + + + + + + + + + + + ------------------------------------------------------------------------ + ------------------------------------------------------------------------ + + -- wait for statemachine to react + -- DHDR + wait until rising_edge(ipu_dataready_out); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + + DATA_LOOP: for LOOP_I in 34 downto 0 loop + -- one data word + wait until rising_edge(ipu_dataready_out); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); + ipu_read_in <= '1'; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + end loop DATA_LOOP; + + + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- Stay a while, stay forever.... wuhahahahaha + wait; +end process THE_TESTBENCH_PROC; + + +END; + diff --git a/src/tb_logic_analyzer.vhd b/src/tb_logic_analyzer.vhd new file mode 100644 index 0000000..a76bcc4 --- /dev/null +++ b/src/tb_logic_analyzer.vhd @@ -0,0 +1,148 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT logic_analyzer + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + ARM_IN : IN std_logic; + TRG_IN : IN std_logic; + MAX_SAMPLE_IN : IN std_logic_vector(9 downto 0); + SM_ADDR_OUT : OUT std_logic_vector(9 downto 0); + SM_CE_OUT : OUT std_logic; + SM_WE_OUT : OUT std_logic; + CLEAR_OUT : OUT std_logic; + RUN_OUT : OUT std_logic; + SAMPLE_OUT : OUT std_logic; + READY_OUT : OUT std_logic; + LAST_OUT : OUT std_logic; + BSM_OUT : OUT std_logic_vector(3 downto 0); + STAT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL ARM_IN : std_logic; + SIGNAL TRG_IN : std_logic; + SIGNAL MAX_SAMPLE_IN : std_logic_vector(9 downto 0); + SIGNAL SM_ADDR_OUT : std_logic_vector(9 downto 0); + SIGNAL SM_CE_OUT : std_logic; + SIGNAL SM_WE_OUT : std_logic; + SIGNAL CLEAR_OUT : std_logic; + SIGNAL RUN_OUT : std_logic; + SIGNAL SAMPLE_OUT : std_logic; + SIGNAL READY_OUT : std_logic; + SIGNAL LAST_OUT : std_logic; + SIGNAL BSM_OUT : std_logic_vector(3 downto 0); + SIGNAL STAT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: logic_analyzer PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + ARM_IN => ARM_IN, + TRG_IN => TRG_IN, + MAX_SAMPLE_IN => MAX_SAMPLE_IN, + SM_ADDR_OUT => SM_ADDR_OUT, + SM_CE_OUT => SM_CE_OUT, + SM_WE_OUT => SM_WE_OUT, + CLEAR_OUT => CLEAR_OUT, + RUN_OUT => RUN_OUT, + SAMPLE_OUT => SAMPLE_OUT, + READY_OUT => READY_OUT, + LAST_OUT => LAST_OUT, + BSM_OUT => BSM_OUT, + STAT => STAT + ); + + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + trg_in <= '0'; + arm_in <= '0'; + max_sample_in <= b"00_0000_1000"; + wait for 100 ns; + + -- Reset all + reset_in <= '1'; + wait for 100 ns; + reset_in <= '0'; + wait for 400 ns; + + -- Tests may start now + -- arm the machine + wait until rising_edge(clk_in); + arm_in <= '1'; + wait until rising_edge(clk_in); + arm_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- wait for memory clear + wait until rising_edge(run_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- trigger it + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trg_in <= '1'; + wait until rising_edge(clk_in); + trg_in <= '0'; + wait until rising_edge(clk_in); + + -- wait for end of cycle + wait until rising_edge(last_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 200 ns; + + -- retrigger + max_sample_in <= b"00_0000_1111"; + wait until rising_edge(clk_in); + arm_in <= '1'; + wait until rising_edge(clk_in); + arm_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- wait for memory clear + wait until rising_edge(run_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- trigger it + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trg_in <= '1'; + wait until rising_edge(clk_in); + trg_in <= '0'; + wait until rising_edge(clk_in); + + + -- Stay a while, stay forever! + wait; +end process THE_TEST_BENCH; + +END; diff --git a/src/tb_max_data.vhd b/src/tb_max_data.vhd new file mode 100644 index 0000000..70c93e7 --- /dev/null +++ b/src/tb_max_data.vhd @@ -0,0 +1,88 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT max_data + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + TODO_3_IN : IN std_logic_vector(3 downto 0); + TODO_2_IN : IN std_logic_vector(3 downto 0); + TODO_1_IN : IN std_logic_vector(3 downto 0); + TODO_0_IN : IN std_logic_vector(3 downto 0); + TODO_MAX_OUT : OUT std_logic_vector(3 downto 0); + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL TODO_3_IN : std_logic_vector(3 downto 0); + SIGNAL TODO_2_IN : std_logic_vector(3 downto 0); + SIGNAL TODO_1_IN : std_logic_vector(3 downto 0); + SIGNAL TODO_0_IN : std_logic_vector(3 downto 0); + SIGNAL TODO_MAX_OUT : std_logic_vector(3 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: max_data PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TODO_3_IN => TODO_3_IN, + TODO_2_IN => TODO_2_IN, + TODO_1_IN => TODO_1_IN, + TODO_0_IN => TODO_0_IN, + TODO_MAX_OUT => TODO_MAX_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + todo_3_in <= x"0"; + todo_2_in <= x"5"; + todo_1_in <= x"0"; + todo_0_in <= x"7"; + + -- Sync reset + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 140 ns; + + -- Tests may start now + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + todo_3_in <= x"0"; + todo_2_in <= x"1"; + todo_1_in <= x"f"; + todo_0_in <= x"c"; + + + -- Stay a while, stay forever.... + wait; +end process THE_TEST_BENCH; + + +END; diff --git a/src/tb_mult_3x8.vhd b/src/tb_mult_3x8.vhd new file mode 100644 index 0000000..b9ad321 --- /dev/null +++ b/src/tb_mult_3x8.vhd @@ -0,0 +1,125 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +library work; +use work.adcmv3_components.all; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT mult_3x8 is + PORT( CLOCK : in std_logic; + CLKEN : in std_logic; + ACLR : in std_logic; + DATAA : in std_logic_vector(2 downto 0); + DATAB : in std_logic_vector(7 downto 0); + RESULT : out std_logic_vector(10 downto 0) + ); + END COMPONENT; + + SIGNAL CLOCK : std_logic; + SIGNAL CLKEN : std_logic; + SIGNAL ACLR : std_logic; + SIGNAL DATAA : std_logic_vector(2 downto 0); + SIGNAL DATAB : std_logic_vector(7 downto 0); + SIGNAL RESULT : std_logic_vector(10 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: mult_3x8 PORT MAP( + CLOCK => CLOCK, + CLKEN => CLKEN, + ACLR => ACLR, + DATAA => DATAA, + DATAB => DATAB, + RESULT => RESULT + ); + +-- Generate the clock +THE_CLOCK_GEN: process +begin + clock <= '0'; wait for 5 ns; + clock <= '1'; wait for 5 ns; +end process THE_CLOCK_GEN; + +-- The real testbench +THE_TESTBENCH_PROC: process +begin + -- Setup signals + aclr <= '0'; + clken <= '1'; + dataa <= b"000"; + datab <= b"0000_0000"; + + wait for 20 ns; + + -- Do a reset + wait until rising_edge(clock); + aclr <= '1'; + wait until rising_edge(clock); + wait until rising_edge(clock); + aclr <= '0'; + wait until rising_edge(clock); + wait until rising_edge(clock); + + -- test may start here + wait until rising_edge(clock); + dataa <= b"000"; + datab <= x"81"; + wait until rising_edge(clock); + wait until rising_edge(clock); + + wait until rising_edge(clock); + dataa <= b"001"; + datab <= x"81"; + wait until rising_edge(clock); + wait until rising_edge(clock); + + wait until rising_edge(clock); + dataa <= b"010"; + datab <= x"81"; + wait until rising_edge(clock); + wait until rising_edge(clock); + + wait until rising_edge(clock); + dataa <= b"011"; + datab <= x"81"; + wait until rising_edge(clock); + wait until rising_edge(clock); + + wait until rising_edge(clock); + dataa <= b"100"; + datab <= x"81"; + wait until rising_edge(clock); + wait until rising_edge(clock); + + wait until rising_edge(clock); + dataa <= b"101"; + datab <= x"81"; + wait until rising_edge(clock); + wait until rising_edge(clock); + + wait until rising_edge(clock); + dataa <= b"110"; + datab <= x"81"; + wait until rising_edge(clock); + wait until rising_edge(clock); + + wait until rising_edge(clock); + dataa <= b"111"; + datab <= x"81"; + wait until rising_edge(clock); + wait until rising_edge(clock); + + -- Stay a while, stay forever.... wuhahahahaha + wait; +end process THE_TESTBENCH_PROC; + + +END; + + diff --git a/src/tb_mult_3x8_tmpl.vhd b/src/tb_mult_3x8_tmpl.vhd new file mode 100644 index 0000000..4e92e9b --- /dev/null +++ b/src/tb_mult_3x8_tmpl.vhd @@ -0,0 +1,72 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component mult_3x8 + port (Clock: in std_logic; ClkEn: in std_logic; + Aclr: in std_logic; DataA : in std_logic_vector(2 downto 0); + DataB : in std_logic_vector(7 downto 0); + Result : out std_logic_vector(10 downto 0) + ); + end component; + + signal Clock: std_logic := '0'; + signal ClkEn: std_logic := '0'; + signal Aclr: std_logic := '0'; + signal DataA : std_logic_vector(2 downto 0) := (others => '0'); + signal DataB : std_logic_vector(7 downto 0) := (others => '0'); + signal Result : std_logic_vector(10 downto 0); +begin + u1 : mult_3x8 + port map (Clock => Clock, ClkEn => ClkEn, Aclr => Aclr, DataA => DataA, + DataB => DataB, Result => Result + ); + + Clock <= not Clock after 5.00 ns; + + process + + begin + ClkEn <= '1' ; + wait; + end process; + + process + + begin + Aclr <= '1' ; + wait for 100 ns; + Aclr <= '0' ; + wait; + end process; + + process + + begin + DataA <= (others => '0') ; + for i in 0 to 200 loop + wait until Clock'event and Clock = '1'; + DataA <= DataA + '1' after 1 ns; + end loop; + wait; + end process; + + process + + begin + DataB <= (others => '0') ; + for i in 0 to 200 loop + wait until Clock'event and Clock = '1'; + DataB <= DataB + '1' after 1 ns; + end loop; + wait; + end process; + +end architecture test; diff --git a/src/tb_my_sbuf.vhd b/src/tb_my_sbuf.vhd new file mode 100644 index 0000000..35e5255 --- /dev/null +++ b/src/tb_my_sbuf.vhd @@ -0,0 +1,112 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT my_sbuf + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + CLK_EN : IN std_logic; + COMB_DATAREADY_IN : IN std_logic; + COMB_READ_IN : IN std_logic; + COMB_DATA_IN : IN std_logic_vector(18 downto 0); + SYN_READ_IN : IN std_logic; + COMB_NEXT_READ_OUT : OUT std_logic; + SYN_DATAREADY_OUT : OUT std_logic; + SYN_DATA_OUT : OUT std_logic_vector(18 downto 0); + DEBUG_OUT : OUT std_logic_vector(31 downto 0); + STAT_BUFFER : OUT std_logic + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL CLK_EN : std_logic; + SIGNAL COMB_DATAREADY_IN : std_logic; + SIGNAL COMB_NEXT_READ_OUT : std_logic; + SIGNAL COMB_READ_IN : std_logic; + SIGNAL COMB_DATA_IN : std_logic_vector(18 downto 0); + SIGNAL SYN_DATAREADY_OUT : std_logic; + SIGNAL SYN_DATA_OUT : std_logic_vector(18 downto 0); + SIGNAL SYN_READ_IN : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + SIGNAL STAT_BUFFER : std_logic; + +BEGIN + +-- Please check and add your generic clause manually + uut: my_sbuf PORT MAP( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => COMB_DATAREADY_IN, + COMB_NEXT_READ_OUT => COMB_NEXT_READ_OUT, + COMB_READ_IN => COMB_READ_IN, + COMB_DATA_IN => COMB_DATA_IN, + SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, + SYN_DATA_OUT => SYN_DATA_OUT, + SYN_READ_IN => SYN_READ_IN, + DEBUG_OUT => DEBUG_OUT, + STAT_BUFFER => STAT_BUFFER + ); + +THE_CLOCK_GEN: process +begin + clk <= '1'; wait for 5.0 ns; + clk <= '0'; wait for 5.0 ns; +end process THE_CLOCK_GEN; + +THE_TESTBENCH_PROC: process +begin + -- Setup signals + reset <= '0'; + clk_en <= '1'; + comb_dataready_in <= '0'; + comb_read_in <= '0'; + comb_data_in <= b"000_0000_0000_0000_0000"; + syn_read_in <= '0'; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait until rising_edge(clk); + + -- Tests may begin now + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_read_in <= '1'; + comb_data_in <= b"100_0000_0000_0000_0000"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0001"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0010"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0011"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0100"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0101"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + comb_read_in <= '0'; + + wait until rising_edge(clk); + syn_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + syn_read_in <= '0'; + + -- Stay a while... stay FOREVER!!! MUHAHAHAHA! + wait; + +end process THE_TESTBENCH_PROC; + +END; diff --git a/src/tb_onewire_master.vhd b/src/tb_onewire_master.vhd new file mode 100644 index 0000000..ecdc96a --- /dev/null +++ b/src/tb_onewire_master.vhd @@ -0,0 +1,658 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +library work; +use work.trb_net_std.all; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT onewire_master + GENERIC( + CLK_PERIOD : integer := 10 --clk period in ns + ); + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + READOUT_ENABLE_IN : IN std_logic; + ONEWIRE : INOUT std_logic_vector(15 downto 0); + BP_ONEWIRE : INOUT std_logic; + BP_DATA_OUT : OUT std_logic_vector(15 downto 0); + DATA_OUT : OUT std_logic_vector(15 downto 0); + ADDR_OUT : OUT std_logic_vector(6 downto 0); + WRITE_OUT : OUT std_logic; + BUSY_OUT : OUT std_logic; + BSM_OUT : OUT std_logic_vector(7 downto 0); + STAT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL READOUT_ENABLE_IN : std_logic; + SIGNAL ONEWIRE : std_logic_vector(15 downto 0); + SIGNAL BP_ONEWIRE : std_logic; + SIGNAL BP_DATA_OUT : std_logic_vector(15 downto 0); + SIGNAL DATA_OUT : std_logic_vector(15 downto 0); + SIGNAL ADDR_OUT : std_logic_vector(6 downto 0); + SIGNAL WRITE_OUT : std_logic; + SIGNAL BUSY_OUT : std_logic; + SIGNAL BSM_OUT : std_logic_vector(7 downto 0); + SIGNAL STAT : std_logic_vector(15 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: onewire_master + GENERIC MAP( + CLK_PERIOD => 10 + ) + PORT MAP( + CLK => CLK, + RESET => RESET, + READOUT_ENABLE_IN => READOUT_ENABLE_IN, + ONEWIRE => ONEWIRE, + BP_ONEWIRE => BP_ONEWIRE, + BP_DATA_OUT => BP_DATA_OUT, + DATA_OUT => DATA_OUT, + ADDR_OUT => ADDR_OUT, + WRITE_OUT => WRITE_OUT, + BUSY_OUT => BUSY_OUT, + BSM_OUT => BSM_OUT, + STAT => STAT + ); + +THE_CLOCK_GEN: process +begin + clk <= '1'; wait for 5 ns; + clk <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + readout_enable_in <= '0'; + reset <= '0'; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- Reset all + wait for 10 ns; + reset <= '1'; + wait for 200 ns; + reset <= '0'; + + -- Tests may start now + wait for 1 us; + wait until rising_edge(clk); + readout_enable_in <= '1'; + wait until rising_edge(clk); + readout_enable_in <= '0'; + wait until rising_edge(clk); + + -- wait for reset pulse (READ_ID) + wait until falling_edge(onewire(0)); + wait until rising_edge(onewire(0)); + wait for 30 us; + onewire <= b"0000_0000_0000_0000"; + bp_onewire <= '0'; + wait for 120 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + + -- skip the command sequence + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + + -- serial number + -- bit 0 + wait until falling_edge(onewire(0)); + onewire <= x"fe80"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 1 + wait until falling_edge(onewire(0)); + onewire <= x"ef71"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 2 + wait until falling_edge(onewire(0)); + onewire <= x"d062"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 3 + wait until falling_edge(onewire(0)); + onewire <= x"c153"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 4 + wait until falling_edge(onewire(0)); + onewire <= x"b244"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 5 + wait until falling_edge(onewire(0)); + onewire <= x"a335"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 6 + wait until falling_edge(onewire(0)); + onewire <= x"9426"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 7 + wait until falling_edge(onewire(0)); + onewire <= x"8517"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 8 + wait until falling_edge(onewire(0)); + onewire <= x"7608"; + bp_onewire <= '1'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 9 + wait until falling_edge(onewire(0)); + onewire <= x"67f9"; + bp_onewire <= '1'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 10 + wait until falling_edge(onewire(0)); + onewire <= x"58ea"; + bp_onewire <= '1'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 11 + wait until falling_edge(onewire(0)); + onewire <= x"49db"; + bp_onewire <= '1'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 12 + wait until falling_edge(onewire(0)); + onewire <= x"3acc"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 13 + wait until falling_edge(onewire(0)); + onewire <= x"2bbd"; + bp_onewire <= '0'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 14 + wait until falling_edge(onewire(0)); + onewire <= x"1cae"; + bp_onewire <= '1'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 15 + wait until falling_edge(onewire(0)); + onewire <= x"0d9f"; + bp_onewire <= '1'; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + + -- bit 16 + wait until falling_edge(onewire(0)); + onewire <= x"dead"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 17 + wait until falling_edge(onewire(0)); + onewire <= x"beef"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 18 + wait until falling_edge(onewire(0)); + onewire <= x"affe"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 19 + wait until falling_edge(onewire(0)); + onewire <= x"d00f"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 20 + wait until falling_edge(onewire(0)); + onewire <= x"facc"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 21 + wait until falling_edge(onewire(0)); + onewire <= x"0123"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 22 + wait until falling_edge(onewire(0)); + onewire <= x"4567"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 23 + wait until falling_edge(onewire(0)); + onewire <= x"89ab"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 24 + wait until falling_edge(onewire(0)); + onewire <= x"cdef"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 25 + wait until falling_edge(onewire(0)); + onewire <= x"aaaa"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 26 + wait until falling_edge(onewire(0)); + onewire <= x"5555"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 27 + wait until falling_edge(onewire(0)); + onewire <= x"6271"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 28 + wait until falling_edge(onewire(0)); + onewire <= x"4711"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 29 + wait until falling_edge(onewire(0)); + onewire <= x"0666"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 30 + wait until falling_edge(onewire(0)); + onewire <= x"7550"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 31 + wait until falling_edge(onewire(0)); + onewire <= x"bacc"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + + -- bit 32 + wait until falling_edge(onewire(0)); + onewire <= x"0123"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 33 + wait until falling_edge(onewire(0)); + onewire <= x"4567"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 34 + wait until falling_edge(onewire(0)); + onewire <= x"89ab"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 35 + wait until falling_edge(onewire(0)); + onewire <= x"cdef"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 36 + wait until falling_edge(onewire(0)); + onewire <= x"0f1e"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 37 + wait until falling_edge(onewire(0)); + onewire <= x"2d3c"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 38 + wait until falling_edge(onewire(0)); + onewire <= x"4b5a"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 39 + wait until falling_edge(onewire(0)); + onewire <= x"6978"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 40 + wait until falling_edge(onewire(0)); + onewire <= x"8796"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 41 + wait until falling_edge(onewire(0)); + onewire <= x"a5b4"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 42 + wait until falling_edge(onewire(0)); + onewire <= x"c3d2"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 43 + wait until falling_edge(onewire(0)); + onewire <= x"e1f0"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 44 + wait until falling_edge(onewire(0)); + onewire <= x"fedc"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 45 + wait until falling_edge(onewire(0)); + onewire <= x"ba98"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 46 + wait until falling_edge(onewire(0)); + onewire <= x"7654"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 47 + wait until falling_edge(onewire(0)); + onewire <= x"3210"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + + -- bit 48 + wait until falling_edge(onewire(0)); + onewire <= x"fffe"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 49 + wait until falling_edge(onewire(0)); + onewire <= x"fffd"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 50 + wait until falling_edge(onewire(0)); + onewire <= x"fffb"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 51 + wait until falling_edge(onewire(0)); + onewire <= x"fff7"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 52 + wait until falling_edge(onewire(0)); + onewire <= x"ffef"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 53 + wait until falling_edge(onewire(0)); + onewire <= x"ffdf"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 54 + wait until falling_edge(onewire(0)); + onewire <= x"ffbf"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 55 + wait until falling_edge(onewire(0)); + onewire <= x"ff7f"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 56 + wait until falling_edge(onewire(0)); + onewire <= x"feff"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 57 + wait until falling_edge(onewire(0)); + onewire <= x"fdff"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 58 + wait until falling_edge(onewire(0)); + onewire <= x"fbff"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 59 + wait until falling_edge(onewire(0)); + onewire <= x"f7ff"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 60 + wait until falling_edge(onewire(0)); + onewire <= x"efff"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 61 + wait until falling_edge(onewire(0)); + onewire <= x"dfff"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 62 + wait until falling_edge(onewire(0)); + onewire <= x"bfff"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 63 + wait until falling_edge(onewire(0)); + onewire <= x"7fff"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + + -- wait for reset pulse (CONV_TEMP) + wait until falling_edge(onewire(0)); + wait until rising_edge(onewire(0)); + wait for 30 us; + onewire <= b"0000_0000_0000_0000"; + bp_onewire <= '0'; + wait for 120 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + + -- skip the command sequence + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + + -- wait for reset pulse (READ_TEMP) + wait until falling_edge(onewire(0)); + wait until rising_edge(onewire(0)); + wait for 30 us; + onewire <= b"0000_0000_0000_0000"; + bp_onewire <= '0'; + wait for 120 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + + -- skip the command sequence + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + wait until falling_edge(onewire(0)); + + -- temparature + -- bit 0 + wait until falling_edge(onewire(0)); + onewire <= x"4001"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 1 + wait until falling_edge(onewire(0)); + onewire <= x"5002"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 2 + wait until falling_edge(onewire(0)); + onewire <= x"6004"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 3 + wait until falling_edge(onewire(0)); + onewire <= x"7008"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 4 + wait until falling_edge(onewire(0)); + onewire <= x"8010"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 5 + wait until falling_edge(onewire(0)); + onewire <= x"9020"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 6 + wait until falling_edge(onewire(0)); + onewire <= x"a040"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 7 + wait until falling_edge(onewire(0)); + onewire <= x"b080"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 8 + wait until falling_edge(onewire(0)); + onewire <= x"c100"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 9 + wait until falling_edge(onewire(0)); + onewire <= x"d200"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 10 + wait until falling_edge(onewire(0)); + onewire <= x"e400"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + -- bit 11 + wait until falling_edge(onewire(0)); + onewire <= x"f800"; + wait for 30 us; + onewire <= (others => 'H'); + bp_onewire <= 'H'; + + -- Stay a while, stay forever. + wait; + +end process THE_TEST_BENCH; + + +END; \ No newline at end of file diff --git a/src/tb_onewire_spare_one_tmpl.vhd b/src/tb_onewire_spare_one_tmpl.vhd new file mode 100644 index 0000000..8a91575 --- /dev/null +++ b/src/tb_onewire_spare_one_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component onewire_spare_one + port (Address : in std_logic_vector(2 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(2 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : onewire_spare_one + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 11 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/src/tb_ped_corr_ctrl.vhd b/src/tb_ped_corr_ctrl.vhd new file mode 100644 index 0000000..f968586 --- /dev/null +++ b/src/tb_ped_corr_ctrl.vhd @@ -0,0 +1,1236 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT ped_corr_ctrl + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + EDS_DATA_IN : IN std_logic_vector(39 downto 0); + EDS_AVAIL_IN : IN std_logic; + EVT_TYPE_IN : IN std_logic_vector(2 downto 0); + BUF_TICK_IN : IN std_logic_vector(15 downto 0); + BUF_START_IN : IN std_logic_vector(15 downto 0); + BUF_0_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_1_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_2_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_3_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_4_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_5_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_6_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_7_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_8_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_9_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_10_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_11_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_12_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_13_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_14_DATA_IN : IN std_logic_vector(37 downto 0); + BUF_15_DATA_IN : IN std_logic_vector(37 downto 0); + PED_0_DATA_IN : IN std_logic_vector(17 downto 0); + PED_1_DATA_IN : IN std_logic_vector(17 downto 0); + PED_2_DATA_IN : IN std_logic_vector(17 downto 0); + PED_3_DATA_IN : IN std_logic_vector(17 downto 0); + PED_4_DATA_IN : IN std_logic_vector(17 downto 0); + PED_5_DATA_IN : IN std_logic_vector(17 downto 0); + PED_6_DATA_IN : IN std_logic_vector(17 downto 0); + PED_7_DATA_IN : IN std_logic_vector(17 downto 0); + PED_8_DATA_IN : IN std_logic_vector(17 downto 0); + PED_9_DATA_IN : IN std_logic_vector(17 downto 0); + PED_10_DATA_IN : IN std_logic_vector(17 downto 0); + PED_11_DATA_IN : IN std_logic_vector(17 downto 0); + PED_12_DATA_IN : IN std_logic_vector(17 downto 0); + PED_13_DATA_IN : IN std_logic_vector(17 downto 0); + PED_14_DATA_IN : IN std_logic_vector(17 downto 0); + PED_15_DATA_IN : IN std_logic_vector(17 downto 0); + THR_0_DATA_IN : IN std_logic_vector(17 downto 0); + THR_1_DATA_IN : IN std_logic_vector(17 downto 0); + THR_2_DATA_IN : IN std_logic_vector(17 downto 0); + THR_3_DATA_IN : IN std_logic_vector(17 downto 0); + THR_4_DATA_IN : IN std_logic_vector(17 downto 0); + THR_5_DATA_IN : IN std_logic_vector(17 downto 0); + THR_6_DATA_IN : IN std_logic_vector(17 downto 0); + THR_7_DATA_IN : IN std_logic_vector(17 downto 0); + THR_8_DATA_IN : IN std_logic_vector(17 downto 0); + THR_9_DATA_IN : IN std_logic_vector(17 downto 0); + THR_10_DATA_IN : IN std_logic_vector(17 downto 0); + THR_11_DATA_IN : IN std_logic_vector(17 downto 0); + THR_12_DATA_IN : IN std_logic_vector(17 downto 0); + THR_13_DATA_IN : IN std_logic_vector(17 downto 0); + THR_14_DATA_IN : IN std_logic_vector(17 downto 0); + THR_15_DATA_IN : IN std_logic_vector(17 downto 0); + EDS_DONE_OUT : OUT std_logic; + DHDR_DATA_OUT : OUT std_logic_vector(31 downto 0); + DHDR_LENGTH_OUT : OUT std_logic_vector(15 downto 0); + DHDR_STORE_OUT : OUT std_logic; + PED_ADDR_OUT : OUT std_logic_vector(6 downto 0); + THR_ADDR_OUT : OUT std_logic_vector(6 downto 0); + BUF_ADDR_OUT : OUT std_logic_vector(6 downto 0); + BUF_DONE_OUT : OUT std_logic; + FIFO_START_OUT : OUT std_logic; + FIFO_0_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_1_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_2_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_3_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_4_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_5_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_6_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_7_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_8_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_9_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_10_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_11_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_12_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_13_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_14_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_15_DATA_OUT : OUT std_logic_vector(39 downto 0); + FIFO_WE_OUT : OUT std_logic_vector(15 downto 0); + FIFO_DONE_OUT : OUT std_logic; + DBG_BSM_OUT : OUT std_logic_vector(7 downto 0); + DBG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL EDS_DATA_IN : std_logic_vector(39 downto 0); + SIGNAL EDS_AVAIL_IN : std_logic; + SIGNAL EDS_DONE_OUT : std_logic; + SIGNAL DHDR_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL DHDR_LENGTH_OUT : std_logic_vector(15 downto 0); + SIGNAL DHDR_STORE_OUT : std_logic; + SIGNAL EVT_TYPE_IN : std_logic_vector(2 downto 0); + SIGNAL BUF_ADDR_OUT : std_logic_vector(6 downto 0); + SIGNAL BUF_DONE_OUT : std_logic; + SIGNAL BUF_TICK_IN : std_logic_vector(15 downto 0); + SIGNAL BUF_START_IN : std_logic_vector(15 downto 0); + SIGNAL BUF_0_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_1_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_2_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_3_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_4_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_5_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_6_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_7_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_8_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_9_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_10_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_11_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_12_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_13_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_14_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL BUF_15_DATA_IN : std_logic_vector(37 downto 0); + SIGNAL THR_ADDR_OUT : std_logic_vector(6 downto 0); + SIGNAL THR_0_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_1_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_2_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_3_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_4_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_5_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_6_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_7_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_8_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_9_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_10_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_11_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_12_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_13_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_14_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL THR_15_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_ADDR_OUT : std_logic_vector(6 downto 0); + SIGNAL PED_0_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_1_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_2_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_3_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_4_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_5_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_6_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_7_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_8_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_9_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_10_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_11_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_12_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_13_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_14_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL PED_15_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL FIFO_START_OUT : std_logic; + SIGNAL FIFO_0_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_1_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_2_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_3_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_4_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_5_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_6_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_7_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_8_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_9_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_10_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_11_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_12_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_13_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_14_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_15_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL FIFO_WE_OUT : std_logic_vector(15 downto 0); + SIGNAL FIFO_DONE_OUT : std_logic; + SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0); + SIGNAL DBG_OUT : std_logic_vector(15 downto 0); + + + SIGNAL BUF_ADDR : std_logic_vector(6 downto 0); + SIGNAL PED_ADDR : std_logic_vector(6 downto 0); + SIGNAL THR_ADDR : std_logic_vector(6 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: ped_corr_ctrl PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + EDS_DATA_IN => EDS_DATA_IN, + EDS_AVAIL_IN => EDS_AVAIL_IN, + EDS_DONE_OUT => EDS_DONE_OUT, + DHDR_DATA_OUT => DHDR_DATA_OUT, + DHDR_LENGTH_OUT => DHDR_LENGTH_OUT, + DHDR_STORE_OUT => DHDR_STORE_OUT, + EVT_TYPE_IN => EVT_TYPE_IN, + BUF_ADDR_OUT => BUF_ADDR_OUT, + BUF_DONE_OUT => BUF_DONE_OUT, + BUF_TICK_IN => BUF_TICK_IN, + BUF_START_IN => BUF_START_IN, + BUF_0_DATA_IN => BUF_0_DATA_IN, + BUF_1_DATA_IN => BUF_1_DATA_IN, + BUF_2_DATA_IN => BUF_2_DATA_IN, + BUF_3_DATA_IN => BUF_3_DATA_IN, + BUF_4_DATA_IN => BUF_4_DATA_IN, + BUF_5_DATA_IN => BUF_5_DATA_IN, + BUF_6_DATA_IN => BUF_6_DATA_IN, + BUF_7_DATA_IN => BUF_7_DATA_IN, + BUF_8_DATA_IN => BUF_8_DATA_IN, + BUF_9_DATA_IN => BUF_9_DATA_IN, + BUF_10_DATA_IN => BUF_10_DATA_IN, + BUF_11_DATA_IN => BUF_11_DATA_IN, + BUF_12_DATA_IN => BUF_12_DATA_IN, + BUF_13_DATA_IN => BUF_13_DATA_IN, + BUF_14_DATA_IN => BUF_14_DATA_IN, + BUF_15_DATA_IN => BUF_15_DATA_IN, + PED_ADDR_OUT => PED_ADDR_OUT, + PED_0_DATA_IN => PED_0_DATA_IN, + PED_1_DATA_IN => PED_1_DATA_IN, + PED_2_DATA_IN => PED_2_DATA_IN, + PED_3_DATA_IN => PED_3_DATA_IN, + PED_4_DATA_IN => PED_4_DATA_IN, + PED_5_DATA_IN => PED_5_DATA_IN, + PED_6_DATA_IN => PED_6_DATA_IN, + PED_7_DATA_IN => PED_7_DATA_IN, + PED_8_DATA_IN => PED_8_DATA_IN, + PED_9_DATA_IN => PED_9_DATA_IN, + PED_10_DATA_IN => PED_10_DATA_IN, + PED_11_DATA_IN => PED_11_DATA_IN, + PED_12_DATA_IN => PED_12_DATA_IN, + PED_13_DATA_IN => PED_13_DATA_IN, + PED_14_DATA_IN => PED_14_DATA_IN, + PED_15_DATA_IN => PED_15_DATA_IN, + THR_ADDR_OUT => THR_ADDR_OUT, + THR_0_DATA_IN => THR_0_DATA_IN, + THR_1_DATA_IN => THR_1_DATA_IN, + THR_2_DATA_IN => THR_2_DATA_IN, + THR_3_DATA_IN => THR_3_DATA_IN, + THR_4_DATA_IN => THR_4_DATA_IN, + THR_5_DATA_IN => THR_5_DATA_IN, + THR_6_DATA_IN => THR_6_DATA_IN, + THR_7_DATA_IN => THR_7_DATA_IN, + THR_8_DATA_IN => THR_8_DATA_IN, + THR_9_DATA_IN => THR_9_DATA_IN, + THR_10_DATA_IN => THR_10_DATA_IN, + THR_11_DATA_IN => THR_11_DATA_IN, + THR_12_DATA_IN => THR_12_DATA_IN, + THR_13_DATA_IN => THR_13_DATA_IN, + THR_14_DATA_IN => THR_14_DATA_IN, + THR_15_DATA_IN => THR_15_DATA_IN, + FIFO_START_OUT => FIFO_START_OUT, + FIFO_0_DATA_OUT => FIFO_0_DATA_OUT, + FIFO_1_DATA_OUT => FIFO_1_DATA_OUT, + FIFO_2_DATA_OUT => FIFO_2_DATA_OUT, + FIFO_3_DATA_OUT => FIFO_3_DATA_OUT, + FIFO_4_DATA_OUT => FIFO_4_DATA_OUT, + FIFO_5_DATA_OUT => FIFO_5_DATA_OUT, + FIFO_6_DATA_OUT => FIFO_6_DATA_OUT, + FIFO_7_DATA_OUT => FIFO_7_DATA_OUT, + FIFO_8_DATA_OUT => FIFO_8_DATA_OUT, + FIFO_9_DATA_OUT => FIFO_9_DATA_OUT, + FIFO_10_DATA_OUT => FIFO_10_DATA_OUT, + FIFO_11_DATA_OUT => FIFO_11_DATA_OUT, + FIFO_12_DATA_OUT => FIFO_12_DATA_OUT, + FIFO_13_DATA_OUT => FIFO_13_DATA_OUT, + FIFO_14_DATA_OUT => FIFO_14_DATA_OUT, + FIFO_15_DATA_OUT => FIFO_15_DATA_OUT, + FIFO_WE_OUT => FIFO_WE_OUT, + FIFO_DONE_OUT => FIFO_DONE_OUT, + DBG_BSM_OUT => DBG_BSM_OUT, + DBG_OUT => DBG_OUT + ); + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +-- Delay the BUF and PED address reaction +THE_ADDR_DELAY: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + buf_addr <= buf_addr_out; + thr_addr <= thr_addr_out; + ped_addr <= ped_addr_out; + end if; +end process THE_ADDR_DELAY; + + +-- The real testbench +TESTBENCH: process +begin + -- Setup signal + reset_in <= '0'; + eds_data_in <= (others => '0'); + eds_avail_in <= '0'; + evt_type_in <= "000"; + buf_start_in <= (others => '0'); + buf_tick_in <= (others => '0'); + -- Buffer level information: 7 -> good, 6 -> broken, 5 -> ignore, rest LEVEL + buf_0_data_in(37 downto 30) <= x"80"; -- good + buf_1_data_in(37 downto 30) <= x"20"; -- ignore + buf_2_data_in(37 downto 30) <= x"20"; -- ignore + buf_3_data_in(37 downto 30) <= x"20"; -- ignore + buf_4_data_in(37 downto 30) <= x"40"; -- broken!!! + buf_5_data_in(37 downto 30) <= x"20"; -- ignore + buf_6_data_in(37 downto 30) <= x"20"; -- ignore + buf_7_data_in(37 downto 30) <= x"20"; -- ignore + buf_8_data_in(37 downto 30) <= x"20"; -- ignore + buf_9_data_in(37 downto 30) <= x"20"; -- ignore + buf_10_data_in(37 downto 30) <= x"20"; -- ignore + buf_11_data_in(37 downto 30) <= x"20"; -- ignore + buf_12_data_in(37 downto 30) <= x"20"; -- ignore + buf_13_data_in(37 downto 30) <= x"20"; -- ignore + buf_14_data_in(37 downto 30) <= x"20"; -- ignore + buf_15_data_in(37 downto 30) <= x"20"; -- ignore + -- Buffer frame information: 8 -> APV error, [7:0] row + buf_0_data_in(29 downto 18) <= x"011"; -- row 0x11, no error + buf_1_data_in(29 downto 18) <= x"0ee"; -- + buf_2_data_in(29 downto 18) <= x"0ee"; -- + buf_3_data_in(29 downto 18) <= x"0ee"; -- + buf_4_data_in(29 downto 18) <= x"0aa"; -- + buf_5_data_in(29 downto 18) <= x"0ee"; -- + buf_6_data_in(29 downto 18) <= x"0ee"; -- + buf_7_data_in(29 downto 18) <= x"0ee"; -- + buf_8_data_in(29 downto 18) <= x"0ee"; -- + buf_9_data_in(29 downto 18) <= x"0ee"; -- + buf_10_data_in(29 downto 18) <= x"0ee"; -- + buf_11_data_in(29 downto 18) <= x"0ee"; -- + buf_12_data_in(29 downto 18) <= x"0ee"; -- + buf_13_data_in(29 downto 18) <= x"0ee"; -- + buf_14_data_in(29 downto 18) <= x"0ee"; -- + buf_15_data_in(29 downto 18) <= x"0ee"; -- + -- Buffer data + buf_0_data_in(17 downto 14) <= x"0"; + buf_1_data_in(17 downto 14) <= x"0"; buf_1_data_in(13 downto 0) <= "00000000000000"; + buf_2_data_in(17 downto 14) <= x"0"; buf_2_data_in(13 downto 0) <= "00000000000000"; + buf_3_data_in(17 downto 14) <= x"0"; buf_3_data_in(13 downto 0) <= "00000000000000"; + buf_4_data_in(17 downto 14) <= x"0"; buf_4_data_in(13 downto 0) <= "00000000000000"; + buf_5_data_in(17 downto 14) <= x"0"; buf_5_data_in(13 downto 0) <= "00000000000000"; + buf_6_data_in(17 downto 14) <= x"0"; buf_6_data_in(13 downto 0) <= "00000000000000"; + buf_7_data_in(17 downto 14) <= x"0"; buf_7_data_in(13 downto 0) <= "00000000000000"; + buf_8_data_in(17 downto 14) <= x"0"; buf_8_data_in(13 downto 0) <= "00000000000000"; + buf_9_data_in(17 downto 14) <= x"0"; buf_9_data_in(13 downto 0) <= "00000000000000"; + buf_10_data_in(17 downto 14) <= x"0"; buf_10_data_in(13 downto 0) <= "00000000000000"; + buf_11_data_in(17 downto 14) <= x"0"; buf_11_data_in(13 downto 0) <= "00000000000000"; + buf_12_data_in(17 downto 14) <= x"0"; buf_12_data_in(13 downto 0) <= "00000000000000"; + buf_13_data_in(17 downto 14) <= x"0"; buf_13_data_in(13 downto 0) <= "00000000000000"; + buf_14_data_in(17 downto 14) <= x"0"; buf_14_data_in(13 downto 0) <= "00000000000000"; + buf_15_data_in(17 downto 14) <= x"0"; buf_15_data_in(13 downto 0) <= "00000000000000"; + -- Pedestal data +-- ped_0_data_in <= "00" & x"0000"; + ped_1_data_in <= "00" & x"0000"; + ped_2_data_in <= "00" & x"0000"; + ped_3_data_in <= "00" & x"0000"; + ped_4_data_in <= "00" & x"0000"; + ped_5_data_in <= "00" & x"0000"; + ped_6_data_in <= "00" & x"0000"; + ped_7_data_in <= "00" & x"0000"; + ped_8_data_in <= "00" & x"0000"; + ped_9_data_in <= "00" & x"0000"; + ped_10_data_in <= "00" & x"0000"; + ped_11_data_in <= "00" & x"0000"; + ped_12_data_in <= "00" & x"0000"; + ped_13_data_in <= "00" & x"0000"; + ped_14_data_in <= "00" & x"0000"; + ped_15_data_in <= "00" & x"0000"; + -- Threshold data +-- thr_0_data_in <= "00" & x"0000"; + thr_1_data_in <= "00" & x"0000"; + thr_2_data_in <= "00" & x"0000"; + thr_3_data_in <= "00" & x"0000"; + thr_4_data_in <= "00" & x"0000"; + thr_5_data_in <= "00" & x"0000"; + thr_6_data_in <= "00" & x"0000"; + thr_7_data_in <= "00" & x"0000"; + thr_8_data_in <= "00" & x"0000"; + thr_9_data_in <= "00" & x"0000"; + thr_10_data_in <= "00" & x"0000"; + thr_11_data_in <= "00" & x"0000"; + thr_12_data_in <= "00" & x"0000"; + thr_13_data_in <= "00" & x"0000"; + thr_14_data_in <= "00" & x"0000"; + thr_15_data_in <= "00" & x"0000"; + + -- Reset + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + + ---------------------------------------------------------------------------------------- + ---------------------------------------------------------------------------------------- + ---------------------------------------------------------------------------------------- + ---------------------------------------------------------------------------------------- + + ---------------------------------------------------------------- + -- "000" -> RAW128 + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "000"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee01"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"82"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"83"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + + ---------------------------------------------------------------- + -- "001" -> PED128 + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "001"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee11"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"82"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"83"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + ---------------------------------------------------------------- + -- "010" -> PED128THR + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "010"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee21"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"82"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"83"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + ---------------------------------------------------------------------------------------- + ---------------------------------------------------------------------------------------- + ---------------------------------------------------------------------------------------- + ---------------------------------------------------------------------------------------- + wait; + + -- Tests may start now + ---------------------------------------------------------------- + -- "000" -> RAW128 + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "000"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee01"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + ---------------------------------------------------------------- + -- "001" -> PED128 + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "001"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee01"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + ---------------------------------------------------------------- + -- "010" -> PED128THR + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "010"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee01"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + ---------------------------------------------------------------- + -- "100" -> NC64PED64 + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "100"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee01"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + ---------------------------------------------------------------- + -- "101" -> NC64 + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "101"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee01"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + ---------------------------------------------------------------- + -- "110" -> NC64GOOD + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "110"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee01"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + ---------------------------------------------------------------- + -- "111" -> NC64THR + ---------------------------------------------------------------- + wait until rising_edge(clk_in); + reset_in <= '1'; + evt_type_in <= "111"; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 55 ns; + wait until rising_edge(clk_in); + + -- EDS comes in + eds_data_in <= x"01abcdee01"; + wait until rising_edge(clk_in); + eds_avail_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + eds_avail_in <= '0'; + wait until rising_edge(clk_in); + + -- Buffer 0 becomes ready + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + buf_0_data_in(37 downto 30) <= x"81"; + + -- wait for first buffer + wait until rising_edge(buf_done_out); + wait for 300 ns; + wait until rising_edge(clk_in); + + + + + + + -- stay a while, stay forever! + wait; +end process TESTBENCH; + +-- Data faker for "APV 0"... +BUF_0_DATA_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + case buf_addr is + when "0000000" => buf_0_data_in(13 downto 0) <= "00" & x"44b"; + when "0000001" => buf_0_data_in(13 downto 0) <= "00" & x"474"; + when "0000010" => buf_0_data_in(13 downto 0) <= "00" & x"462"; + when "0000011" => buf_0_data_in(13 downto 0) <= "00" & x"45f"; +-- when "0000100" => buf_0_data_in(13 downto 0) <= "00" & x"44c"; + when "0000100" => buf_0_data_in(13 downto 0) <= "01" & x"111"; -- physical UNDERFLOW + when "0000101" => buf_0_data_in(13 downto 0) <= "00" & x"457"; + when "0000110" => buf_0_data_in(13 downto 0) <= "00" & x"476"; + when "0000111" => buf_0_data_in(13 downto 0) <= "00" & x"456"; + when "0001000" => buf_0_data_in(13 downto 0) <= "00" & x"450"; + when "0001001" => buf_0_data_in(13 downto 0) <= "00" & x"45c"; +-- when "0001010" => buf_0_data_in(13 downto 0) <= "00" & x"46b"; + when "0001010" => buf_0_data_in(13 downto 0) <= "10" & x"eee"; -- physical OVERFLOW + when "0001011" => buf_0_data_in(13 downto 0) <= "00" & x"461"; + when "0001100" => buf_0_data_in(13 downto 0) <= "00" & x"466"; + when "0001101" => buf_0_data_in(13 downto 0) <= "00" & x"449"; + when "0001110" => buf_0_data_in(13 downto 0) <= "00" & x"450"; + when "0001111" => buf_0_data_in(13 downto 0) <= "00" & x"451"; + when "0010000" => buf_0_data_in(13 downto 0) <= "00" & x"432"; +-- when "0010001" => buf_0_data_in(13 downto 0) <= "00" & x"459"; + when "0010001" => buf_0_data_in(13 downto 0) <= "01" & x"111"; -- correction UNDERFLOW + when "0010010" => buf_0_data_in(13 downto 0) <= "00" & x"45c"; + when "0010011" => buf_0_data_in(13 downto 0) <= "00" & x"430"; + when "0010100" => buf_0_data_in(13 downto 0) <= "00" & x"42f"; + when "0010101" => buf_0_data_in(13 downto 0) <= "00" & x"452"; + when "0010110" => buf_0_data_in(13 downto 0) <= "00" & x"43a"; +-- when "0010111" => buf_0_data_in(13 downto 0) <= "00" & x"431"; + when "0010111" => buf_0_data_in(13 downto 0) <= "10" & x"eee"; -- correction OVERFLOW + when "0011000" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; + when "0011001" => buf_0_data_in(13 downto 0) <= "00" & x"443"; + when "0011010" => buf_0_data_in(13 downto 0) <= "00" & x"424"; + when "0011011" => buf_0_data_in(13 downto 0) <= "00" & x"436"; + when "0011100" => buf_0_data_in(13 downto 0) <= "00" & x"45e"; + when "0011101" => buf_0_data_in(13 downto 0) <= "00" & x"453"; + when "0011110" => buf_0_data_in(13 downto 0) <= "00" & x"44c"; + when "0011111" => buf_0_data_in(13 downto 0) <= "00" & x"449"; + when "0100000" => buf_0_data_in(13 downto 0) <= "00" & x"40a"; + when "0100001" => buf_0_data_in(13 downto 0) <= "00" & x"43f"; +-- when "0100010" => buf_0_data_in(13 downto 0) <= "00" & x"411"; + when "0100010" => buf_0_data_in(13 downto 0) <= "00" & x"411"; -- physical OFF + when "0100011" => buf_0_data_in(13 downto 0) <= "00" & x"455"; + when "0100100" => buf_0_data_in(13 downto 0) <= "00" & x"44b"; + when "0100101" => buf_0_data_in(13 downto 0) <= "00" & x"431"; + when "0100110" => buf_0_data_in(13 downto 0) <= "00" & x"425"; + when "0100111" => buf_0_data_in(13 downto 0) <= "00" & x"44a"; + when "0101000" => buf_0_data_in(13 downto 0) <= "00" & x"442"; + when "0101001" => buf_0_data_in(13 downto 0) <= "00" & x"446"; + when "0101010" => buf_0_data_in(13 downto 0) <= "00" & x"43e"; + when "0101011" => buf_0_data_in(13 downto 0) <= "00" & x"441"; + when "0101100" => buf_0_data_in(13 downto 0) <= "00" & x"45b"; + when "0101101" => buf_0_data_in(13 downto 0) <= "00" & x"44e"; + when "0101110" => buf_0_data_in(13 downto 0) <= "00" & x"452"; +-- when "0101111" => buf_0_data_in(13 downto 0) <= "00" & x"469"; + when "0101111" => buf_0_data_in(13 downto 0) <= "00" & x"469"; -- correction OFF + when "0110000" => buf_0_data_in(13 downto 0) <= "00" & x"456"; + when "0110001" => buf_0_data_in(13 downto 0) <= "00" & x"45b"; + when "0110010" => buf_0_data_in(13 downto 0) <= "00" & x"482"; + when "0110011" => buf_0_data_in(13 downto 0) <= "00" & x"461"; + when "0110100" => buf_0_data_in(13 downto 0) <= "00" & x"444"; + when "0110101" => buf_0_data_in(13 downto 0) <= "00" & x"458"; + when "0110110" => buf_0_data_in(13 downto 0) <= "00" & x"446"; + when "0110111" => buf_0_data_in(13 downto 0) <= "00" & x"475"; + when "0111000" => buf_0_data_in(13 downto 0) <= "00" & x"447"; + when "0111001" => buf_0_data_in(13 downto 0) <= "00" & x"44f"; + when "0111010" => buf_0_data_in(13 downto 0) <= "00" & x"433"; + when "0111011" => buf_0_data_in(13 downto 0) <= "00" & x"470"; + when "0111100" => buf_0_data_in(13 downto 0) <= "00" & x"46d"; + when "0111101" => buf_0_data_in(13 downto 0) <= "00" & x"45e"; + when "0111110" => buf_0_data_in(13 downto 0) <= "00" & x"439"; + when "0111111" => buf_0_data_in(13 downto 0) <= "00" & x"45a"; + when "1000000" => buf_0_data_in(13 downto 0) <= "00" & x"43b"; + when "1000001" => buf_0_data_in(13 downto 0) <= "00" & x"42a"; + when "1000010" => buf_0_data_in(13 downto 0) <= "00" & x"430"; + when "1000011" => buf_0_data_in(13 downto 0) <= "00" & x"444"; + when "1000100" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; + when "1000101" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; + when "1000110" => buf_0_data_in(13 downto 0) <= "00" & x"403"; + when "1000111" => buf_0_data_in(13 downto 0) <= "00" & x"429"; + when "1001000" => buf_0_data_in(13 downto 0) <= "00" & x"3f4"; + when "1001001" => buf_0_data_in(13 downto 0) <= "00" & x"41b"; + when "1001010" => buf_0_data_in(13 downto 0) <= "00" & x"42f"; + when "1001011" => buf_0_data_in(13 downto 0) <= "00" & x"434"; + when "1001100" => buf_0_data_in(13 downto 0) <= "00" & x"40a"; + when "1001101" => buf_0_data_in(13 downto 0) <= "00" & x"416"; + when "1001110" => buf_0_data_in(13 downto 0) <= "00" & x"412"; + when "1001111" => buf_0_data_in(13 downto 0) <= "00" & x"418"; + when "1010000" => buf_0_data_in(13 downto 0) <= "00" & x"411"; + when "1010001" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; + when "1010010" => buf_0_data_in(13 downto 0) <= "00" & x"4d6"; + when "1010011" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; + when "1010100" => buf_0_data_in(13 downto 0) <= "00" & x"3ec"; + when "1010101" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; + when "1010110" => buf_0_data_in(13 downto 0) <= "00" & x"419"; + when "1010111" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; + when "1011000" => buf_0_data_in(13 downto 0) <= "00" & x"3f1"; + when "1011001" => buf_0_data_in(13 downto 0) <= "00" & x"3fa"; + when "1011010" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; + when "1011011" => buf_0_data_in(13 downto 0) <= "00" & x"408"; + when "1011100" => buf_0_data_in(13 downto 0) <= "00" & x"3ee"; + when "1011101" => buf_0_data_in(13 downto 0) <= "00" & x"3fd"; + when "1011110" => buf_0_data_in(13 downto 0) <= "00" & x"41b"; + when "1011111" => buf_0_data_in(13 downto 0) <= "00" & x"3f3"; + when "1100000" => buf_0_data_in(13 downto 0) <= "00" & x"3b2"; + when "1100001" => buf_0_data_in(13 downto 0) <= "00" & x"3d6"; + when "1100010" => buf_0_data_in(13 downto 0) <= "00" & x"3f2"; + when "1100011" => buf_0_data_in(13 downto 0) <= "00" & x"3f2"; + when "1100100" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; + when "1100101" => buf_0_data_in(13 downto 0) <= "00" & x"3e4"; + when "1100110" => buf_0_data_in(13 downto 0) <= "00" & x"902"; + when "1100111" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; + when "1101000" => buf_0_data_in(13 downto 0) <= "00" & x"3d2"; + when "1101001" => buf_0_data_in(13 downto 0) <= "00" & x"3ef"; + when "1101010" => buf_0_data_in(13 downto 0) <= "00" & x"490"; + when "1101011" => buf_0_data_in(13 downto 0) <= "00" & x"402"; + when "1101100" => buf_0_data_in(13 downto 0) <= "00" & x"3bd"; + when "1101101" => buf_0_data_in(13 downto 0) <= "00" & x"3d1"; + when "1101110" => buf_0_data_in(13 downto 0) <= "00" & x"497"; + when "1101111" => buf_0_data_in(13 downto 0) <= "00" & x"3d2"; + when "1110000" => buf_0_data_in(13 downto 0) <= "00" & x"3b7"; + when "1110001" => buf_0_data_in(13 downto 0) <= "00" & x"3da"; + when "1110010" => buf_0_data_in(13 downto 0) <= "00" & x"4bd"; + when "1110011" => buf_0_data_in(13 downto 0) <= "00" & x"3c9"; + when "1110100" => buf_0_data_in(13 downto 0) <= "00" & x"3ba"; + when "1110101" => buf_0_data_in(13 downto 0) <= "00" & x"3c9"; + when "1110110" => buf_0_data_in(13 downto 0) <= "00" & x"4e9"; + when "1110111" => buf_0_data_in(13 downto 0) <= "00" & x"3cc"; + when "1111000" => buf_0_data_in(13 downto 0) <= "00" & x"3e4"; + when "1111001" => buf_0_data_in(13 downto 0) <= "00" & x"3b2"; + when "1111010" => buf_0_data_in(13 downto 0) <= "10" & x"edc"; -- real physical OVERFLOW + when "1111011" => buf_0_data_in(13 downto 0) <= "00" & x"3c4"; + when "1111100" => buf_0_data_in(13 downto 0) <= "00" & x"3e6"; + when "1111101" => buf_0_data_in(13 downto 0) <= "00" & x"3f0"; + when "1111110" => buf_0_data_in(13 downto 0) <= "00" & x"896"; + when "1111111" => buf_0_data_in(13 downto 0) <= "00" & x"402"; + when others => buf_0_data_in(13 downto 0) <= "00" & x"fff"; + end case; + end if; +end process BUF_0_DATA_PROC; + + +BUF_0_PED_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + case ped_addr is + when "0000000" => ped_0_data_in <= "00" & x"0485"; + when "0000001" => ped_0_data_in <= "00" & x"148b"; + when "0000010" => ped_0_data_in <= "00" & x"2466"; + when "0000011" => ped_0_data_in <= "00" & x"3479"; +-- when "0000100" => ped_0_data_in <= "00" & x"446e"; + when "0000100" => ped_0_data_in <= "00" & x"446e"; -- physical UNDERFLOW + when "0000101" => ped_0_data_in <= "00" & x"5470"; + when "0000110" => ped_0_data_in <= "00" & x"647c"; + when "0000111" => ped_0_data_in <= "00" & x"7472"; + when "0001000" => ped_0_data_in <= "00" & x"0472"; + when "0001001" => ped_0_data_in <= "00" & x"1478"; +-- when "0001010" => ped_0_data_in <= "00" & x"247f"; + when "0001010" => ped_0_data_in <= "00" & x"247f"; -- physical OVERFLOW + when "0001011" => ped_0_data_in <= "00" & x"3480"; + when "0001100" => ped_0_data_in <= "00" & x"4479"; + when "0001101" => ped_0_data_in <= "00" & x"5464"; + when "0001110" => ped_0_data_in <= "00" & x"645c"; + when "0001111" => ped_0_data_in <= "00" & x"7464"; + when "0010000" => ped_0_data_in <= "00" & x"045a"; +-- when "0010001" => ped_0_data_in <= "00" & x"146f"; + when "0010001" => ped_0_data_in <= "00" & x"146f"; -- correction UNDERFLOW + when "0010010" => ped_0_data_in <= "00" & x"245c"; + when "0010011" => ped_0_data_in <= "00" & x"3445"; + when "0010100" => ped_0_data_in <= "00" & x"4448"; + when "0010101" => ped_0_data_in <= "00" & x"546e"; + when "0010110" => ped_0_data_in <= "00" & x"6450"; +-- when "0010111" => ped_0_data_in <= "00" & x"7448"; + when "0010111" => ped_0_data_in <= "00" & x"7448"; -- correction OVERFLOW + when "0011000" => ped_0_data_in <= "00" & x"044d"; + when "0011001" => ped_0_data_in <= "00" & x"145c"; + when "0011010" => ped_0_data_in <= "00" & x"243b"; + when "0011011" => ped_0_data_in <= "00" & x"345a"; + when "0011100" => ped_0_data_in <= "00" & x"4469"; + when "0011101" => ped_0_data_in <= "00" & x"546f"; + when "0011110" => ped_0_data_in <= "00" & x"6455"; + when "0011111" => ped_0_data_in <= "00" & x"7463"; + when "0100000" => ped_0_data_in <= "00" & x"0429"; + when "0100001" => ped_0_data_in <= "00" & x"145b"; +-- when "0100010" => ped_0_data_in <= "00" & x"2435"; + when "0100010" => ped_0_data_in <= "01" & x"2435"; -- physical OFF + when "0100011" => ped_0_data_in <= "00" & x"346f"; + when "0100100" => ped_0_data_in <= "00" & x"4463"; + when "0100101" => ped_0_data_in <= "00" & x"5454"; + when "0100110" => ped_0_data_in <= "00" & x"6452"; + when "0100111" => ped_0_data_in <= "00" & x"746e"; + when "0101000" => ped_0_data_in <= "00" & x"0469"; + when "0101001" => ped_0_data_in <= "00" & x"1462"; + when "0101010" => ped_0_data_in <= "00" & x"2464"; + when "0101011" => ped_0_data_in <= "00" & x"345e"; + when "0101100" => ped_0_data_in <= "00" & x"4469"; + when "0101101" => ped_0_data_in <= "00" & x"5469"; + when "0101110" => ped_0_data_in <= "00" & x"646d"; +-- when "0101111" => ped_0_data_in <= "00" & x"7485"; + when "0101111" => ped_0_data_in <= "01" & x"7485"; -- correction OFF + when "0110000" => ped_0_data_in <= "00" & x"0478"; + when "0110001" => ped_0_data_in <= "00" & x"147d"; + when "0110010" => ped_0_data_in <= "00" & x"2468"; + when "0110011" => ped_0_data_in <= "00" & x"3480"; + when "0110100" => ped_0_data_in <= "00" & x"447d"; + when "0110101" => ped_0_data_in <= "00" & x"5480"; + when "0110110" => ped_0_data_in <= "00" & x"6468"; + when "0110111" => ped_0_data_in <= "00" & x"7496"; + when "0111000" => ped_0_data_in <= "00" & x"0471"; + when "0111001" => ped_0_data_in <= "00" & x"1474"; + when "0111010" => ped_0_data_in <= "00" & x"246b"; + when "0111011" => ped_0_data_in <= "00" & x"349b"; + when "0111100" => ped_0_data_in <= "00" & x"4499"; + when "0111101" => ped_0_data_in <= "00" & x"5484"; + when "0111110" => ped_0_data_in <= "00" & x"646d"; + when "0111111" => ped_0_data_in <= "00" & x"7486"; + when "1000000" => ped_0_data_in <= "00" & x"048e"; + when "1000001" => ped_0_data_in <= "00" & x"146e"; + when "1000010" => ped_0_data_in <= "00" & x"2488"; + when "1000011" => ped_0_data_in <= "00" & x"3491"; + when "1000100" => ped_0_data_in <= "00" & x"4487"; + when "1000101" => ped_0_data_in <= "00" & x"5476"; + when "1000110" => ped_0_data_in <= "00" & x"6453"; + when "1000111" => ped_0_data_in <= "00" & x"7484"; + when "1001000" => ped_0_data_in <= "00" & x"0452"; + when "1001001" => ped_0_data_in <= "00" & x"146f"; + when "1001010" => ped_0_data_in <= "00" & x"248d"; + when "1001011" => ped_0_data_in <= "00" & x"3486"; + when "1001100" => ped_0_data_in <= "00" & x"445c"; + when "1001101" => ped_0_data_in <= "00" & x"5475"; + when "1001110" => ped_0_data_in <= "00" & x"6476"; + when "1001111" => ped_0_data_in <= "00" & x"7475"; + when "1010000" => ped_0_data_in <= "00" & x"0472"; + when "1010001" => ped_0_data_in <= "00" & x"146f"; + when "1010010" => ped_0_data_in <= "00" & x"244c"; + when "1010011" => ped_0_data_in <= "00" & x"3479"; + when "1010100" => ped_0_data_in <= "00" & x"4469"; + when "1010101" => ped_0_data_in <= "00" & x"547f"; + when "1010110" => ped_0_data_in <= "00" & x"6478"; + when "1010111" => ped_0_data_in <= "00" & x"7478"; + when "1011000" => ped_0_data_in <= "00" & x"0472"; + when "1011001" => ped_0_data_in <= "00" & x"146c"; + when "1011010" => ped_0_data_in <= "00" & x"2478"; + when "1011011" => ped_0_data_in <= "00" & x"3481"; + when "1011100" => ped_0_data_in <= "00" & x"447a"; + when "1011101" => ped_0_data_in <= "00" & x"547f"; + when "1011110" => ped_0_data_in <= "00" & x"649f"; + when "1011111" => ped_0_data_in <= "00" & x"746f"; + when "1100000" => ped_0_data_in <= "00" & x"0443"; + when "1100001" => ped_0_data_in <= "00" & x"145d"; + when "1100010" => ped_0_data_in <= "00" & x"246f"; + when "1100011" => ped_0_data_in <= "00" & x"3482"; + when "1100100" => ped_0_data_in <= "00" & x"4498"; + when "1100101" => ped_0_data_in <= "00" & x"5483"; + when "1100110" => ped_0_data_in <= "00" & x"649b"; + when "1100111" => ped_0_data_in <= "00" & x"74a9"; + when "1101000" => ped_0_data_in <= "00" & x"0471"; + when "1101001" => ped_0_data_in <= "00" & x"1488"; + when "1101010" => ped_0_data_in <= "00" & x"249a"; + when "1101011" => ped_0_data_in <= "00" & x"349f"; + when "1101100" => ped_0_data_in <= "00" & x"4473"; + when "1101101" => ped_0_data_in <= "00" & x"5479"; + when "1101110" => ped_0_data_in <= "00" & x"648b"; + when "1101111" => ped_0_data_in <= "00" & x"747e"; + when "1110000" => ped_0_data_in <= "00" & x"0480"; + when "1110001" => ped_0_data_in <= "00" & x"1492"; + when "1110010" => ped_0_data_in <= "00" & x"2482"; + when "1110011" => ped_0_data_in <= "00" & x"3483"; + when "1110100" => ped_0_data_in <= "00" & x"447a"; + when "1110101" => ped_0_data_in <= "00" & x"548a"; + when "1110110" => ped_0_data_in <= "00" & x"6493"; + when "1110111" => ped_0_data_in <= "00" & x"7496"; + when "1111000" => ped_0_data_in <= "00" & x"0495"; + when "1111001" => ped_0_data_in <= "00" & x"1493"; + when "1111010" => ped_0_data_in <= "00" & x"2487"; -- real physical OVERFLOW + when "1111011" => ped_0_data_in <= "00" & x"3496"; + when "1111100" => ped_0_data_in <= "00" & x"449d"; + when "1111101" => ped_0_data_in <= "00" & x"54cb"; + when "1111110" => ped_0_data_in <= "00" & x"64b9"; + when "1111111" => ped_0_data_in <= "00" & x"74df"; + when others => ped_0_data_in <= "00" & x"ffff"; + end case; + end if; +end process BUF_0_PED_PROC; + + +-- Data faker for "APV 0"... +BUF_0_THR_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + case thr_addr is + when "0000000" => thr_0_data_in <= "00" & x"001e"; + when "0000001" => thr_0_data_in <= "00" & x"100f"; + when "0000010" => thr_0_data_in <= "00" & x"201e"; + when "0000011" => thr_0_data_in <= "00" & x"300f"; + when "0000100" => thr_0_data_in <= "00" & x"401e"; + when "0000101" => thr_0_data_in <= "00" & x"500f"; + when "0000110" => thr_0_data_in <= "00" & x"601b"; + when "0000111" => thr_0_data_in <= "00" & x"700f"; + when "0001000" => thr_0_data_in <= "00" & x"001e"; + when "0001001" => thr_0_data_in <= "00" & x"100f"; + when "0001010" => thr_0_data_in <= "00" & x"201e"; + when "0001011" => thr_0_data_in <= "00" & x"300f"; + when "0001100" => thr_0_data_in <= "00" & x"4021"; + when "0001101" => thr_0_data_in <= "00" & x"500f"; + when "0001110" => thr_0_data_in <= "00" & x"601e"; + when "0001111" => thr_0_data_in <= "00" & x"700f"; + when "0010000" => thr_0_data_in <= "00" & x"001e"; + when "0010001" => thr_0_data_in <= "00" & x"100f"; + when "0010010" => thr_0_data_in <= "00" & x"2021"; + when "0010011" => thr_0_data_in <= "00" & x"300f"; + when "0010100" => thr_0_data_in <= "00" & x"402d"; + when "0010101" => thr_0_data_in <= "00" & x"500f"; + when "0010110" => thr_0_data_in <= "00" & x"602a"; + when "0010111" => thr_0_data_in <= "00" & x"700f"; + when "0011000" => thr_0_data_in <= "00" & x"001e"; + when "0011001" => thr_0_data_in <= "00" & x"100f"; + when "0011010" => thr_0_data_in <= "00" & x"2021"; + when "0011011" => thr_0_data_in <= "00" & x"300f"; + when "0011100" => thr_0_data_in <= "00" & x"401e"; + when "0011101" => thr_0_data_in <= "00" & x"500f"; + when "0011110" => thr_0_data_in <= "00" & x"601b"; + when "0011111" => thr_0_data_in <= "00" & x"700f"; + when "0100000" => thr_0_data_in <= "00" & x"001e"; + when "0100001" => thr_0_data_in <= "00" & x"100f"; + when "0100010" => thr_0_data_in <= "00" & x"201e"; + when "0100011" => thr_0_data_in <= "00" & x"300f"; + when "0100100" => thr_0_data_in <= "00" & x"4021"; + when "0100101" => thr_0_data_in <= "00" & x"500f"; + when "0100110" => thr_0_data_in <= "00" & x"601b"; + when "0100111" => thr_0_data_in <= "00" & x"700f"; + when "0101000" => thr_0_data_in <= "00" & x"001b"; + when "0101001" => thr_0_data_in <= "00" & x"100f"; + when "0101010" => thr_0_data_in <= "00" & x"201e"; + when "0101011" => thr_0_data_in <= "00" & x"300f"; + when "0101100" => thr_0_data_in <= "00" & x"401e"; + when "0101101" => thr_0_data_in <= "00" & x"500f"; + when "0101110" => thr_0_data_in <= "00" & x"601b"; + when "0101111" => thr_0_data_in <= "00" & x"700f"; + when "0110000" => thr_0_data_in <= "00" & x"000f"; + when "0110001" => thr_0_data_in <= "00" & x"100f"; + when "0110010" => thr_0_data_in <= "00" & x"201e"; + when "0110011" => thr_0_data_in <= "00" & x"300f"; + when "0110100" => thr_0_data_in <= "00" & x"4021"; + when "0110101" => thr_0_data_in <= "00" & x"500f"; + when "0110110" => thr_0_data_in <= "00" & x"601e"; + when "0110111" => thr_0_data_in <= "00" & x"700f"; + when "0111000" => thr_0_data_in <= "00" & x"0021"; + when "0111001" => thr_0_data_in <= "00" & x"100f"; + when "0111010" => thr_0_data_in <= "00" & x"2027"; + when "0111011" => thr_0_data_in <= "00" & x"300f"; + when "0111100" => thr_0_data_in <= "00" & x"400f"; + when "0111101" => thr_0_data_in <= "00" & x"500f"; + when "0111110" => thr_0_data_in <= "00" & x"6048"; + when "0111111" => thr_0_data_in <= "00" & x"700f"; + when "1000000" => thr_0_data_in <= "00" & x"0024"; + when "1000001" => thr_0_data_in <= "00" & x"100f"; + when "1000010" => thr_0_data_in <= "00" & x"2024"; + when "1000011" => thr_0_data_in <= "00" & x"300f"; + when "1000100" => thr_0_data_in <= "00" & x"4021"; + when "1000101" => thr_0_data_in <= "00" & x"500f"; + when "1000110" => thr_0_data_in <= "00" & x"6021"; + when "1000111" => thr_0_data_in <= "00" & x"700f"; + when "1001000" => thr_0_data_in <= "00" & x"001e"; + when "1001001" => thr_0_data_in <= "00" & x"100f"; + when "1001010" => thr_0_data_in <= "00" & x"2021"; + when "1001011" => thr_0_data_in <= "00" & x"300f"; + when "1001100" => thr_0_data_in <= "00" & x"4021"; + when "1001101" => thr_0_data_in <= "00" & x"500f"; + when "1001110" => thr_0_data_in <= "00" & x"601b"; + when "1001111" => thr_0_data_in <= "00" & x"700f"; + when "1010000" => thr_0_data_in <= "00" & x"001b"; + when "1010001" => thr_0_data_in <= "00" & x"100f"; + when "1010010" => thr_0_data_in <= "00" & x"201e"; + when "1010011" => thr_0_data_in <= "00" & x"300f"; + when "1010100" => thr_0_data_in <= "00" & x"4021"; + when "1010101" => thr_0_data_in <= "00" & x"500f"; + when "1010110" => thr_0_data_in <= "00" & x"601e"; + when "1010111" => thr_0_data_in <= "00" & x"700f"; + when "1011000" => thr_0_data_in <= "00" & x"001e"; + when "1011001" => thr_0_data_in <= "00" & x"100f"; + when "1011010" => thr_0_data_in <= "00" & x"2021"; + when "1011011" => thr_0_data_in <= "00" & x"300f"; + when "1011100" => thr_0_data_in <= "00" & x"4021"; + when "1011101" => thr_0_data_in <= "00" & x"500f"; + when "1011110" => thr_0_data_in <= "00" & x"601e"; + when "1011111" => thr_0_data_in <= "00" & x"700f"; + when "1100000" => thr_0_data_in <= "00" & x"001e"; + when "1100001" => thr_0_data_in <= "00" & x"100f"; + when "1100010" => thr_0_data_in <= "00" & x"2021"; + when "1100011" => thr_0_data_in <= "00" & x"300f"; + when "1100100" => thr_0_data_in <= "00" & x"4021"; + when "1100101" => thr_0_data_in <= "00" & x"500f"; + when "1100110" => thr_0_data_in <= "00" & x"601e"; + when "1100111" => thr_0_data_in <= "00" & x"700f"; + when "1101000" => thr_0_data_in <= "00" & x"0021"; + when "1101001" => thr_0_data_in <= "00" & x"100f"; + when "1101010" => thr_0_data_in <= "00" & x"2027"; + when "1101011" => thr_0_data_in <= "00" & x"300f"; + when "1101100" => thr_0_data_in <= "00" & x"4024"; + when "1101101" => thr_0_data_in <= "00" & x"500f"; + when "1101110" => thr_0_data_in <= "00" & x"6021"; + when "1101111" => thr_0_data_in <= "00" & x"700f"; + when "1110000" => thr_0_data_in <= "00" & x"001e"; + when "1110001" => thr_0_data_in <= "00" & x"100f"; + when "1110010" => thr_0_data_in <= "00" & x"2024"; + when "1110011" => thr_0_data_in <= "00" & x"300f"; + when "1110100" => thr_0_data_in <= "00" & x"400f"; + when "1110101" => thr_0_data_in <= "00" & x"500f"; + when "1110110" => thr_0_data_in <= "00" & x"601e"; + when "1110111" => thr_0_data_in <= "00" & x"700f"; + when "1111000" => thr_0_data_in <= "00" & x"001e"; + when "1111001" => thr_0_data_in <= "00" & x"100f"; + when "1111010" => thr_0_data_in <= "00" & x"2024"; + when "1111011" => thr_0_data_in <= "00" & x"300f"; + when "1111100" => thr_0_data_in <= "00" & x"4021"; + when "1111101" => thr_0_data_in <= "00" & x"500f"; + when "1111110" => thr_0_data_in <= "00" & x"6021"; + when "1111111" => thr_0_data_in <= "00" & x"700f"; + when others => thr_0_data_in <= "00" & x"ffff"; + end case; + end if; +end process BUF_0_THR_PROC; + +END; diff --git a/src/tb_pulse_stretch.vhd b/src/tb_pulse_stretch.vhd new file mode 100644 index 0000000..c68635f --- /dev/null +++ b/src/tb_pulse_stretch.vhd @@ -0,0 +1,70 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT pulse_stretch + PORT( + RESET_IN : IN std_logic; + CLK_IN : IN std_logic; + START_IN : IN std_logic; + PULSE_OUT : OUT std_logic; + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL RESET_IN : std_logic; + SIGNAL CLK_IN : std_logic; + SIGNAL START_IN : std_logic; + SIGNAL PULSE_OUT : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: pulse_stretch PORT MAP( + RESET_IN => RESET_IN, + CLK_IN => CLK_IN, + START_IN => START_IN, + PULSE_OUT => PULSE_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + start_in <= '0'; + + -- Sync reset + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 140 ns; + + -- Tests may start now + wait until rising_edge(clk_in); + start_in <= '1'; + wait until rising_edge(clk_in); + start_in <= '0'; + wait until rising_edge(clk_in); + + + + -- Stay a while, stay forever.... + wait; +end process THE_TEST_BENCH; + +END; diff --git a/src/tb_raw_buf_stage.vhd b/src/tb_raw_buf_stage.vhd new file mode 100644 index 0000000..9197bfc --- /dev/null +++ b/src/tb_raw_buf_stage.vhd @@ -0,0 +1,260 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT raw_buf_stage + PORT( + CLK_IN : IN std_logic; + RESET_APV_IN : IN std_logic; + RESET_IN : IN std_logic; + APV_SYNC_IN : IN std_logic; + APV_FRAME_REQD_IN : IN std_logic; + ADC0_PLL_LOCK_IN : IN std_logic; + ADC0_CLK40M_IN : IN std_logic; + ADC0_0_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_1_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_2_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_3_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_4_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_5_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_6_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_7_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_PLL_LOCK_IN : IN std_logic; + ADC1_CLK40M_IN : IN std_logic; + ADC1_0_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_1_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_2_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_3_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_4_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_5_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_6_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_7_DATA_IN : IN std_logic_vector(11 downto 0); + MAX_TRG_NUM_IN : IN std_logic_vector(3 downto 0); + BIT_LOW_IN : IN std_logic_vector(11 downto 0); + BIT_HIGH_IN : IN std_logic_vector(11 downto 0); + FL_LOW_IN : IN std_logic_vector(11 downto 0); + FL_HIGH_IN : IN std_logic_vector(11 downto 0); + APV_ON_IN : IN std_logic_vector(15 downto 0); + BUF_ADDR_IN : IN std_logic_vector(6 downto 0); + BUF_DONE_IN : IN std_logic; + BUF_FULL_OUT : OUT std_logic; + BUF_TICK_OUT : OUT std_logic_vector(15 downto 0); + BUF_START_OUT : OUT std_logic_vector(15 downto 0); + BUF_READY_OUT : OUT std_logic_vector(15 downto 0); + BUF_0_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_1_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_2_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_3_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_4_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_5_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_6_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_7_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_8_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_9_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_10_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_11_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_12_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_13_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_14_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_15_DATA_OUT : OUT std_logic_vector(37 downto 0); + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_APV_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL APV_SYNC_IN : std_logic; + SIGNAL APV_FRAME_REQD_IN : std_logic; + SIGNAL ADC0_PLL_LOCK_IN : std_logic; + SIGNAL ADC0_CLK40M_IN : std_logic; + SIGNAL ADC0_0_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_1_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_2_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_3_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_4_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_5_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_6_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_7_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_PLL_LOCK_IN : std_logic; + SIGNAL ADC1_CLK40M_IN : std_logic; + SIGNAL ADC1_0_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_1_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_2_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_3_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_4_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_5_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_6_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_7_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL MAX_TRG_NUM_IN : std_logic_vector(3 downto 0); + SIGNAL BIT_LOW_IN : std_logic_vector(11 downto 0); + SIGNAL BIT_HIGH_IN : std_logic_vector(11 downto 0); + SIGNAL FL_LOW_IN : std_logic_vector(11 downto 0); + SIGNAL FL_HIGH_IN : std_logic_vector(11 downto 0); + SIGNAL APV_ON_IN : std_logic_vector(15 downto 0); + SIGNAL BUF_FULL_OUT : std_logic; + SIGNAL BUF_ADDR_IN : std_logic_vector(6 downto 0); + SIGNAL BUF_DONE_IN : std_logic; + SIGNAL BUF_TICK_OUT : std_logic_vector(15 downto 0); + SIGNAL BUF_START_OUT : std_logic_vector(15 downto 0); + SIGNAL BUF_READY_OUT : std_logic_vector(15 downto 0); + SIGNAL BUF_0_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_1_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_2_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_3_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_4_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_5_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_6_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_7_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_8_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_9_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_10_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_11_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_12_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_13_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_14_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_15_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: raw_buf_stage PORT MAP( + CLK_IN => CLK_IN, + RESET_APV_IN => RESET_APV_IN, + RESET_IN => RESET_IN, + APV_SYNC_IN => APV_SYNC_IN, + APV_FRAME_REQD_IN => APV_FRAME_REQD_IN, + ADC0_PLL_LOCK_IN => ADC0_PLL_LOCK_IN, + ADC0_CLK40M_IN => ADC0_CLK40M_IN, + ADC0_0_DATA_IN => ADC0_0_DATA_IN, + ADC0_1_DATA_IN => ADC0_1_DATA_IN, + ADC0_2_DATA_IN => ADC0_2_DATA_IN, + ADC0_3_DATA_IN => ADC0_3_DATA_IN, + ADC0_4_DATA_IN => ADC0_4_DATA_IN, + ADC0_5_DATA_IN => ADC0_5_DATA_IN, + ADC0_6_DATA_IN => ADC0_6_DATA_IN, + ADC0_7_DATA_IN => ADC0_7_DATA_IN, + ADC1_PLL_LOCK_IN => ADC1_PLL_LOCK_IN, + ADC1_CLK40M_IN => ADC1_CLK40M_IN, + ADC1_0_DATA_IN => ADC1_0_DATA_IN, + ADC1_1_DATA_IN => ADC1_1_DATA_IN, + ADC1_2_DATA_IN => ADC1_2_DATA_IN, + ADC1_3_DATA_IN => ADC1_3_DATA_IN, + ADC1_4_DATA_IN => ADC1_4_DATA_IN, + ADC1_5_DATA_IN => ADC1_5_DATA_IN, + ADC1_6_DATA_IN => ADC1_6_DATA_IN, + ADC1_7_DATA_IN => ADC1_7_DATA_IN, + MAX_TRG_NUM_IN => MAX_TRG_NUM_IN, + BIT_LOW_IN => BIT_LOW_IN, + BIT_HIGH_IN => BIT_HIGH_IN, + FL_LOW_IN => FL_LOW_IN, + FL_HIGH_IN => FL_HIGH_IN, + APV_ON_IN => APV_ON_IN, + BUF_FULL_OUT => BUF_FULL_OUT, + BUF_ADDR_IN => BUF_ADDR_IN, + BUF_DONE_IN => BUF_DONE_IN, + BUF_TICK_OUT => BUF_TICK_OUT, + BUF_START_OUT => BUF_START_OUT, + BUF_READY_OUT => BUF_READY_OUT, + BUF_0_DATA_OUT => BUF_0_DATA_OUT, + BUF_1_DATA_OUT => BUF_1_DATA_OUT, + BUF_2_DATA_OUT => BUF_2_DATA_OUT, + BUF_3_DATA_OUT => BUF_3_DATA_OUT, + BUF_4_DATA_OUT => BUF_4_DATA_OUT, + BUF_5_DATA_OUT => BUF_5_DATA_OUT, + BUF_6_DATA_OUT => BUF_6_DATA_OUT, + BUF_7_DATA_OUT => BUF_7_DATA_OUT, + BUF_8_DATA_OUT => BUF_8_DATA_OUT, + BUF_9_DATA_OUT => BUF_9_DATA_OUT, + BUF_10_DATA_OUT => BUF_10_DATA_OUT, + BUF_11_DATA_OUT => BUF_11_DATA_OUT, + BUF_12_DATA_OUT => BUF_12_DATA_OUT, + BUF_13_DATA_OUT => BUF_13_DATA_OUT, + BUF_14_DATA_OUT => BUF_14_DATA_OUT, + BUF_15_DATA_OUT => BUF_15_DATA_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +-- ADC0 and ADC1 40MHz clock +THE_ADC_CLOCK_GEN: process +begin + adc0_clk40m_in <= '1'; adc1_clk40m_in <= '1'; wait for 12.5 ns; + adc0_clk40m_in <= '0'; adc1_clk40m_in <= '0'; wait for 12.5 ns; +end process THE_ADC_CLOCK_GEN; + +-- 100MHz system clock +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + reset_apv_in <= '0'; + apv_sync_in <= '0'; + apv_frame_reqd_in <= '0'; + adc0_pll_lock_in <= '0'; + adc0_0_data_in <= x"000"; + adc0_1_data_in <= x"800"; + adc0_2_data_in <= x"800"; + adc0_3_data_in <= x"800"; + adc0_4_data_in <= x"800"; + adc0_5_data_in <= x"800"; + adc0_6_data_in <= x"800"; + adc0_7_data_in <= x"800"; + adc1_pll_lock_in <= '0'; + adc1_0_data_in <= x"800"; + adc1_1_data_in <= x"800"; + adc1_2_data_in <= x"800"; + adc1_3_data_in <= x"800"; + adc1_4_data_in <= x"800"; + adc1_5_data_in <= x"800"; + adc1_6_data_in <= x"800"; + adc1_7_data_in <= x"800"; + max_trg_num_in <= x"1"; + bit_low_in <= x"200"; + bit_high_in <= x"e00"; + fl_low_in <= x"780"; + fl_high_in <= x"880"; + apv_on_in <= x"0001"; + buf_addr_in <= (others => '0'); + buf_done_in <= '0'; + wait for 100 ns; + + -- Reset all + wait until rising_edge(clk_in); + reset_in <= '1'; + reset_apv_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '0'; + reset_apv_in <= '0'; + wait for 100 ns; + + wait until rising_edge(clk_in); + adc0_pll_lock_in <= '1'; + adc1_pll_lock_in <= '1'; + wait until rising_edge(clk_in); + + -- Tests may start now + wait until rising_edge(clk_in); + + + + + + -- Stay a while, stay forever! + wait; + +end process THE_TEST_BENCH; + +END; diff --git a/src/tb_raw_buf_stage_new.vhd b/src/tb_raw_buf_stage_new.vhd new file mode 100755 index 0000000..771f30f --- /dev/null +++ b/src/tb_raw_buf_stage_new.vhd @@ -0,0 +1,260 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT raw_buf_stage_new + PORT( + CLK_IN : IN std_logic; + RESET_APV_IN : IN std_logic; + RESET_IN : IN std_logic; + APV_SYNC_IN : IN std_logic; + APV_FRAME_REQD_IN : IN std_logic; + ADC0_PLL_LOCK_IN : IN std_logic; + ADC0_CLK40M_IN : IN std_logic; + ADC0_0_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_1_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_2_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_3_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_4_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_5_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_6_DATA_IN : IN std_logic_vector(11 downto 0); + ADC0_7_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_PLL_LOCK_IN : IN std_logic; + ADC1_CLK40M_IN : IN std_logic; + ADC1_0_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_1_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_2_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_3_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_4_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_5_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_6_DATA_IN : IN std_logic_vector(11 downto 0); + ADC1_7_DATA_IN : IN std_logic_vector(11 downto 0); + MAX_TRG_NUM_IN : IN std_logic_vector(3 downto 0); + BIT_LOW_IN : IN std_logic_vector(11 downto 0); + BIT_HIGH_IN : IN std_logic_vector(11 downto 0); + FL_LOW_IN : IN std_logic_vector(11 downto 0); + FL_HIGH_IN : IN std_logic_vector(11 downto 0); + APV_ON_IN : IN std_logic_vector(15 downto 0); + BUF_ADDR_IN : IN std_logic_vector(6 downto 0); + BUF_DONE_IN : IN std_logic; + BUF_FULL_OUT : OUT std_logic; + BUF_TICK_OUT : OUT std_logic_vector(15 downto 0); + BUF_START_OUT : OUT std_logic_vector(15 downto 0); + BUF_READY_OUT : OUT std_logic_vector(15 downto 0); + BUF_0_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_1_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_2_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_3_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_4_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_5_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_6_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_7_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_8_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_9_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_10_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_11_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_12_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_13_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_14_DATA_OUT : OUT std_logic_vector(37 downto 0); + BUF_15_DATA_OUT : OUT std_logic_vector(37 downto 0); + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_APV_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL APV_SYNC_IN : std_logic; + SIGNAL APV_FRAME_REQD_IN : std_logic; + SIGNAL ADC0_PLL_LOCK_IN : std_logic; + SIGNAL ADC0_CLK40M_IN : std_logic; + SIGNAL ADC0_0_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_1_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_2_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_3_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_4_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_5_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_6_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC0_7_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_PLL_LOCK_IN : std_logic; + SIGNAL ADC1_CLK40M_IN : std_logic; + SIGNAL ADC1_0_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_1_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_2_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_3_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_4_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_5_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_6_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL ADC1_7_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL MAX_TRG_NUM_IN : std_logic_vector(3 downto 0); + SIGNAL BIT_LOW_IN : std_logic_vector(11 downto 0); + SIGNAL BIT_HIGH_IN : std_logic_vector(11 downto 0); + SIGNAL FL_LOW_IN : std_logic_vector(11 downto 0); + SIGNAL FL_HIGH_IN : std_logic_vector(11 downto 0); + SIGNAL APV_ON_IN : std_logic_vector(15 downto 0); + SIGNAL BUF_FULL_OUT : std_logic; + SIGNAL BUF_ADDR_IN : std_logic_vector(6 downto 0); + SIGNAL BUF_DONE_IN : std_logic; + SIGNAL BUF_TICK_OUT : std_logic_vector(15 downto 0); + SIGNAL BUF_START_OUT : std_logic_vector(15 downto 0); + SIGNAL BUF_READY_OUT : std_logic_vector(15 downto 0); + SIGNAL BUF_0_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_1_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_2_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_3_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_4_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_5_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_6_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_7_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_8_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_9_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_10_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_11_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_12_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_13_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_14_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL BUF_15_DATA_OUT : std_logic_vector(37 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: raw_buf_stage_new PORT MAP( + CLK_IN => CLK_IN, + RESET_APV_IN => RESET_APV_IN, + RESET_IN => RESET_IN, + APV_SYNC_IN => APV_SYNC_IN, + APV_FRAME_REQD_IN => APV_FRAME_REQD_IN, + ADC0_PLL_LOCK_IN => ADC0_PLL_LOCK_IN, + ADC0_CLK40M_IN => ADC0_CLK40M_IN, + ADC0_0_DATA_IN => ADC0_0_DATA_IN, + ADC0_1_DATA_IN => ADC0_1_DATA_IN, + ADC0_2_DATA_IN => ADC0_2_DATA_IN, + ADC0_3_DATA_IN => ADC0_3_DATA_IN, + ADC0_4_DATA_IN => ADC0_4_DATA_IN, + ADC0_5_DATA_IN => ADC0_5_DATA_IN, + ADC0_6_DATA_IN => ADC0_6_DATA_IN, + ADC0_7_DATA_IN => ADC0_7_DATA_IN, + ADC1_PLL_LOCK_IN => ADC1_PLL_LOCK_IN, + ADC1_CLK40M_IN => ADC1_CLK40M_IN, + ADC1_0_DATA_IN => ADC1_0_DATA_IN, + ADC1_1_DATA_IN => ADC1_1_DATA_IN, + ADC1_2_DATA_IN => ADC1_2_DATA_IN, + ADC1_3_DATA_IN => ADC1_3_DATA_IN, + ADC1_4_DATA_IN => ADC1_4_DATA_IN, + ADC1_5_DATA_IN => ADC1_5_DATA_IN, + ADC1_6_DATA_IN => ADC1_6_DATA_IN, + ADC1_7_DATA_IN => ADC1_7_DATA_IN, + MAX_TRG_NUM_IN => MAX_TRG_NUM_IN, + BIT_LOW_IN => BIT_LOW_IN, + BIT_HIGH_IN => BIT_HIGH_IN, + FL_LOW_IN => FL_LOW_IN, + FL_HIGH_IN => FL_HIGH_IN, + APV_ON_IN => APV_ON_IN, + BUF_FULL_OUT => BUF_FULL_OUT, + BUF_ADDR_IN => BUF_ADDR_IN, + BUF_DONE_IN => BUF_DONE_IN, + BUF_TICK_OUT => BUF_TICK_OUT, + BUF_START_OUT => BUF_START_OUT, + BUF_READY_OUT => BUF_READY_OUT, + BUF_0_DATA_OUT => BUF_0_DATA_OUT, + BUF_1_DATA_OUT => BUF_1_DATA_OUT, + BUF_2_DATA_OUT => BUF_2_DATA_OUT, + BUF_3_DATA_OUT => BUF_3_DATA_OUT, + BUF_4_DATA_OUT => BUF_4_DATA_OUT, + BUF_5_DATA_OUT => BUF_5_DATA_OUT, + BUF_6_DATA_OUT => BUF_6_DATA_OUT, + BUF_7_DATA_OUT => BUF_7_DATA_OUT, + BUF_8_DATA_OUT => BUF_8_DATA_OUT, + BUF_9_DATA_OUT => BUF_9_DATA_OUT, + BUF_10_DATA_OUT => BUF_10_DATA_OUT, + BUF_11_DATA_OUT => BUF_11_DATA_OUT, + BUF_12_DATA_OUT => BUF_12_DATA_OUT, + BUF_13_DATA_OUT => BUF_13_DATA_OUT, + BUF_14_DATA_OUT => BUF_14_DATA_OUT, + BUF_15_DATA_OUT => BUF_15_DATA_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +-- ADC0 and ADC1 40MHz clock +THE_ADC_CLOCK_GEN: process +begin + adc0_clk40m_in <= '1'; adc1_clk40m_in <= '1'; wait for 12.5 ns; + adc0_clk40m_in <= '0'; adc1_clk40m_in <= '0'; wait for 12.5 ns; +end process THE_ADC_CLOCK_GEN; + +-- 100MHz system clock +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + reset_apv_in <= '0'; + apv_sync_in <= '0'; + apv_frame_reqd_in <= '0'; + adc0_pll_lock_in <= '0'; + adc0_0_data_in <= x"000"; + adc0_1_data_in <= x"800"; + adc0_2_data_in <= x"800"; + adc0_3_data_in <= x"800"; + adc0_4_data_in <= x"800"; + adc0_5_data_in <= x"800"; + adc0_6_data_in <= x"800"; + adc0_7_data_in <= x"800"; + adc1_pll_lock_in <= '0'; + adc1_0_data_in <= x"800"; + adc1_1_data_in <= x"800"; + adc1_2_data_in <= x"800"; + adc1_3_data_in <= x"800"; + adc1_4_data_in <= x"800"; + adc1_5_data_in <= x"800"; + adc1_6_data_in <= x"800"; + adc1_7_data_in <= x"800"; + max_trg_num_in <= x"1"; + bit_low_in <= x"200"; + bit_high_in <= x"e00"; + fl_low_in <= x"780"; + fl_high_in <= x"880"; + apv_on_in <= x"0001"; + buf_addr_in <= (others => '0'); + buf_done_in <= '0'; + wait for 100 ns; + + -- Reset all + wait until rising_edge(clk_in); + reset_in <= '1'; + reset_apv_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '0'; + reset_apv_in <= '0'; + wait for 100 ns; + + wait until rising_edge(clk_in); + adc0_pll_lock_in <= '1'; + adc1_pll_lock_in <= '1'; + wait until rising_edge(clk_in); + + -- Tests may start now + wait until rising_edge(clk_in); + + + + + + -- Stay a while, stay forever! + wait; + +end process THE_TEST_BENCH; + +END; diff --git a/src/tb_real_trg_handler.vhd b/src/tb_real_trg_handler.vhd new file mode 100644 index 0000000..3250152 --- /dev/null +++ b/src/tb_real_trg_handler.vhd @@ -0,0 +1,245 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT real_trg_handler + PORT( + CLK_IN : IN std_logic; + CLEAR_IN : IN std_logic; + RESET_IN : IN std_logic; + TIME_TRG_IN : IN std_logic_vector(3 downto 0); + TRB_TRG_IN : IN std_logic_vector(3 downto 0); + APV_TRGDONE_IN : IN std_logic; + TRG_3_TODO_IN : IN std_logic_vector(3 downto 0); + TRG_2_TODO_IN : IN std_logic_vector(3 downto 0); + TRG_1_TODO_IN : IN std_logic_vector(3 downto 0); + TRG_0_TODO_IN : IN std_logic_vector(3 downto 0); + TRB_TTAG_IN : IN std_logic_vector(15 downto 0); + TRB_TRND_IN : IN std_logic_vector(7 downto 0); + TRB_TTYPE_IN : IN std_logic_vector(3 downto 0); + TRB_TRGRCVD_IN : IN std_logic; + BUSY_RELEASE_IN : IN std_logic; + TRB_MISMATCH_OUT : OUT std_logic; + LVL1_COUNTER_OUT : OUT std_logic_vector(15 downto 0); + APV_TRGSEL_OUT : OUT std_logic_vector(3 downto 0); + APV_TRGSTART_OUT : OUT std_logic; + EDS_DATA_OUT : OUT std_logic_vector(39 downto 0); + EDS_WE_OUT : OUT std_logic; + EDS_START_OUT : OUT std_logic; + EDS_READY_OUT : OUT std_logic; + DBG_FRMCTR_OUT : OUT std_logic_vector(3 downto 0); + BSM_OUT : OUT std_logic_vector(7 downto 0); + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL CLEAR_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL TIME_TRG_IN : std_logic_vector(3 downto 0); + SIGNAL TRB_TRG_IN : std_logic_vector(3 downto 0); + SIGNAL APV_TRGDONE_IN : std_logic; + SIGNAL TRG_3_TODO_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_2_TODO_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_1_TODO_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_0_TODO_IN : std_logic_vector(3 downto 0); + SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0); + SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0); + SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0); + SIGNAL TRB_TRGRCVD_IN : std_logic; + SIGNAL TRB_MISMATCH_OUT : std_logic; + SIGNAL LVL1_COUNTER_OUT : std_logic_vector(15 downto 0); + SIGNAL BUSY_RELEASE_IN : std_logic; + SIGNAL APV_TRGSEL_OUT : std_logic_vector(3 downto 0); + SIGNAL APV_TRGSTART_OUT : std_logic; + SIGNAL EDS_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL EDS_WE_OUT : std_logic; + SIGNAL EDS_START_OUT : std_logic; + SIGNAL EDS_READY_OUT : std_logic; + SIGNAL DBG_FRMCTR_OUT : std_logic_vector(3 downto 0); + SIGNAL BSM_OUT : std_logic_vector(7 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: real_trg_handler PORT MAP( + CLK_IN => CLK_IN, + CLEAR_IN => CLEAR_IN, + RESET_IN => RESET_IN, + TIME_TRG_IN => TIME_TRG_IN, + TRB_TRG_IN => TRB_TRG_IN, + APV_TRGDONE_IN => APV_TRGDONE_IN, + TRG_3_TODO_IN => TRG_3_TODO_IN, + TRG_2_TODO_IN => TRG_2_TODO_IN, + TRG_1_TODO_IN => TRG_1_TODO_IN, + TRG_0_TODO_IN => TRG_0_TODO_IN, + TRB_TTAG_IN => TRB_TTAG_IN, + TRB_TRND_IN => TRB_TRND_IN, + TRB_TTYPE_IN => TRB_TTYPE_IN, + TRB_TRGRCVD_IN => TRB_TRGRCVD_IN, + TRB_MISMATCH_OUT => TRB_MISMATCH_OUT, + LVL1_COUNTER_OUT => LVL1_COUNTER_OUT, + BUSY_RELEASE_IN => BUSY_RELEASE_IN, + APV_TRGSEL_OUT => APV_TRGSEL_OUT, + APV_TRGSTART_OUT => APV_TRGSTART_OUT, + EDS_DATA_OUT => EDS_DATA_OUT, + EDS_WE_OUT => EDS_WE_OUT, + EDS_START_OUT => EDS_START_OUT, + EDS_READY_OUT => EDS_READY_OUT, + DBG_FRMCTR_OUT => DBG_FRMCTR_OUT, + BSM_OUT => BSM_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + clear_in <= '0'; + reset_in <= '0'; + time_trg_in <= x"0"; + trb_trg_in <= x"0"; + apv_trgdone_in <= '0'; + trg_3_todo_in <= x"0"; + trg_2_todo_in <= x"3"; + trg_1_todo_in <= x"2"; + trg_0_todo_in <= x"1"; + trb_ttag_in <= x"dead"; + trb_trnd_in <= x"fc"; + trb_ttype_in <= x"1"; + trb_trgrcvd_in <= '0'; + busy_release_in <= '0'; + -- Reset all + clear_in <= '1'; wait for 50 ns; + clear_in <= '0'; wait for 50 ns; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + -- Tests may start here + + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + + -- First sync trigger + wait until rising_edge(clk_in); + trb_trg_in <= x"8"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trg_in <= x"0"; + wait until rising_edge(clk_in); + + wait for 155 ns; + wait until rising_edge(clk_in); + apv_trgdone_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + apv_trgdone_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 200 ns; + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 300 ns; + wait until rising_edge(clk_in); + busy_release_in <= '1'; + wait until rising_edge(clk_in); + busy_release_in <= '0'; + wait until rising_edge(clk_in); + + wait for 100 ns; + + -- Second trigger + wait until rising_edge(clk_in); + trb_trg_in <= x"1"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trg_in <= x"0"; + wait until rising_edge(clk_in); + + wait for 155 ns; + wait until rising_edge(clk_in); + apv_trgdone_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + apv_trgdone_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 200 ns; + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 300 ns; + wait until rising_edge(clk_in); + busy_release_in <= '1'; + wait until rising_edge(clk_in); + busy_release_in <= '0'; + wait until rising_edge(clk_in); + + wait for 100 ns; + + -- Check it + wait until rising_edge(clk_in); + trb_trg_in <= x"c"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trg_in <= x"0"; + wait until rising_edge(clk_in); + + wait for 155 ns; + wait until rising_edge(clk_in); + apv_trgdone_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + apv_trgdone_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 200 ns; + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 300 ns; + wait until rising_edge(clk_in); + busy_release_in <= '1'; + wait until rising_edge(clk_in); + busy_release_in <= '0'; + wait until rising_edge(clk_in); + + + -- Stay a while, stay forever. + wait; + +end process THE_TEST_BENCH; + + +END; + diff --git a/src/tb_reboot_handler.vhd b/src/tb_reboot_handler.vhd new file mode 100644 index 0000000..851a58b --- /dev/null +++ b/src/tb_reboot_handler.vhd @@ -0,0 +1,71 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT reboot_handler + PORT( + RESET_IN : IN std_logic; + CLK_IN : IN std_logic; + START_IN : IN std_logic; + REBOOT_OUT : OUT std_logic; + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL RESET_IN : std_logic; + SIGNAL CLK_IN : std_logic; + SIGNAL START_IN : std_logic; + SIGNAL REBOOT_OUT : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: reboot_handler PORT MAP( + RESET_IN => RESET_IN, + CLK_IN => CLK_IN, + START_IN => START_IN, + REBOOT_OUT => REBOOT_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + start_in <= '0'; + + -- Sync reset + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 140 ns; + + -- Tests may start now + wait until rising_edge(clk_in); + start_in <= '1'; + wait until rising_edge(clk_in); + start_in <= '0'; + wait until rising_edge(clk_in); + + + + -- Stay a while, stay forever.... + wait; +end process THE_TEST_BENCH; + +END; + diff --git a/src/tb_reset_handler.vhd b/src/tb_reset_handler.vhd new file mode 100644 index 0000000..82ff279 --- /dev/null +++ b/src/tb_reset_handler.vhd @@ -0,0 +1,76 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT reset_handler + PORT( + CLEAR_IN : IN std_logic; + RESET_IN : IN std_logic; + CLK_IN : IN std_logic; + TRB_RESET_IN : IN std_logic; + RESET_OUT : OUT std_logic; + DEBUG_OUT : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + SIGNAL CLEAR_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL CLK_IN : std_logic; + SIGNAL TRB_RESET_IN : std_logic; + SIGNAL RESET_OUT : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: reset_handler PORT MAP( + CLEAR_IN => CLEAR_IN, + RESET_IN => RESET_IN, + CLK_IN => CLK_IN, + TRB_RESET_IN => TRB_RESET_IN, + RESET_OUT => RESET_OUT, + DEBUG_OUT => DEBUG_OUT + ); + + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + clear_in <= '1'; + reset_in <= '0'; + trb_reset_in <= '0'; + + + -- Tests may start now + wait for 300 ns; + wait until rising_edge(clk_in); + + wait for 3.33 ns; + clear_in <= '0'; + + wait for 2 us; + + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + reset_in <= '0'; + + wait for 2 us; + + -- Stay a while, stay forever.... + wait; +end process THE_TEST_BENCH; + +END; + diff --git a/src/tb_slv_adc_la.vhd b/src/tb_slv_adc_la.vhd new file mode 100644 index 0000000..4429969 --- /dev/null +++ b/src/tb_slv_adc_la.vhd @@ -0,0 +1,94 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT slv_adc_la + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + SLV_ADDR_IN : IN std_logic_vector(9 downto 0); + SLV_READ_IN : IN std_logic; + SLV_WRITE_IN : IN std_logic; + SLV_DATA_IN : IN std_logic_vector(31 downto 0); + ADC_CLK_IN : IN std_logic; + ADC_DATA_IN : IN std_logic_vector(11 downto 0); + SLV_ACK_OUT : OUT std_logic; + SLV_DATA_OUT : OUT std_logic_vector(31 downto 0); + ADC_SEL_OUT : OUT std_logic_vector(2 downto 0); + STAT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL SLV_ADDR_IN : std_logic_vector(9 downto 0); + SIGNAL SLV_READ_IN : std_logic; + SIGNAL SLV_WRITE_IN : std_logic; + SIGNAL SLV_ACK_OUT : std_logic; + SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL ADC_SEL_OUT : std_logic_vector(2 downto 0); + SIGNAL ADC_CLK_IN : std_logic; + SIGNAL ADC_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL STAT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: slv_adc_la PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + ADC_SEL_OUT => ADC_SEL_OUT, + ADC_CLK_IN => ADC_CLK_IN, + ADC_DATA_IN => ADC_DATA_IN, + STAT => STAT + ); + + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_ADC_CLOCK_GEN: process +begin + adc_clk_in <= '1'; wait for 12.5 ns; + adc_clk_in <= '0'; wait for 12.5 ns; +end process THE_ADC_CLOCK_GEN; + + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + slv_addr_in <= b"00_0000_0000"; + slv_read_in <= '0'; + slv_write_in <= '0'; + slv_data_in <= x"0000_0000"; + wait for 100 ns; + + -- Reset all + reset_in <= '1'; + wait for 100 ns; + reset_in <= '0'; + wait for 400 ns; + + -- Tests may start now + + -- stay a while.... stay forever!!! + wait; +end process THE_TEST_BENCH; + +END; diff --git a/src/tb_slv_adc_snoop.vhd b/src/tb_slv_adc_snoop.vhd new file mode 100644 index 0000000..9c3012c --- /dev/null +++ b/src/tb_slv_adc_snoop.vhd @@ -0,0 +1,243 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT slv_adc_snoop + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + SLV_ADDR_IN : IN std_logic_vector(9 downto 0); + SLV_READ_IN : IN std_logic; + SLV_WRITE_IN : IN std_logic; + SLV_DATA_IN : IN std_logic_vector(31 downto 0); + ADC_CLK_IN : IN std_logic; + ADC_DATA_IN : IN std_logic_vector(11 downto 0); + SLV_ACK_OUT : OUT std_logic; + SLV_DATA_OUT : OUT std_logic_vector(31 downto 0); + ADC_SEL_OUT : OUT std_logic_vector(2 downto 0); + STAT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL SLV_ADDR_IN : std_logic_vector(9 downto 0); + SIGNAL SLV_READ_IN : std_logic; + SIGNAL SLV_WRITE_IN : std_logic; + SIGNAL SLV_ACK_OUT : std_logic; + SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL ADC_SEL_OUT : std_logic_vector(2 downto 0); + SIGNAL ADC_CLK_IN : std_logic; + SIGNAL ADC_DATA_IN : std_logic_vector(11 downto 0); + SIGNAL STAT : std_logic_vector(31 downto 0); + + signal adc_real : std_logic_vector(11 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: slv_adc_snoop PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + ADC_SEL_OUT => ADC_SEL_OUT, + ADC_CLK_IN => ADC_CLK_IN, + ADC_DATA_IN => ADC_DATA_IN, + STAT => STAT + ); + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_ADC_CLK_GEN: process +begin + adc_clk_in <= '1'; wait for 12 ns; + adc_clk_in <= '0'; wait for 12 ns; +end process THE_ADC_CLK_GEN; + +BLA: process +variable adc_data : unsigned(11 downto 0) := x"000"; +begin + adc_real <= std_logic_vector(adc_data); + wait until rising_edge(adc_clk_in); + adc_data_in <= adc_real; + adc_data := adc_data + 1; +end process BLA; + +THE_TEST_BENCH: process +variable addr : unsigned(9 downto 0) := b"00_0000_0000"; +begin + -- Setup signals + reset_in <= '0'; + slv_read_in <= '0'; + slv_write_in <= '0'; + slv_data_in <= x"0000_0000"; + slv_addr_in <= b"00_0000_0000"; + + -- Reset the whole bunch + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + + -- Tests may start now + + -- One write access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_data_in <= x"0000_4000"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 500 ns; + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 500 ns; + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 500 ns; + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 500 ns; + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 500 ns; + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 500 ns; + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + wait for 500 ns; + + -- Stop the sampling + -- One write access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_data_in <= x"0000_0000"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- get last written address + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + + addr := unsigned(slv_data_out(25 downto 16)); + addr := addr + 1; + + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read back the whole stuff + READ_LOOP: for I in 0 to 1023 loop + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= std_logic_vector(addr); --b"00_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + addr := addr + 1; + end loop READ_LOOP; + + + -- Stay a while, stay forever! + wait; +end process THE_TEST_BENCH; + + +END; diff --git a/src/tb_slv_onewire_memory.vhd b/src/tb_slv_onewire_memory.vhd new file mode 100644 index 0000000..5a86454 --- /dev/null +++ b/src/tb_slv_onewire_memory.vhd @@ -0,0 +1,958 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT slv_onewire_memory + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + SLV_ADDR_IN : IN std_logic_vector(5 downto 0); + SLV_READ_IN : IN std_logic; + SLV_WRITE_IN : IN std_logic; + BACKPLANE_IN : IN std_logic_vector(2 downto 0); + ONEWIRE_START_IN : IN std_logic; + ONEWIRE_INOUT : INOUT std_logic_vector(15 downto 0); + BP_ONEWIRE_INOUT : INOUT std_logic; + SLV_ACK_OUT : OUT std_logic; + SLV_BUSY_OUT : OUT std_logic; + SLV_DATA_OUT : OUT std_logic_vector(31 downto 0); + STAT : OUT std_logic_vector(63 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL SLV_ADDR_IN : std_logic_vector(5 downto 0); + SIGNAL SLV_READ_IN : std_logic; + SIGNAL SLV_WRITE_IN : std_logic; + SIGNAL BACKPLANE_IN : std_logic_vector(2 downto 0); + SIGNAL SLV_ACK_OUT : std_logic; + SIGNAL SLV_BUSY_OUT : std_logic; + SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL ONEWIRE_START_IN : std_logic; + SIGNAL ONEWIRE_INOUT : std_logic_vector(15 downto 0); + SIGNAL BP_ONEWIRE_INOUT : std_logic; + SIGNAL STAT : std_logic_vector(63 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: slv_onewire_memory PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + BACKPLANE_IN => BACKPLANE_IN, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_OUT => SLV_DATA_OUT, + SLV_BUSY_OUT => SLV_BUSY_OUT, + ONEWIRE_START_IN => ONEWIRE_START_IN, + ONEWIRE_INOUT => ONEWIRE_INOUT, + BP_ONEWIRE_INOUT => BP_ONEWIRE_INOUT, + STAT => STAT + ); + +CLK_GEN_PROC: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process CLK_GEN_PROC; + +THE_TESTBENCH: process +begin + -- Setup signals + reset_in <= '0'; + slv_addr_in <= (others => '0'); + backplane_in <= b"000"; + slv_read_in <= '0'; + slv_write_in <= '0'; + onewire_start_in <= '0'; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + + -- Do a reset + wait for 50 ns; + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + + -- Tests may start here + + -- Start one cycle + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(clk_in); + + -- 1Wire access + -- wait for reset pulse (READ_ID) + wait until falling_edge(onewire_inout(0)); + wait until rising_edge(onewire_inout(0)); + wait for 30 us; + onewire_inout <= b"0000_0000_0000_0000"; + bp_onewire_inout <= '0'; + wait for 120 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + + -- skip the command sequence + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + + -- serial number + -- bit 0 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"fe80"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 1 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"ef71"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 2 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"d062"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 3 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"c153"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 4 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"b244"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 5 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"a335"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 6 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"9426"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 7 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"8517"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 8 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"7608"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 9 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"67f9"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 10 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"58ea"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 11 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"49db"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 12 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"3acc"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 13 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"2bbd"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 14 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"1cae"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 15 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"0d9f"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + + -- bit 16 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"dead"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 17 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"beef"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 18 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"affe"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 19 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"d00f"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 20 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"facc"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 21 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"0123"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 22 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"4567"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 23 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"89ab"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 24 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"cdef"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 25 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"aaaa"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 26 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"5555"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 27 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"6271"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 28 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"4711"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 29 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"0666"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 30 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"7550"; + bp_onewire_inout <= '0'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 31 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"bacc"; + bp_onewire_inout <= '1'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + + -- bit 32 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"0123"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 33 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"4567"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 34 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"89ab"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 35 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"cdef"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 36 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"0f1e"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 37 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"2d3c"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 38 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"4b5a"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 39 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"6978"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 40 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"8796"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 41 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"a5b4"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 42 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"c3d2"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 43 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"e1f0"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 44 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"fedc"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 45 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"ba98"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 46 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"7654"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 47 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"3210"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + + -- bit 48 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"fffe"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 49 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"fffd"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 50 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"fffb"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 51 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"fff7"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 52 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"ffef"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 53 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"ffdf"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 54 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"ffbf"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 55 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"ff7f"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 56 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"feff"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 57 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"fdff"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 58 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"fbff"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 59 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"f7ff"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 60 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"efff"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 61 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"dfff"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 62 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"bfff"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 63 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"7fff"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + + -- wait for reset pulse (CONV_TEMP) + wait until falling_edge(onewire_inout(0)); + wait until rising_edge(onewire_inout(0)); + wait for 30 us; + onewire_inout <= b"0000_0000_0000_0000"; + bp_onewire_inout <= '0'; + wait for 120 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + + -- skip the command sequence + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + + -- wait for reset pulse (READ_TEMP) + wait until falling_edge(onewire_inout(0)); + wait until rising_edge(onewire_inout(0)); + wait for 30 us; + onewire_inout <= b"0000_0000_0000_0000"; + bp_onewire_inout <= '0'; + wait for 120 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + + -- skip the command sequence + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + wait until falling_edge(onewire_inout(0)); + + -- temparature + -- bit 0 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"4001"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 1 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"5002"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 2 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"6004"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 3 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"7008"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 4 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"8010"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 5 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"9020"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 6 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"a040"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 7 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"b080"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 8 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"c100"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 9 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"d200"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 10 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"e400"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + -- bit 11 + wait until falling_edge(onewire_inout(0)); + onewire_inout <= x"f800"; + bp_onewire_inout <= 'H'; + wait for 30 us; + onewire_inout <= (others => 'H'); + bp_onewire_inout <= 'H'; + + + -- wait for end of 1Wire access + wait until falling_edge(slv_busy_out); + wait for 100 ns; + + -- 1Wire 0 + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0000"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0001"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0010"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0011"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- 1Wire 1 + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0100"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0101"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0110"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_0111"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- 1Wire 1 + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_1000"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_1001"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_1010"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_1011"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- 1Wire 3 + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_1100"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_1101"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_1110"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"00_1111"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + + + + -- 1Wire 15 + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"11_1100"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"11_1101"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"11_1110"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- read one address + wait until rising_edge(clk_in); + slv_addr_in <= b"11_1111"; + wait until rising_edge(clk_in); + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- Do a write + + -- Stay a while, stay forever! + wait; +end process THE_TESTBENCH; + + + +END; + diff --git a/src/tb_slv_ped_thr_mem.vhd b/src/tb_slv_ped_thr_mem.vhd new file mode 100644 index 0000000..f46fcf5 --- /dev/null +++ b/src/tb_slv_ped_thr_mem.vhd @@ -0,0 +1,225 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT slv_ped_thr_mem + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + SLV_ADDR_IN : IN std_logic_vector(10 downto 0); + SLV_READ_IN : IN std_logic; + SLV_WRITE_IN : IN std_logic; + SLV_DATA_IN : IN std_logic_vector(31 downto 0); + BACKPLANE_IN : IN std_logic_vector(2 downto 0); + MEM_CLK_IN : IN std_logic; + MEM_ADDR_IN : IN std_logic_vector(6 downto 0); + SLV_ACK_OUT : OUT std_logic; + SLV_DATA_OUT : OUT std_logic_vector(31 downto 0); + MEM_0_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_1_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_2_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_3_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_4_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_5_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_6_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_7_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_8_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_9_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_10_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_11_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_12_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_13_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_14_D_OUT : OUT std_logic_vector(17 downto 0); + MEM_15_D_OUT : OUT std_logic_vector(17 downto 0); + STAT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL SLV_ADDR_IN : std_logic_vector(10 downto 0); + SIGNAL SLV_READ_IN : std_logic; + SIGNAL SLV_WRITE_IN : std_logic; + SIGNAL SLV_ACK_OUT : std_logic; + SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL BACKPLANE_IN : std_logic_vector(2 downto 0); + SIGNAL MEM_CLK_IN : std_logic; + SIGNAL MEM_ADDR_IN : std_logic_vector(6 downto 0); + SIGNAL MEM_0_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_1_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_2_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_3_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_4_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_5_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_6_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_7_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_8_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_9_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_10_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_11_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_12_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_13_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_14_D_OUT : std_logic_vector(17 downto 0); + SIGNAL MEM_15_D_OUT : std_logic_vector(17 downto 0); + SIGNAL STAT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: slv_ped_thr_mem PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + BACKPLANE_IN => BACKPLANE_IN, + MEM_CLK_IN => MEM_CLK_IN, + MEM_ADDR_IN => MEM_ADDR_IN, + MEM_0_D_OUT => MEM_0_D_OUT, + MEM_1_D_OUT => MEM_1_D_OUT, + MEM_2_D_OUT => MEM_2_D_OUT, + MEM_3_D_OUT => MEM_3_D_OUT, + MEM_4_D_OUT => MEM_4_D_OUT, + MEM_5_D_OUT => MEM_5_D_OUT, + MEM_6_D_OUT => MEM_6_D_OUT, + MEM_7_D_OUT => MEM_7_D_OUT, + MEM_8_D_OUT => MEM_8_D_OUT, + MEM_9_D_OUT => MEM_9_D_OUT, + MEM_10_D_OUT => MEM_10_D_OUT, + MEM_11_D_OUT => MEM_11_D_OUT, + MEM_12_D_OUT => MEM_12_D_OUT, + MEM_13_D_OUT => MEM_13_D_OUT, + MEM_14_D_OUT => MEM_14_D_OUT, + MEM_15_D_OUT => MEM_15_D_OUT, + STAT => STAT + ); + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; mem_clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; mem_clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + slv_read_in <= '0'; + slv_write_in <= '0'; + slv_data_in <= x"0000_0000"; + slv_addr_in <= b"111_1111_1111"; + backplane_in <= b"001"; + mem_addr_in <= b"000_0000"; + + -- Reset the whole bunch + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + + + -- Tests may start now + + -- One write access + wait until rising_edge(clk_in); + slv_addr_in <= b"000_0000_0000"; + slv_data_in <= x"0000_dead"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access + wait until rising_edge(clk_in); + slv_addr_in <= b"000_0000_0001"; + slv_data_in <= x"0000_beef"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access + wait until rising_edge(clk_in); + slv_addr_in <= b"000_0000_0010"; + slv_data_in <= x"0000_affe"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access + wait until rising_edge(clk_in); + slv_addr_in <= b"000_0000_0011"; + slv_data_in <= x"0000_d00f"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"000_0000_0000"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"000_0000_0001"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"000_0000_0010"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access + wait until rising_edge(clk_in); + slv_addr_in <= b"000_0000_0011"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + + + -- Stay a while, stay forever.... + wait; +end process THE_TEST_BENCH; + +END; + diff --git a/src/tb_slv_register_bank.vhd b/src/tb_slv_register_bank.vhd new file mode 100644 index 0000000..1b2c86b --- /dev/null +++ b/src/tb_slv_register_bank.vhd @@ -0,0 +1,565 @@ + +-- VHDL Test Bench Created from source file slv_register_bank.vhd -- 07-MAY-2008 01:09:40 +-- +-- Notes: +-- 1) This testbench template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the unit under test. +-- Lattice recommends that these types always be used for the top-level +-- I/O of a design in order to guarantee that the testbench will bind +-- correctly to the timing (post-route) simulation model. +-- 2) To use this template as your testbench, change the filename to any +-- name of your choice with the extension .vhd, and use the "source->import" +-- menu in the ispLEVER Project Navigator to import the testbench. +-- Then edit the user defined section below, adding code to generate the +-- stimulus for your design. +-- 3) VHDL simulations will produce errors if there are Lattice FPGA library +-- elements in your design that require the instantiation of GSR, PUR, and +-- TSALL and they are not present in the testbench. For more information see +-- the How To section of online help. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT slv_register_bank + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + SLV_ADDR_IN : IN std_logic_vector(3 downto 0); + SLV_READ_IN : IN std_logic; + SLV_WRITE_IN : IN std_logic; + SLV_DATA_IN : IN std_logic_vector(31 downto 0); + BACKPLANE_IN : IN std_logic_vector(2 downto 0); + STAT_0_IN : IN std_logic_vector(15 downto 0); + STAT_1_IN : IN std_logic_vector(15 downto 0); + STAT_2_IN : IN std_logic_vector(15 downto 0); + STAT_3_IN : IN std_logic_vector(15 downto 0); + STAT_4_IN : IN std_logic_vector(15 downto 0); + STAT_5_IN : IN std_logic_vector(15 downto 0); + STAT_6_IN : IN std_logic_vector(15 downto 0); + STAT_7_IN : IN std_logic_vector(15 downto 0); + STAT_8_IN : IN std_logic_vector(15 downto 0); + STAT_9_IN : IN std_logic_vector(15 downto 0); + STAT_10_IN : IN std_logic_vector(15 downto 0); + STAT_11_IN : IN std_logic_vector(15 downto 0); + STAT_12_IN : IN std_logic_vector(15 downto 0); + STAT_13_IN : IN std_logic_vector(15 downto 0); + STAT_14_IN : IN std_logic_vector(15 downto 0); + STAT_15_IN : IN std_logic_vector(15 downto 0); + SLV_ACK_OUT : OUT std_logic; + SLV_DATA_OUT : OUT std_logic_vector(31 downto 0); + CTRL_0_OUT : OUT std_logic_vector(15 downto 0); + CTRL_1_OUT : OUT std_logic_vector(15 downto 0); + CTRL_2_OUT : OUT std_logic_vector(15 downto 0); + CTRL_3_OUT : OUT std_logic_vector(15 downto 0); + CTRL_4_OUT : OUT std_logic_vector(15 downto 0); + CTRL_5_OUT : OUT std_logic_vector(15 downto 0); + CTRL_6_OUT : OUT std_logic_vector(15 downto 0); + CTRL_7_OUT : OUT std_logic_vector(15 downto 0); + CTRL_8_OUT : OUT std_logic_vector(15 downto 0); + CTRL_9_OUT : OUT std_logic_vector(15 downto 0); + CTRL_10_OUT : OUT std_logic_vector(15 downto 0); + CTRL_11_OUT : OUT std_logic_vector(15 downto 0); + CTRL_12_OUT : OUT std_logic_vector(15 downto 0); + CTRL_13_OUT : OUT std_logic_vector(15 downto 0); + CTRL_14_OUT : OUT std_logic_vector(15 downto 0); + CTRL_15_OUT : OUT std_logic_vector(15 downto 0); + STAT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL SLV_ADDR_IN : std_logic_vector(3 downto 0); + SIGNAL SLV_READ_IN : std_logic; + SIGNAL SLV_WRITE_IN : std_logic; + SIGNAL SLV_ACK_OUT : std_logic; + SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL BACKPLANE_IN : std_logic_vector(2 downto 0); + SIGNAL CTRL_0_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_1_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_2_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_3_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_4_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_5_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_6_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_7_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_8_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_9_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_10_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_11_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_12_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_13_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_14_OUT : std_logic_vector(15 downto 0); + SIGNAL CTRL_15_OUT : std_logic_vector(15 downto 0); + SIGNAL STAT_0_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_1_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_2_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_3_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_4_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_5_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_6_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_7_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_8_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_9_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_10_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_11_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_12_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_13_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_14_IN : std_logic_vector(15 downto 0); + SIGNAL STAT_15_IN : std_logic_vector(15 downto 0); + SIGNAL STAT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: slv_register_bank PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + BACKPLANE_IN => BACKPLANE_IN, + CTRL_0_OUT => CTRL_0_OUT, + CTRL_1_OUT => CTRL_1_OUT, + CTRL_2_OUT => CTRL_2_OUT, + CTRL_3_OUT => CTRL_3_OUT, + CTRL_4_OUT => CTRL_4_OUT, + CTRL_5_OUT => CTRL_5_OUT, + CTRL_6_OUT => CTRL_6_OUT, + CTRL_7_OUT => CTRL_7_OUT, + CTRL_8_OUT => CTRL_8_OUT, + CTRL_9_OUT => CTRL_9_OUT, + CTRL_10_OUT => CTRL_10_OUT, + CTRL_11_OUT => CTRL_11_OUT, + CTRL_12_OUT => CTRL_12_OUT, + CTRL_13_OUT => CTRL_13_OUT, + CTRL_14_OUT => CTRL_14_OUT, + CTRL_15_OUT => CTRL_15_OUT, + STAT_0_IN => STAT_0_IN, + STAT_1_IN => STAT_1_IN, + STAT_2_IN => STAT_2_IN, + STAT_3_IN => STAT_3_IN, + STAT_4_IN => STAT_4_IN, + STAT_5_IN => STAT_5_IN, + STAT_6_IN => STAT_6_IN, + STAT_7_IN => STAT_7_IN, + STAT_8_IN => STAT_8_IN, + STAT_9_IN => STAT_9_IN, + STAT_10_IN => STAT_10_IN, + STAT_11_IN => STAT_11_IN, + STAT_12_IN => STAT_12_IN, + STAT_13_IN => STAT_13_IN, + STAT_14_IN => STAT_14_IN, + STAT_15_IN => STAT_15_IN, + STAT => STAT + ); + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + slv_read_in <= '0'; + slv_write_in <= '0'; + slv_data_in <= x"0000_0000"; + slv_addr_in <= b"0000"; + backplane_in <= b"000"; + stat_0_in <= x"aa00"; + stat_1_in <= x"aa01"; + stat_2_in <= x"aa02"; + stat_3_in <= x"aa03"; + stat_4_in <= x"aa04"; + stat_5_in <= x"aa05"; + stat_6_in <= x"aa06"; + stat_7_in <= x"aa07"; + stat_8_in <= x"aa08"; + stat_9_in <= x"aa09"; + stat_10_in <= x"aa0a"; + stat_11_in <= x"aa0b"; + stat_12_in <= x"aa0c"; + stat_13_in <= x"aa0d"; + stat_14_in <= x"aa0e"; + stat_15_in <= x"aa0f"; + + -- Reset the whole bunch + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + + + -- Tests may start now + + -- One write access (APV0) + wait until rising_edge(clk_in); + slv_addr_in <= x"0"; + slv_data_in <= x"0000_ff00"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV1) + wait until rising_edge(clk_in); + slv_addr_in <= x"1"; + slv_data_in <= x"0000_ff01"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV2) + wait until rising_edge(clk_in); + slv_addr_in <= x"2"; + slv_data_in <= x"0000_ff02"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV3) + wait until rising_edge(clk_in); + slv_addr_in <= x"3"; + slv_data_in <= x"0000_ff03"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV4) + wait until rising_edge(clk_in); + slv_addr_in <= x"4"; + slv_data_in <= x"0000_ff04"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV5) + wait until rising_edge(clk_in); + slv_addr_in <= x"5"; + slv_data_in <= x"0000_ff05"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV6) + wait until rising_edge(clk_in); + slv_addr_in <= x"6"; + slv_data_in <= x"0000_ff06"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV7) + wait until rising_edge(clk_in); + slv_addr_in <= x"7"; + slv_data_in <= x"0000_ff07"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV8) + wait until rising_edge(clk_in); + slv_addr_in <= x"8"; + slv_data_in <= x"0000_ff08"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV9) + wait until rising_edge(clk_in); + slv_addr_in <= x"9"; + slv_data_in <= x"0000_ff09"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV10) + wait until rising_edge(clk_in); + slv_addr_in <= x"a"; + slv_data_in <= x"0000_ff0a"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV11) + wait until rising_edge(clk_in); + slv_addr_in <= x"b"; + slv_data_in <= x"0000_ff0b"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV12) + wait until rising_edge(clk_in); + slv_addr_in <= x"c"; + slv_data_in <= x"0000_ff0c"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV13) + wait until rising_edge(clk_in); + slv_addr_in <= x"d"; + slv_data_in <= x"0000_ff0d"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV14) + wait until rising_edge(clk_in); + slv_addr_in <= x"e"; + slv_data_in <= x"0000_ff0e"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One write access (APV15) + wait until rising_edge(clk_in); + slv_addr_in <= x"f"; + slv_data_in <= x"0000_ff0f"; + slv_write_in <= '1'; + wait until rising_edge(clk_in); + slv_write_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + + + + -- One read access (APV0) + wait until rising_edge(clk_in); + slv_addr_in <= x"0"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV1) + wait until rising_edge(clk_in); + slv_addr_in <= x"1"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV2) + wait until rising_edge(clk_in); + slv_addr_in <= x"2"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV3) + wait until rising_edge(clk_in); + slv_addr_in <= x"3"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV4) + wait until rising_edge(clk_in); + slv_addr_in <= x"4"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV5) + wait until rising_edge(clk_in); + slv_addr_in <= x"5"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV6) + wait until rising_edge(clk_in); + slv_addr_in <= x"6"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV7) + wait until rising_edge(clk_in); + slv_addr_in <= x"7"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV8) + wait until rising_edge(clk_in); + slv_addr_in <= x"8"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV9) + wait until rising_edge(clk_in); + slv_addr_in <= x"9"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV10) + wait until rising_edge(clk_in); + slv_addr_in <= x"a"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV11) + wait until rising_edge(clk_in); + slv_addr_in <= x"b"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV12) + wait until rising_edge(clk_in); + slv_addr_in <= x"c"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV13) + wait until rising_edge(clk_in); + slv_addr_in <= x"d"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV14) + wait until rising_edge(clk_in); + slv_addr_in <= x"e"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- One read access (APV15) + wait until rising_edge(clk_in); + slv_addr_in <= x"f"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + stat_7_in <= x"dead"; + -- One read access (APV15) + wait until rising_edge(clk_in); + slv_addr_in <= x"f"; + slv_read_in <= '1'; + wait until rising_edge(clk_in); + slv_read_in <= '0'; + wait until rising_edge(slv_ack_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- Stay a while, stay forever.... + wait; +end process THE_TEST_BENCH; + +END; + diff --git a/src/tb_spi_master.vhd b/src/tb_spi_master.vhd new file mode 100644 index 0000000..f567858 --- /dev/null +++ b/src/tb_spi_master.vhd @@ -0,0 +1,160 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT spi_master + PORT( + CLK_IN : IN std_logic; + RESET_IN : IN std_logic; + BUS_READ_IN : IN std_logic; + BUS_WRITE_IN : IN std_logic; + BUS_ADDR_IN : IN std_logic_vector(0 to 0); + BUS_DATA_IN : IN std_logic_vector(31 downto 0); + SPI_SDI_IN : IN std_logic; + BRAM_WR_D_IN : IN std_logic_vector(7 downto 0); + BUS_BUSY_OUT : OUT std_logic; + BUS_ACK_OUT : OUT std_logic; + BUS_DATA_OUT : OUT std_logic_vector(31 downto 0); + SPI_CS_OUT : OUT std_logic; + SPI_SDO_OUT : OUT std_logic; + SPI_SCK_OUT : OUT std_logic; + BRAM_A_OUT : OUT std_logic_vector(7 downto 0); + BRAM_RD_D_OUT : OUT std_logic_vector(7 downto 0); + BRAM_WE_OUT : OUT std_logic; + STAT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK_IN : std_logic; + SIGNAL RESET_IN : std_logic; + SIGNAL BUS_READ_IN : std_logic; + SIGNAL BUS_WRITE_IN : std_logic; + SIGNAL BUS_BUSY_OUT : std_logic; + SIGNAL BUS_ACK_OUT : std_logic; + SIGNAL BUS_ADDR_IN : std_logic_vector(0 to 0); + SIGNAL BUS_DATA_IN : std_logic_vector(31 downto 0); + SIGNAL BUS_DATA_OUT : std_logic_vector(31 downto 0); + SIGNAL SPI_CS_OUT : std_logic; + SIGNAL SPI_SDI_IN : std_logic; + SIGNAL SPI_SDO_OUT : std_logic; + SIGNAL SPI_SCK_OUT : std_logic; + SIGNAL BRAM_A_OUT : std_logic_vector(7 downto 0); + SIGNAL BRAM_WR_D_IN : std_logic_vector(7 downto 0); + SIGNAL BRAM_RD_D_OUT : std_logic_vector(7 downto 0); + SIGNAL BRAM_WE_OUT : std_logic; + SIGNAL STAT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: spi_master PORT MAP( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + BUS_READ_IN => BUS_READ_IN, + BUS_WRITE_IN => BUS_WRITE_IN, + BUS_BUSY_OUT => BUS_BUSY_OUT, + BUS_ACK_OUT => BUS_ACK_OUT, + BUS_ADDR_IN => BUS_ADDR_IN, + BUS_DATA_IN => BUS_DATA_IN, + BUS_DATA_OUT => BUS_DATA_OUT, + SPI_CS_OUT => SPI_CS_OUT, + SPI_SDI_IN => SPI_SDI_IN, + SPI_SDO_OUT => SPI_SDO_OUT, + SPI_SCK_OUT => SPI_SCK_OUT, + BRAM_A_OUT => BRAM_A_OUT, + BRAM_WR_D_IN => BRAM_WR_D_IN, + BRAM_RD_D_OUT => BRAM_RD_D_OUT, + BRAM_WE_OUT => BRAM_WE_OUT, + STAT => STAT + ); + +THE_CLOCK_GEN: process +begin + clk_in <= '1'; wait for 5 ns; + clk_in <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + reset_in <= '0'; + spi_sdi_in <= '0'; + bus_read_in <= '0'; + bus_write_in <= '0'; + bus_addr_in <= b"0"; + bus_data_in <= x"0000_0000"; + bram_wr_d_in <= x"00"; + + -- Sync reset + wait until rising_edge(clk_in); + reset_in <= '1'; + wait until rising_edge(clk_in); + reset_in <= '0'; + wait until rising_edge(clk_in); + wait for 140 ns; + + -- Tests may start now + + -- Set MAX to 0x03 = 4 bytes + wait until rising_edge(clk_in); + bus_addr_in <= b"1"; + bus_data_in <= x"03_00_00_00"; + wait until rising_edge(clk_in); + bus_write_in <= '1'; + wait until rising_edge(clk_in); + bus_write_in <= '0'; + wait until falling_edge(bus_ack_out); + bus_data_in <= x"0000_0000"; + bus_addr_in <= b"0"; + wait until rising_edge(clk_in); + + -- Start SPI access (ReadManId) + wait until rising_edge(clk_in); + bus_addr_in <= b"0"; + bus_data_in <= x"9f_aa_bb_cc"; + wait until rising_edge(clk_in); + bus_write_in <= '1'; + wait until rising_edge(clk_in); + bus_write_in <= '0'; + wait until falling_edge(bus_ack_out); + bus_data_in <= x"0000_0000"; + bus_addr_in <= b"0"; + wait until rising_edge(clk_in); + + -- SPI is busy now... + wait until rising_edge(clk_in); + bus_addr_in <= b"0"; + wait until rising_edge(clk_in); + bus_read_in <= '1'; + wait until rising_edge(clk_in); + bus_read_in <= '0'; + wait until rising_edge(clk_in); + bus_addr_in <= b"0"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- SPI is busy now... + wait until rising_edge(clk_in); + bus_addr_in <= b"1"; + wait until rising_edge(clk_in); + bus_read_in <= '1'; + wait until rising_edge(clk_in); + bus_read_in <= '0'; + wait until rising_edge(clk_in); + bus_addr_in <= b"0"; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + -- Stay a while... stay forever!!! + wait; + +end process THE_TEST_BENCH; +END; + diff --git a/src/tb_spi_real_slim.vhd b/src/tb_spi_real_slim.vhd new file mode 100644 index 0000000..d437357 --- /dev/null +++ b/src/tb_spi_real_slim.vhd @@ -0,0 +1,140 @@ + +-- VHDL Test Bench Created from source file spi_real_slim.vhd -- 07-MAY-2008 01:09:40 +-- +-- Notes: +-- 1) This testbench template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the unit under test. +-- Lattice recommends that these types always be used for the top-level +-- I/O of a design in order to guarantee that the testbench will bind +-- correctly to the timing (post-route) simulation model. +-- 2) To use this template as your testbench, change the filename to any +-- name of your choice with the extension .vhd, and use the "source->import" +-- menu in the ispLEVER Project Navigator to import the testbench. +-- Then edit the user defined section below, adding code to generate the +-- stimulus for your design. +-- 3) VHDL simulations will produce errors if there are Lattice FPGA library +-- elements in your design that require the instantiation of GSR, PUR, and +-- TSALL and they are not present in the testbench. For more information see +-- the How To section of online help. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT spi_real_slim + PORT( + SYSCLK : IN std_logic; + CLEAR : IN std_logic; + RESET : IN std_logic; + START_IN : IN std_logic; + CMD_IN : IN std_logic_vector(7 downto 0); + BUSY_OUT : OUT std_logic; + SPI_SCK_OUT : OUT std_logic; + SPI_CS_OUT : OUT std_logic; + SPI_SDO_OUT : OUT std_logic; + CLK_EN_OUT : OUT std_logic; + BSM_OUT : OUT std_logic_vector(7 downto 0); + DEBUG_OUT : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL SYSCLK : std_logic; + SIGNAL CLEAR : std_logic; + SIGNAL RESET : std_logic; + SIGNAL START_IN : std_logic; + SIGNAL BUSY_OUT : std_logic; + SIGNAL CMD_IN : std_logic_vector(7 downto 0); + SIGNAL SPI_SCK_OUT : std_logic; + SIGNAL SPI_CS_OUT : std_logic; + SIGNAL SPI_SDO_OUT : std_logic; + SIGNAL CLK_EN_OUT : std_logic; + SIGNAL BSM_OUT : std_logic_vector(7 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: spi_real_slim PORT MAP( + SYSCLK => SYSCLK, + CLEAR => CLEAR, + RESET => RESET, + START_IN => START_IN, + BUSY_OUT => BUSY_OUT, + CMD_IN => CMD_IN, + SPI_SCK_OUT => SPI_SCK_OUT, + SPI_CS_OUT => SPI_CS_OUT, + SPI_SDO_OUT => SPI_SDO_OUT, + CLK_EN_OUT => CLK_EN_OUT, + BSM_OUT => BSM_OUT, + DEBUG_OUT => DEBUG_OUT + ); + +THE_CLOCK_GEN: process +begin + sysclk <= '1'; wait for 5 ns; + sysclk <= '0'; wait for 5 ns; +end process THE_CLOCK_GEN; + +THE_TEST_BENCH: process +begin + -- Setup signals + clear <= '0'; + reset <= '0'; + start_in <= '0'; + cmd_in <= x"00"; + + -- Reset all + wait for 10 ns; + clear <= '1'; + wait for 10 ns; + clear <= '0'; + wait for 150 ns; + + -- Sync reset + wait until rising_edge(sysclk); + reset <= '1'; + wait until rising_edge(sysclk); + reset <= '0'; + wait until rising_edge(sysclk); + wait for 140 ns; + + + -- Tests may start now + + -- check any command + wait until rising_edge(sysclk); + cmd_in <= x"a1"; + start_in <= '1'; + wait until rising_edge(sysclk); + start_in <= '0'; + cmd_in <= x"00"; + wait until rising_edge(busy_out); + -- Mission accomplished + wait until falling_edge(busy_out); + wait for 500 ns; + + -- check any command + wait until rising_edge(sysclk); + cmd_in <= x"c2"; + start_in <= '1'; + wait until rising_edge(sysclk); + start_in <= '0'; + cmd_in <= x"00"; + wait until rising_edge(busy_out); + -- Mission accomplished + wait until falling_edge(busy_out); + wait for 500 ns; + + ----------------------------------------------- + -- Stay a while, stay forever... muahahahaha! + ----------------------------------------------- + wait; + +end process THE_TEST_BENCH; + +END; diff --git a/src/tb_suber_12bit_tmpl.vhd b/src/tb_suber_12bit_tmpl.vhd new file mode 100644 index 0000000..f4afdf6 --- /dev/null +++ b/src/tb_suber_12bit_tmpl.vhd @@ -0,0 +1,72 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component suber_12bit + port (DataA : in std_logic_vector(11 downto 0); + DataB : in std_logic_vector(11 downto 0); Clock: in std_logic; + Reset: in std_logic; ClockEn: in std_logic; + Result : out std_logic_vector(11 downto 0) + ); + end component; + + signal DataA : std_logic_vector(11 downto 0) := (others => '0'); + signal DataB : std_logic_vector(11 downto 0) := (others => '0'); + signal Clock: std_logic := '0'; + signal Reset: std_logic := '0'; + signal ClockEn: std_logic := '0'; + signal Result : std_logic_vector(11 downto 0); +begin + u1 : suber_12bit + port map (DataA => DataA, DataB => DataB, Clock => Clock, Reset => Reset, + ClockEn => ClockEn, Result => Result + ); + + process + + begin + DataA <= (others => '0') ; + for i in 0 to 200 loop + wait until Clock'event and Clock = '1'; + DataA <= DataA + '1' after 1 ns; + end loop; + wait; + end process; + + process + + begin + DataB <= (others => '0') ; + for i in 0 to 200 loop + wait until Clock'event and Clock = '1'; + DataB <= DataB + '1' after 1 ns; + end loop; + wait; + end process; + + Clock <= not Clock after 5.00 ns; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + ClockEn <= '1' ; + wait; + end process; + +end architecture test; diff --git a/src/tb_trb_net16_ibuf2.vhd b/src/tb_trb_net16_ibuf2.vhd new file mode 100755 index 0000000..856e797 --- /dev/null +++ b/src/tb_trb_net16_ibuf2.vhd @@ -0,0 +1,254 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT trb_net16_ibuf2 + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + CLK_EN : IN std_logic; + MED_DATAREADY_IN : IN std_logic; + MED_DATA_IN : IN std_logic_vector(15 downto 0); + MED_PACKET_NUM_IN : IN std_logic_vector(2 downto 0); + MED_ERROR_IN : IN std_logic_vector(2 downto 0); + INT_INIT_READ_IN : IN std_logic; + INT_REPLY_READ_IN : IN std_logic; + MED_READ_OUT : OUT std_logic; + INT_INIT_DATA_OUT : OUT std_logic_vector(15 downto 0); + INT_INIT_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0); + INT_INIT_DATAREADY_OUT : OUT std_logic; + INT_REPLY_DATA_OUT : OUT std_logic_vector(15 downto 0); + INT_REPLY_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0); + INT_REPLY_DATAREADY_OUT : OUT std_logic; + INT_ERROR_OUT : OUT std_logic_vector(2 downto 0); + STAT_BUFFER_COUNTER : OUT std_logic_vector(31 downto 0); + STAT_BUFFER : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL CLK_EN : std_logic; + SIGNAL MED_DATAREADY_IN : std_logic; + SIGNAL MED_DATA_IN : std_logic_vector(15 downto 0); + SIGNAL MED_PACKET_NUM_IN : std_logic_vector(2 downto 0); + SIGNAL MED_READ_OUT : std_logic; + SIGNAL MED_ERROR_IN : std_logic_vector(2 downto 0); + SIGNAL INT_INIT_DATA_OUT : std_logic_vector(15 downto 0); + SIGNAL INT_INIT_PACKET_NUM_OUT : std_logic_vector(2 downto 0); + SIGNAL INT_INIT_DATAREADY_OUT : std_logic; + SIGNAL INT_INIT_READ_IN : std_logic; + SIGNAL INT_REPLY_DATA_OUT : std_logic_vector(15 downto 0); + SIGNAL INT_REPLY_PACKET_NUM_OUT : std_logic_vector(2 downto 0); + SIGNAL INT_REPLY_DATAREADY_OUT : std_logic; + SIGNAL INT_REPLY_READ_IN : std_logic; + SIGNAL INT_ERROR_OUT : std_logic_vector(2 downto 0); + SIGNAL STAT_BUFFER_COUNTER : std_logic_vector(31 downto 0); + SIGNAL STAT_BUFFER : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: trb_net16_ibuf2 + PORT MAP( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_ERROR_IN => MED_ERROR_IN, + INT_INIT_DATA_OUT => INT_INIT_DATA_OUT, + INT_INIT_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT, + INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, + INT_INIT_READ_IN => INT_INIT_READ_IN, + INT_REPLY_DATA_OUT => INT_REPLY_DATA_OUT, + INT_REPLY_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT, + INT_REPLY_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, + INT_REPLY_READ_IN => INT_REPLY_READ_IN, + INT_ERROR_OUT => INT_ERROR_OUT, + STAT_BUFFER_COUNTER => STAT_BUFFER_COUNTER, + STAT_BUFFER => STAT_BUFFER + ); + +CLOCK_GEN_PROC: process +begin + clk <= '1'; wait for 5.0 ns; + clk <= '0'; wait for 5.0 ns; +end process CLOCK_GEN_PROC; + +THE_TESTBENCH_PROC: process +begin + -- Setup signals + reset <= '0'; + clk_en <= '1'; + med_dataready_in <= '0'; + med_data_in <= x"0000"; + med_packet_num_in <= b"000"; + med_error_in <= b"000"; + int_init_read_in <= '0'; + int_reply_read_in <= '0'; + wait for 33 ns; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + -- Tests may start here + + -- First packet + wait until rising_edge(clk); + med_data_in <= x"0001"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + + wait until rising_edge(clk); + wait until rising_edge(clk); + int_init_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + + -- Second packet + wait until rising_edge(clk); + med_data_in <= x"0001"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + + + + -- Third packet + wait until rising_edge(clk); + med_data_in <= x"0001"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + + -- Fourth packet + wait until rising_edge(clk); + med_data_in <= x"0009"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + int_reply_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + + -- Fifth packet + wait until rising_edge(clk); + med_data_in <= x"0009"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + -- Stay a while... stay forever!!! Muhahaha!!!! + wait; + +end process THE_TESTBENCH_PROC; + + +END; diff --git a/src/tb_trb_net_sbuf2.vhd b/src/tb_trb_net_sbuf2.vhd new file mode 100644 index 0000000..6684ad5 --- /dev/null +++ b/src/tb_trb_net_sbuf2.vhd @@ -0,0 +1,119 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT trb_net_sbuf2 + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + CLK_EN : IN std_logic; + COMB_DATAREADY_IN : IN std_logic; + COMB_READ_IN : IN std_logic; + COMB_DATA_IN : IN std_logic_vector(18 downto 0); + SYN_READ_IN : IN std_logic; + COMB_NEXT_READ_OUT : OUT std_logic; + SYN_DATAREADY_OUT : OUT std_logic; + SYN_DATA_OUT : OUT std_logic_vector(18 downto 0); + FIFO_WR_OUT : OUT std_logic; + FIFO_RD_OUT : OUT std_logic; + STAT_BUFFER : OUT std_logic + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL CLK_EN : std_logic; + SIGNAL COMB_DATAREADY_IN : std_logic; + SIGNAL COMB_NEXT_READ_OUT : std_logic; + SIGNAL COMB_READ_IN : std_logic; + SIGNAL COMB_DATA_IN : std_logic_vector(18 downto 0); + SIGNAL SYN_DATAREADY_OUT : std_logic; + SIGNAL SYN_DATA_OUT : std_logic_vector(18 downto 0); + SIGNAL SYN_READ_IN : std_logic; + signal FIFO_WR_OUT : std_logic; + signal FIFO_RD_OUT : std_logic; + SIGNAL STAT_BUFFER : std_logic; + +BEGIN + +-- Please check and add your generic clause manually + uut: trb_net_sbuf2 PORT MAP( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => COMB_DATAREADY_IN, + COMB_NEXT_READ_OUT => COMB_NEXT_READ_OUT, + COMB_READ_IN => COMB_READ_IN, + COMB_DATA_IN => COMB_DATA_IN, + SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, + SYN_DATA_OUT => SYN_DATA_OUT, + SYN_READ_IN => SYN_READ_IN, + FIFO_WR_OUT => FIFO_WR_OUT, + FIFO_RD_OUT => FIFO_RD_OUT, + STAT_BUFFER => STAT_BUFFER + ); + +CLOCK_GEN_PROC: process +begin + clk <= '1'; wait for 5.0 ns; + clk <= '0'; wait for 5.0 ns; +end process CLOCK_GEN_PROC; + +THE_TEST_BENCH_PROC: process +begin + -- Setup signals + reset <= '0'; + clk_en <= '1'; + comb_dataready_in <= '0'; + comb_read_in <= '0'; + comb_data_in <= (others => '0'); + syn_read_in <= '0'; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait until rising_edge(clk); + + -- Tests may start now... + -- see what happens if nothing is in the SBUF + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + -- now write some data in + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_read_in <= '1'; + comb_data_in <= b"100_0000_0000_0000_0000"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0001"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0010"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0011"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0100"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0101"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0110"; + wait until rising_edge(clk); + comb_data_in <= b"100_0000_0000_0000_0111"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + + -- Stay a while... stay forever! Muhahaha!!! + wait; + +end process THE_TEST_BENCH_PROC; + +END; \ No newline at end of file diff --git a/src/tb_trb_net_sbuf3.vhd b/src/tb_trb_net_sbuf3.vhd new file mode 100755 index 0000000..5f76c13 --- /dev/null +++ b/src/tb_trb_net_sbuf3.vhd @@ -0,0 +1,119 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT trb_net_sbuf3 + GENERIC( + DATA_WIDTH : integer := 18 + ); + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + CLK_EN : IN std_logic; + COMB_DATAREADY_IN : IN std_logic; + COMB_READ_IN : IN std_logic; + COMB_DATA_IN : IN std_logic_vector(17 downto 0); + SYN_READ_IN : IN std_logic; + COMB_NEXT_READ_OUT : OUT std_logic; + SYN_DATAREADY_OUT : OUT std_logic; + SYN_DATA_OUT : OUT std_logic_vector(17 downto 0); + DEBUG_OUT : OUT std_logic_vector(15 downto 0); + STAT_BUFFER : OUT std_logic + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL CLK_EN : std_logic; + SIGNAL COMB_DATAREADY_IN : std_logic; + SIGNAL COMB_NEXT_READ_OUT : std_logic; + SIGNAL COMB_READ_IN : std_logic; + SIGNAL COMB_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL SYN_DATAREADY_OUT : std_logic; + SIGNAL SYN_DATA_OUT : std_logic_vector(17 downto 0); + SIGNAL SYN_READ_IN : std_logic; + SIGNAL STAT_BUFFER : std_logic; + SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: trb_net_sbuf3 PORT MAP( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => COMB_DATAREADY_IN, + COMB_NEXT_READ_OUT => COMB_NEXT_READ_OUT, + COMB_READ_IN => COMB_READ_IN, + COMB_DATA_IN => COMB_DATA_IN, + SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, + SYN_DATA_OUT => SYN_DATA_OUT, + SYN_READ_IN => SYN_READ_IN, + DEBUG_OUT => DEBUG_OUT, + STAT_BUFFER => STAT_BUFFER + ); + +CLOCK_GEN_PROC: process +begin + clk <= '1'; wait for 5.0 ns; + clk <= '0'; wait for 5.0 ns; +end process CLOCK_GEN_PROC; + +THE_TEST_BENCH_PROC: process +begin + -- Setup signals + reset <= '0'; + clk_en <= '1'; + comb_dataready_in <= '0'; + comb_read_in <= '0'; + comb_data_in <= (others => '0'); + syn_read_in <= '0'; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait until rising_edge(clk); + + -- Tests may start now... + -- see what happens if nothing is in the SBUF + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + -- now write some data in + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_read_in <= '1'; + comb_data_in <= b"10_0000_0000_0000_0000"; + wait until rising_edge(clk); + comb_data_in <= b"10_0000_0000_0000_0001"; + wait until rising_edge(clk); + comb_data_in <= b"10_0000_0000_0000_0010"; + wait until rising_edge(clk); + comb_data_in <= b"10_0000_0000_0000_0011"; + wait until rising_edge(clk); + comb_data_in <= b"10_0000_0000_0000_0100"; + wait until rising_edge(clk); + comb_data_in <= b"10_0000_0000_0000_0101"; + wait until rising_edge(clk); + comb_data_in <= b"10_0000_0000_0000_0110"; + wait until rising_edge(clk); + comb_data_in <= b"10_0000_0000_0000_0111"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + + -- Stay a while... stay forever! Muhahaha!!! + wait; + +end process THE_TEST_BENCH_PROC; + +END; \ No newline at end of file diff --git a/src/test_fifo.lpc b/src/test_fifo.lpc new file mode 100755 index 0000000..e316e34 --- /dev/null +++ b/src/test_fifo.lpc @@ -0,0 +1,44 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.7 +ModuleName=test_fifo +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/14/2009 +Time=14:54:15 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=1024 +Width=18 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +EnECC=0 diff --git a/src/test_fifo.vhd b/src/test_fifo.vhd new file mode 100755 index 0000000..cc85678 --- /dev/null +++ b/src/test_fifo.vhd @@ -0,0 +1,853 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 4.7 +--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 1024 -width 18 -depth 1024 -no_enable -pe -1 -pf -1 -e + +-- Mon Dec 14 14:54:16 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity test_fifo is + port ( + Data: in std_logic_vector(17 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); +end test_fifo; + +architecture Structure of test_fifo is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal co5: std_logic; + signal cnt_con: std_logic; + signal co4: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal wren_i: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_10: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co3_3: std_logic; + signal iwcount_10: std_logic; + signal co5_1: std_logic; + signal wcount_10: std_logic; + signal co4_3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co1_4: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co2_4: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co3_4: std_logic; + signal ircount_10: std_logic; + signal co5_2: std_logic; + signal rcount_10: std_logic; + signal scuba_vlo: std_logic; + signal co4_4: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_1 : label is "0x3232"; + attribute initval of LUT4_0 : label is "0x3232"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "test_fifo.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "18"; + attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "18"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wcount_0, + ADA5=>wcount_1, ADA6=>wcount_2, ADA7=>wcount_3, + ADA8=>wcount_4, ADA9=>wcount_5, ADA10=>wcount_6, + ADA11=>wcount_7, ADA12=>wcount_8, ADA13=>wcount_9, + CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>rcount_0, ADB5=>rcount_1, + ADB6=>rcount_2, ADB7=>rcount_3, ADB8=>rcount_4, + ADB9=>rcount_5, ADB10=>rcount_6, ADB11=>rcount_7, + ADB12=>rcount_8, ADB13=>rcount_9, CEB=>rden_i, CLKB=>Clock, + WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), + DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), + DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11), + DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15), + DOB16=>Q(16), DOB17=>Q(17)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_25: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_24: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_23: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_21: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_20: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_19: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_18: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_17: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_15: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_14: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_13: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_12: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + bdcnt_bctr_5: CB2 + port map (CI=>co4, PC0=>fcount_10, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co5, NC0=>ifcount_10, NC1=>open); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>co4_1); + + e_cmp_5: ALEB2 + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + CI=>co3_2, GE=>co4_2); + + g_cmp_5: AGEB2 + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co4_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_ctr_5: CU2 + port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1, + NC0=>iwcount_10, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4, + NC0=>ircount_8, NC1=>ircount_9); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + r_ctr_5: CU2 + port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2, + NC0=>ircount_10, NC1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of test_fifo is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:ALEB2 use entity ecp2m.ALEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:CB2 use entity ecp2m.CB2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/test_fifo_tmpl.vhd b/src/test_fifo_tmpl.vhd new file mode 100755 index 0000000..aada74f --- /dev/null +++ b/src/test_fifo_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 4.7 +-- Mon Dec 14 14:54:16 2009 + +-- parameterized module component declaration +component test_fifo + port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : test_fifo + port map (Data(17 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(17 downto 0)=>__, Empty=>__, Full=>__); diff --git a/src/testfifo.lpc b/src/testfifo.lpc new file mode 100644 index 0000000..01bf25a --- /dev/null +++ b/src/testfifo.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.2 +ModuleName=testfifo +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/18/2009 +Time=17:17:38 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=256 +Width=96 +RDepth=256 +RWidth=96 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/src/testfifo.vhd b/src/testfifo.vhd new file mode 100644 index 0000000..a30d87a --- /dev/null +++ b/src/testfifo.vhd @@ -0,0 +1,1584 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 256 -width 96 -depth 256 -rdata_width 96 -no_enable -pe -1 -pf -1 -e + +-- Wed Nov 18 17:17:38 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity testfifo is + port ( + Data: in std_logic_vector(95 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(95 downto 0); + Empty: out std_logic; + Full: out std_logic); +end testfifo; + +architecture Structure of testfifo is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal co4: std_logic; + signal wcount_8: std_logic; + signal co3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal co4_1: std_logic; + signal rcount_8: std_logic; + signal co3_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KB + -- synopsys translate_off + generic (CSDECODE_R : in std_logic_vector(2 downto 0); + CSDECODE_W : in std_logic_vector(2 downto 0); + GSR : in String; RESETMODE : in String; + REGMODE : in String; DATA_WIDTH_R : in Integer; + DATA_WIDTH_W : in Integer); + -- synopsys translate_on + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_R : string; + attribute CSDECODE_W : string; + attribute RESETMODE : string; + attribute REGMODE : string; + attribute DATA_WIDTH_R : string; + attribute DATA_WIDTH_W : string; + attribute GSR : string; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "testfifo.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_2 : label is ""; + attribute CSDECODE_R of pdp_ram_0_0_2 : label is "0b000"; + attribute CSDECODE_W of pdp_ram_0_0_2 : label is "0b001"; + attribute GSR of pdp_ram_0_0_2 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_2 : label is "ASYNC"; + attribute REGMODE of pdp_ram_0_0_2 : label is "NOREG"; + attribute DATA_WIDTH_R of pdp_ram_0_0_2 : label is "36"; + attribute DATA_WIDTH_W of pdp_ram_0_0_2 : label is "36"; + attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "testfifo.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_1 : label is ""; + attribute CSDECODE_R of pdp_ram_0_1_1 : label is "0b000"; + attribute CSDECODE_W of pdp_ram_0_1_1 : label is "0b001"; + attribute GSR of pdp_ram_0_1_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_1_1 : label is "ASYNC"; + attribute REGMODE of pdp_ram_0_1_1 : label is "NOREG"; + attribute DATA_WIDTH_R of pdp_ram_0_1_1 : label is "36"; + attribute DATA_WIDTH_W of pdp_ram_0_1_1 : label is "36"; + attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "testfifo.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is ""; + attribute CSDECODE_R of pdp_ram_0_2_0 : label is "0b000"; + attribute CSDECODE_W of pdp_ram_0_2_0 : label is "0b001"; + attribute GSR of pdp_ram_0_2_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_2_0 : label is "ASYNC"; + attribute REGMODE of pdp_ram_0_2_0 : label is "NOREG"; + attribute DATA_WIDTH_R of pdp_ram_0_2_0 : label is "36"; + attribute DATA_WIDTH_W of pdp_ram_0_2_0 : label is "36"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t18: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t17: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t16: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t15: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t14: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t13: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t12: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t11: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t10: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t9: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t8: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t7: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t6: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t5: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t4: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t3: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t2: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t1: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t0: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_0); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_1); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>wcount_r6, DO0=>wcount_r3); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r2); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r20, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_0); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_1); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>rcount_w6, DO0=>rcount_w3); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w2); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w20, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_8, AD2=>rcount_8, AD1=>w_gcount_r28, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_8, AD2=>rcount_8, AD1=>w_gcount_r28, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w28, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w28, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_2: PDPW16KB + -- synopsys translate_off + generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, + ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, + ADR12=>rptr_7, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>RdClock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), + DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), + DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), + DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), + DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), + DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), + DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), + DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), + DO35=>Q(17)); + + pdp_ram_0_1_1: PDPW16KB + -- synopsys translate_off + generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), + DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), + DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), + DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), + DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), + DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), + DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), + DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), + DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, + ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, + ADW7=>wptr_7, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, + ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7, + ADR13=>scuba_vlo, CER=>rden_i, CLKR=>RdClock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>Q(54), DO1=>Q(55), DO2=>Q(56), DO3=>Q(57), + DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), DO7=>Q(61), DO8=>Q(62), + DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), DO12=>Q(66), + DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), DO16=>Q(70), + DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), DO20=>Q(38), + DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), DO24=>Q(42), + DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), DO28=>Q(46), + DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), DO32=>Q(50), + DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); + + pdp_ram_0_2_0: PDPW16KB + -- synopsys translate_off + generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(72), DI1=>Data(73), DI2=>Data(74), + DI3=>Data(75), DI4=>Data(76), DI5=>Data(77), DI6=>Data(78), + DI7=>Data(79), DI8=>Data(80), DI9=>Data(81), DI10=>Data(82), + DI11=>Data(83), DI12=>Data(84), DI13=>Data(85), + DI14=>Data(86), DI15=>Data(87), DI16=>Data(88), + DI17=>Data(89), DI18=>Data(90), DI19=>Data(91), + DI20=>Data(92), DI21=>Data(93), DI22=>Data(94), + DI23=>Data(95), DI24=>scuba_vlo, DI25=>scuba_vlo, + DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo, + DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, + DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, + DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, + ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, + ADW7=>wptr_7, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, + ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7, + ADR13=>scuba_vlo, CER=>rden_i, CLKR=>RdClock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>Q(90), DO1=>Q(91), DO2=>Q(92), DO3=>Q(93), + DO4=>Q(94), DO5=>Q(95), DO6=>open, DO7=>open, DO8=>open, + DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, + DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(72), + DO19=>Q(73), DO20=>Q(74), DO21=>Q(75), DO22=>Q(76), + DO23=>Q(77), DO24=>Q(78), DO25=>Q(79), DO26=>Q(80), + DO27=>Q(81), DO28=>Q(82), DO29=>Q(83), DO30=>Q(84), + DO31=>Q(85), DO32=>Q(86), DO33=>Q(87), DO34=>Q(88), + DO35=>Q(89)); + + FF_91: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_64: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_49: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_48: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_47: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_46: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_45: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_44: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_43: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_42: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_41: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_40: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_39: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_38: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4, + NC0=>iwcount_8, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>scuba_vlo, CO=>co4_1, + NC0=>ircount_8, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>w_g2b_xor_cluster_0, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co3_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>r_g2b_xor_cluster_0, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co3_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of testfifo is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/src/testfifo_tmpl.vhd b/src/testfifo_tmpl.vhd new file mode 100644 index 0000000..c802148 --- /dev/null +++ b/src/testfifo_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +-- Wed Nov 18 17:17:38 2009 + +-- parameterized module component declaration +component testfifo + port (Data: in std_logic_vector(95 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(95 downto 0); + Empty: out std_logic; Full: out std_logic); +end component; + +-- parameterized module component instance +__ : testfifo + port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/src/trb_net_sbuf2.vhd b/src/trb_net_sbuf2.vhd new file mode 100644 index 0000000..cfe04f8 --- /dev/null +++ b/src/trb_net_sbuf2.vhd @@ -0,0 +1,129 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +--library work; +--use work.trb_net_std.all; + +entity trb_net_sbuf2 is + generic( DATA_WIDTH : integer := 19; + VERSION : integer := 0 + ); + port( CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- connections to data source A + COMB_DATAREADY_IN : in std_logic; + COMB_NEXT_READ_OUT : out std_logic; + COMB_READ_IN : in std_logic; + COMB_DATA_IN : in std_logic_vector (DATA_WIDTH-1 downto 0); + -- connections to data sink B + SYN_DATAREADY_OUT : out std_logic; + SYN_DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0); + SYN_READ_IN : in std_logic; + -- status signals + FIFO_WR_OUT : out std_logic; + FIFO_RD_OUT : out std_logic; + STAT_BUFFER : out std_logic + ); +end trb_net_sbuf2; + +architecture trb_net_sbuf_arch of trb_net_sbuf2 is + + component fifo_sbuf is + port( Data : in std_logic_vector(18 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(18 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + signal fifo_data_in : std_logic_vector(18 downto 0); + signal fifo_data_out : std_logic_vector(18 downto 0); + signal reg_fifo_data_out : std_logic_vector(18 downto 0); + signal fifo_wr_en : std_logic; + signal fifo_rd_en : std_logic; + signal fifo_empty : std_logic; + signal fifo_full : std_logic; + signal fifo_almost_full : std_logic; + signal fifo_read_before : std_logic; + signal next_last_fifo_read : std_logic; + signal last_fifo_read : std_logic; + signal comb_next_read : std_logic; + +begin + +-- write to fifo if fifo is not full and data is available +fifo_data_in <= comb_data_in; +fifo_wr_en <= comb_dataready_in and comb_read_in and not fifo_full; +comb_next_read <= not fifo_almost_full; + +-- fifo read signal +--fifo_rd_en <= syn_read_in or not fifo_read_before; +fifo_rd_en <= syn_read_in or (not next_last_fifo_read and not fifo_read_before); + +-- the fifo +THE_BUFFER : fifo_sbuf +port map( Data => fifo_data_in, + Clock => clk, + WrEn => fifo_wr_en, + RdEn => fifo_rd_en, + Reset => reset, + Q => fifo_data_out, + Empty => fifo_empty, + Full => fifo_full, + AlmostFull => fifo_almost_full + ); + +-- is data on output valid? +PROC_DETECT_VALID_READS : process( clk ) +begin + if( rising_edge(CLK) ) then + if ( reset = '1' ) then + fifo_read_before <= '0'; + elsif( clk_en = '1' ) then + if ( next_last_fifo_read = '1' ) then + fifo_read_before <= '1'; + elsif( syn_read_in = '1' ) then + fifo_read_before <= '0'; + end if; + end if; + end if; +end process PROC_DETECT_VALID_READS; + +-- keep track of fifo read operations +PROC_LAST_FIFO_READ : process( clk ) +begin + if( rising_edge(clk) ) then + next_last_fifo_read <= fifo_rd_en and not fifo_empty; + last_fifo_read <= next_last_fifo_read and not RESET; + end if; +end process PROC_LAST_FIFO_READ; + +-- register on fifo outputs +PROC_SYNC_FIFO_OUTPUTS: process( clk ) +begin + if( rising_edge(clk) )then + if( next_last_fifo_read = '1' ) then + reg_fifo_data_out <= fifo_data_out; + end if; + end if; +end process PROC_SYNC_FIFO_OUTPUTS; + +-- connect to outputs +syn_dataready_out <= fifo_read_before; +syn_data_out <= reg_fifo_data_out; +comb_next_read_out <= comb_next_read; + +fifo_wr_out <= fifo_wr_en; +fifo_rd_out <= fifo_rd_en; + +stat_buffer <= fifo_full; + +end architecture; \ No newline at end of file diff --git a/src/trb_net_sbuf3.vhd b/src/trb_net_sbuf3.vhd new file mode 100755 index 0000000..0936bd3 --- /dev/null +++ b/src/trb_net_sbuf3.vhd @@ -0,0 +1,213 @@ + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +entity trb_net_sbuf3 is + generic( DATA_WIDTH : integer := 18 ); + port( -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN : in std_logic; --comb logic provides data word + COMB_next_READ_OUT : out std_logic; --sbuf can read in NEXT cycle + COMB_READ_IN : in std_logic; --comb logic IS reading + -- the COMB_next_READ_OUT should be connected via comb. logic to a register + -- to provide COMB_READ_IN (feedback path with 1 cycle delay) + COMB_DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0); -- Data word + -- Port to synchronous output. + SYN_DATAREADY_OUT : out std_logic; + SYN_DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Data word + SYN_READ_IN : in std_logic; + -- Status and control port + DEBUG_OUT : out std_logic_vector(15 downto 0); + STAT_BUFFER : out std_logic + ); +end entity; + +architecture trb_net_sbuf3_arch of trb_net_sbuf3 is + +signal current_b0_buffer : std_logic_vector (DATA_WIDTH-1 downto 0); +signal current_b1_buffer : std_logic_vector (DATA_WIDTH-1 downto 0); +signal current_b2_buffer : std_logic_vector (DATA_WIDTH-1 downto 0); + +signal next_next_READ_OUT : std_logic; +signal current_next_READ_OUT : std_logic; +signal next_SYN_DATAREADY_OUT : std_logic; +signal current_SYN_DATAREADY_OUT : std_logic; + +type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL,BUFFER_B0_FULL); +signal current_buffer_state : BUFFER_STATE; +signal next_buffer_state : BUFFER_STATE; +signal current_buffer_state_int : std_logic_vector(1 downto 0); + +signal current_got_overflow : std_logic; +signal next_got_overflow : std_logic; +signal combined_COMB_DATAREADY_IN : std_logic; + +signal move_b1_b2 : std_logic; +signal move_b0_b1 : std_logic; + +signal load_b2 : std_logic; +signal load_b1 : std_logic; +signal load_b0 : std_logic; + +signal debug : std_logic_vector(15 downto 0); + +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_preserve of current_SYN_DATAREADY_OUT : signal is true; +attribute syn_keep of current_SYN_DATAREADY_OUT : signal is true; +attribute syn_preserve of current_next_READ_OUT : signal is true; +attribute syn_keep of current_next_READ_OUT : signal is true; +attribute syn_hier : string; +attribute syn_hier of trb_net_sbuf3_arch : architecture is "flatten, firm"; + + +begin + +SYN_DATA_OUT <= current_b2_buffer; +SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT; +COMB_next_READ_OUT <= current_next_READ_OUT; + +STAT_BUFFER <= current_got_overflow; + +combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN); + +THE_FSM: process(current_buffer_state, SYN_READ_IN, + current_SYN_DATAREADY_OUT, current_got_overflow, + combined_COMB_DATAREADY_IN) +begin -- process COMB + next_buffer_state <= current_buffer_state; + next_next_READ_OUT <= '1'; + load_b0 <= '0'; + load_b1 <= '0'; + load_b2 <= '0'; + move_b1_b2 <= '0'; + move_b0_b1 <= '0'; + next_SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT; + next_got_overflow <= current_got_overflow; + + case current_buffer_state is + + when BUFFER_EMPTY => + current_buffer_state_int <= "00"; + if( combined_COMB_DATAREADY_IN = '1' ) then + next_buffer_state <= BUFFER_B2_FULL; + load_b2 <= '1'; + next_SYN_DATAREADY_OUT <= '1'; + end if; + + when BUFFER_B2_FULL => + current_buffer_state_int <= "01"; + next_SYN_DATAREADY_OUT <= '1'; + if ( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '1') ) then + load_b2 <= '1'; + elsif( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '0') ) then + next_buffer_state <= BUFFER_B1_FULL; + next_next_READ_OUT <= '0'; + load_b1 <= '1'; + elsif( (combined_COMB_DATAREADY_IN = '0') and (SYN_READ_IN = '1') ) then + next_buffer_state <= BUFFER_EMPTY; + next_SYN_DATAREADY_OUT <= '0'; + end if; + + when BUFFER_B1_FULL => + current_buffer_state_int <= "10"; + next_SYN_DATAREADY_OUT <= '1'; + next_next_READ_OUT <= '0'; + if ( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '1') ) then + load_b1 <= '1'; + move_b1_b2 <= '1'; + elsif( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '0') ) then + next_buffer_state <= BUFFER_B0_FULL; + load_b0 <= '1'; + elsif( (combined_COMB_DATAREADY_IN = '0') and (SYN_READ_IN = '1') ) then + next_buffer_state <= BUFFER_B2_FULL; + next_next_READ_OUT <= '1'; + move_b1_b2 <= '1'; + end if; + + when BUFFER_B0_FULL => + current_buffer_state_int <= "11"; + next_SYN_DATAREADY_OUT <= '1'; + next_next_READ_OUT <= '0'; + if ( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '0') ) then + next_got_overflow <= '1'; + elsif( (combined_COMB_DATAREADY_IN = '0') and (SYN_READ_IN = '1') ) then + move_b1_b2 <= '1'; + move_b0_b1 <= '1'; + next_buffer_state <= BUFFER_B1_FULL; + elsif( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '1') ) then + move_b1_b2 <= '1'; + move_b0_b1 <= '1'; + load_b0 <= '1'; + end if; + + end case; +end process; + +PROC_FSM_REG : process(CLK) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + current_buffer_state <= BUFFER_EMPTY; + current_got_overflow <= '0'; + current_SYN_DATAREADY_OUT <= '0'; + current_next_READ_OUT <= '0'; + elsif( CLK_EN = '1' ) then + current_buffer_state <= next_buffer_state; + current_got_overflow <= next_got_overflow; + current_SYN_DATAREADY_OUT <= next_SYN_DATAREADY_OUT; + current_next_READ_OUT <= next_next_READ_OUT; + end if; + end if; +end process; + + +PROC_REG_BUFFERS : process(CLK) +begin + if( rising_edge(CLK) ) then + if move_b1_b2 = '1' then + current_b2_buffer <= current_b1_buffer; + end if; + + if move_b0_b1 = '1' then + current_b1_buffer <= current_b0_buffer; + end if; + + if load_b2 = '1' then + current_b2_buffer <= COMB_DATA_IN; + end if; + + if load_b1 = '1' then + current_b1_buffer <= COMB_DATA_IN; + end if; + + if load_b0 = '1' then + current_b0_buffer <= COMB_DATA_IN; + end if; + end if; +end process; + +-- Debug signals +debug(15 downto 14) <= current_buffer_state_int; + +debug(13 downto 6) <= (others => '0'); + +debug(5) <= move_b1_b2; +debug(4) <= move_b0_b1; +debug(3) <= '0'; +debug(2) <= load_b2; +debug(1) <= load_b1; +debug(0) <= load_b0; + +debug_out <= debug; + +end architecture; + diff --git a/src/version.vhd b/src/version.vhd new file mode 100644 index 0000000..45d398a --- /dev/null +++ b/src/version.vhd @@ -0,0 +1,14 @@ + +--## attention, automatically generated. Don't change by hand. +library ieee; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use ieee.numeric_std.all; + +package version is + + constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := CONV_STD_LOGIC_VECTOR(1264600226,32); + +end package version; +