From: Tobias Weber Date: Sat, 28 Apr 2018 16:31:00 +0000 (+0200) Subject: moving serdes readout into mupix board entity. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f6fa12414f88b4d9e1169b0d949f64a0b91e3311;p=trb3.git moving serdes readout into mupix board entity. --- diff --git a/base/trb3_periph_mupix8.lpf b/base/trb3_periph_mupix8.lpf index 7f3f8e4..82b9d43 100644 --- a/base/trb3_periph_mupix8.lpf +++ b/base/trb3_periph_mupix8.lpf @@ -112,7 +112,7 @@ IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; ################################################################# #MuPix 8 ################################################################# -LOCATE COMP "mupix_data_link/the_mupix_serdes/PCSD_INST" SITE "PCSB"; +LOCATE COMP "MupixBoard8_0/mupix_data_link/the_mupix_serdes/PCSD_INST" SITE "PCSB"; LOCATE COMP "led_addon_0" SITE "P1"; LOCATE COMP "led_addon_1" SITE "P2"; diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index 7dc00a0..5b13b01 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -16,9 +16,10 @@ use work.StdTypes.all; entity MupixBoard8 is port( --Clock signal - clk : in std_logic; - fast_clk : in std_logic; - reset : in std_logic; + clk : in std_logic; --trb system clock for slow control + fast_clk : in std_logic; --200 MHz clock for hitbus sampling + data_clk : in std_logic; --mupix clock + reset : in std_logic; --reset input --slow control signals testpulse : out std_logic; --generate injection pulse @@ -38,11 +39,8 @@ entity MupixBoard8 is spi_ld_thres : out std_logic; --load threshold and injection dac hitbus : in std_logic; --hitbus signal - --connections to data fifos - fifo_rden : out std_logic_vector(3 downto 0); -- read enable to mupix data FIFOs - fifo_empty : in std_logic_vector(3 downto 0); -- mupix data FIFO empty flags - fifo_full : in std_logic_vector(3 downto 0); -- mupix data FIFO full flags - fifo_data : in std_logic_vector(127 downto 0); -- mupix readout data from FIFOs + mupix_data : in std_logic_vector(7 downto 0); --serdes data link from mupix + channel_status_led : out std_logic_vector(3 downto 0); --status leds of serdes connection --resets timestampreset_in : in std_logic; --time stamp reset @@ -121,11 +119,11 @@ architecture Behavioral of MupixBoard8 is signal hit_sync : std_logic; signal testpulse_i : std_logic; - signal spi_clk_i : std_logic; - signal spi_din_i : std_logic; - signal spi_ld_tmp_dac_i : std_logic; - signal spi_cs_adc_i : std_logic; - signal spi_ld_thres_i : std_logic; + signal spi_clk_i : std_logic; + signal spi_din_i : std_logic; + signal spi_ld_tmp_dac_i : std_logic; + signal spi_cs_adc_i : std_logic; + signal spi_ld_thres_i : std_logic; component HitbusHistogram generic( @@ -286,6 +284,32 @@ architecture Behavioral of MupixBoard8 is SLV_UNKNOWN_ADDR_OUT : out std_logic ); end component FrameGeneratorMux; + + component MupixDataLink is + port( + sysclk : in std_logic; + dataclk : in std_logic; + rst : in std_logic; + clear : in std_logic; + rst_fifo : in std_logic; + mupix_data : in std_logic_vector(7 downto 0); + refclk2core : out std_logic; + clk_rx_half_out : out std_logic; + clk_rx_full_out : out std_logic; + fifo_rden : in std_logic_vector(3 downto 0); + fifo_empty : out std_logic_vector(3 downto 0); + fifo_full : out std_logic_vector(3 downto 0); + fifo_data : out std_logic_vector(127 downto 0); + channel_status_led : out std_logic_vector(3 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic); + end component MupixDataLink; constant FIFO_DEPTH : positive := 256; --size of pseudo data generator fifos constant DATA_WIDTH : natural := 32; --width of datawords @@ -297,7 +321,7 @@ architecture Behavioral of MupixBoard8 is --signal declarations -- Bus Handler - constant NUM_PORTS : integer := 6; + constant NUM_PORTS : integer := 7; signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); @@ -312,6 +336,12 @@ architecture Behavioral of MupixBoard8 is signal mupixreadout_busy_i : std_logic; signal mupixdata_valid_i : std_logic; signal mupixdata_i : std_logic_vector(31 downto 0); + + --connections between mupix data fifos and mupix board + signal fifo_rden_serdes_i : std_logic_vector(3 downto 0); + signal fifo_empty_serdes_i : std_logic_vector(3 downto 0); + signal fifo_full_serdes_i : std_logic_vector(3 downto 0); + signal fifo_data_serdes_i : std_logic_vector(127 downto 0); begin -- Behavioral @@ -329,7 +359,8 @@ begin -- Behavioral 2 => x"0090", -- Board Control 3 => x"0100", -- mupix readout 4 => x"0120", -- trigger handler - 5 => x"0140", -- hit generator + 5 => x"0140", -- hit generator + 6 => x"0160", -- mupix serdes others => x"0000"), PORT_ADDR_MASK => ( 0 => 4, -- HitBus Histograms @@ -337,7 +368,8 @@ begin -- Behavioral 2 => 4, -- Board Control 3 => 4, -- mupix readout 4 => 4, -- trigger handler - 5 => 4, -- hit generator + 5 => 4, -- hit generator + 6 => 4, -- mupix serdes others => 0) --PORT_MASK_ENABLE => 1 ) @@ -553,11 +585,11 @@ begin -- Behavioral port map( clk => clk, reset => reset, - serdes_data => fifo_data, - serdes_fifo_full => fifo_full, - serdes_fifo_empty => fifo_empty, - serdes_fifo_rden => fifo_rden, - in_rden => mux_fifo_rden, + serdes_data => fifo_data_serdes_i, + serdes_fifo_full => fifo_full_serdes_i, + serdes_fifo_empty => fifo_empty_serdes_i, + serdes_fifo_rden => fifo_rden_serdes_i, + in_rden => mux_fifo_rden, out_data => mux_fifo_data, out_fifo_full => mux_fifo_full, out_fifo_empty => mux_fifo_empty, @@ -571,5 +603,31 @@ begin -- Behavioral SLV_NO_MORE_DATA_OUT => slv_no_more_data(5), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5) ); + + mupix_data_link : entity work.MupixDataLink + port map( + sysclk => clk, + dataclk => data_clk, + rst => reset, + clear => reset, + mupix_data => mupix_data, + refclk2core => open, + clk_rx_half_out => open, + clk_rx_full_out => open, + fifo_rden => fifo_rden_serdes_i, + fifo_empty => fifo_empty_serdes_i, + fifo_full => fifo_full_serdes_i, + fifo_data => fifo_data_serdes_i, + --misc + channel_status_led => channel_status_led, + --trb slow control + SLV_READ_IN => slv_read(6), + SLV_WRITE_IN => slv_write(6), + SLV_DATA_OUT => slv_data_rd(6*32 + 31 downto 6*32), + SLV_DATA_IN => slv_data_wr(6*32 + 31 downto 6*32), + SLV_ADDR_IN => slv_addr(6*16 + 15 downto 6*16), + SLV_ACK_OUT => slv_ack(6), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6)); end Behavioral; diff --git a/mupix/Mupix8/sources/MupixDataLink.vhd b/mupix/Mupix8/sources/MupixDataLink.vhd index bd663d7..68f83d7 100644 --- a/mupix/Mupix8/sources/MupixDataLink.vhd +++ b/mupix/Mupix8/sources/MupixDataLink.vhd @@ -12,7 +12,6 @@ entity MupixDataLink is dataclk : in std_logic; --mupix link clock from FPGA PLL(50 - 150 MHz) rst : in std_logic; --synchronous reset clear : in std_logic; --asynchronous reset - rst_fifo : in std_logic; --synchronous fifo reset --lattice serdes mupix_data : in std_logic_vector(7 downto 0); --lvds pairs of 4 incoming data channels refclk2core : out std_logic; --reference clk from serdes (not really needed since clock sync is done internally with FIFOs?) @@ -74,6 +73,8 @@ architecture rtl of MupixDataLink is type error_cnt_type is array (0 to c_used_serdes_channels - 1) of unsigned(31 downto 0); signal error_cnt : error_cnt_type := (others => (others => '0')); + signal reset_data_fifo_i : std_logic := '0'; + component InputSynchronizer generic(depth : integer := 2; width : integer := 1); @@ -271,8 +272,8 @@ begin RdClock => sysclk, WrEn => fifo_wren(i), RdEn => fifo_rden(i), - Reset => rst_fifo, - RPReset => rst_fifo, + Reset => reset_data_fifo_i, + RPReset => reset_data_fifo_i, Q => fifo_data((i + 1)*32 - 1 downto i*32), RCNT => serdes_fifo_rdcnt_i((i + 1)*c_serdes_fifo_rdcnt_width - 1 downto i*c_serdes_fifo_rdcnt_width), Empty => fifo_empty(i), @@ -287,8 +288,8 @@ begin RdClock => sysclk, WrEn => fifo_wren(3), RdEn => fifo_rden(3), - Reset => rst_fifo, - RPReset => rst_fifo, + Reset => reset_data_fifo_i, + RPReset => reset_data_fifo_i, Q => fifo_data(4*32 - 1 downto 3*32), RCNT => serdes_fifo_large_rdcnt_i, Empty => fifo_empty(3), @@ -359,52 +360,50 @@ begin SLV_NO_MORE_DATA_OUT <= '0'; SLV_ACK_OUT <= '0'; reset_error_cnt_i <= '0'; + reset_data_fifo_i <= '0'; if SLV_READ_IN = '1' then case SLV_ADDR_IN is - when x"0000" => --read counters are already synchronous to trb system clock + when x"0160" => --read counters are already synchronous to trb system clock SLV_DATA_OUT(c_serdes_fifo_rdcnt_width - 1 downto 0) <= serdes_fifo_rdcnt_i(c_serdes_fifo_rdcnt_width - 1 downto 0); SLV_ACK_OUT <= '1'; - when x"0001" => + when x"0161" => SLV_DATA_OUT(c_serdes_fifo_rdcnt_width - 1 downto 0) <= serdes_fifo_rdcnt_i(2*c_serdes_fifo_rdcnt_width - 1 downto c_serdes_fifo_rdcnt_width); SLV_ACK_OUT <= '1'; - when x"0002" => + when x"0162" => SLV_DATA_OUT(c_serdes_fifo_rdcnt_width - 1 downto 0) <= serdes_fifo_rdcnt_i(3*c_serdes_fifo_rdcnt_width - 1 downto 2*c_serdes_fifo_rdcnt_width); SLV_ACK_OUT <= '1'; - when x"0003" => + when x"0163" => SLV_DATA_OUT(c_serdes_fifo_large_rdcnt_width - 1 downto 0) <= serdes_fifo_large_rdcnt_i; SLV_ACK_OUT <= '1'; - when x"0004" => + when x"0164" => SLV_DATA_OUT(2 downto 0) <= rx_cdr_lol_s_sync(0) & rx_los_low_s_sync(0) & lsm_status_s_sync(0); SLV_DATA_OUT(4 downto 3) <= rx_disp_err(0) & rx_cv_err(0); SLV_ACK_OUT <= '1'; - when x"0005" => + when x"0165" => SLV_DATA_OUT(2 downto 0) <= rx_cdr_lol_s_sync(1) & rx_los_low_s_sync(1) & lsm_status_s_sync(1); SLV_DATA_OUT(4 downto 3) <= rx_disp_err(1) & rx_cv_err(1); SLV_ACK_OUT <= '1'; - when x"0006" => + when x"0166" => SLV_DATA_OUT(2 downto 0) <= rx_cdr_lol_s_sync(2) & rx_los_low_s_sync(2) & lsm_status_s_sync(2); SLV_DATA_OUT(4 downto 3) <= rx_disp_err(2) & rx_cv_err(2); SLV_ACK_OUT <= '1'; - when x"0007" => + when x"0167" => SLV_DATA_OUT(2 downto 0) <= rx_cdr_lol_s_sync(3) & rx_los_low_s_sync(3) & lsm_status_s_sync(3); SLV_DATA_OUT(4 downto 3) <= rx_disp_err(3) & rx_cv_err(3); SLV_ACK_OUT <= '1'; - when x"0008" => + when x"0168" => SLV_DATA_OUT <= std_logic_vector(error_cnt(0)); SLV_ACK_OUT <= '1'; - when x"0009" => + when x"0169" => SLV_DATA_OUT <= std_logic_vector(error_cnt(1)); SLV_ACK_OUT <= '1'; - when x"000a" => + when x"016a" => SLV_DATA_OUT <= std_logic_vector(error_cnt(2)); SLV_ACK_OUT <= '1'; - when x"000b" => + when x"016b" => SLV_DATA_OUT <= std_logic_vector(error_cnt(3)); SLV_ACK_OUT <= '1'; - when x"000c" => - SLV_DATA_OUT <= x"aabbccdd"; - SLV_ACK_OUT <= '1'; when others => SLV_UNKNOWN_ADDR_OUT <= '1'; end case; @@ -412,9 +411,12 @@ begin if SLV_WRITE_IN = '1' then case SLV_ADDR_IN is - when x"000c" => + when x"016c" => reset_error_cnt_i <= SLV_DATA_IN(0); SLV_ACK_OUT <= '1'; + when x"016d" => + reset_data_fifo_i <= SLV_DATA_IN(0); + SLV_ACK_OUT <= '1'; when others => SLV_UNKNOWN_ADDR_OUT <= '1'; end case; diff --git a/mupix/Mupix8/sources/MupixTRBReadout.vhd b/mupix/Mupix8/sources/MupixTRBReadout.vhd index f30c929..77e8d40 100644 --- a/mupix/Mupix8/sources/MupixTRBReadout.vhd +++ b/mupix/Mupix8/sources/MupixTRBReadout.vhd @@ -265,6 +265,7 @@ begin --0x108: circular memory empty/full flags, fill cnt (read-only) --0x109: circular memory input word frequency (read-only) --0x10a: circular memory output word frequency (read-only) + --0x10b: readout controller read-enable (debug read-only) ----------------------------------------------------------------------------------- slv_bus_handler : process(clk) is begin @@ -351,6 +352,9 @@ begin when x"010a" => SLV_DATA_OUT <= cycl_outword_freq; SLV_ACK_OUT <= '1'; + when x"010b" => + SLV_DATA_OUT(3 downto 0) <= busy & start_readout & start_readout_slow_to_buffer & trb_trigger; + SLV_ACK_OUT <= '1'; when others => slv_unknown_addr_out <= '1'; end case; diff --git a/mupix/Mupix8/sources/ResetHandler.vhd b/mupix/Mupix8/sources/ResetHandler.vhd index 3453b3e..12e98ce 100644 --- a/mupix/Mupix8/sources/ResetHandler.vhd +++ b/mupix/Mupix8/sources/ResetHandler.vhd @@ -14,7 +14,6 @@ entity resethandler is RESET_IN : in std_logic; -- reset input timestampreset_out : out std_logic; -- reset FPGA timestamps eventcounterreset_out : out std_logic; -- reset FPGA event counters - mupixdata_reset_out : out std_logic; -- reset data structures holding mupix data -- Slave bus SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -30,10 +29,8 @@ architecture behavioral of resethandler is signal timestampreset_i : std_logic := '0'; signal eventcounterreset_i : std_logic := '0'; - signal mupixdata_reset_i : std_logic := '0'; signal timestampreset_edge : std_logic_vector(1 downto 0) := (others => '0'); signal eventcounterreset_edge : std_logic_vector(1 downto 0) := (others => '0'); - signal mupixdatareset_edge : std_logic_vector(1 downto 0) := (others => '0'); begin -- architecture behavioral @@ -72,30 +69,12 @@ begin -- architecture behavioral end if; end process eventcounter_edge_detect; - data_struct_reset : process (CLK_IN) is - begin - if rising_edge(CLK_IN) then - if reset_in = '1' then - mupixdatareset_edge <= (others => '0'); - mupixdata_reset_out <= '0'; - else - mupixdatareset_edge <= mupixdatareset_edge(0) & mupixdata_reset_i; - if mupixdatareset_edge = "01" then - mupixdata_reset_out <= '1'; - else - mupixdata_reset_out <= '0'; - end if; - end if; - end if; - end process data_struct_reset; - ------------------------------------------------------------ --TRB SLV-BUS Hanlder ------------------------------------------------------------ --0x0001: reset timestamps --0x0002: reset eventcounter - --0x0003: reset data structures slv_bus_handler : process(CLK_IN) is begin -- process slv_bus_handler if rising_edge(CLK_IN) then @@ -112,9 +91,6 @@ begin -- architecture behavioral when x"0002" => eventcounterreset_i <= SLV_DATA_IN(0); slv_ack_out <= '1'; - when x"0003" => - mupixdata_reset_i <= SLV_DATA_IN(0); - slv_ack_out <= '1'; when others => slv_unknown_addr_out <= '1'; end case; @@ -128,9 +104,6 @@ begin -- architecture behavioral when x"0002" => slv_data_out(0) <= eventcounterreset_i; slv_ack_out <= '1'; - when x"0003" => - slv_data_out(0) <= mupixdata_reset_i; - slv_ack_out <= '1'; when others => slv_unknown_addr_out <= '1'; end case; diff --git a/mupix/Mupix8/trb3_periph.vhd b/mupix/Mupix8/trb3_periph.vhd index 67adcb1..bb15ba1 100644 --- a/mupix/Mupix8/trb3_periph.vhd +++ b/mupix/Mupix8/trb3_periph.vhd @@ -130,6 +130,7 @@ architecture trb3_periph_arch of trb3_periph is --Clock signal clk : in std_logic; fast_clk : in std_logic; + data_clk : in std_logic; reset : in std_logic; --slow control signals @@ -150,12 +151,9 @@ architecture trb3_periph_arch of trb3_periph is spi_ld_thres : out std_logic; --load threshold and injection dac hitbus : in std_logic; --hitbus signal - --connections to data fifos - fifo_rden : out std_logic_vector(3 downto 0); - fifo_empty : in std_logic_vector(3 downto 0); - fifo_full : in std_logic_vector(3 downto 0); - fifo_data : in std_logic_vector(127 downto 0); - + mupix_data : in std_logic_vector(7 downto 0); + channel_status_led : out std_logic_vector(3 downto 0); + --resets timestampreset_in : in std_logic; --time stamp reset eventcounterreset_in : in std_logic; --event number reset @@ -209,32 +207,6 @@ architecture trb3_periph_arch of trb3_periph is SLV_UNKNOWN_ADDR_OUT : out std_logic); end component resethandler; - component MupixDataLink is - port( - sysclk : in std_logic; - dataclk : in std_logic; - rst : in std_logic; - clear : in std_logic; - rst_fifo : in std_logic; - mupix_data : in std_logic_vector(7 downto 0); - refclk2core : out std_logic; - clk_rx_half_out : out std_logic; - clk_rx_full_out : out std_logic; - fifo_rden : in std_logic_vector(3 downto 0); - fifo_empty : out std_logic_vector(3 downto 0); - fifo_full : out std_logic_vector(3 downto 0); - fifo_data : out std_logic_vector(127 downto 0); - channel_status_led : out std_logic_vector(3 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic); - end component MupixDataLink; - component pll_mupix_main port (CLK : in std_logic; CLKOP : out std_logic; @@ -378,22 +350,9 @@ architecture trb3_periph_arch of trb3_periph is signal mu_regio_no_more_data_out_0 : std_logic; signal mu_regio_unknown_addr_out_0 : std_logic; - -- MuPix data link Regio Bus - signal mupixdata_regio_addr_in_0 : std_logic_vector (15 downto 0) := (others => '0'); - signal mupixdata_regio_data_in_0 : std_logic_vector (31 downto 0); - signal mupixdata_regio_data_out_0 : std_logic_vector (31 downto 0); - signal mupixdata_regio_read_enable_in_0 : std_logic; - signal mupixdata_regio_write_enable_in_0 : std_logic; - signal mupixdata_regio_timeout_in_0 : std_logic; - signal mupixdata_regio_dataready_out_0 : std_logic; - signal mupixdata_regio_ack_out_0 : std_logic; - signal mupixdata_regio_no_more_data_out_0 : std_logic; - signal mupixdata_regio_unknown_addr_out_0 : std_logic; - --common reset signals for mupix frontends signal reset_timestamps_i : std_logic; signal reset_eventcounters_i : std_logic; - signal reset_mupixdata_i : std_logic; signal resethandler_regio_addr_in_0 : std_logic_vector (15 downto 0) := (others => '0'); signal resethandler_regio_data_in_0 : std_logic_vector (31 downto 0); signal resethandler_regio_data_out_0 : std_logic_vector (31 downto 0); @@ -404,12 +363,6 @@ architecture trb3_periph_arch of trb3_periph is signal resethandler_regio_no_more_data_out_0 : std_logic; signal resethandler_regio_unknown_addr_out_0 : std_logic; - --connections between mupix data fifos and mupix board - signal fifo_rden_i : std_logic_vector(3 downto 0); - signal fifo_empty_i : std_logic_vector(3 downto 0); - signal fifo_full_i : std_logic_vector(3 downto 0); - signal fifo_data_i : std_logic_vector(127 downto 0); - --dummy signal dummy_counter : integer range 0 to 8 := 0; signal mupix_clk_i : std_logic; @@ -625,18 +578,16 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 5, + PORT_NUMBER => 4, PORT_ADDRESSES => (0 => x"d000", -- spi master 1 => x"d100", -- spi memory 2 => x"8000", -- Mupix 0 - 3 => x"9000", -- data link from mupix - 4 => x"c000", -- Reset + 3 => x"c000", -- Reset others => x"0000"), PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 12, - 3 => 12, - 4 => 12, + 3 => 12, others => 0) ) port map( @@ -693,31 +644,18 @@ begin BUS_NO_MORE_DATA_IN(2) => mu_regio_no_more_data_out_0, BUS_UNKNOWN_ADDR_IN(2) => mu_regio_unknown_addr_out_0, - --mupix data link - BUS_READ_ENABLE_OUT(3) => mupixdata_regio_read_enable_in_0, - BUS_WRITE_ENABLE_OUT(3) => mupixdata_regio_write_enable_in_0, - BUS_DATA_OUT(3*32+31 downto 3*32) => mupixdata_regio_data_in_0, - BUS_ADDR_OUT(3*16+11 downto 3*16) => mupixdata_regio_addr_in_0(11 downto 0), + --Common Reset + BUS_READ_ENABLE_OUT(3) => resethandler_regio_read_enable_in_0, + BUS_WRITE_ENABLE_OUT(3) => resethandler_regio_write_enable_in_0, + BUS_DATA_OUT(3*32+31 downto 3*32) => resethandler_regio_data_in_0, + BUS_ADDR_OUT(3*16+11 downto 3*16) => resethandler_regio_addr_in_0(11 downto 0), BUS_ADDR_OUT(3*16+15 downto 3*16+12) => open, BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => mupixdata_regio_data_out_0, - BUS_DATAREADY_IN(3) => mupixdata_regio_ack_out_0, - BUS_WRITE_ACK_IN(3) => mupixdata_regio_ack_out_0, - BUS_NO_MORE_DATA_IN(3) => mupixdata_regio_no_more_data_out_0, - BUS_UNKNOWN_ADDR_IN(3) => mupixdata_regio_unknown_addr_out_0, - - --Common Reset - BUS_READ_ENABLE_OUT(4) => resethandler_regio_read_enable_in_0, - BUS_WRITE_ENABLE_OUT(4) => resethandler_regio_write_enable_in_0, - BUS_DATA_OUT(4*32+31 downto 4*32) => resethandler_regio_data_in_0, - BUS_ADDR_OUT(4*16+11 downto 4*16) => resethandler_regio_addr_in_0(11 downto 0), - BUS_ADDR_OUT(4*16+15 downto 4*16+12) => open, - BUS_TIMEOUT_OUT(4) => open, - BUS_DATA_IN(4*32+31 downto 4*32) => resethandler_regio_data_out_0, - BUS_DATAREADY_IN(4) => resethandler_regio_ack_out_0, - BUS_WRITE_ACK_IN(4) => resethandler_regio_ack_out_0, - BUS_NO_MORE_DATA_IN(4) => resethandler_regio_no_more_data_out_0, - BUS_UNKNOWN_ADDR_IN(4) => resethandler_regio_unknown_addr_out_0, + BUS_DATA_IN(3*32+31 downto 3*32) => resethandler_regio_data_out_0, + BUS_DATAREADY_IN(3) => resethandler_regio_ack_out_0, + BUS_WRITE_ACK_IN(3) => resethandler_regio_ack_out_0, + BUS_NO_MORE_DATA_IN(3) => resethandler_regio_no_more_data_out_0, + BUS_UNKNOWN_ADDR_IN(3) => resethandler_regio_unknown_addr_out_0, STAT_DEBUG => open ); @@ -798,16 +736,15 @@ begin port map ( clk => clk_100_i, fast_clk => clk_200_i, + data_clk => mupix_clk_i, reset => reset_i, timestampreset_in => reset_timestamps_i, eventcounterreset_in => reset_eventcounters_i, - fifo_rden => fifo_rden_i, - fifo_empty => fifo_empty_i, - fifo_full => fifo_full_i, - fifo_data => fifo_data_i, - + mupix_data => mupix_serdes_rx, + channel_status_led => led_line, + --slow control signals testpulse => testpulse, ctrl_din => ctrl_din, @@ -856,41 +793,12 @@ begin REGIO_UNKNOWN_ADDR_OUT => mu_regio_unknown_addr_out_0); - mupix_data_link : entity work.MupixDataLink - port map( - sysclk => clk_100_i, - dataclk => mupix_clk_i, - rst => reset_i, - clear => clear_i, - rst_fifo => reset_mupixdata_i, - mupix_data => mupix_serdes_rx, - refclk2core => open, - clk_rx_half_out => open, - clk_rx_full_out => open, - fifo_rden => fifo_rden_i, - fifo_empty => fifo_empty_i, - fifo_full => fifo_full_i, - fifo_data => fifo_data_i, - --misc - channel_status_led => led_addon, - --trb slow control - SLV_READ_IN => mupixdata_regio_read_enable_in_0, - SLV_WRITE_IN => mupixdata_regio_write_enable_in_0, - SLV_DATA_OUT => mupixdata_regio_data_out_0, - SLV_DATA_IN => mupixdata_regio_data_in_0, - SLV_ADDR_IN => mupixdata_regio_addr_in_0, - SLV_ACK_OUT => mupixdata_regio_ack_out_0, - SLV_NO_MORE_DATA_OUT => mupixdata_regio_no_more_data_out_0, - SLV_UNKNOWN_ADDR_OUT => mupixdata_regio_unknown_addr_out_0); - - resethandler_1 : entity work.resethandler port map ( CLK_IN => clk_100_i, RESET_IN => reset_i, TimestampReset_OUT => reset_timestamps_i, EventCounterReset_OUT => reset_eventcounters_i, - mupixdata_reset_out => reset_mupixdata_i, SLV_READ_IN => resethandler_regio_read_enable_in_0, SLV_WRITE_IN => resethandler_regio_write_enable_in_0, SLV_DATA_OUT => resethandler_regio_data_out_0,