From: hadeshyp Date: Fri, 8 Oct 2010 14:08:50 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f78d3d567e4518fe9dab66b614aa393f13742022;p=mdcoep.git *** empty log message *** --- diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl index adef833..0241344 100755 --- a/compile_frankfurt.pl +++ b/compile_frankfurt.pl @@ -100,7 +100,7 @@ $c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p " execute($c); print Dumper $ENV{LM_LICENSE_FILE}; - +$ENV{'LM_LICENSE_FILE'}="1702\@localhost"; my $tpmap = $TOPNAME . "_map" ; diff --git a/design2/data_handler.vhd b/design2/data_handler.vhd index d7d41a3..abf7788 100644 --- a/design2/data_handler.vhd +++ b/design2/data_handler.vhd @@ -313,6 +313,10 @@ begin data_i <= word_dummy; data_write_buf := '1'; dummy_counter <= dummy_counter + to_unsigned(1,1); + else + data_i <= word_dummy; + data_write_buf := '0'; + dummy_counter <= dummy_counter; end if; if FINISHED_READOUT_IN = '1' then current_state <= FINISH; diff --git a/design2/load_mode_line.vhd b/design2/load_mode_line.vhd index 18b365d..08e24a8 100644 --- a/design2/load_mode_line.vhd +++ b/design2/load_mode_line.vhd @@ -9,9 +9,7 @@ use work.trb_net_components.all; entity load_mode_line is - generic ( - timecounter_width : integer := 13 - ); + port( CLK : in std_logic; RESET : in std_logic; @@ -36,6 +34,7 @@ entity load_mode_line is START_DEBUG_READOUT_OUT : out std_logic; TDC_SETTINGS_WRITTEN : out std_logic; CAL1_WRITTEN : out std_logic; + TIMEOUT_OUT : out std_logic; --Debug DEBUG_REGISTER : out std_logic_vector(31 downto 0) @@ -58,7 +57,9 @@ architecture Behavioral of load_mode_line is --ok for 25MHz --constant time_limit : std_logic_vector(width - 1 downto 0) := "0011111010000"; - constant time_limit : unsigned(timecounter_width - 1 downto 0) := (others => '1'); + + constant timecounter_width : integer := 16; + signal time_limit : unsigned(timecounter_width - 1 downto 0); type state_type is (idle_state, reset_mode_state, jtag_state, init_state, @@ -82,12 +83,12 @@ architecture Behavioral of load_mode_line is set_mode_after_loaded_CAL1, dummy_calibration_state); - signal current_state : state_type; - signal next_state : state_type; + signal current_state : state_type; + signal next_state : state_type; - signal time_counter : unsigned(timecounter_width - 1 downto 0); - signal clear_time_counter : std_logic; - signal reg_MODD : std_logic; + signal time_counter : unsigned(timecounter_width-1 downto 0); + signal clear_time_counter : std_logic; + signal reg_MODD : std_logic; signal reg_RES : std_logic; signal reg_TOK : std_logic; signal reg_WRM : std_logic; @@ -96,21 +97,25 @@ architecture Behavioral of load_mode_line is signal reg_start_load_tdc_settings : std_logic; signal next_start_load_tdc_settings : std_logic; - signal reg_TDC_SETTINGS_WRITTEN : std_logic; - signal next_TDC_SETTINGS_WRITTEN : std_logic; - signal reg_cal1_written : std_logic; - signal next_cal1_written : std_logic; + signal reg_TDC_SETTINGS_WRITTEN : std_logic; + signal next_TDC_SETTINGS_WRITTEN : std_logic; + signal reg_cal1_written : std_logic; + signal next_cal1_written : std_logic; + signal next_timeout : std_logic; + signal reg_timeout : std_logic; - signal next_do_debug_readout : std_logic; - signal reg_do_debug_readout : std_logic; + signal next_do_debug_readout : std_logic; + signal reg_do_debug_readout : std_logic; - signal reg_state_bits : std_logic_vector(7 downto 0); - signal next_state_bits : std_logic_vector(7 downto 0); + signal reg_state_bits : std_logic_vector(7 downto 0); + signal next_state_bits : std_logic_vector(7 downto 0); signal next_MOD_RES_TOK_WRM_RDM_GDE : std_logic_vector(5 downto 0); begin + time_limit <= to_unsigned(2**13-1,timecounter_width); + ------------------------------------------------------------------------------- -- I/O ------------------------------------------------------------------------------- @@ -124,7 +129,7 @@ begin START_DEBUG_READOUT_OUT <= reg_do_debug_readout; TDC_SETTINGS_WRITTEN <= reg_TDC_SETTINGS_WRITTEN; CAL1_WRITTEN <= reg_cal1_written; - + TIMEOUT_OUT <= reg_timeout; ------------------------------------------------------------------------------- -- FSM ------------------------------------------------------------------------------- @@ -145,6 +150,7 @@ begin reg_cal1_written <= '0'; reg_do_debug_readout <= '0'; reg_TDC_SETTINGS_WRITTEN <= '0'; + reg_timeout <= '0'; else current_state <= next_state; reg_GDE <= next_MOD_RES_TOK_WRM_RDM_GDE(0); @@ -158,6 +164,7 @@ begin reg_state_bits <= next_state_bits; reg_cal1_written <= next_cal1_written; reg_do_debug_readout <= next_do_debug_readout; + reg_timeout <= next_timeout; end if; end if; end process; @@ -175,6 +182,7 @@ begin clear_time_counter <= '0'; next_state <= current_state; next_do_debug_readout <= '0'; + next_timeout <= '0'; case current_state is @@ -286,7 +294,7 @@ begin when wait_state => --wait until finished loading TDC settings next_state_bits <= x"0A"; next_MOD_RES_TOK_WRM_RDM_GDE <= "001001"; -- hex 48 - clear_time_counter <= '1'; + clear_time_counter <= '1'; if TDC_SETTING_LOADED_IN = '1' then next_state <= debug_readout; next_do_debug_readout <= '1'; @@ -295,9 +303,11 @@ begin when debug_readout => --here the MBO sends back data next_state_bits <= x"DD"; next_MOD_RES_TOK_WRM_RDM_GDE <= "011111"; -- hex 6D - clear_time_counter <= '1'; if RDO = '1' then next_state <= set_mode_after_loaded_ROC1; + elsif time_counter(timecounter_width-1) = '1' then + next_state <= idle_state; + next_timeout <= '1'; end if; diff --git a/design2/mdc_control.vhd b/design2/mdc_control.vhd index 512b65f..693c919 100644 --- a/design2/mdc_control.vhd +++ b/design2/mdc_control.vhd @@ -182,8 +182,8 @@ begin ------------------------------------------------------------------------------- TRIGGER_OUT <= ((TRIGGER_IN xor switch_polarity) and cms_active_i) or trigger_pseudo_tmg_long; - TRIGGER_MONITOR_OUT <= ((TRIGGER_IN xor switch_polarity) and cms_active_i) or trigger_pseudo_tmg_long; - + --TRIGGER_MONITOR_OUT <= ((TRIGGER_IN xor switch_polarity) and cms_active_i) or trigger_pseudo_tmg_long; + TRIGGER_MONITOR_OUT <= TRIGGER_IN; PULSE_PSEUDO_TIMING : process(CLK) begin @@ -531,7 +531,7 @@ counter_retransmit_sent_i <= (others => '0'); proc_statistics_ctr : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or reset_statistics_i = '1' then + if reset_statistics_i = '1' then counter_discarded_hit1_i <= (others => '0'); counter_discarded_hit0_i <= (others => '0'); counter_calib_i <= (others => '0'); diff --git a/design2/mdc_oepb_pack.vhd b/design2/mdc_oepb_pack.vhd index 07f6414..2c85160 100644 --- a/design2/mdc_oepb_pack.vhd +++ b/design2/mdc_oepb_pack.vhd @@ -234,9 +234,6 @@ package mdc_oepb_pack is component load_mode_line is - generic ( - timecounter_width : integer := 13 - ); port( CLK : in std_logic; RESET : in std_logic; @@ -261,7 +258,7 @@ package mdc_oepb_pack is START_DEBUG_READOUT_OUT : out std_logic; TDC_SETTINGS_WRITTEN : out std_logic; CAL1_WRITTEN : out std_logic; - + TIMEOUT_OUT : out std_logic; --Debug DEBUG_REGISTER : out std_logic_vector(31 downto 0) ); diff --git a/design2/trigger_begrun_state.vhd b/design2/trigger_begrun_state.vhd index 72a9fe9..603c12f 100644 --- a/design2/trigger_begrun_state.vhd +++ b/design2/trigger_begrun_state.vhd @@ -43,6 +43,7 @@ entity trigger_begrun_state is FINISHED_BEGRUN_OUT : out std_logic; FINISHED_LOAD_CALIB_OUT : out std_logic; START_DEBUG_READOUT_OUT : out std_logic; + TIMEOUT_OUT : out std_logic; DEBUG_REGISTER : out std_logic_vector(31 downto 0); DEBUG_REGISTER_LOAD_MODE : out std_logic_vector(31 downto 0); DEBUG_REGISTER_LOAD_TDC : out std_logic_vector(31 downto 0) @@ -97,6 +98,8 @@ architecture Behavioral of trigger_begrun_state is signal state_load_mode_line_i : std_logic_vector(7 downto 0); signal state_load_tdc_setup_i : std_logic_vector(7 downto 0); + signal timeout_i : std_logic; + begin FINISHED_BEGRUN_OUT <= finished_begrun_i; @@ -109,11 +112,9 @@ begin state_load_tdc_setup_i <= debug_register_load_tdc_setup_i(7 downto 0); DEBUG_REGISTER_LOAD_MODE <= debug_register_load_mode_line_i; DEBUG_REGISTER_LOAD_TDC <= debug_register_load_tdc_setup_i; + TIMEOUT_OUT <= timeout_i; MODE_LINE : load_mode_line - generic map( - timecounter_width => 13 - ) port map( CLK => CLK, RESET => reset_i, @@ -135,6 +136,7 @@ begin START_DEBUG_READOUT_OUT => start_debug_readout_i, TDC_SETTINGS_WRITTEN => finished_begrun_i, CAL1_WRITTEN => finished_load_calib_i, + TIMEOUT_OUT => timeout_i, --Debug DEBUG_REGISTER => debug_register_load_mode_line_i ); diff --git a/design2/trigger_handler.vhd b/design2/trigger_handler.vhd index eea9c58..81d0ff2 100644 --- a/design2/trigger_handler.vhd +++ b/design2/trigger_handler.vhd @@ -135,11 +135,11 @@ begin elsif LVL1_VALID_NOTIMING_TRG_IN = '1' and LVL1_TRG_TYPE_IN = x"E" then current_state <= WAIT_FOR_FINISHED_STORING; start_send_data_i <= '1'; - elsif LVL1_VALID_NOTIMING_TRG_IN = '1' then + elsif LVL1_VALID_NOTIMING_TRG_IN = '1' or LVL1_INVALID_TRG_IN = '1' then start_readout_i <= '1'; --dummy to get trigger released current_state <= RELEASE_LVL1; end if; - elsif LVL1_VALID_NOTIMING_TRG_IN = '1' or LVL1_VALID_TIMING_TRG_IN = '1' then + elsif LVL1_VALID_NOTIMING_TRG_IN = '1' or LVL1_VALID_TIMING_TRG_IN = '1' or LVL1_INVALID_TRG_IN = '1' then current_state <= RELEASE_LVL1; end if; @@ -153,6 +153,12 @@ begin end if; mbo_configured_i <= '1'; finished_readout_i <= '1'; + elsif TOKEN_MISSING_IN = '1' then + mbo_configured_i <= '0'; + reinit_running <= '1'; + inc_reinit_counter <= '1'; + reset_mbo_i <= '1'; + current_state <= DO_REINIT; end if; when DO_REINIT => diff --git a/mdc_oepb.prj b/mdc_oepb.prj index 603491b..ba46a66 100644 --- a/mdc_oepb.prj +++ b/mdc_oepb.prj @@ -9,6 +9,7 @@ add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_CRC8.vhd" add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd" add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" add_file -vhdl -lib work "../trbnet/basics/ram.vhd" @@ -20,6 +21,8 @@ add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" add_file -vhdl -lib work "../trbnet/basics/ram_dp.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd" add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf6.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" @@ -75,7 +78,9 @@ add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x16_dualport.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_8bit_16bit_bram_dualport.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16b_16b_dualport.vhd" diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index cb64139..e543930 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -1,7 +1,8 @@ LIBRARY ieee; use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - +-- USE IEEE.numeric_std.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.trb_net_std.all; use work.mdc_oepb_pack.all; @@ -100,7 +101,7 @@ architecture mdc_oepb_arch of mdc_oepb is signal reset_internal : std_logic; signal reset_sync : std_logic; signal reset_async : std_logic; - signal reset_counter : unsigned(23 downto 0); + signal reset_counter : std_logic_vector(23 downto 0); signal gsr_n : std_logic; --Media Interface to internal logic @@ -191,7 +192,7 @@ architecture mdc_oepb_arch of mdc_oepb is --Flash control signal delayed_restart_fpga : std_logic; - signal restart_fpga_counter : unsigned(11 downto 0); + signal restart_fpga_counter : std_logic_vector(11 downto 0); signal flash_rom_read : std_logic; signal flash_rom_write : std_logic; signal next_flash_rom_select : std_logic; @@ -260,15 +261,35 @@ architecture mdc_oepb_arch of mdc_oepb is signal led_blink : std_logic; signal blink_enable : std_logic; - signal time_counter : unsigned(9 downto 0); + signal time_counter : std_logic_vector(9 downto 0); signal debug_data_handler_i : std_logic_vector(31 downto 0); signal debug_ipu_handler_i : std_logic_vector(31 downto 0); - signal med_stat_reg_i : std_logic_vector(31 downto 0); + signal med_stat_reg_i : std_logic_vector(127 downto 0); signal buf_reset_led : std_logic; signal buf_restart_led : std_logic; signal buf_request_led : std_logic; + signal toggle1 : std_logic; + signal counter1 : std_logic_vector(11 downto 0); + signal read1 : std_logic; + signal dataready1 : std_logic; + signal number1 : std_logic_vector(2 downto 0); + signal data1 : std_logic_vector(15 downto 0); + + signal toggle2 : std_logic; + signal counter2 : std_logic_vector(11 downto 0); + signal read2 : std_logic; + signal dataready2 : std_logic; + signal number2 : std_logic_vector(2 downto 0); + signal data2 : std_logic_vector(15 downto 0); + + signal medreg_addr : std_logic_vector(1 downto 0); + signal medreg_data : std_logic_vector(31 downto 0); + signal medreg_read : std_logic; + signal medreg_ready: std_logic; + signal medreg_write: std_logic; + begin --------------------------------------------------------------------- @@ -312,7 +333,7 @@ begin begin if rising_edge(CLK) then if MED_STAT_OP(13) = '1' or pll_locked = '0' then --pll not locked or reset request received - reset_counter <= x"00000E"; + reset_counter <= x"000E00"; reset_internal <= '1'; reset_startup <= '1'; elsif MED_STAT_OP(14) = '1' and reset_counter >= x"000F00" then --no cable connected @@ -377,8 +398,9 @@ begin REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,--3, --8 cotrol reg ADDRESS_MASK => x"F37F", BROADCAST_BITMASK => x"FD", - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + REGIO_COMPILE_TIME => conv_std_logic_vector(VERSION_NUMBER_TIME,32), REGIO_HARDWARE_VERSION => x"23000001", + REGIO_INIT_ADDRESS => x"f0eb", CLOCK_FREQUENCY => 100, TIMING_TRIGGER_RAW => c_YES, --Configure data handler @@ -394,14 +416,14 @@ begin CLK => clk_100, RESET => reset_internal, CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, - MED_DATA_OUT => med_data_out, - MED_PACKET_NUM_OUT => med_packet_num_out, + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- MED_READ_IN => med_read_in, MED_DATAREADY_IN => med_dataready_in, MED_DATA_IN => med_data_in, MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, + MED_READ_OUT => med_read_out, -- open, -- MED_STAT_OP_IN => med_stat_op, MED_CTRL_OP_OUT => med_ctrl_op, @@ -473,11 +495,11 @@ begin THE_REG_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 9, + PORT_NUMBER => 10, PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"d200", - 5 => x"e000", 6 => x"9000", 7 => x"e100", 8 => x"9100", others => x"0000"), + 5 => x"e000", 6 => x"9000", 7 => x"e100", 8 => x"9100", 9 => x"9200", others => x"0000"), PORT_ADDR_MASK => (0 => 9, 1 => 6, 2 => 1, 3 => 6, 4 => 0, - 5 => 0, 6 => 4, 7 => 0, 8 => 4, others => 0) + 5 => 0, 6 => 4, 7 => 0, 8 => 4, 9 => 2, others => 0) ) port map( CLK => clk_100, @@ -602,6 +624,18 @@ begin BUS_WRITE_ACK_IN(8) => '0', BUS_NO_MORE_DATA_IN(8) => '0', BUS_UNKNOWN_ADDR_IN(8) => statisticreg_write, + --Media Interface + BUS_READ_ENABLE_OUT(9) => medreg_read, + BUS_WRITE_ENABLE_OUT(9) => medreg_write, + BUS_DATA_OUT(9*32+31 downto 9*32) => open, + BUS_ADDR_OUT(9*16+1 downto 9*16) => medreg_addr, + BUS_ADDR_OUT(9*16+15 downto 9*16+2) => open, + BUS_TIMEOUT_OUT(9) => open, + BUS_DATA_IN(9*32+31 downto 9*32) => medreg_data, + BUS_DATAREADY_IN(9) => medreg_ready, + BUS_WRITE_ACK_IN(9) => '0', + BUS_NO_MORE_DATA_IN(9) => '0', + BUS_UNKNOWN_ADDR_IN(9) => medreg_write, --Debugging STAT_DEBUG => open ); @@ -715,6 +749,18 @@ begin end if; end process; +------------------------------------------------------------------------------- +-- Media Interface Register +------------------------------------------------------------------------------- + PROC_LSM_STAT : process(clk_100, medreg_addr) + variable tmp : integer range 0 to 3; + begin + tmp := conv_integer(medreg_addr); + if rising_edge(clk_100) then + medreg_ready <= medreg_read; + medreg_data <= med_stat_reg_i(tmp*32+31 downto tmp*32); + end if; + end process; ------------------------------------------------------------------------------- -- Readback FiFo (used for Debugging) @@ -757,42 +803,6 @@ begin end if; end process; --- DEBUG_OUT( 0) <= dat_fifo_read(0); --- DEBUG_OUT( 1) <= dat_fifo_valid_read; --- DEBUG_OUT( 2) <= ipu_dataready_i; --- DEBUG_OUT( 3) <= ipu_read_in; --- DEBUG_OUT( 7 downto 4) <= DAT_DATA_FLAGS_IN(3 downto 0); --- DEBUG_OUT(11 downto 8) <= state_bits; --- DEBUG_OUT(16) <= data_buffer_write(0); --- DEBUG_OUT(17) <= IPU_DATA_READ_IN(0); --- DEBUG_OUT(23 downto 20) <= data_buffer_data_in(35 downto 32); - --- handler_ipu --- STATUS_OUT( 3 downto 0) <= state_bits; --- STATUS_OUT( 4) <= dat_fifo_read(0); --- STATUS_OUT( 5) <= dat_fifo_valid_read; --- STATUS_OUT( 6) <= ipu_dataready_i; --- STATUS_OUT( 7) <= ipu_read_in; --- STATUS_OUT(11 downto 8) <= DAT_DATA_FLAGS_IN(3 downto 0); --- STATUS_OUT(11 downto 4) <= (others => '0'); --- STATUS_OUT(12) <= error_not_found; --- STATUS_OUT(13) <= error_missing; --- STATUS_OUT(14) <= error_sync; --- STATUS_OUT(15) <= error_not_configured; --- STATUS_OUT(31 downto 16) <= (others => '0'); --- --- --- handler_data --- DEBUG_OUT(0) <= data_buffer_write(0); --- DEBUG_OUT(1) <= IPU_DATA_READ_IN(0); --- DEBUG_OUT(3 downto 2) <= "00"; --- DEBUG_OUT(7 downto 4) <= data_buffer_data_in(35 downto 32); --- DEBUG_OUT(10 downto 8) <= lvl1_state_bits; --- DEBUG_OUT(11) <= '0'; --- DEBUG_OUT(14 downto 12) <= buffer_state_bits(0); --- DEBUG_OUT(31 downto 15) <= (others => '0'); - - --------------------------------------------------------------------- -- Select Flash FF --------------------------------------------------------------------- @@ -839,14 +849,14 @@ begin CLK => clk_100, RESET => reset_internal, - A_ADD => open,--TAD, - A_AOD => open,--TAOD, - A_DST => open,--TDST, - A_RDM => open,--RDYI, - A_GDE => open,--GDE, + A_ADD => TAD, --open,-- + A_AOD => TAOD, --open,-- + A_DST => TDST, --open,-- + A_RDM => RDYI, --open,-- + A_GDE => GDE, --open,-- A_RDO => TRDYO, - A_MOD => open,--MODD, - A_RES => open,--RES, + A_MOD => MODD, --open,-- + A_RES => RES, --open,-- A_TOK => TOK, A_WRM => WRM, A_RESERVE => TRSV, @@ -900,22 +910,141 @@ begin DEBUG_OUT => debug_mdc_control_i ); + + +--------------------------------------------------------------------- +--Test... +--------------------------------------------------------------------- +-- process(clk_100) +-- begin +-- if rising_edge(clk_100) then +-- if reset_internal = '1' then +-- number1 <= "100"; +-- dataready1 <= '0'; +-- toggle1 <= '0'; +-- counter1 <= (others => '0'); +-- else +-- if ((counter1 < 19 and toggle1 = '1') or (counter1 < 14 and toggle1 = '0')) or +-- (((counter1 < 20 and toggle1 = '1') or (counter1 < 15 and toggle1 = '0')) and read1 = '0') then +-- dataready1 <= '1'; +-- if read1 = '1' and dataready1 = '1' then +-- counter1 <= counter1 + 1; +-- end if; +-- else +-- dataready1 <= '0'; +-- if counter1 = 1800 then +-- counter1 <= (others => '0'); +-- toggle1 <= not toggle1; +-- else +-- counter1 <= counter1 + 1; +-- end if; +-- end if; +-- if read1 = '1' and dataready1 = '1' then +-- if number1 = "100" then +-- number1 <= "000"; +-- else +-- number1 <= number1 + 1; +-- end if; +-- end if; +-- end if; +-- end if; +-- end process; +-- +-- process(clk_100) +-- begin +-- if rising_edge(clk_100) then +-- if reset_internal = '1' then +-- number2 <= "100"; +-- dataready2 <= '0'; +-- toggle2 <= '0'; +-- counter2 <= (others => '0'); +-- else +-- if ((counter2 < 24 and toggle2 = '1') or (counter2 < 19 and toggle2 = '0')) or +-- (((counter2 < 25 and toggle2 = '1') or (counter2 < 20 and toggle2 = '0')) and read2 = '0') then +-- dataready2 <= '1'; +-- if read2 = '1' and dataready2 = '1' then +-- counter2 <= counter2 + 1; +-- end if; +-- else +-- dataready2 <= '0'; +-- if counter2 = 2047 then +-- counter2 <= (others => '0'); +-- toggle2 <= not toggle2; +-- else +-- counter2 <= counter2 + 1; +-- end if; +-- end if; +-- if read2 = '1' and dataready2 = '1' then +-- if number2 = "100" then +-- number2 <= "000"; +-- else +-- number2 <= number2 + 1; +-- end if; +-- end if; +-- end if; +-- end if; +-- end process; +-- +-- data1 <= (counter1(7 downto 0)) & (counter1(7 downto 0)); +-- data2 <= (counter2(7 downto 0)) & (counter2(7 downto 0)); +-- +-- the_test_mux : trb_net16_io_multiplexer +-- generic map ( +-- USE_INPUT_SBUF => (others => c_NO) +-- ) +-- port map( +-- -- Misc +-- CLK => clk_100, +-- RESET => reset_internal, +-- CLK_EN => '1', +-- -- Media direction port +-- MED_DATAREADY_IN => med_dataready_in, +-- MED_DATA_IN => med_data_in, +-- MED_PACKET_NUM_IN => med_packet_num_in, +-- MED_READ_OUT => med_read_out, +-- MED_DATAREADY_OUT => med_dataready_out, +-- MED_DATA_OUT => med_data_out, +-- MED_PACKET_NUM_OUT => med_packet_num_out, +-- MED_READ_IN => med_read_in, +-- -- Internal direction port +-- INT_DATA_OUT => open, +-- INT_PACKET_NUM_OUT => open, +-- INT_DATAREADY_OUT => open, +-- INT_READ_IN => (others => '1'), +-- INT_DATAREADY_IN(0) => dataready1, +-- INT_DATAREADY_IN(1) => '0', +-- INT_DATAREADY_IN(2) => dataready2, +-- INT_DATAREADY_IN(7 downto 3) => (others => '0'), +-- INT_DATA_IN(15 downto 0) => data1, +-- INT_DATA_IN(31 downto 16) => (others => '0'), +-- INT_DATA_IN(47 downto 32) => data2, +-- INT_DATA_IN(127 downto 48) => (others => '0'), +-- INT_PACKET_NUM_IN(2 downto 0) => number1, +-- INT_PACKET_NUM_IN(5 downto 3) => "000", +-- INT_PACKET_NUM_IN(8 downto 6) => number2, +-- INT_PACKET_NUM_IN(23 downto 9)=> (others => '0'), +-- INT_READ_OUT(0) => read1, +-- INT_READ_OUT(2) => read2, +-- ctrl => (others => '0') +-- ); + + ------------------------------------------------------------------------------- -- LED ------------------------------------------------------------------------------- --- D(4) <= not buf_restart_led; -- toggle with restart --- D(3) <= not buf_request_led; -- toggle with request --- D(2) <= not buf_reset_led; -- toggle with network reset --- D(1) <= med_stat_debug(51); -- not comma locked + D(4) <= not buf_restart_led; -- toggle with restart + D(3) <= not buf_request_led; -- toggle with request + D(2) <= not buf_reset_led; -- toggle with network reset + D(1) <= med_stat_debug(51); -- not comma locked + -D <= not MED_STAT_OP(7 downto 4); process(clk_100) begin if rising_edge(clk_100) then if timer_ticks(1) = '1' then - time_counter <= time_counter + to_unsigned(1,1); + time_counter <= time_counter + 1; end if; if blink_enable = '1' then @@ -934,20 +1063,24 @@ D <= not MED_STAT_OP(7 downto 4); buf_request_led <= not buf_request_led; end if; - - -TAD(3 downto 0) <= MED_STAT_OP(7 downto 4); -TAD(4) <= reset_internal; -TAD(5) <= reset_startup; -TAD(6) <= reset_async; -TAD(7) <= MED_STAT_DEBUG(49); -TAD(8) <= MED_STAT_DEBUG(50); -TAOD <= MED_STAT_DEBUG(51); -TDST <= MED_STAT_DEBUG(52); -RDYI <= MED_STAT_DEBUG(53); -GDE <= MED_STAT_DEBUG(54); -MODD <= MED_STAT_DEBUG(55); -RES <= MED_STAT_DEBUG(63); +-- TAD(7 downto 0) <= med_stat_debug(39 downto 32); +-- TAD(8) <= med_stat_debug(62); +-- TAOD <= med_stat_op(8); +-- TDST <= med_stat_op(12); + + +-- TAD(3 downto 0) <= MED_STAT_OP(7 downto 4); +-- TAD(4) <= reset_internal; +-- TAD(5) <= reset_startup; +-- TAD(6) <= reset_async; +-- TAD(7) <= MED_STAT_DEBUG(49); +-- TAD(8) <= MED_STAT_DEBUG(50); +-- TAOD <= MED_STAT_DEBUG(51); +-- TDST <= MED_STAT_DEBUG(52); +-- RDYI <= MED_STAT_DEBUG(53); +-- GDE <= MED_STAT_DEBUG(54); +-- MODD <= MED_STAT_DEBUG(55); +-- RES <= MED_STAT_DEBUG(63); end if; end process; @@ -961,14 +1094,7 @@ RES <= MED_STAT_DEBUG(63); reg_common_stat_reg_in(159 downto 144) <= (others => '0'); blink_enable <= reg_registers_out(32); -------------------------------------------------------------------------------- --- pins not used -------------------------------------------------------------------------------- --- STAT_DEBUG(16) <= request_retransmit_i; --- STAT_DEBUG(17) <= start_retransmit_i; --- STAT_DEBUG(25 downto 18) <= rx_data; --- STAT_DEBUG(26) <= rx_k; --- STAT_DEBUG(31 downto 27) <= (others => '0'); + ------------------------------------------------------------------------------- -- SEU circuit -------------------------------------------------------------------------------