From: Jan Michel Date: Wed, 3 Mar 2021 14:37:33 +0000 (+0100) Subject: Update TDC Project and Config files X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f7b33f379360e3b9bbeaf98b014815b4163d9c58;p=trb3.git Update TDC Project and Config files --- diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd index e671bf3..40e50bc 100644 --- a/32PinAddOn/config.vhd +++ b/32PinAddOn/config.vhd @@ -12,14 +12,14 @@ package config is --TDC settings constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 9; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 3; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, -- 3: same channel with stretcher - constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size -- mode: 0, 1, 2, 3, 7 -- size: 32, 64, 96, 128, dyn constant TDC_DATA_FORMAT : integer range 0 to 15 := 0; --type of data format for the TDC diff --git a/ADA_Addon/config.vhd b/ADA_Addon/config.vhd index fc0c011..0ceb7e6 100644 --- a/ADA_Addon/config.vhd +++ b/ADA_Addon/config.vhd @@ -12,8 +12,8 @@ package config is --TDC settings constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 17; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, @@ -28,17 +28,17 @@ package config is -- 13: Debug - single fine time and the chain for the 0x3ff hits -- 14: Debug - single fine time and the ROM addresses for the two transitions -- 15: Debug - complete carry chain dump - constant USE_PINOUT : integer := 3; --1: normal, 3: every 4th channel (HPTDC) + constant USE_PINOUT : integer := 1; --1: normal, 3: every 4th channel (HPTDC) constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N constant EVENT_MAX_SIZE : integer := 1000; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 --Include SPI on AddOn connector - constant INCLUDE_UART : integer := c_YES; + constant INCLUDE_UART : integer := c_NO; constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_NO; - constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --constant SPI_FOR_PADI : integer := c_NO; -- YES: PADI SPI NO: Normal SPI --Add logic to generate configurable trigger signal from input signals. @@ -57,7 +57,7 @@ package config is --Address settings constant INIT_ADDRESS : std_logic_vector := x"F305"; - constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"48"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"47"; --47: TOF ------------------------------------------------------------------------------ --End of design configuration diff --git a/ADA_Addon/config_compile_frankfurt.pl b/ADA_Addon/config_compile_frankfurt.pl index d2785ec..2b17a74 100644 --- a/ADA_Addon/config_compile_frankfurt.pl +++ b/ADA_Addon/config_compile_frankfurt.pl @@ -2,8 +2,8 @@ TOPNAME => "trb3_periph_ADA", project_path => "ADA_Addon", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', -synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', # synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", diff --git a/ADA_Addon/trb3_periph_ADA.prj b/ADA_Addon/trb3_periph_ADA.prj index 74f4af5..6cfeea3 100644 --- a/ADA_Addon/trb3_periph_ADA.prj +++ b/ADA_Addon/trb3_periph_ADA.prj @@ -86,7 +86,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" diff --git a/gpin/config_compile_frankfurt.pl b/gpin/config_compile_frankfurt.pl index ad46ca4..465a029 100644 --- a/gpin/config_compile_frankfurt.pl +++ b/gpin/config_compile_frankfurt.pl @@ -2,8 +2,8 @@ TOPNAME => "trb3_periph_gpin", project_path => "gpin", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', -synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', +synplify_path => '/d/jspc29/lattice/synplify/P-2019.09-SP1/', # synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", diff --git a/gpin/trb3_periph_gpin.prj b/gpin/trb3_periph_gpin.prj index 64aef30..09f6cd4 100644 --- a/gpin/trb3_periph_gpin.prj +++ b/gpin/trb3_periph_gpin.prj @@ -83,7 +83,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" diff --git a/trb3_gbe/trb3_central_gbe.prj b/trb3_gbe/trb3_central_gbe.prj index cb2e081..378b9f8 100644 --- a/trb3_gbe/trb3_central_gbe.prj +++ b/trb3_gbe/trb3_central_gbe.prj @@ -69,6 +69,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/uart.vhd" @@ -134,10 +135,12 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vh #trbnet and base files -add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_accel.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_accel.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_record.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" @@ -172,6 +175,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" + add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" diff --git a/wasa/config.vhd b/wasa/config.vhd index 9968ce0..f4e3ba0 100644 --- a/wasa/config.vhd +++ b/wasa/config.vhd @@ -13,8 +13,8 @@ package config is --TDC settings constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 49; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, @@ -45,7 +45,7 @@ package config is --Add logic to generate configurable trigger signal from input signals. constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; constant INCLUDE_STATISTICS : integer := c_YES; --Do histos of all inputs - constant PHYSICAL_INPUTS : integer := 48; --number of inputs connected + constant PHYSICAL_INPUTS : integer := 52; --number of inputs connected constant TRIG_GEN_OUTPUT_NUM : integer := 4; constant MONITOR_INPUT_NUM : integer := PHYSICAL_INPUTS+TRIG_GEN_OUTPUT_NUM; constant TRIG_GEN_INPUT_NUM : integer := PHYSICAL_INPUTS; diff --git a/wasa/par.p2t b/wasa/par.p2t index 37870ba..a9f6917 100644 --- a/wasa/par.p2t +++ b/wasa/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 12 --t 1 +-t 8 -c 1 -e 2 -i 15 diff --git a/wasa/trb3_periph_padiwa.prj b/wasa/trb3_periph_padiwa.prj index a24e88c..971b09a 100644 --- a/wasa/trb3_periph_padiwa.prj +++ b/wasa/trb3_periph_padiwa.prj @@ -84,7 +84,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" @@ -145,7 +145,8 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.v add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" -add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" +#add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib work "../base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../base/code/input_statistics.vhd" add_file -vhdl -lib work "../base/code/sedcheck.vhd"