From: hadeshyp Date: Fri, 14 Dec 2007 15:24:34 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~657 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f845df7d856073020e3c27512a93dc9747f3fd0a;p=trbnet.git *** empty log message *** --- diff --git a/compile_hub.pl b/compile_hub.pl deleted file mode 100755 index a190b52..0000000 --- a/compile_hub.pl +++ /dev/null @@ -1,135 +0,0 @@ -#!/usr/bin/perl -########################################### -# Script file to run the flow -# -########################################### -# -# Command line for synplify_pro -# - - -use FileHandle; - - -$ENV{LM_LICENSE_FILE}="1709\@hadeb05"; - - - -$PLD_DEVICE="LFSCM3GA25EP1-5FFN1020C"; -$TOPNAME="hub"; - - - -#set -e -#set -o errexit - -system("env| grep LM_"); -$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; -#$c=("( netcat -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)& /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj"); -$r=execute($c, "do_not_exit" ); - - - -chdir "workdir"; -my $fh = new FileHandle("; -$fh -> close; - -#if ($r) { -#$c="cat $TOPNAME.srr"; -#system($c); -#exit 129; -#} - -foreach (@a) -{ - if(/\@E:/) - { - $c="cat $TOPNAME.srr"; - system($c); - print "bdabdhsadbhjasdhasldhbas"; - exit 129; - } -} -#if (0){ - -#$c=("/opt/lattice/isplever7.0/isptools/ispcpld/bin/checkini -err=automake.err /opt/lattice/isplever7.0/isptools/ispcpld/config/or5s00.ini"); - - -#$c=("/opt/lattice/isplever7.0/isptools/ispcpld/bin/edfin -i hub.edf -jhd hub.jhd -log hub.log -dev orca -lbp \"/opt/lattice/isplever7.0/isptools/ispfpga/data\""); - -#$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/lci2prf -oc hub.lct -log hub.log ../hub.lpf"); - -#$c=("export FOUNDRY=\"/opt/lattice/isplever7.0/isptools/ispfpga\""); - -#$c=("export LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH:/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin\""); - -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/edif2ngd -l LatticeSCM -d LFSCM3GA25EP1 \"hub.edf\" \"hub.ngo\""); -execute($c); -execute($c); - -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/edfupdate -t \"hub.tcy\" -w \"hub.ngo\" -m \"hub.ngo\" \"hub.ngx\""); -execute($c); - -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/ngdbuild -a LatticeSCM -d LFSCM3GA25EP1 -p \"/opt/lattice/isplever7.0/isptools/ispfpga/or5s00/data\" -dt \"hub.ngo\" \"hub.ngd\""); -execute($c); - -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/map -a LatticeSCM -p LFSCM3GA25EP1 -t FFBGA1020 -s 5 \"hub.ngd\" -o \"hub_map.ncd\" -mp \"hub.mrp\" \"hub.lpf\""); -execute($c); - -#$c=("/home/marek/.isplever_lin1/ispcpld/bin/checkpoint -to \"checkpnt.twr\" -log \"hub.log\" -rpt \"hub.mrp\" -m -f \"hub.cmm\" -f \"hub.cm2\" -arch LatticeSCM \"hub_map.ncd\""); -#execute($c); - -#$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/trce -v 1 -gt -o checkpnt.twr hub_map.ncd hub.prf"); - -#$c="/home/marek/.isplever_lin1/ispcpld/bin/checkpoint -to \"checkpnt.twr\" -log \"hub.log\" -rpt \"hub.mrp\" -m -f \"hub.cmm\" -f \"hub.cm2\" -arch LatticeSCM \"hub_map.ncd\""; -system("rm hub.ncd"); -#execute($c); - -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/multipar -pr \"hub.prf\" -o \"hub_mpar.rpt\" -log \"hub_mpar.log\" -p \"hub.p2t\" -f \"hub.p3t\" \"hub_map.ncd\" \"hub.ncd\""); -execute($c); - -#$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/par \"hub_map.ncd\" \"hub.ncd\""); -#execute($c); - - - - -$c=("/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/bitgen -w \"hub.ncd\" -f \"hub.t2b\" \"hub.prf\""); -execute($c); -#$c=(". ~/bin/ispvm17"); -#execute($c); - -chdir ".."; - - -#$c=(". ~/bin/ispvm17"); - -$c=("ispvm -infile hub_1.xcf -outfiletype -svf"); -execute($c); -$c=("perl -i -ne 'print unless(/!/)' hub_1.svf"); -execute($c); -$c=("impact -batch impact_batch_hub.txt"); -execute($c); -$c=("scp hub_chain.stapl hadaq\@hadeb05:/var/diskless/etrax_fs/"); -execute($c); - -#} -#$c=("impact -batch impact_batch_hub.txt"); - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/f_divider.vhd b/f_divider.vhd deleted file mode 100644 index 7366e7e..0000000 --- a/f_divider.vhd +++ /dev/null @@ -1,173 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_arith.all; -use IEEE.STD_LOGIC_unsigned.all; - - -entity f_divider is - - generic( - cnt : integer := 4000 -- Der Teiler teilt durch "cnt" , wenn Test = 0 ist. -- - ); - - port ( - clk : in std_logic; - ena_cnt : in std_logic; - f_div : out std_logic - ); - -end f_divider; - - - -architecture arch_f_divider of f_divider is - - function How_many_Bits (int : integer) return integer is - variable i, tmp : integer; - begin - tmp := int; - i := 0; - while tmp > 0 loop - tmp := tmp / 2; - i := i + 1; - end loop; - return i; - end How_many_bits; - - - --+ - --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können? | - --+ - constant c_counter_width : integer := How_many_Bits(cnt - 2); - - --+ ---------------------------------------------------------------------------------------------+ - --| Des Zähler "s_counter" muss ein Bit breiter definiert werden, als zur Abarbeitung des "cnt" | - --| nötig wäre. Dieses Bit wird beim Zählerunterlauf '1'. Der Zählerablauf wird dadurch ohne | - --| Komparator erkannt, er steht als getaktetes physikalisches Signal zur Verfügung. | - --+ ---------------------------------------------------------------------------------------------+ - signal s_counter : std_logic_vector(c_counter_width downto 0) := conv_std_logic_vector(0, c_counter_width+1); - - --+ ---------------------------------------------------------------------------------------------+ - --| Teiler muss mit einen um -2 geringeren Wert geladen werden. Da das Neuladen erst durch dem | - --| Unterlauf Zählers erfolgt. D.h. die Null und minus Eins werden mitgezählt. | - --+ ---------------------------------------------------------------------------------------------+ - constant c_ld_value : integer := cnt - 2; - -begin - p_f_divider : process (clk) - begin - if clk'event and clk = '1' then - if s_counter(s_counter'high) = '1' then -- Bei underflow wird neu geladen -- - s_counter <= conv_std_logic_vector(c_ld_value, s_counter'length); - elsif ena_cnt = '1' then - if s_counter(s_counter'high) = '0' then -- Kein underflow erreicht weiter -- - s_counter <= s_counter - 1; -- subtrahieren. -- - end if; - end if; - end if; - end process p_f_divider; - - f_div <= s_counter(s_counter'high); - -end arch_f_divider; - - - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - - ---library synplify; ---use synplify.attributes.all; - - -entity edge_to_pulse is - - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - -end edge_to_pulse; - -architecture arch_edge_to_pulse of edge_to_pulse is - signal signal_sync : std_logic; - signal old_sync : std_logic; - type state is (idle, high, wait_for_low); -- state - signal current_state, next_state : state; - -begin -- arch_edge_to_pulse - - fsm : process (clock) - begin -- process fsm - if rising_edge(clock) then -- rising clock edge - if en_clk = '1' then - current_state <= next_state; - signal_sync <= signal_in; - end if; - end if; - end process fsm; - - - fsm_comb : process (current_state, signal_sync) - begin -- process fsm_comb - case current_state is - when idle => - pulse <= '0'; - if signal_sync = '1' then - next_state <= high; - else - next_state <= idle; - end if; - when high => - pulse <= '1'; - next_state <= wait_for_low; --- when wait_for_low_1 => --- pulse <= '1'; --- next_state <= wait_for_low; - when wait_for_low => - pulse <= '0'; - if signal_sync = '0' then - next_state <= idle; - else - next_state <= wait_for_low; - end if; - when others => - next_state <= idle; - end case; - end process fsm_comb; - - -end arch_edge_to_pulse; - - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -package support is - - component f_divider - generic ( - cnt : integer); - port ( - clk : in std_logic; - ena_cnt : in std_logic; - f_div : out std_logic); - end component; - - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - - -end support; - diff --git a/flexi_PCS_channel_synch.vhd b/flexi_PCS_channel_synch.vhd deleted file mode 100644 index 67f6e6d..0000000 --- a/flexi_PCS_channel_synch.vhd +++ /dev/null @@ -1,242 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.all; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; - -entity flexi_PCS_channel_synch is - - port ( - CLK : in std_logic; - RX_CLK : in std_logic; - RESET : in std_logic; - RXD : in std_logic_vector(15 downto 0); - RXD_SYNCH : out std_logic_vector(15 downto 0); - RX_K : in std_logic_vector(1 downto 0); - RX_RST : out std_logic; - CV : in std_logic_vector(1 downto 0); - TXD : in std_logic_vector(15 downto 0); - TXD_SYNCH : out std_logic_vector(15 downto 0); - TX_FORCE_DISP : out std_logic_vector(1 downto 0); - DATA_VALID_IN : in std_logic; - DATA_VALID_OUT : out std_logic; - FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0) - ); - -end flexi_PCS_channel_synch; -architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is - component flexi_PCS_fifo_EBR - port ( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(17 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic); - end component; - component simpleupcounter_16bit - port ( - QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component simpleupcounter_8bit - port ( - QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - type SYNCH_MACHINE is (IDLE, SYNCH_START, RESYNC1, RESYNC2, RESYNC3, NORMAL_OPERATION); - signal SYNCH_CURRENT, SYNCH_NEXT : SYNCH_MACHINE; - signal fsm_debug_register : std_logic_vector(2 downto 0); - signal resync_counter_up :std_logic; - signal resync_counter_clr :std_logic; - signal resync_counter : std_logic_vector(15 downto 0); - signal cv_i : std_logic_vector(1 downto 0); - signal cv_or : std_logic; - signal cv_counter : std_logic_vector(15 downto 0); - signal rx_rst_i : std_logic; - signal rxd_synch_i : std_logic_vector(15 downto 0); - signal fifo_data_in : std_logic_vector(17 downto 0); - signal fifo_data_out : std_logic_vector(17 downto 0); - signal fifo_wr_en : std_logic; - signal fifo_rd_en : std_logic; - signal fifo_rst : std_logic; - signal fifo_full : std_logic; - signal fifo_almost_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - -begin - TX_FORCE_DISP(0) <= '0'; - SYNCH_PROCESS : process (CLK) - begin - if rising_edge(CLK) then - RX_RST <= rx_rst_i; - FLEXI_PCS_STATUS(2 downto 0) <= fsm_debug_register; - FLEXI_PCS_STATUS(7 downto 3) <= fifo_empty & fifo_almost_empty & fifo_full & fifo_almost_full & '0'; - FLEXI_PCS_STATUS(15 downto 8) <= cv_counter(15 downto 12) & cv_counter(3 downto 0); - end if; - end process SYNCH_PROCESS; - VALID_DATA_SEND_TO_OPTICAL: process (CLK, RESET, DATA_VALID_IN) - begin - if rising_edge(CLK) then - if RESET = '1' then - TX_FORCE_DISP(1) <= '1'; - TXD_SYNCH <= (others => '0'); - elsif DATA_VALID_IN = '1' then - TX_FORCE_DISP(1) <= '0'; - TXD_SYNCH <= TXD; - else - TX_FORCE_DISP(1) <= '1'; - TXD_SYNCH <= x"bc50"; - end if; - end if; - end process VALID_DATA_SEND_TO_OPTICAL; - fifo_data_in <= RX_K & RXD; - CHANNEL_FIFO: flexi_PCS_fifo_EBR - port map ( - Data => fifo_data_in, - WrClock => RX_CLK, - RdClock => CLK, - WrEn => fifo_wr_en, - RdEn => fifo_rd_en, - Reset => fifo_rst, - RPReset => fifo_rst, - Q => fifo_data_out, - Empty => fifo_empty, - Full => fifo_full, - AlmostEmpty => fifo_almost_empty, - AlmostFull => fifo_almost_full - ); --- fifo_wr_en <= ; --- fifo_rd_en <= ; - RXD_SYNCH <= fifo_data_out(15 downto 0); - DATA_VALID_OUT <= fifo_data_out(16); - VALID_DATA_SEND_TO_API: process (RX_CLK, RESET) - begin - if rising_edge(RX_CLK) then - if RESET = '1' then - rxd_synch_i <= (others => '0'); - else-- RX_K(0) = '1' then - rxd_synch_i <= RXD; - end if; - end if; - end process VALID_DATA_SEND_TO_API; - SYNCH_CLOCK : process (CLK, RESET) - begin - if rising_edge (CLK) then - if RESET = '1' then - SYNCH_CURRENT <= IDLE; - cv_i <= (others => '0'); - else - SYNCH_CURRENT <= SYNCH_NEXT; - cv_i <= CV; - end if; - end if; - end process SYNCH_CLOCK; - SYNCH_FSM : process( SYNCH_CURRENT, rxd_synch_i, resync_counter, cv_i) - begin - case (SYNCH_CURRENT) is - when IDLE => - fifo_rst <= '0'; - fifo_wr_en <= '1'; - fifo_rd_en <= '1'; - fsm_debug_register(2 downto 0) <= "001"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '1'; - if rxd_synch_i = x"bc50" then - SYNCH_NEXT <= NORMAL_OPERATION; - else - SYNCH_NEXT <= RESYNC1; - end if; - when RESYNC1 => - fifo_rst <= '1'; - fifo_wr_en <= '0'; - fifo_rd_en <= '0'; - fsm_debug_register(2 downto 0) <= "010"; - rx_rst_i <= '1'; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter = 20003 then - SYNCH_NEXT <= RESYNC2; - else - SYNCH_NEXT <= RESYNC1; - end if; - when RESYNC2 => - fifo_rst <= '0'; - fifo_wr_en <= '1'; - fifo_rd_en <= '0'; - fsm_debug_register(2 downto 0) <= "011"; - rx_rst_i <= '0'; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter = 20200 then - SYNCH_NEXT <= RESYNC3; - else - SYNCH_NEXT <= RESYNC2; - end if; - when RESYNC3 => - fifo_rst <= '0'; - fifo_wr_en <= '1'; - fifo_rd_en <= '1'; - fsm_debug_register(2 downto 0) <= "011"; - rx_rst_i <= '0'; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter = 60000 then - SYNCH_NEXT <= IDLE; - else - SYNCH_NEXT <= RESYNC3; - end if; - when NORMAL_OPERATION => - fifo_rst <= '0'; - fifo_wr_en <= '1'; - fifo_rd_en <= '1'; - fsm_debug_register(2 downto 0) <= "100"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '0'; - if cv_i(0) = '1' or cv_i(1) = '1' then - SYNCH_NEXT <= IDLE; - else - SYNCH_NEXT <= NORMAL_OPERATION; - end if; - when others => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - fifo_rd_en <= '0'; - fsm_debug_register(2 downto 0) <= "000"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '1'; - SYNCH_NEXT <= IDLE; - end case; - end process SYNCH_FSM; - RESYNC_COUNTER_INST : simpleupcounter_16bit - port map ( - QOUT => resync_counter, - UP => resync_counter_up, - CLK => CLK, - CLR => resync_counter_clr); - cv_or <= cv_i(0) or cv_i(1); - CV_COUNTER_INST: simpleupcounter_16bit - port map ( - QOUT => cv_counter, - UP => cv_or, - CLK => CLK, - CLR => '0'); -end flexi_PCS_channel_synch; diff --git a/flexi_PCS_fifo_EBR.vhd b/flexi_PCS_fifo_EBR.vhd deleted file mode 100644 index 5fbed36..0000000 --- a/flexi_PCS_fifo_EBR.vhd +++ /dev/null @@ -1,180 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55) --- Module Version: 4.2 ---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n flexi_PCS_fifo_EBR -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -e - --- Tue Nov 27 10:58:36 2007 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library SCM; -use SCM.COMPONENTS.all; --- synopsys translate_on - -entity flexi_PCS_fifo_EBR is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end flexi_PCS_fifo_EBR; - -architecture Structure of flexi_PCS_fifo_EBR is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal Empty_int: std_logic; - signal Full_int: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component FIFO16KA - -- synopsys translate_off - generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); - FULLPOINTER : in std_logic_vector(14 downto 0); - AFPOINTER1 : in std_logic_vector(14 downto 0); - AEPOINTER1 : in std_logic_vector(14 downto 0); - AFPOINTER : in std_logic_vector(14 downto 0); - AEPOINTER : in std_logic_vector(14 downto 0); - CSDECODE_R : in std_logic_vector(1 downto 0); - CSDECODE_W : in std_logic_vector(1 downto 0); - RESETMODE : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - -- synopsys translate_on - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - FULLI: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; EMPTYI: in std_logic; - CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic; - RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic; - RST: in std_logic; RPRST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic; - EF: out std_logic; AEF: out std_logic; AFF: out std_logic; - FF: out std_logic); - end component; - attribute FULLPOINTER1 : string; - attribute FULLPOINTER : string; - attribute AFPOINTER1 : string; - attribute AFPOINTER : string; - attribute AEPOINTER1 : string; - attribute AEPOINTER : string; - attribute RESETMODE : string; - attribute REGMODE : string; - attribute CSDECODE_R : string; - attribute CSDECODE_W : string; - attribute DATA_WIDTH_R : string; - attribute DATA_WIDTH_W : string; - attribute FULLPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111000001"; - attribute FULLPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111100001"; - attribute AFPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101000001"; - attribute AFPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101100001"; - attribute AEPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101111111"; - attribute AEPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101011111"; - attribute RESETMODE of flexi_PCS_fifo_EBR_0_0 : label is "ASYNC"; - attribute REGMODE of flexi_PCS_fifo_EBR_0_0 : label is "NOREG"; - attribute CSDECODE_R of flexi_PCS_fifo_EBR_0_0 : label is "0b11"; - attribute CSDECODE_W of flexi_PCS_fifo_EBR_0_0 : label is "0b11"; - attribute DATA_WIDTH_R of flexi_PCS_fifo_EBR_0_0 : label is "36"; - attribute DATA_WIDTH_W of flexi_PCS_fifo_EBR_0_0 : label is "36"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - flexi_PCS_fifo_EBR_0_0: FIFO16KA - -- synopsys translate_off - generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", - AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001", - AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", - CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - -- synopsys translate_on - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo, - DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, - DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, - DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, - DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, - DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, - FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, - EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, - WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, - RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, - DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, - DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, - DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), - DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), - DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), - DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), - DO33=>Q(15), DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, - AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int); - - Empty <= Empty_int; - Full <= Full_int; -end Structure; - --- synopsys translate_off -library SCM; -configuration Structure_CON of flexi_PCS_fifo_EBR is - for Structure - for all:VHI use entity SCM.VHI(V); end for; - for all:VLO use entity SCM.VLO(V); end for; - for all:FIFO16KA use entity SCM.FIFO16KA(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/flexi_PCS_fifo_LUT.vhd b/flexi_PCS_fifo_LUT.vhd deleted file mode 100644 index 8a06336..0000000 --- a/flexi_PCS_fifo_LUT.vhd +++ /dev/null @@ -1,1167 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55) --- Module Version: 4.2 ---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n flexi_PCS_fifo_LUT -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 8 -width 18 -rwidth 18 -pfu_fifo -no_enable -pe 3 -pf 6 -e - --- Fri Nov 23 08:28:34 2007 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library SCM; -use SCM.COMPONENTS.all; --- synopsys translate_on - -entity flexi_PCS_fifo_LUT is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end flexi_PCS_fifo_LUT; - -architecture Structure of flexi_PCS_fifo_LUT is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal wptr_3: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal rptr_3: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal empty_i: std_logic; - signal full_i: std_logic; - signal rRst: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co1: std_logic; - signal wcount_3: std_logic; - signal co0: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co1_1: std_logic; - signal rcount_3: std_logic; - signal co0_1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_2: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_2: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal iae_setcount_0: std_logic; - signal iae_setcount_1: std_logic; - signal iae_setcount_2: std_logic; - signal iae_setcount_3: std_logic; - signal co1_2: std_logic; - signal ae_setcount_3: std_logic; - signal co0_4: std_logic; - signal rden_i: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r1: std_logic; - signal ae_setcount_0: std_logic; - signal ae_setcount_1: std_logic; - signal co0_5: std_logic; - signal wcount_r2: std_logic; - signal ae_set_cmp_clr: std_logic; - signal ae_setcount_2: std_logic; - signal ae_set_cmp_set: std_logic; - signal ae_set_d: std_logic; - signal ae_set_d_c: std_logic; - signal iaf_setcount_0: std_logic; - signal iaf_setcount_1: std_logic; - signal iaf_setcount_2: std_logic; - signal iaf_setcount_3: std_logic; - signal co1_3: std_logic; - signal af_setcount_3: std_logic; - signal co0_6: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w1: std_logic; - signal af_setcount_0: std_logic; - signal af_setcount_1: std_logic; - signal co0_7: std_logic; - signal rcount_w2: std_logic; - signal af_set_cmp_clr: std_logic; - signal af_setcount_2: std_logic; - signal af_set_cmp_set: std_logic; - signal af_set: std_logic; - signal af_set_c: std_logic; - signal rdataout17: std_logic; - signal rdataout16: std_logic; - signal rdataout15: std_logic; - signal rdataout14: std_logic; - signal rdataout13: std_logic; - signal rdataout12: std_logic; - signal rdataout11: std_logic; - signal rdataout10: std_logic; - signal rdataout9: std_logic; - signal rdataout8: std_logic; - signal rdataout7: std_logic; - signal rdataout6: std_logic; - signal rdataout5: std_logic; - signal rdataout4: std_logic; - signal rdataout3: std_logic; - signal rdataout2: std_logic; - signal rdataout1: std_logic; - signal rdataout0: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal wren_i: std_logic; - signal scuba_vhi: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component DPR16X2 - -- synopsys translate_off - generic (INITVAL : in String; GSR : in String); - -- synopsys translate_on - port (DI0: in std_logic; DI1: in std_logic; - WAD3: in std_logic; WAD2: in std_logic; - WAD1: in std_logic; WAD0: in std_logic; WRE: in std_logic; - WPE: in std_logic; WCK: in std_logic; RAD3: in std_logic; - RAD2: in std_logic; RAD1: in std_logic; - RAD0: in std_logic; WDO0: out std_logic; - WDO1: out std_logic; RDO0: out std_logic; - RDO1: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component FADD2 - port (A1: in std_logic; A0: in std_logic; B1: in std_logic; - B0: in std_logic; CI: in std_logic; COUT1: out std_logic; - COUT0: out std_logic; S1: out std_logic; - S0: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic; - CO: out std_logic; NC1: out std_logic; NC0: out std_logic); - end component; - component AGEB2 - port (A1: in std_logic; A0: in std_logic; B1: in std_logic; - B0: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - attribute GSR : string; - attribute initval : string; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x0410"; - attribute initval of LUT4_6 : label is "0x1004"; - attribute initval of LUT4_5 : label is "0x0140"; - attribute initval of LUT4_4 : label is "0x4001"; - attribute initval of LUT4_3 : label is "0x13c8"; - attribute initval of LUT4_2 : label is "0x2004"; - attribute initval of LUT4_1 : label is "0x4c32"; - attribute initval of LUT4_0 : label is "0x8001"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute GSR of fifo_pfu_0_0 : label is "ENABLED"; - attribute initval of fifo_pfu_0_0 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_1 : label is "ENABLED"; - attribute initval of fifo_pfu_0_1 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_2 : label is "ENABLED"; - attribute initval of fifo_pfu_0_2 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_3 : label is "ENABLED"; - attribute initval of fifo_pfu_0_3 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_4 : label is "ENABLED"; - attribute initval of fifo_pfu_0_4 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_5 : label is "ENABLED"; - attribute initval of fifo_pfu_0_5 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_6 : label is "ENABLED"; - attribute initval of fifo_pfu_0_6 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_7 : label is "ENABLED"; - attribute initval of fifo_pfu_0_7 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_8 : label is "ENABLED"; - attribute initval of fifo_pfu_0_8 : label is "0x0000000000000000"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t8: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t7: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t6: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t5: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t4: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t3: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t2: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t1: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t0: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_0); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_0); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x13c8") - -- synopsys translate_on - port map (AD3=>ae_setcount_3, AD2=>rcount_3, AD1=>w_gcount_r23, - AD0=>rptr_3, DO0=>ae_set_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x2004") - -- synopsys translate_on - port map (AD3=>ae_setcount_3, AD2=>rcount_3, AD1=>w_gcount_r23, - AD0=>rptr_3, DO0=>ae_set_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4c32") - -- synopsys translate_on - port map (AD3=>af_setcount_3, AD2=>wcount_3, AD1=>r_gcount_w23, - AD0=>wptr_3, DO0=>af_set_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8001") - -- synopsys translate_on - port map (AD3=>af_setcount_3, AD2=>wcount_3, AD1=>r_gcount_w23, - AD0=>wptr_3, DO0=>af_set_cmp_clr); - - FF_69: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_57: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_49: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_48: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_47: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_46: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_45: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(0)); - - FF_44: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(1)); - - FF_43: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(2)); - - FF_42: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(3)); - - FF_41: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(4)); - - FF_40: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(5)); - - FF_39: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(6)); - - FF_38: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(7)); - - FF_37: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(8)); - - FF_36: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(9)); - - FF_35: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(10)); - - FF_34: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(11)); - - FF_33: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(12)); - - FF_32: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(13)); - - FF_31: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(14)); - - FF_30: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(15)); - - FF_29: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(16)); - - FF_28: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(17)); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_11: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_9: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_0); - - FF_8: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_1); - - FF_7: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_2, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>ae_setcount_2); - - FF_6: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_3); - - FF_5: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ae_set_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - FF_4: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_0); - - FF_3: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_1); - - FF_2: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_2); - - FF_1: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_3); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); - - w_gctr_0: CU2 - port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0, - NC1=>iwcount_1, NC0=>iwcount_0); - - w_gctr_1: CU2 - port map (CI=>co0, PC1=>wcount_3, PC0=>wcount_2, CO=>co1, - NC1=>iwcount_3, NC0=>iwcount_2); - - r_gctr_0: CU2 - port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_1, - NC1=>ircount_1, NC0=>ircount_0); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_1, - NC1=>ircount_3, NC0=>ircount_2); - - empty_cmp_0: AGEB2 - port map (A1=>rcount_1, A0=>rcount_0, B1=>wcount_r1, - B0=>w_g2b_xor_cluster_0, CI=>rden_i, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A1=>empty_cmp_set, A0=>rcount_2, B1=>empty_cmp_clr, - B0=>wcount_r2, CI=>co0_2, GE=>empty_d_c); - - a0: FADD2 - port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, - B0=>scuba_vlo, CI=>empty_d_c, COUT1=>open, COUT0=>open, - S1=>open, S0=>empty_d); - - full_cmp_0: AGEB2 - port map (A1=>wcount_1, A0=>wcount_0, B1=>rcount_w1, - B0=>r_g2b_xor_cluster_0, CI=>wren_i, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A1=>full_cmp_set, A0=>wcount_2, B1=>full_cmp_clr, - B0=>rcount_w2, CI=>co0_3, GE=>full_d_c); - - a1: FADD2 - port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, - B0=>scuba_vlo, CI=>full_d_c, COUT1=>open, COUT0=>open, - S1=>open, S0=>full_d); - - ae_set_ctr_0: CU2 - port map (CI=>scuba_vhi, PC1=>ae_setcount_1, PC0=>ae_setcount_0, - CO=>co0_4, NC1=>iae_setcount_1, NC0=>iae_setcount_0); - - ae_set_ctr_1: CU2 - port map (CI=>co0_4, PC1=>ae_setcount_3, PC0=>ae_setcount_2, - CO=>co1_2, NC1=>iae_setcount_3, NC0=>iae_setcount_2); - - ae_set_cmp_0: AGEB2 - port map (A1=>ae_setcount_1, A0=>ae_setcount_0, B1=>wcount_r1, - B0=>w_g2b_xor_cluster_0, CI=>rden_i, GE=>co0_5); - - ae_set_cmp_1: AGEB2 - port map (A1=>ae_set_cmp_set, A0=>ae_setcount_2, - B1=>ae_set_cmp_clr, B0=>wcount_r2, CI=>co0_5, GE=>ae_set_d_c); - - a2: FADD2 - port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, - B0=>scuba_vlo, CI=>ae_set_d_c, COUT1=>open, COUT0=>open, - S1=>open, S0=>ae_set_d); - - af_set_ctr_0: CU2 - port map (CI=>scuba_vhi, PC1=>af_setcount_1, PC0=>af_setcount_0, - CO=>co0_6, NC1=>iaf_setcount_1, NC0=>iaf_setcount_0); - - af_set_ctr_1: CU2 - port map (CI=>co0_6, PC1=>af_setcount_3, PC0=>af_setcount_2, - CO=>co1_3, NC1=>iaf_setcount_3, NC0=>iaf_setcount_2); - - af_set_cmp_0: AGEB2 - port map (A1=>af_setcount_1, A0=>af_setcount_0, B1=>rcount_w1, - B0=>r_g2b_xor_cluster_0, CI=>wren_i, GE=>co0_7); - - af_set_cmp_1: AGEB2 - port map (A1=>af_set_cmp_set, A0=>af_setcount_2, - B1=>af_set_cmp_clr, B0=>rcount_w2, CI=>co0_7, GE=>af_set_c); - - a3: FADD2 - port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, - B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open, - S1=>open, S0=>af_set); - - fifo_pfu_0_0: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(16), DI1=>Data(17), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout16, RDO1=>rdataout17); - - fifo_pfu_0_1: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(14), DI1=>Data(15), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout14, RDO1=>rdataout15); - - fifo_pfu_0_2: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(12), DI1=>Data(13), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout12, RDO1=>rdataout13); - - fifo_pfu_0_3: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(10), DI1=>Data(11), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout10, RDO1=>rdataout11); - - fifo_pfu_0_4: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(8), DI1=>Data(9), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout8, RDO1=>rdataout9); - - fifo_pfu_0_5: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(6), DI1=>Data(7), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout6, RDO1=>rdataout7); - - fifo_pfu_0_6: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(4), DI1=>Data(5), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout4, RDO1=>rdataout5); - - fifo_pfu_0_7: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(2), DI1=>Data(3), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout2, RDO1=>rdataout3); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - fifo_pfu_0_8: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(0), DI1=>Data(1), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout0, RDO1=>rdataout1); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library SCM; -configuration Structure_CON of flexi_PCS_fifo_LUT is - for Structure - for all:DPR16X2 use entity SCM.DPR16X2(V); end for; - for all:ROM16X1 use entity SCM.ROM16X1(V); end for; - for all:AND2 use entity SCM.AND2(V); end for; - for all:OR2 use entity SCM.OR2(V); end for; - for all:XOR2 use entity SCM.XOR2(V); end for; - for all:INV use entity SCM.INV(V); end for; - for all:VHI use entity SCM.VHI(V); end for; - for all:VLO use entity SCM.VLO(V); end for; - for all:FADD2 use entity SCM.FADD2(V); end for; - for all:CU2 use entity SCM.CU2(V); end for; - for all:AGEB2 use entity SCM.AGEB2(V); end for; - for all:FD1P3BX use entity SCM.FD1P3BX(V); end for; - for all:FD1P3DX use entity SCM.FD1P3DX(V); end for; - for all:FD1S3BX use entity SCM.FD1S3BX(V); end for; - for all:FD1S3DX use entity SCM.FD1S3DX(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/flexi_PCS_synch.vhd b/flexi_PCS_synch.vhd deleted file mode 100644 index c4f94e3..0000000 --- a/flexi_PCS_synch.vhd +++ /dev/null @@ -1,70 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.all; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; - -entity flexi_PCS_synch is - generic ( - HOW_MANY_CHANNELS : positive); - port ( - CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RESET : in std_logic; - RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - RXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - TXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TX_FORCE_DISP : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0) - ); -end flexi_PCS_synch; -architecture flexi_PCS_synch of flexi_PCS_synch is - component flexi_PCS_channel_synch - port ( - CLK : in std_logic; - RX_CLK : in std_logic; - RESET : in std_logic; - RXD : in std_logic_vector(15 downto 0); - RXD_SYNCH : out std_logic_vector(15 downto 0); - RX_K : in std_logic_vector(1 downto 0); - RX_RST : out std_logic; - CV : in std_logic_vector(1 downto 0); - TXD : in std_logic_vector(15 downto 0); - TXD_SYNCH : out std_logic_vector(15 downto 0); - TX_FORCE_DISP : out std_logic_vector(1 downto 0); - DATA_VALID_IN : in std_logic; - DATA_VALID_OUT : out std_logic; - FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0)); - end component; -begin - CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate - begin - SYNCH :flexi_PCS_channel_synch - port map ( - CLK => CLK(bit_index/4), --4 different channles clk - RX_CLK => RX_CLK(bit_index), - RESET => RESET, - RXD => RXD((bit_index*16+15) downto bit_index*16), - RXD_SYNCH => RXD_SYNCH((bit_index*16+15) downto bit_index*16), - RX_K => RX_K(bit_index*2+1 downto bit_index*2), - RX_RST => RX_RST(bit_index), - CV => CV((bit_index*2+1) downto bit_index*2), - TXD => TXD((bit_index*16+15) downto bit_index*16), - TXD_SYNCH => TXD_SYNCH((bit_index*16+15) downto bit_index*16), - TX_FORCE_DISP => TX_FORCE_DISP(bit_index*2+1 downto bit_index*2), - DATA_VALID_IN => DATA_VALID_IN(bit_index), - DATA_VALID_OUT => DATA_VALID_OUT(bit_index), - FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16) - ); - end generate CHANNEL_GENERATE; -end flexi_PCS_synch; diff --git a/hub.lpf b/hub.lpf deleted file mode 100644 index 99a8988..0000000 --- a/hub.lpf +++ /dev/null @@ -1,477 +0,0 @@ -COMMERCIAL; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -#LOCATE COMP "ADDON_RESET" SITE "J21" ; -#LOCATE COMP "ADO_CLKOUTN" SITE "AE4" ; -#LOCATE COMP "ADO_CLKOUTP" SITE "AE3" ; -#LOCATE COMP "ADO_LV_0" SITE "D32" ; -#LOCATE COMP "ADO_LV_1" SITE "D31" ; -#LOCATE COMP "ADO_LV_2" SITE "F32" ; -#LOCATE COMP "ADO_LV_3" SITE "F31" ; -#LOCATE COMP "ADO_LV_4" SITE "J29" ; -#LOCATE COMP "ADO_LV_5" SITE "H29" ; -#LOCATE COMP "ADO_LV_6" SITE "L32" ; -#LOCATE COMP "ADO_LV_7" SITE "M32" ; -#LOCATE COMP "ADO_LV_8" SITE "P30" ; -#LOCATE COMP "ADO_LV_9" SITE "P29" ; -#LOCATE COMP "ADO_LV_10" SITE "R30" ; -#LOCATE COMP "ADO_LV_11" SITE "R29" ; -#LOCATE COMP "ADO_LV_12" SITE "T31" ; -#LOCATE COMP "ADO_LV_13" SITE "T32" ; -#LOCATE COMP "ADO_LV_14" SITE "V32" ; -#LOCATE COMP "ADO_LV_15" SITE "V31" ; -#LOCATE COMP "ADO_LV_16" SITE "W30" ; -#LOCATE COMP "ADO_LV_17" SITE "W29" ; -#LOCATE COMP "ADO_LV_18" SITE "W28" ; -#LOCATE COMP "ADO_LV_19" SITE "Y28" ; -#LOCATE COMP "ADO_LV_20" SITE "AB32" ; -#LOCATE COMP "ADO_LV_21" SITE "AA32" ; -#LOCATE COMP "ADO_LV_22" SITE "AD29" ; -#LOCATE COMP "ADO_LV_23" SITE "AD30" ; -#LOCATE COMP "ADO_LV_24" SITE "AC32" ; -#LOCATE COMP "ADO_LV_25" SITE "AD32" ; -#LOCATE COMP "ADO_LV_26" SITE "AE31" ; -#LOCATE COMP "ADO_LV_27" SITE "AE32" ; -#LOCATE COMP "ADO_LV_28" SITE "E32" ; -#LOCATE COMP "ADO_LV_29" SITE "E31" ; -#LOCATE COMP "ADO_LV_30" SITE "G31" ; -#LOCATE COMP "ADO_LV_31" SITE "G32" ; -#LOCATE COMP "ADO_LV_32" SITE "H31" ; -#LOCATE COMP "ADO_LV_33" SITE "H32" ; -#LOCATE COMP "ADO_LV_34" SITE "N31" ; -#LOCATE COMP "ADO_LV_35" SITE "N32" ; -#LOCATE COMP "ADO_LV_36" SITE "P32" ; -#LOCATE COMP "ADO_LV_37" SITE "P31" ; -#LOCATE COMP "ADO_LV_38" SITE "R31" ; -#LOCATE COMP "ADO_LV_39" SITE "R32" ; -#LOCATE COMP "ADO_LV_40" SITE "U32" ; -#LOCATE COMP "ADO_LV_41" SITE "U31" ; -#LOCATE COMP "ADO_LV_42" SITE "V29" ; -#LOCATE COMP "ADO_LV_43" SITE "V30" ; -#LOCATE COMP "ADO_LV_44" SITE "W31" ; -#LOCATE COMP "ADO_LV_45" SITE "Y31" ; -#LOCATE COMP "ADO_LV_46" SITE "W32" ; -#LOCATE COMP "ADO_LV_47" SITE "Y32" ; -#LOCATE COMP "ADO_LV_48" SITE "AD31" ; -#LOCATE COMP "ADO_LV_49" SITE "AC31" ; -#LOCATE COMP "ADO_LV_50" SITE "AC28" ; -#LOCATE COMP "ADO_LV_51" SITE "AD28" ; -#LOCATE COMP "ADO_LV_52" SITE "AE30" ; -#LOCATE COMP "ADO_LV_53" SITE "AE29" ; -#LOCATE COMP "ADO_LV_54" SITE "AF32" ; -#LOCATE COMP "ADO_LV_55" SITE "AF31" ; -#LOCATE COMP "ADO_LV_56" SITE "AG1" ; -#LOCATE COMP "ADO_LV_57" SITE "AG2" ; -#LOCATE COMP "ADO_LV_58" SITE "AE2" ; -#LOCATE COMP "ADO_LV_59" SITE "AE1" ; -#LOCATE COMP "ADO_LV_60" SITE "AF1" ; -#LOCATE COMP "ADO_LV_61" SITE "AF2" ; -LOCATE COMP "ADO_TTL_0" SITE "AJ32" ; -LOCATE COMP "ADO_TTL_1" SITE "AF27" ; -LOCATE COMP "ADO_TTL_2" SITE "AK31" ; -LOCATE COMP "ADO_TTL_3" SITE "AE25" ; -LOCATE COMP "ADO_TTL_4" SITE "AK30" ; -LOCATE COMP "ADO_TTL_5" SITE "AD23" ; -LOCATE COMP "ADO_TTL_6" SITE "AK29" ; -LOCATE COMP "ADO_TTL_7" SITE "AF26" ; -LOCATE COMP "ADO_TTL_8" SITE "AJ28" ; -LOCATE COMP "ADO_TTL_9" SITE "AJ31" ; -LOCATE COMP "ADO_TTL_10" SITE "AM30" ; -LOCATE COMP "ADO_TTL_11" SITE "AH29" ; -LOCATE COMP "ADO_TTL_12" SITE "AJ27" ; -LOCATE COMP "ADO_TTL_13" SITE "AE22" ; -LOCATE COMP "ADO_TTL_14" SITE "AL28" ; -LOCATE COMP "ADO_TTL_15" SITE "AC21" ; -LOCATE COMP "ADO_TTL_16" SITE "AM28" ; -LOCATE COMP "ADO_TTL_17" SITE "AG23" ; -LOCATE COMP "ADO_TTL_18" SITE "AG26" ; -LOCATE COMP "ADO_TTL_19" SITE "AL26" ; -LOCATE COMP "ADO_TTL_20" SITE "AK32" ; -LOCATE COMP "ADO_TTL_21" SITE "AG28" ; -LOCATE COMP "ADO_TTL_22" SITE "AL31" ; -LOCATE COMP "ADO_TTL_23" SITE "AE24" ; -LOCATE COMP "ADO_TTL_24" SITE "AL30" ; -LOCATE COMP "ADO_TTL_25" SITE "AE23" ; -LOCATE COMP "ADO_TTL_26" SITE "AL29" ; -LOCATE COMP "ADO_TTL_27" SITE "AF25" ; -LOCATE COMP "ADO_TTL_28" SITE "AK28" ; -LOCATE COMP "ADO_TTL_29" SITE "AH30" ; -LOCATE COMP "ADO_TTL_30" SITE "AM29" ; -LOCATE COMP "ADO_TTL_31" SITE "AH28" ; -LOCATE COMP "ADO_TTL_32" SITE "AK27" ; -LOCATE COMP "ADO_TTL_33" SITE "AF23" ; -LOCATE COMP "ADO_TTL_34" SITE "AL27" ; -LOCATE COMP "ADO_TTL_35" SITE "AD21" ; -LOCATE COMP "ADO_TTL_36" SITE "AM27" ; -LOCATE COMP "ADO_TTL_37" SITE "AF22" ; -LOCATE COMP "ADO_TTL_38" SITE "AG25" ; -LOCATE COMP "ADO_TTL_39" SITE "AM26" ; -LOCATE COMP "ADO_TTL_40" SITE "AK24" ; -LOCATE COMP "ADO_TTL_41" SITE "AE20" ; -LOCATE COMP "ADO_TTL_42" SITE "AJ24" ; -LOCATE COMP "ADO_TTL_43" SITE "AE21" ; -LOCATE COMP "ADO_TTL_44" SITE "AJ22" ; -LOCATE COMP "ADO_TTL_45" SITE "AK22" ; -LOCATE COMP "ADO_TTL_46" SITE "AG22" ; -IOBUF PORT "ADO_TTL_0" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_1" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_2" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_3" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_4" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_5" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_6" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_7" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_8" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_9" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_10" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_11" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_12" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_13" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_14" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_15" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_16" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_17" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_18" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_19" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_20" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_21" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_22" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_23" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_24" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_25" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_26" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_27" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_28" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_29" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_30" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_31" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_32" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_33" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_34" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_35" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_36" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_37" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_38" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_39" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_40" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_41" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_42" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_43" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_44" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_45" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_46" IO_TYPE=LVTTL33 ; -LOCATE COMP "DBAD" SITE "AM20" ; -LOCATE COMP "DGOOD" SITE "AH20" ; -LOCATE COMP "DINT" SITE "AJ18" ; -LOCATE COMP "DWAIT" SITE "AH21" ; -IOBUF PORT "DBAD" IO_TYPE=LVTTL33 ; -IOBUF PORT "DGOOD" IO_TYPE=LVTTL33 ; -IOBUF PORT "DINT" IO_TYPE=LVTTL33 ; -IOBUF PORT "DWAIT" IO_TYPE=LVTTL33 ; -#LOCATE COMP "FROM_TRB_TO_ADDON_CLK" SITE "T10" ; -#LOCATE COMP "FROM_TRB_TO_ADDON_CLKB" SITE "T9" ; -#LOCATE COMP "FS_PE_0" SITE "J13" ; -#LOCATE COMP "FS_PE_1" SITE "K9" ; -#LOCATE COMP "FS_PE_2" SITE "J12" ; -#LOCATE COMP "FS_PE_5" SITE "AM16" ; -#LOCATE COMP "FS_PE_6" SITE "AL16" ; -#LOCATE COMP "FS_PE_7" SITE "AM15" ; -#LOCATE COMP "FS_PE_8" SITE "AL15" ; -#LOCATE COMP "FS_PE_9" SITE "AM14" ; -#LOCATE COMP "FS_PE_10" SITE "AC16" ; -#LOCATE COMP "FS_PE_11" SITE "AH16" ; -#LOCATE COMP "FS_PE_12" SITE "AK15" ; -#LOCATE COMP "FS_PE_13" SITE "AH14" ; -#LOCATE COMP "FS_PE_14" SITE "AM13" ; -#LOCATE COMP "FS_PE_15" SITE "AH12" ; -#LOCATE COMP "FS_PE_16" SITE "AK14" ; -#LOCATE COMP "FS_PE_17" SITE "AD15" ; - -LOCATE COMP "OPLL" SITE "AL11" ; -LOCATE COMP "IPLL" SITE "AL10" ; -LOCATE COMP "LOK_1" SITE "AJ1" ; -LOCATE COMP "LOK_2" SITE "AL2" ; -LOCATE COMP "LOK_3" SITE "AK3" ; -LOCATE COMP "LOK_4" SITE "AL4" ; -LOCATE COMP "LOK_5" SITE "AM4" ; -LOCATE COMP "LOK_6" SITE "AH5" ; -LOCATE COMP "LOK_7" SITE "AG5" ; -LOCATE COMP "LOK_8" SITE "AK5" ; -LOCATE COMP "LOK_9" SITE "AK6" ; -LOCATE COMP "LOK_10" SITE "AM5" ; -LOCATE COMP "LOK_11" SITE "AM6" ; -LOCATE COMP "LOK_12" SITE "AF8" ; -LOCATE COMP "LOK_13" SITE "AE9" ; -LOCATE COMP "LOK_14" SITE "AE10" ; -LOCATE COMP "LOK_15" SITE "AF11" ; -LOCATE COMP "LOK_16" SITE "AD12" ; -IOBUF PORT "IPLL" IO_TYPE=LVTTL33 ; -IOBUF PORT "OPLL" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_1" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_2" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_3" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_4" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_5" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_6" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_7" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_8" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_9" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_10" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_11" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_12" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_13" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_14" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_15" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_16" IO_TYPE=LVTTL33 ; -LOCATE COMP "LVDS_CLK_200P" SITE "P3" ; -#LOCATE COMP "LVDS_CLK_200N" SITE "P4" ; -IOBUF PORT "LVDS_CLK_200P" IO_TYPE=LVDS ; -#IOBUF PORT "LVDS_CLK_200N" IO_TYPE=LVDS ; -FREQUENCY PORT "LVDS_CLK_200P" 100.000000 MHz ; -#FREQUENCY PORT "LVDS_CLK_200N" 200.000000 MHz ; -IOBUF PORT "LVDS_CLK_200P" DIFFRESISTOR=120 ; - -#LOCATE COMP "RESET" SITE "AL23" ; -LOCATE COMP "RT_1" SITE "AK1" ; -LOCATE COMP "RT_2" SITE "AK2" ; -LOCATE COMP "RT_3" SITE "AJ3" ; -LOCATE COMP "RT_4" SITE "AL3" ; -LOCATE COMP "RT_5" SITE "AM3" ; -LOCATE COMP "RT_6" SITE "AH4" ; -LOCATE COMP "RT_7" SITE "AF6" ; -LOCATE COMP "RT_8" SITE "AJ5" ; -LOCATE COMP "RT_9" SITE "AJ6" ; -LOCATE COMP "RT_10" SITE "AL5" ; -LOCATE COMP "RT_11" SITE "AL6" ; -LOCATE COMP "RT_12" SITE "AF7" ; -LOCATE COMP "RT_13" SITE "AE8" ; -LOCATE COMP "RT_14" SITE "AD10" ; -LOCATE COMP "RT_15" SITE "AE11" ; -LOCATE COMP "RT_16" SITE "AE12" ; -IOBUF PORT "RT_1" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_2" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_3" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_4" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_5" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_6" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_7" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_8" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_9" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_10" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_11" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_12" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_13" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_14" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_15" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_16" IO_TYPE=LVTTL33 ; -#LOCATE COMP "GBIT_INP_N" SITE "C2" ; -#LOCATE COMP "GBIT_INP_P" SITE "C1" ; -#LOCATE COMP "GBIT_OUT_N" SITE "B3" ; -#LOCATE COMP "GBIT_OUT_P" SITE "A3" ; -#LOCATE COMP "GBIT_SFP_LOS" SITE "J15" ; -#LOCATE COMP "GBIT_SFP_MOD_0" SITE "A19" ; -#LOCATE COMP "GBIT_SFP_MOD_1" SITE "H18" ; -#LOCATE COMP "GBIT_SFP_MOD_2" SITE "H17" ; - -#LOCATE COMP "GBIT_TX_FAULT" SITE "K15" ; -#LOCATE COMP "S1_GBIT_SFP_MOD_0" SITE "AG17" ; -#LOCATE COMP "S1_GBIT_TX_FAULT" SITE "AK21" ; -#LOCATE COMP "S2_GBIT_TX_DIS" SITE "AF19" ; -#LOCATE COMP "S2_GBIT_SFP_LOS" SITE "AM22" ; -#LOCATE COMP "S2_GBIT_SFP_MOD_0" SITE "AC17" ; -#LOCATE COMP "S3_GBIT_SFP_LOS" SITE "AL21" ; -#LOCATE COMP "S2_GBIT_TX_FAULT" SITE "AM23" ; -#LOCATE COMP "S3_GBIT_SFP_MOD_0" SITE "AM17" ; -#LOCATE COMP "S3_GBIT_TX_FAULT" SITE "AH26" ; -#LOCATE COMP "S3_GBIT_TX_DIS" SITE "AH25" ; -#LOCATE COMP "S1_GBIT_SFP_LOS" SITE "AE19" ; -#LOCATE COMP "S1_GBIT_TX_DIS" SITE "AJ21" ; -#LOCATE COMP "S1_GBIT_SFP_MOD_1" SITE "AL18" ; -#LOCATE COMP "S3_GBIT_SFP_MOD_1" SITE "AE17" ; -#LOCATE COMP "S2_GBIT_SFP_MOD_1" SITE "AD17" ; -#LOCATE COMP "S2_GBIT_SFP_MOD_2" SITE "AL17" ; -#LOCATE COMP "S3_GBIT_SFP_MOD_2" SITE "AF17" ; -#LOCATE COMP "S1_GBIT_SFP_MOD_2" SITE "AM18" ; -#LOCATE COMP "SERDES_125P" SITE "C5" ; -#LOCATE COMP "SERDES_200N" SITE "D28" ; -#LOCATE COMP "SERDES_200P" SITE "C28" ; -#LOCATE COMP "SERDES_200N" SITE "A_REFCLKN_L" ; -#LOCATE COMP "SERDES_200P" SITE "A_REFCLKP_L" ; - -#LOCATE COMP "SERDES_125N" SITE "D5" ; -#LOCATE COMP "SFP7_MOD_0" SITE "AE14" ; -#LOCATE COMP "SFP2_MOD_0" SITE "J18" ; -#LOCATE COMP "SFP1_MOD_0" SITE "F20" ; -#LOCATE COMP "SFP4_MOD_0" SITE "D20" ; -#LOCATE COMP "SFP3_MOD_0" SITE "G20" ; -#LOCATE COMP "SFP8_MOD_0" SITE "AK12" ; -#LOCATE COMP "SFP12_MOD_0" SITE "J17" ; -#LOCATE COMP "SFP9_MOD_0" SITE "AM10" ; -#LOCATE COMP "SFP5_MOD_0" SITE "C19" ; -#LOCATE COMP "SFP11_MOD_0" SITE "D18" ; -#LOCATE COMP "SFP6_MOD_0" SITE "E17" ; -#LOCATE COMP "SFP10_MOD_0" SITE "AG14" ; -#LOCATE COMP "SFP12_MOD_1" SITE "L20" ; -#LOCATE COMP "SFP11_MOD_1" SITE "C18" ; -#LOCATE COMP "SFP9_MOD_1" SITE "AM11" ; -#LOCATE COMP "SFP6_MOD_1" SITE "B20" ; -#LOCATE COMP "SFP8_MOD_1" SITE "AH10" ; -#LOCATE COMP "SFP4_MOD_1" SITE "G19" ; -#LOCATE COMP "SFP5_MOD_1" SITE "C20" ; -#LOCATE COMP "SFP3_MOD_1" SITE "H20" ; -#LOCATE COMP "SFP7_MOD_1" SITE "AF14" ; -#LOCATE COMP "SFP1_MOD_1" SITE "E20" ; -#LOCATE COMP "SFP2_MOD_1" SITE "F19" ; -#LOCATE COMP "SFP10_MOD_1" SITE "AL12" ; -#LOCATE COMP "SFP10_MOD_2" SITE "AL13" ; -#LOCATE COMP "SFP5_MOD_2" SITE "E18" ; -#LOCATE COMP "SFP4_MOD_2" SITE "H19" ; -#LOCATE COMP "SFP9_MOD_2" SITE "AG13" ; -#LOCATE COMP "SFP6_MOD_2" SITE "B19" ; -#LOCATE COMP "SFP2_MOD_2" SITE "E19" ; -#LOCATE COMP "SFP7_MOD_2" SITE "AJ12" ; -#LOCATE COMP "SFP3_MOD_2" SITE "D19" ; -#LOCATE COMP "SFP1_MOD_2" SITE "K18" ; -#LOCATE COMP "SFP8_MOD_2" SITE "AH11" ; -#LOCATE COMP "SFP12_MOD_2" SITE "A20" ; -#LOCATE COMP "SFP11_MOD_2" SITE "K17" ; -#IOBUF PORT "SFP7_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP2_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP1_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP4_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP3_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP8_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP12_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP9_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP5_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP11_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP6_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP10_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP12_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP11_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP9_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP6_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP8_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP4_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP5_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP3_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP7_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP1_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP2_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP10_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP10_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP5_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP4_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP9_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP6_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP2_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP7_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP3_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP1_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP8_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP12_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP11_MOD_2" IO_TYPE=LVTTL33 ; - - -#LOCATE COMP "SFP_LOS_1" SITE "A18" ; -#LOCATE COMP "SFP_LOS_2" SITE "A15" ; -#LOCATE COMP "SFP_LOS_3" SITE "B15" ; -#LOCATE COMP "SFP_LOS_4" SITE "G16" ; -#LOCATE COMP "SFP_LOS_5" SITE "H16" ; -#LOCATE COMP "SFP_LOS_6" SITE "J16" ; -#LOCATE COMP "SFP_LOS_7" SITE "L13" ; -#LOCATE COMP "SFP_LOS_8" SITE "C14" ; -#LOCATE COMP "SFP_LOS_9" SITE "E15" ; -#LOCATE COMP "SFP_LOS_10" SITE "G14" ; -#LOCATE COMP "SFP_LOS_11" SITE "E14" ; -#LOCATE COMP "SFP_LOS_12" SITE "F13" ; -#IOBUF PORT "SFP_LOS_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_3" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_4" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_5" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_6" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_7" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_8" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_9" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_10" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_11" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP_LOS_12" IO_TYPE=LVTTL33 ; - - -#LOCATE COMP "quad_a/PCSA_INST" SITE "PCS36000" ; -LOCATE COMP "QUAD_GENERATE_0_QUAD/PCSA_INST" SITE "PCS36000" ; -LOCATE COMP "QUAD_GENERATE_1_QUAD/PCSA_INST" SITE "PCS36100" ; -LOCATE COMP "QUAD_GENERATE_2_QUAD/PCSA_INST" SITE "PCS3E100" ; -LOCATE COMP "QUAD_GENERATE_3_QUAD/PCSA_INST" SITE "PCS3E000" ; -#LOCATE COMP "TEST/PCSA_INST" SITE "PCS36000" ; -FREQUENCY PORT "ref_pclk_0/QUAD_GENERATE_0_QUAD" 100.000000MHz; -FREQUENCY PORT "ref_pclk_1/QUAD_GENERATE_1_QUAD" 100.000000MHz; -FREQUENCY PORT "ref_pclk_2/QUAD_GENERATE_2_QUAD" 100.000000MHz; -FREQUENCY PORT "ref_pclk_3/QUAD_GENERATE_3_QUAD" 100.000000MHz; -#FREQUENCY PORT "rxa_pclk_a/quad_a" 100.000000MHz; -#FREQUENCY PORT "rx_1_sclk_a/quad_a" 100.000000MHz; -#FREQUENCY PORT "rx_2_sclk_a/quad_a" 100.000000MHz; -#FREQUENCY PORT "rx_3_sclk_a/quad_a" 100.000000MHz; - -#LOCATE COMP "SUPPL_RESET" SITE "B18" ; -LOCATE COMP "TX_DIS_1" SITE "G17" ; -LOCATE COMP "TX_DIS_2" SITE "A17" ; -LOCATE COMP "TX_DIS_3" SITE "A16" ; -LOCATE COMP "TX_DIS_4" SITE "B16" ; -LOCATE COMP "TX_DIS_5" SITE "A13" ; -LOCATE COMP "TX_DIS_6" SITE "H15" ; -LOCATE COMP "TX_DIS_7" SITE "D15" ; -LOCATE COMP "TX_DIS_8" SITE "B13" ; -LOCATE COMP "TX_DIS_9" SITE "C13" ; -LOCATE COMP "TX_DIS_10" SITE "D14" ; -LOCATE COMP "TX_DIS_11" SITE "H14" ; -LOCATE COMP "TX_DIS_12" SITE "G13" ; -LOCATE COMP "TX_DIS_13" SITE "E13" ; -LOCATE COMP "TX_DIS_14" SITE "AJ21" ; -LOCATE COMP "TX_DIS_15" SITE "AF19" ; -LOCATE COMP "TX_DIS_16" SITE "AH25" ; - -IOBUF PORT "TX_DIS_1" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_2" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_3" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_4" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_5" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_6" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_7" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_8" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_9" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_10" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_11" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_12" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_13" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_14" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_15" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_16" IO_TYPE=LVTTL33 ; - -#LOCATE COMP "TX_FAULT_1" SITE "F17" ; -#LOCATE COMP "TX_FAULT_2" SITE "L17" ; -#LOCATE COMP "TX_FAULT_3" SITE "L16" ; -#LOCATE COMP "TX_FAULT_4" SITE "F16" ; -#LOCATE COMP "TX_FAULT_5" SITE "A14" ; -#LOCATE COMP "TX_FAULT_6" SITE "K16" ; -#LOCATE COMP "TX_FAULT_7" SITE "C15" ; -#LOCATE COMP "TX_FAULT_8" SITE "B14" ; -#LOCATE COMP "TX_FAULT_9" SITE "E16" ; -#LOCATE COMP "TX_FAULT_10" SITE "D13" ; -#LOCATE COMP "TX_FAULT_11" SITE "F14" ; -#LOCATE COMP "TX_FAULT_12" SITE "H13" ; -#IOBUF PORT "TX_FAULT_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_3" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_4" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_5" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_6" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_7" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_8" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_9" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_10" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_11" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_12" IO_TYPE=LVTTL33 ; - - diff --git a/hub.vhd b/hub.vhd deleted file mode 100644 index 3eb41b0..0000000 --- a/hub.vhd +++ /dev/null @@ -1,776 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.all; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; -use work.trb_net_std.all; -use work.trb_net16_hub_func.all; --- library sc; --- use sc.components.all; -entity hub is - port ( - LVDS_CLK_200P : in std_logic; --- LVDS_CLK_200N : in std_logic; --- SERDES_200N : in std_logic; --- SERDES_200P : in std_logic; --- ADO_LV : in std_logic_vector(61 downto 0); - ADO_TTL : inout std_logic_vector(46 downto 0); - DBAD : out std_logic; - DGOOD : out std_logic; - DINT : out std_logic; - DWAIT : out std_logic; - LOK : out std_logic_vector(16 downto 1); - RT : out std_logic_vector(16 downto 1); - TX_DIS : out std_logic_vector(16 downto 1); - IPLL : out std_logic; - OPLL : out std_logic; - SFP_INP_N : in std_logic_vector(15 downto 0); - SFP_INP_P : in std_logic_vector(15 downto 0); - SFP_OUT_N : out std_logic_vector(15 downto 0); - SFP_OUT_P : out std_logic_vector(15 downto 0); - --------------------------------------------------------------------------- - -- sim - --------------------------------------------------------------------------- - OPT_DATA_IN : in std_logic_vector(31 downto 0); - OPT_DATA_OUT : out std_logic_vector(31 downto 0); - OPT_DATA_VALID_IN : in std_logic_vector(1 downto 0); - OPT_DATA_VALID_OUT : out std_logic_vector(1 downto 0) - ); -end hub; -architecture hub of hub is - component trb_hub_interface - port ( - CLK : in std_logic; - RESET : in std_logic; - STROBE : in std_logic; - INTERNAL_DATA_IN : in std_logic_vector(7 downto 0); - INTERNAL_DATA_OUT : out std_logic_vector(7 downto 0); - INTERNAL_ADDRESS : in std_logic_vector(15 downto 0); - INTERNAL_MODE : in std_logic; - VALID_DATA_SENT : out std_logic; - hub_register_00 : in std_logic_vector(7 downto 0); - hub_register_01 : in std_logic_vector(7 downto 0); - hub_register_02 : in std_logic_vector(7 downto 0); - hub_register_03 : in std_logic_vector(7 downto 0); - hub_register_04 : in std_logic_vector(7 downto 0); - hub_register_05 : in std_logic_vector(7 downto 0); - hub_register_06 : in std_logic_vector(7 downto 0); - hub_register_07 : in std_logic_vector(7 downto 0); - hub_register_08 : in std_logic_vector(7 downto 0); - hub_register_09 : in std_logic_vector(7 downto 0); - hub_register_0a : out std_logic_vector(7 downto 0); - hub_register_0b : out std_logic_vector(7 downto 0); - hub_register_0c : out std_logic_vector(7 downto 0); - hub_register_0d : out std_logic_vector(7 downto 0); - hub_register_0e : out std_logic_vector(7 downto 0); - hub_register_0f : out std_logic_vector(7 downto 0); - hub_register_10 : in std_logic_vector(7 downto 0); - hub_register_11 : in std_logic_vector(7 downto 0); - hub_register_12 : in std_logic_vector(7 downto 0); - hub_register_13 : in std_logic_vector(7 downto 0); - hub_register_14 : in std_logic_vector(7 downto 0); - hub_register_15 : in std_logic_vector(7 downto 0); - hub_register_16 : in std_logic_vector(7 downto 0) - ); - end component; - component serdes_fpga_ref_clk--serdes - port( --- refclkp : in std_logic; --- refclkn : in std_logic; - rxrefclk : in std_logic; - refclk : in std_logic; - hdinp_0 : in std_logic; - hdinn_0 : in std_logic; - tclk_0 : in std_logic; - rclk_0 : in std_logic; - tx_rst_0 : in std_logic; - rx_rst_0 : in std_logic; - txd_0 : in std_logic_vector(15 downto 0); - tx_k_0 : in std_logic_vector(1 downto 0); - tx_force_disp_0 : in std_logic_vector(1 downto 0); - tx_disp_sel_0 : in std_logic_vector(1 downto 0); - tx_crc_init_0 : in std_logic_vector(1 downto 0); - word_align_en_0 : in std_logic; - mca_align_en_0 : in std_logic; - felb_0 : in std_logic; - lsm_en_0 : in std_logic; - hdinp_1 : in std_logic; - hdinn_1 : in std_logic; - tclk_1 : in std_logic; - rclk_1 : in std_logic; - tx_rst_1 : in std_logic; - rx_rst_1 : in std_logic; - txd_1 : in std_logic_vector(15 downto 0); - tx_k_1 : in std_logic_vector(1 downto 0); - tx_force_disp_1 : in std_logic_vector(1 downto 0); - tx_disp_sel_1 : in std_logic_vector(1 downto 0); - tx_crc_init_1 : in std_logic_vector(1 downto 0); - word_align_en_1 : in std_logic; - mca_align_en_1 : in std_logic; - felb_1 : in std_logic; - lsm_en_1 : in std_logic; - hdinp_2 : in std_logic; - hdinn_2 : in std_logic; - tclk_2 : in std_logic; - rclk_2 : in std_logic; - tx_rst_2 : in std_logic; - rx_rst_2 : in std_logic; - txd_2 : in std_logic_vector(15 downto 0); - tx_k_2 : in std_logic_vector(1 downto 0); - tx_force_disp_2 : in std_logic_vector(1 downto 0); - tx_disp_sel_2 : in std_logic_vector(1 downto 0); - tx_crc_init_2 : in std_logic_vector(1 downto 0); - word_align_en_2 : in std_logic; - mca_align_en_2 : in std_logic; - felb_2 : in std_logic; - lsm_en_2 : in std_logic; - hdinp_3 : in std_logic; - hdinn_3 : in std_logic; - tclk_3 : in std_logic; - rclk_3 : in std_logic; - tx_rst_3 : in std_logic; - rx_rst_3 : in std_logic; - txd_3 : in std_logic_vector(15 downto 0); - tx_k_3 : in std_logic_vector(1 downto 0); - tx_force_disp_3 : in std_logic_vector(1 downto 0); - tx_disp_sel_3 : in std_logic_vector(1 downto 0); - tx_crc_init_3 : in std_logic_vector(1 downto 0); - word_align_en_3 : in std_logic; - mca_align_en_3 : in std_logic; - felb_3 : in std_logic; - lsm_en_3 : in std_logic; - mca_resync_01 : in std_logic; - mca_resync_23 : in std_logic; - quad_rst : in std_logic; - serdes_rst : in std_logic; - rxa_pclk : out std_logic; - rxb_pclk : out std_logic; - hdoutp_0 : out std_logic; - hdoutn_0 : out std_logic; - ref_0_sclk : out std_logic; - rx_0_sclk : out std_logic; - rxd_0 : out std_logic_vector(15 downto 0); - rx_k_0 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_0 : out std_logic_vector(1 downto 0); - rx_cv_detect_0 : out std_logic_vector(1 downto 0); - rx_crc_eop_0 : out std_logic_vector(1 downto 0); - lsm_status_0 : out std_logic; - hdoutp_1 : out std_logic; - hdoutn_1 : out std_logic; - ref_1_sclk : out std_logic; - rx_1_sclk : out std_logic; - rxd_1 : out std_logic_vector(15 downto 0); - rx_k_1 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_1 : out std_logic_vector(1 downto 0); - rx_cv_detect_1 : out std_logic_vector(1 downto 0); - rx_crc_eop_1 : out std_logic_vector(1 downto 0); - lsm_status_1 : out std_logic; - hdoutp_2 : out std_logic; - hdoutn_2 : out std_logic; - ref_2_sclk : out std_logic; - rx_2_sclk : OUT std_logic; - rxd_2 : OUT std_logic_vector(15 downto 0); - rx_k_2 : OUT std_logic_vector(1 downto 0); - rx_disp_err_detect_2 : OUT std_logic_vector(1 downto 0); - rx_cv_detect_2 : OUT std_logic_vector(1 downto 0); - rx_crc_eop_2 : OUT std_logic_vector(1 downto 0); - lsm_status_2 : OUT std_logic; - hdoutp_3 : OUT std_logic; - hdoutn_3 : OUT std_logic; - ref_3_sclk : OUT std_logic; - rx_3_sclk : OUT std_logic; - rxd_3 : OUT std_logic_vector(15 downto 0); - rx_k_3 : OUT std_logic_vector(1 downto 0); - rx_disp_err_detect_3 : out std_logic_vector(1 downto 0); - rx_cv_detect_3 : out std_logic_vector(1 downto 0); - rx_crc_eop_3 : out std_logic_vector(1 downto 0); - lsm_status_3 : out std_logic; - mca_aligned_01 : out std_logic; - mca_inskew_01 : out std_logic; - mca_outskew_01 : out std_logic; - mca_aligned_23 : out std_logic; - mca_inskew_23 : out std_logic; - mca_outskew_23 : out std_logic; - ref_pclk : out std_logic - ); - end component; - component flexi_PCS_synch - generic ( - HOW_MANY_CHANNELS : positive); - port ( - CLK : in std_logic_vector((HOW_MANY_CHANNELS+3)/4-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RESET : in std_logic; - RXD : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - RXD_SYNCH : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - CV : in std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0); - TXD : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - TXD_SYNCH : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - TX_FORCE_DISP : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0) - ); - end component; - component pll_ref - port ( - clk : in std_logic; - clkop : out std_logic; - clkos : out std_logic; - lock : out std_logic); - end component; - component trb_net16_hub_base - generic ( - MUX_SECURE_MODE : integer range 0 to 1; - MUX_WIDTH : integer range 1 to 3; - DATA_WIDTH : integer range 16 to 16; - NUM_WIDTH : integer range 2 to 2; - HUB_ADDRESS : std_logic_vector(15 downto 0); - HUB_CTRL_CHANNELNUM : integer range 0 to 3 :=3; - HUB_CTRL_DEPTH : integer range 0 to 6; - HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7; - MII_NUMBER : integer range 2 to 16; --- MII_INIT_DEPTH : hub_iobuf_config_t; --- MII_REPLY_DEPTH : hub_iobuf_config_t; - API_NUMBER : integer range 0 to 16; --- API_CHANNELS : hub_api_config_t; --- API_TYPE : hub_api_config_t; --- API_FIFO_TO_INT_DEPTH : hub_api_config_t; --- API_FIFO_TO_APL_DEPTH : hub_api_config_t; - TRG_NUMBER : integer range 0 to 16); --- TRG_CHANNELS : hub_api_config_t); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_OUT : out std_logic_vector (MII_NUMBER*DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_IN : in std_logic_vector (MII_NUMBER*DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0); - APL_DATA_IN : in std_logic_vector (API_NUMBER*DATA_WIDTH downto 0); - APL_PACKET_NUM_IN : in std_logic_vector (API_NUMBER*NUM_WIDTH downto 0); - APL_WRITE_IN : in std_logic_vector (API_NUMBER downto 0); - APL_FIFO_FULL_OUT : out std_logic_vector (API_NUMBER downto 0); - APL_SHORT_TRANSFER_IN : in std_logic_vector (API_NUMBER downto 0); - APL_DTYPE_IN : in std_logic_vector (API_NUMBER*4 downto 0); - APL_ERROR_PATTERN_IN : in std_logic_vector (API_NUMBER*32 downto 0); - APL_SEND_IN : in std_logic_vector (API_NUMBER downto 0); - APL_TARGET_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0); - APL_DATA_OUT : out std_logic_vector (API_NUMBER*16 downto 0); - APL_PACKET_NUM_OUT : out std_logic_vector (API_NUMBER*NUM_WIDTH downto 0); - APL_TYP_OUT : out std_logic_vector (API_NUMBER*3 downto 0); - APL_DATAREADY_OUT : out std_logic_vector (API_NUMBER downto 0); - APL_READ_IN : in std_logic_vector (API_NUMBER downto 0); - APL_RUN_OUT : out std_logic_vector (API_NUMBER downto 0); - APL_MY_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0); - APL_SEQNR_OUT : out std_logic_vector (API_NUMBER*8 downto 0); - TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0); - TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0); - TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0); - TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0); - TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0); - TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0); - HUB_STAT_CHANNEL : out std_logic_vector (2**(MUX_WIDTH-1)*16-1 downto 0); - HUB_STAT_GEN : out std_logic_vector (31 downto 0); - MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); - MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0)); - end component; - component simpleupcounter_16bit - port ( - QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component simpleupcounter_32bit - port ( - QOUT : out std_logic_vector(31 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - ----------------------------------------------------------------------------- - -- FLEXI_PCS - ----------------------------------------------------------------------------- - constant HOW_MANY_CHANNELS : integer := 2; - signal ref_pclk : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0); - signal rxd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal rxd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal rx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal rx_rst_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - signal cv_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal txd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal txd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal tx_force_disp_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal rxb_pclk_a : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0); - signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - signal flexi_pcs_synch_status_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - ----------------------------------------------------------------------------- - -- hub trb interface - ----------------------------------------------------------------------------- - signal hub_register_00_i : std_logic_vector(7 downto 0); - signal hub_register_01_i : std_logic_vector(7 downto 0); - signal hub_register_02_i : std_logic_vector(7 downto 0); - signal hub_register_03_i : std_logic_vector(7 downto 0); - signal hub_register_04_i : std_logic_vector(7 downto 0); - signal hub_register_05_i : std_logic_vector(7 downto 0); - signal hub_register_06_i : std_logic_vector(7 downto 0); - signal hub_register_07_i : std_logic_vector(7 downto 0); - signal hub_register_08_i : std_logic_vector(7 downto 0); - signal hub_register_09_i : std_logic_vector(7 downto 0); - signal hub_register_0a_i : std_logic_vector(7 downto 0); - signal hub_register_0b_i : std_logic_vector(7 downto 0); - signal hub_register_0c_i : std_logic_vector(7 downto 0); - signal hub_register_0d_i : std_logic_vector(7 downto 0); - signal hub_register_0e_i : std_logic_vector(7 downto 0); - signal hub_register_0f_i : std_logic_vector(7 downto 0); - signal hub_register_10_i : std_logic_vector(7 downto 0); - signal hub_register_11_i : std_logic_vector(7 downto 0); - signal hub_register_12_i : std_logic_vector(7 downto 0); - signal hub_register_13_i : std_logic_vector(7 downto 0); - signal hub_register_14_i : std_logic_vector(7 downto 0); - signal hub_register_15_i : std_logic_vector(7 downto 0); - signal hub_register_16_i : std_logic_vector(7 downto 0); - signal ADO_TTL_12 : std_logic; - ----------------------------------------------------------------------------- - -- flexi_PCS to api interface - ----------------------------------------------------------------------------- - signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal data_valid_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - - ----------------------------------------------------------------------------- - -- other - ----------------------------------------------------------------------------- - signal hub_register_0e_and_0d : std_logic_vector(15 downto 0); - signal cv_counter : std_logic_vector(31 downto 0); - signal cv_countera : std_logic_vector(31 downto 0); - signal serdes_ref_clk : std_logic; - signal serdes_ref_lock : std_logic; - signal serdes_ref_clks : std_logic; - signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*2 -1 downto 0); - signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*2 -1 downto 0); - signal med_error_in_i : std_logic_vector(HOW_MANY_CHANNELS*3 -1 downto 0); - signal mplex_ctrl_i : std_logic_vector (HOW_MANY_CHANNELS*32-1 downto 0); - signal word_counter_for_api_00 : std_logic_vector(1 downto 0); - signal word_counter_for_api_01 : std_logic_vector(1 downto 0); -begin - - REF_PLL: pll_ref - port map ( - clk => LVDS_CLK_200P, - clkop => serdes_ref_clk, - clkos => serdes_ref_clks, - lock => serdes_ref_lock); - QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate - begin - QUAD : serdes_fpga_ref_clk - port map ( --- refclkp => SERDES_200P, --- refclkn => SERDES_200N, - rxrefclk => serdes_ref_clk,--LVDS_CLK_200P, - refclk => serdes_ref_clk,--LVDS_CLK_200P, - hdinp_0 => SFP_INP_P(bit_index*4+0), - hdinn_0 => SFP_INP_N(bit_index*4+0), - tclk_0 => ref_pclk(bit_index), - rclk_0 => rx_clk_i(0+bit_index*4), - tx_rst_0 => '0', - rx_rst_0 => rx_rst_i(0+bit_index*4),--hub_register_0a_i(0), - txd_0 => txd_synch_i(15+bit_index*64 downto 0+bit_index*64), - tx_k_0 => "10", - tx_force_disp_0 => tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8), - tx_disp_sel_0 => "00", - tx_crc_init_0 => "00", - word_align_en_0 => '1', - mca_align_en_0 => '0', - felb_0 => '0', - lsm_en_0 => '0', - hdinp_1 => SFP_INP_P(bit_index*4+1), - hdinn_1 => SFP_INP_N(bit_index*4+1), - tclk_1 => ref_pclk(bit_index), - rclk_1 => rx_clk_i(1+bit_index*4), - tx_rst_1 => '0', - rx_rst_1 => rx_rst_i(1+bit_index*4), - txd_1 => txd_synch_i(31+bit_index*64 downto 16+bit_index*64), - tx_k_1 => "10", - tx_force_disp_1 => tx_force_disp_i(3+bit_index*8 downto 2+bit_index*8), - tx_disp_sel_1 => "00", - tx_crc_init_1 => "00", - word_align_en_1 => '1', - mca_align_en_1 => '0', - felb_1 => '0', - lsm_en_1 => '0', - hdinp_2 => SFP_INP_P(bit_index*4+2), - hdinn_2 => SFP_INP_N(bit_index*4+2), - tclk_2 => ref_pclk(bit_index), - rclk_2 => rx_clk_i(2+bit_index*4), - tx_rst_2 => '0', - rx_rst_2 => rx_rst_i(2+bit_index*4), - txd_2 => txd_synch_i(47+bit_index*64 downto 32+bit_index*64), - tx_k_2 => "10", - tx_force_disp_2 => tx_force_disp_i(5+bit_index*8 downto 4+bit_index*8), - tx_disp_sel_2 => "00", - tx_crc_init_2 => "00", - word_align_en_2 => '1', - mca_align_en_2 => '0', - felb_2 => '0', - lsm_en_2 => '0', - hdinp_3 => SFP_INP_P(bit_index*4+3), - hdinn_3 => SFP_INP_N(bit_index*4+3), - tclk_3 => ref_pclk(bit_index), - rclk_3 => rx_clk_i(3+bit_index*4), - tx_rst_3 => '0', - rx_rst_3 => rx_rst_i(3+bit_index*4), - txd_3 => txd_synch_i(63+bit_index*64 downto 48+bit_index*64), - tx_k_3 => "10", - tx_force_disp_3 => tx_force_disp_i(7+bit_index*8 downto 6+bit_index*8), - tx_disp_sel_3 => "00", - tx_crc_init_3 => "00", - word_align_en_3 => '1', - mca_align_en_3 => '0', - felb_3 => '0', - lsm_en_3 => '0', - mca_resync_01 => '0', - mca_resync_23 => '0', - quad_rst => '0', - serdes_rst => '0', - rxa_pclk => rx_clk_i(0+bit_index*4), - rxb_pclk => rxb_pclk_a(bit_index), - hdoutp_0 => SFP_OUT_P(bit_index*4+0), - hdoutn_0 => SFP_OUT_N(bit_index*4+0), - ref_0_sclk => open, - rx_0_sclk => open, - rxd_0 => rxd_i(15+bit_index*64 downto 0+bit_index*64), - rx_k_0 => rx_k_i(1+bit_index*8 downto 0+bit_index*8), - rx_disp_err_detect_0 => open, --rx_disp_err_detect_0_a, - rx_cv_detect_0 => cv_i(1+bit_index*8 downto 0+bit_index*8), - rx_crc_eop_0 => open, - lsm_status_0 => open, - hdoutp_1 => SFP_OUT_P(bit_index*4+1), - hdoutn_1 => SFP_OUT_N(bit_index*4+1), - ref_1_sclk => open, - rx_1_sclk => rx_clk_i(1+bit_index*4), - rxd_1 => rxd_i(31+bit_index*64 downto 16+bit_index*64), - rx_k_1 => rx_k_i(3+bit_index*8 downto 2+bit_index*8), - rx_disp_err_detect_1 => open, --rx_disp_err_detect_1_a, - rx_cv_detect_1 => cv_i(3+bit_index*8 downto 2+bit_index*8), - rx_crc_eop_1 => open, - lsm_status_1 => open, - hdoutp_2 => SFP_OUT_P(bit_index*4+2), - hdoutn_2 => SFP_OUT_N(bit_index*4+2), - ref_2_sclk => open, - rx_2_sclk => rx_clk_i(2+bit_index*4), - rxd_2 => rxd_i(47+bit_index*64 downto 32+bit_index*64), - rx_k_2 => rx_k_i(5+bit_index*8 downto 4+bit_index*8), - rx_disp_err_detect_2 => open, --rx_disp_err_detect_2_a, - rx_cv_detect_2 => cv_i(5+bit_index*8 downto 4+bit_index*8), - rx_crc_eop_2 => open, - lsm_status_2 => open, - hdoutp_3 => SFP_OUT_P(bit_index*4+3), - hdoutn_3 => SFP_OUT_N(bit_index*4+3), - ref_3_sclk => open, - rx_3_sclk => rx_clk_i(3+bit_index*4), - rxd_3 => rxd_i(63+bit_index*64 downto 48+bit_index*64), - rx_k_3 => rx_k_i(7+bit_index*8 downto 6+bit_index*8), - rx_disp_err_detect_3 => open, --rx_disp_err_detect_3_a, - rx_cv_detect_3 => cv_i(7+bit_index*8 downto 6+bit_index*8), - rx_crc_eop_3 => open, - lsm_status_3 => open, - mca_aligned_01 => open, --mca_aligned_01_i, - mca_inskew_01 => open, --mca_inskew_01_i, - mca_outskew_01 => open, --mca_outskew_01_i, - mca_aligned_23 => open, --mca_aligned_23_i, - mca_inskew_23 => open, --mca_inskew_23_i, - mca_outskew_23 => open, --mca_outskew_23_i, - ref_pclk => ref_pclk(bit_index) - ); - end generate QUAD_GENERATE; - FLEXI_PCS_INT : flexi_PCS_synch - generic map ( - HOW_MANY_CHANNELS => HOW_MANY_CHANNELS) - port map ( - CLK => ref_pclk,--, - RX_CLK => rx_clk_i, - RESET => ADO_TTL(0), - RXD => rxd_i, - RXD_SYNCH => rxd_synch_i, - RX_K => rx_k_i, - RX_RST => rx_rst_i, - CV => cv_i, - TXD => txd_i, - TXD_SYNCH => txd_synch_i, - TX_FORCE_DISP => tx_force_disp_i, - DATA_VALID_IN => data_valid_in_i, - DATA_VALID_OUT => data_valid_out_i, - FLEXI_PCS_SYNCH_STATUS => flexi_pcs_synch_status_i - ); - HUB_API: trb_net16_hub_base - generic map ( - MUX_SECURE_MODE => 0, - MUX_WIDTH => 2, - DATA_WIDTH => 16, - NUM_WIDTH => 2, - HUB_ADDRESS => x"F001", - HUB_CTRL_CHANNELNUM => 3, - HUB_CTRL_DEPTH => 1, - HUB_CTRL_REG_ADDR_WIDTH => 4, - MII_NUMBER => HOW_MANY_CHANNELS, - API_NUMBER => 0, - TRG_NUMBER => 0) --- MII_INIT_DEPTH => (6,6,6,6, --MII 6 --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6), --- MII_REPLY_DEPTH => (6,6,6,6,6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6, --- 6,6,6,6), 6,6,6,6), --- API_CHANNELS => (3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3), --- API_TYPE => (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), --- API_FIFO_TO_INT_DEPTH => (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1), --- API_FIFO_TO_APL_DEPTH => (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1), --- TRG_CHANNELS => (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0)) - port map ( - CLK => LVDS_CLK_200P, - RESET => ADO_TTL(0), - CLK_EN => '1', - MED_DATAREADY_OUT => OPT_DATA_VALID_OUT,--data_valid_in_i, - MED_DATA_OUT => OPT_DATA_OUT,--txd_i, - MED_PACKET_NUM_OUT => open, - MED_READ_IN => "11", - MED_DATAREADY_IN => OPT_DATA_VALID_IN,--data_valid_out_i, - MED_DATA_IN => OPT_DATA_IN,--rxd_synch_i, - MED_PACKET_NUM_IN => med_packet_num_in_i, - MED_READ_OUT => open, - MED_ERROR_IN => med_error_in_i, - APL_DATA_IN => (others => '0'), - APL_PACKET_NUM_IN => (others => '0'), - APL_WRITE_IN => (others => '0'), - APL_FIFO_FULL_OUT => open, - APL_SHORT_TRANSFER_IN => (others => '0'), - APL_DTYPE_IN => (others => '0'), - APL_ERROR_PATTERN_IN => (others => '0'), - APL_SEND_IN => (others => '0'), - APL_TARGET_ADDRESS_IN => (others => '0'), - APL_DATA_OUT => open, - APL_PACKET_NUM_OUT => open, - APL_TYP_OUT => open, - APL_DATAREADY_OUT => open, - APL_READ_IN => (others => '0'), - APL_RUN_OUT => open, - APL_MY_ADDRESS_IN => (others => '0'), - APL_SEQNR_OUT => open, - TRG_GOT_TRIGGER_OUT => open, - TRG_ERROR_PATTERN_OUT => open, - TRG_DTYPE_OUT => open, - TRG_SEQNR_OUT => open, - TRG_ERROR_PATTERN_IN => (others => '0'), - TRG_RELEASE_IN => (others => '0'), - HUB_STAT_CHANNEL => open, - HUB_STAT_GEN => open, - MPLEX_CTRL => mplex_ctrl_i, - MPLEX_STAT => open - ); - COUNTER_FOR_API_00: process (ref_pclk(0), ADO_TTL(0)) - begin - if rising_edge(ref_pclk(0)) then - if ADO_TTL(0) = '1' then - word_counter_for_api_00 <= (others => '0'); - elsif data_valid_out_i(0) = '1' then - word_counter_for_api_00 <= word_counter_for_api_00 + 1; - end if; - end if; - end process COUNTER_FOR_API_00; - med_packet_num_in_i(1 downto 0) <= word_counter_for_api_00; - COUNTER_FOR_API_01: process (ref_pclk(0), ADO_TTL(0)) - begin - if rising_edge(ref_pclk(0)) then - if ADO_TTL(0) = '1' then - word_counter_for_api_01 <= (others => '0'); - elsif data_valid_out_i(1) = '1' then - word_counter_for_api_01 <= word_counter_for_api_01 + 1; - end if; - end if; - end process COUNTER_FOR_API_01; - med_packet_num_in_i(3 downto 2) <= word_counter_for_api_01; - - - TRB_HUB_INT : trb_hub_interface - port map ( - CLK => ref_pclk(0), - RESET => ADO_TTL(0), - STROBE => ADO_TTL(9), - internal_data_in => ADO_TTL(18 downto 11), - internal_data_out => ADO_TTL(42 downto 35), - internal_address => ADO_TTL(34 downto 19), - internal_mode => ADO_TTL(10), - VALID_DATA_SENT => ADO_TTL(8), - HUB_REGISTER_00 => hub_register_00_i, - HUB_REGISTER_01 => hub_register_01_i, - HUB_REGISTER_02 => hub_register_02_i, - HUB_REGISTER_03 => hub_register_03_i, - HUB_REGISTER_04 => hub_register_04_i, - HUB_REGISTER_05 => hub_register_05_i, - HUB_REGISTER_06 => hub_register_06_i, - HUB_REGISTER_07 => hub_register_07_i, - HUB_REGISTER_08 => hub_register_08_i, - HUB_REGISTER_09 => hub_register_09_i, - HUB_REGISTER_0a => hub_register_0a_i, - HUB_REGISTER_0b => hub_register_0b_i, - HUB_REGISTER_0c => hub_register_0c_i, - HUB_REGISTER_0d => hub_register_0d_i, - HUB_REGISTER_0e => hub_register_0e_i, - HUB_REGISTER_0f => hub_register_0f_i, - HUB_REGISTER_10 => hub_register_10_i, - HUB_REGISTER_11 => hub_register_11_i, - HUB_REGISTER_12 => hub_register_12_i, - HUB_REGISTER_13 => hub_register_13_i, - HUB_REGISTER_14 => hub_register_14_i, - HUB_REGISTER_15 => hub_register_15_i, - HUB_REGISTER_16 => hub_register_16_i - ); - ADO_TTL(34 downto 9) <= (others => 'Z'); - hub_register_00_i <=flexi_pcs_synch_status_i(7 downto 0); - -- hub_register_01_i <= - hub_register_02_i <= rxd_synch_i(7 downto 0); --; --rxd_1_a(15 downto 8); - hub_register_03_i <= rxd_synch_i(23 downto 16); --cv_counter_ch1; --- hub_register_04_i <= rxd_synch_i(39 downto 32); --- hub_register_05_i <= rxd_synch_i(55 downto 48); --- hub_register_10_i <= rxd_i(7+8*16 downto 0+8*16); --; --rxd_1_a(15 downto 8); --- hub_register_11_i <= rxd_i(23+8*16 downto 16+8*16); --cv_counter_ch1; --- hub_register_12_i <= rxd_i(39+8*16 downto 32+8*16); --- hub_register_13_i <= rxd_i(63+8*16 downto 56+8*16); --- hub_register_14_i <= flexi_pcs_synch_status_i(23+8*16 downto 16+8*16); --- hub_register_15_i <= flexi_pcs_synch_status_i(39+8*16 downto 32+8*16); --- hub_register_16_i <= flexi_pcs_synch_status_i(63+8*16 downto 56+8*16); - --- hub_register_06_i <= flexi_pcs_synch_status_i(23 downto 16); --- hub_register_07_i <= flexi_pcs_synch_status_i(39 downto 32); --- hub_register_08_i <= flexi_pcs_synch_status_i(55 downto 48); --- hub_register_09_i <= x"0" & data_valid_out_i(3 downto 0); --- hub_register_0e_and_0d <= hub_register_0e_i & hub_register_0d_i; --- txd_i(15 downto 0) <= hub_register_0e_and_0d; --- txd_i(31 downto 16) <= hub_register_0e_and_0d; --- txd_i(47 downto 32) <= hub_register_0e_and_0d; --- txd_i(63 downto 48) <= hub_register_0e_and_0d; - --- txd_i(255 downto 64) <= hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & --- hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & --- hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d; --- data_valid_in_i(0) <= hub_register_0a_i(0); --- data_valid_in_i(1) <= hub_register_0a_i(1); --- data_valid_in_i(2) <= hub_register_0a_i(2); --- data_valid_in_i(3) <= hub_register_0a_i(3); --- data_valid_in_i(4) <= hub_register_0a_i(0); --- data_valid_in_i(5) <= hub_register_0a_i(1); --- data_valid_in_i(6) <= hub_register_0a_i(2); --- data_valid_in_i(7) <= hub_register_0a_i(3); --- data_valid_in_i(8) <= hub_register_0a_i(0); --- data_valid_in_i(9) <= hub_register_0a_i(1); --- data_valid_in_i(10) <= hub_register_0a_i(2); --- data_valid_in_i(11) <= hub_register_0a_i(3); --- data_valid_in_i(12) <= hub_register_0a_i(0); --- data_valid_in_i(13) <= hub_register_0a_i(1); --- data_valid_in_i(14) <= hub_register_0a_i(2); --- data_valid_in_i(15) <= hub_register_0a_i(3); - --- data_valid_in_i(15 downto 4) <= hub_register_0a_i(7 downto 0) & hub_register_0a_i(7 downto 4); - - -- RT(16 downto 1) <= (others => '0'); - - LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate - begin - LOK(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16); - TX_DIS(synch_fsm_state+1) <= '0'; - end generate LOK_STATUS_DIOD_EN; - LOK_STATUS_DIOD_DIS : for not_conected in 0 to 16-HOW_MANY_CHANNELS-1 generate - begin - WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate - LOK(16-not_conected) <= '1'; - TX_DIS(16-not_conected) <= '1'; - end generate WHEN_NOT_ALL_EN; - end generate LOK_STATUS_DIOD_DIS; - IPLL <= '0'; - OPLL <= '0'; - DBAD <= ADO_TTL(11); - DGOOD <= '1'; - DINT <= '0'; - DWAIT <= ADO_TTL(0); - CV_COUNTERaaa: process (LVDS_CLK_200P, ADO_TTL(0)) - begin - if rising_edge(LVDS_CLK_200P) then -- rising clock edge - if ADO_TTL(0) = '1' then -- asynchronous reset (active low) - cv_counter <= (others => '0'); - else - cv_counter <= cv_counter + 1; - end if; - end if; - end process CV_COUNTERaaa; - CV_COUNTERaab: process (ref_pclk(0), ADO_TTL(0)) - begin - if rising_edge(ref_pclk(0)) then -- rising clock edge - if ADO_TTL(0) = '1' then -- asynchronous reset (active low) - cv_countera <= (others => '0'); - else - cv_countera <= cv_countera + 1; - end if; - end if; - end process CV_COUNTERaab; - RT(16 downto 8) <= cv_counter(31 downto 23); - RT(2) <= cv_counter(0); - - RT(1) <= ref_pclk(0); - - RT(3) <= LVDS_CLK_200P; - - RT(4) <= cv_countera(0); - - RT(5) <= serdes_ref_clk; - RT(6) <= serdes_ref_clks; - RT(7) <= serdes_ref_lock; - ---------------------------------------------------------------------------- --- simulation - --------------------------------------------------------------------------- --- clock_gclk : process --- begin --- ref_pclk(0) <= '0'; --- wait for 5 ns; --- ref_pclk_a <= '1'; --- wait for 5 ns; --- end process; -end hub; - diff --git a/hub_1.xcf b/hub_1.xcf deleted file mode 100644 index 02b0792..0000000 --- a/hub_1.xcf +++ /dev/null @@ -1,99 +0,0 @@ - - - - - - JTAG - - 1 - NA - Generic JTAG Device - JTAG-NOP - All - JTAG-NOP - - 10 - 1111111111 - 1 - 0 - - Bypass - - - - 2 - hub - Lattice - LatticeSCM - LFSCM3GA25E - 0x0a812157 - 1020-ball FFBGA - LFSCM3GA25EP1-XXFF1020 - - 8 - 11111111 - 1 - 0 - - /home/marek/optical_hub/vhdl/workdir/hub.bit - /home/marek/.isplever_lin1/ispvmsystem/Database/xpga/sc/lfsc3ga25e.msk - 8/15/2007 14:18:24 - Fast Program - - - - 3 - power - NA - Generic JTAG Device - JTAG-NOP - All - JTAG-NOP - - 4 - 1111 - 1 - 0 - - Bypass - - - - - SEQUENTIAL - ENTIRED CHAIN - No Override - TLR - TLR - - - - TMS LOW; - TCK LOW; - TDI LOW; - TDO LOW; - CableEN HIGH; - - - diff --git a/hub_syn.prj b/hub_syn.prj deleted file mode 100644 index abbb35b..0000000 --- a/hub_syn.prj +++ /dev/null @@ -1,86 +0,0 @@ -#-- Synplicity, Inc. -#-- Version Synplify Pro 8.5.1 -#-- Project file /home/hadaq/marek_trbv2_ise/proj_1.prj -#-- Written on Tue Aug 7 10:50:43 2007 - - -#add_file options -add_file -vhdl -lib work "simpleupcounter_32bit.vhd" -#add_file -vhdl -lib work "serdes.vhd" -#add_file -vhdl -lib work "serdes_raw.vhd" -add_file -vhdl -lib work "hub.vhd" -add_file -vhdl -lib work "trb_hub_interface.vhd" -add_file -vhdl -lib work "f_divider.vhd" -add_file -vhdl -lib work "simpleupcounter_16bit.vhd" -add_file -vhdl -lib work "simpleupcounter_8bit.vhd" -add_file -vhdl -lib work "flexi_PCS_synch.vhd" -add_file -vhdl -lib work "flexi_PCS_channel_synch.vhd" -add_file -vhdl -lib work "flexi_PCS_fifo_LUT.vhd" -add_file -vhdl -lib work "flexi_PCS_fifo_EBR.vhd" -add_file -vhdl -lib work "serdes_fpga_ref_clk.vhd" -add_file -vhdl -lib work "pll_ref.vhd" -#add_file -vhdl -lib work "~/trbnet/xilinx/trb_net_fifo_arch.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_base_api.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_std.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_fifo.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_iobuf.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_active_api.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_passive_api.vhd" -#add_file -vhdl -lib work "~/trbnet/xilinx/shift_lut_x16.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_dummy_fifo.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_ibuf.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_io_multiplexer.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_obuf.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_pattern_gen.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_priority_arbiter.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_priority_encoder.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_sbuf.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_term_ibuf.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_term.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_active_apimbuf.vhd" -#add_file -vhdl -lib work "~/trbnet/trb_net_passive_apimbuf.vhd" - - - -#implementation: "workdir" -impl -add workdir -type fpga - -#device options -set_option -technology LATTICE-SCM -set_option -part LFSCM3GA25E -set_option -package FF1020C -set_option -speed_grade -5 - -#compilation/mapping options -set_option -default_enum_encoding sequential -set_option -symbolic_fsm_compiler 1 -set_option -resource_sharing 1 -set_option -top_module "hub" - -#map options -set_option -frequency 200.000 -set_option -fanout_limit 100 -set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 0 -set_option -fixgatedclocks 0 -set_option -force_gsr auto - -#simulation options -set_option -write_verilog 0 -set_option -write_vhdl 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 0 - -#set result format/file last -project -result_format "edif" -project -result_file "workdir/hub.edf" - - -# -#implementation attributes - -set_option -vlog_std v2001 -set_option -project_relative_includes 1 -impl -active "workdir" diff --git a/hub_tb.vhd b/hub_tb.vhd deleted file mode 100644 index 5ddb01c..0000000 --- a/hub_tb.vhd +++ /dev/null @@ -1,110 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.all; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; - -entity hub_tb is - - port ( - LVDS_CLK_200P : in std_logic; - LVDS_CLK_200N : in std_logic; - SERDES_200N : in std_logic; - SERDES_200P : in std_logic; - ADO_TTL : inout std_logic_vector(46 downto 0); - DBAD : out std_logic; - DGOOD : out std_logic; - DINT : out std_logic; - DWAIT : out std_logic; - LOK : out std_logic_vector(16 downto 1); - RT : out std_logic_vector(16 downto 1); - TX_DIS : out std_logic_vector(16 downto 1); - IPLL : out std_logic; - OPLL : out std_logic; - SFP_INP_N : in std_logic_vector(15 downto 0); - SFP_INP_P : in std_logic_vector(15 downto 0); - SFP_OUT_N : out std_logic_vector(15 downto 0); - SFP_OUT_P : out std_logic_vector(15 downto 0); - AAAAAAAA : in std_logic); -end hub_tb; - -architecture hub_tb of hub_tb is - -signal LVDS_CLK_200P_i : std_logic; -signal LVDS_CLK_200N_i : std_logic; -signal SERDES_200N_i : std_logic; -signal SERDES_200P_i : std_logic; -signal ADO_TTL_i : std_logic_vector(46 downto 0); -signal DBAD_i : std_logic; -signal DGOOD_i : std_logic; -signal DINT_i : std_logic; -signal DWAIT_i : std_logic; -signal LOK_i : std_logic_vector(16 downto 1); -signal RT_i : std_logic_vector(16 downto 1); -signal TX_DIS_i : std_logic_vector(16 downto 1); -signal IPLL_i : std_logic; -signal OPLL_i : std_logic; -signal SFP_INP_N_i : std_logic_vector(15 downto 0); -signal SFP_INP_P_i : std_logic_vector(15 downto 0); -signal SFP_OUT_N_i : std_logic_vector(15 downto 0); -signal SFP_OUT_P_i : std_logic_vector(15 downto 0); - -component hub - port ( - LVDS_CLK_200P : in std_logic; - LVDS_CLK_200N : in std_logic; - SERDES_200N : in std_logic; - SERDES_200P : in std_logic; - ADO_TTL : inout std_logic_vector(46 downto 0); - DBAD : out std_logic; - DGOOD : out std_logic; - DINT : out std_logic; - DWAIT : out std_logic; - LOK : out std_logic_vector(16 downto 1); - RT : out std_logic_vector(16 downto 1); - TX_DIS : out std_logic_vector(16 downto 1); - IPLL : out std_logic; - OPLL : out std_logic; - SFP_INP_N : in std_logic_vector(15 downto 0); - SFP_INP_P : in std_logic_vector(15 downto 0); - SFP_OUT_N : out std_logic_vector(15 downto 0); - SFP_OUT_P : out std_logic_vector(15 downto 0)); -end component; - - -begin -- of hub_tb - HUB_SIM: hub - port map ( - LVDS_CLK_200P => LVDS_CLK_200P_i, - LVDS_CLK_200N => LVDS_CLK_200N_i, - SERDES_200N => SERDES_200N_i, - SERDES_200P => SERDES_200P_i, - ADO_TTL => ADO_TTL_i, - DBAD => DBAD_i, - DGOOD => DGOOD_i, - DINT => DINT_i, - DWAIT => DWAIT_i, - LOK => LOK_i, - RT => RT_i, - TX_DIS => TX_DIS_i, - IPLL => IPLL_i, - OPLL => OPLL_i, - SFP_INP_N => SFP_INP_N_i, - SFP_INP_P => SFP_INP_P_i, - SFP_OUT_N => SFP_OUT_N_i, - SFP_OUT_P => SFP_OUT_P_i); - - clock_gclk : process - begin - SERDES_200P_i <= '0'; - SERDES_200N_i <= '1'; - wait for 5 ns; - SERDES_200P_i <= '1'; - SERDES_200N_i <= '0'; - wait for 5 ns; - end process; -end hub_tb; diff --git a/impact_batch_hub.txt b/impact_batch_hub.txt deleted file mode 100644 index 84cf5a7..0000000 --- a/impact_batch_hub.txt +++ /dev/null @@ -1,5 +0,0 @@ -setMode -bs -setCable -port stapl -file "hub_chain.stapl" -addDevice -p 1 -file "hub_1.svf" -Play -quit diff --git a/pll_ref.vhd b/pll_ref.vhd deleted file mode 100644 index 48256f8..0000000 --- a/pll_ref.vhd +++ /dev/null @@ -1,167 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55) --- Module Version: 3.6 ---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n pll_ref -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 100 -mfreq 200 -nfreq 100 -clkos_fdel 0 -fb 1 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e - --- Thu Nov 29 18:28:19 2007 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library SCM; -use SCM.COMPONENTS.all; --- synopsys translate_on - -entity pll_ref is - generic ( - SMI_OFFSET : in String := "0x410" - ); - port ( - clk: in std_logic; - clkop: out std_logic; - clkos: out std_logic; - lock: out std_logic); - attribute dont_touch : string; - attribute dont_touch of pll_ref : entity is "true"; -end pll_ref; - -architecture Structure of pll_ref is - - -- internal signal declarations - signal scuba_vlo: std_logic; - signal scuba_vhi: std_logic; - signal clkos_t: std_logic; - signal clkop_t: std_logic; - signal clk_t: std_logic; - - attribute module_type : string; - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component EHXPLLA - generic (SMI_OFFSET : in String - -- synopsys translate_off - ; GSR : in String; CLKOS_DIV : in Integer; - CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; - CLKI_DIV : in Integer; CLKOS_FDEL : in Integer; - CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer; - CLKOS_MODE : in String; CLKOP_MODE : in String; - PHASEADJ : in Integer; CLKOS_VCODEL : in Integer - -- synopsys translate_on - ); - port (SMIADDR9: in std_logic; SMIADDR8: in std_logic; - SMIADDR7: in std_logic; SMIADDR6: in std_logic; - SMIADDR5: in std_logic; SMIADDR4: in std_logic; - SMIADDR3: in std_logic; SMIADDR2: in std_logic; - SMIADDR1: in std_logic; SMIADDR0: in std_logic; - SMIRD: in std_logic; SMIWR: in std_logic; - SMICLK: in std_logic; SMIWDATA: in std_logic; - SMIRSTN: in std_logic; CLKI: in std_logic; - CLKFB: in std_logic; RSTN: in std_logic; - CLKOS: out std_logic; CLKOP: out std_logic; - LOCK: out std_logic; CLKINTFB: out std_logic; - SMIRDATA: out std_logic); - end component; - attribute module_type of EHXPLLA : component is "EHXPLLA"; - attribute ip_type : string; - attribute FREQUENCY_PIN_CLKOS : string; - attribute FREQUENCY_PIN_CLKOP : string; - attribute FREQUENCY_PIN_CLKI : string; - attribute VCO_LOWERFREQ : string; - attribute GMCFREQSEL : string; - attribute GSR : string; - attribute SPREAD_DIV2 : string; - attribute SPREAD_DIV1 : string; - attribute SPREAD_DRIFT : string; - attribute SPREAD : string; - attribute CLKFB_FDEL : string; - attribute CLKI_FDEL : string; - attribute CLKFB_PDEL : string; - attribute CLKI_PDEL : string; - attribute LF_RESISTOR : string; - attribute LF_IX5UA : string; - attribute CLKOS_FDEL : string; - attribute CLKOS_VCODEL : string; - attribute PHASEADJ : string; - attribute CLKOS_MODE : string; - attribute CLKOP_MODE : string; - attribute CLKOS_DIV : string; - attribute CLKOP_DIV : string; - attribute CLKFB_DIV : string; - attribute CLKI_DIV : string; - attribute ip_type of pll_ref_0_0 : label is "EHXPLLA"; - attribute FREQUENCY_PIN_CLKOS of pll_ref_0_0 : label is "100.000000"; - attribute FREQUENCY_PIN_CLKOP of pll_ref_0_0 : label is "200.000000"; - attribute FREQUENCY_PIN_CLKI of pll_ref_0_0 : label is "100.000000"; - attribute VCO_LOWERFREQ of pll_ref_0_0 : label is "DISABLED"; - attribute GMCFREQSEL of pll_ref_0_0 : label is "HIGH"; - attribute GSR of pll_ref_0_0 : label is "DISABLED"; - attribute SPREAD_DIV2 of pll_ref_0_0 : label is "2"; - attribute SPREAD_DIV1 of pll_ref_0_0 : label is "2"; - attribute SPREAD_DRIFT of pll_ref_0_0 : label is "1"; - attribute SPREAD of pll_ref_0_0 : label is "DISABLED"; - attribute CLKFB_FDEL of pll_ref_0_0 : label is "0"; - attribute CLKI_FDEL of pll_ref_0_0 : label is "0"; - attribute CLKFB_PDEL of pll_ref_0_0 : label is "DEL0"; - attribute CLKI_PDEL of pll_ref_0_0 : label is "DEL0"; - attribute LF_RESISTOR of pll_ref_0_0 : label is "0b111010"; - attribute LF_IX5UA of pll_ref_0_0 : label is "31"; - attribute CLKOS_FDEL of pll_ref_0_0 : label is "0"; - attribute CLKOS_VCODEL of pll_ref_0_0 : label is "0"; - attribute PHASEADJ of pll_ref_0_0 : label is "0"; - attribute CLKOS_MODE of pll_ref_0_0 : label is "DIV"; - attribute CLKOP_MODE of pll_ref_0_0 : label is "DIV"; - attribute CLKOS_DIV of pll_ref_0_0 : label is "6"; - attribute CLKOP_DIV of pll_ref_0_0 : label is "3"; - attribute CLKFB_DIV of pll_ref_0_0 : label is "2"; - attribute CLKI_DIV of pll_ref_0_0 : label is "1"; - attribute syn_keep : boolean; - attribute syn_noprune : boolean; - attribute syn_noprune of Structure : architecture is true; - -begin - -- component instantiation statements - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - pll_ref_0_0: EHXPLLA - generic map (SMI_OFFSET=> SMI_OFFSET - -- synopsys translate_off - , GSR=> "DISABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0, - CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "DIV", - CLKOP_MODE=> "DIV", CLKOS_DIV=> 6, CLKOP_DIV=> 3, CLKFB_DIV=> 2, - CLKI_DIV=> 1 - -- synopsys translate_on - ) - port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, - SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, - SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, - SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, - SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, - SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, - SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>clkop_t, - RSTN=>scuba_vhi, CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, - CLKINTFB=>open, SMIRDATA=>open); - - clkos <= clkos_t; - clkop <= clkop_t; - clk_t <= clk; -end Structure; - --- synopsys translate_off -library SCM; -configuration Structure_CON of pll_ref is - for Structure - for all:VHI use entity SCM.VHI(V); end for; - for all:VLO use entity SCM.VLO(V); end for; - for all:EHXPLLA use entity SCM.EHXPLLA(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/serdes_fpga_ref_clk.txt b/serdes_fpga_ref_clk.txt deleted file mode 100644 index b798524..0000000 --- a/serdes_fpga_ref_clk.txt +++ /dev/null @@ -1,50 +0,0 @@ - - -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCS quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCS quad to the final design requirements. -# channel_0 is in "8b10b" mode -# channel_1 is in "8b10b" mode -# channel_2 is in "8b10b" mode -# channel_3 is in "8b10b" mode - -ch0 13 03 # Powerup Channel -ch0 00 00 -ch1 13 03 # Powerup Channel -ch1 00 00 -ch2 13 03 # Powerup Channel -ch2 00 00 -ch3 13 03 # Powerup Channel -ch3 00 00 -quad 00 00 -quad 01 E4 -quad 28 50 # Reference clock multiplier -quad 29 11 # FPGA sourced refclk -quad 02 00 # ref_pclk source is ch0 -quad 04 00 # MCA enable 4 channels - -quad 18 10 # 8b10b Mode - quad 14 FF # Word Alignment Mask - quad 15 7c # +ve K - quad 16 b6 # -ve K -quad 17 36 - -quad 19 8C # Enable word_align_en port, FPGA bus width is 16-bit/20-bit -ch0 14 90 # 16% pre-emphasis -ch0 15 10 # +6dB equalization -ch1 14 90 # 16% pre-emphasis -ch1 15 10 # +6dB equalization -ch2 14 90 # 16% pre-emphasis -ch2 15 10 # +6dB equalization -ch3 14 90 # 16% pre-emphasis -ch3 15 10 # +6dB equalization - -# These lines must appear last in the autoconfig file. These lines apply the correct -# reset sequence to the PCS block upon bitstream configuration -quad 41 00 # de-assert serdes_rst -quad 40 ff # assert datapath reset for all channels -quad 40 00 # de-assert datapath reset for all channels - - - diff --git a/serdes_fpga_ref_clk.vhd b/serdes_fpga_ref_clk.vhd deleted file mode 100644 index 36d920f..0000000 --- a/serdes_fpga_ref_clk.vhd +++ /dev/null @@ -1,2437 +0,0 @@ - - --- channel_0 is in "8b10b" mode --- channel_1 is in "8b10b" mode --- channel_2 is in "8b10b" mode --- channel_3 is in "8b10b" mode - ---synopsys translate_off - -library pcsa_mti_work; -use pcsa_mti_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSA is -GENERIC( - CONFIG_FILE : String := "serdes_fpga_ref_clk.txt" - ); -port ( - HDINP0 : in std_logic; - HDINN0 : in std_logic; - HDINP1 : in std_logic; - HDINN1 : in std_logic; - HDINP2 : in std_logic; - HDINN2 : in std_logic; - HDINP3 : in std_logic; - HDINN3 : in std_logic; - HDOUTP0 : out std_logic; - HDOUTN0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTP3 : out std_logic; - HDOUTN3 : out std_logic; - REFCLKP : in std_logic; - REFCLKN : in std_logic; - RXREFCLKP : in std_logic; - RXREFCLKN : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_MACRO_RST : in std_logic; - - FFC_LANE_TX_RST0 : in std_logic; - FFC_LANE_TX_RST1 : in std_logic; - FFC_LANE_TX_RST2 : in std_logic; - FFC_LANE_TX_RST3 : in std_logic; - - FFC_LANE_RX_RST0 : in std_logic; - FFC_LANE_RX_RST1 : in std_logic; - FFC_LANE_RX_RST2 : in std_logic; - FFC_LANE_RX_RST3 : in std_logic; - - FFC_PCIE_EI_EN_0 : in std_logic; - FFC_PCIE_EI_EN_1 : in std_logic; - FFC_PCIE_EI_EN_2 : in std_logic; - FFC_PCIE_EI_EN_3 : in std_logic; - - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - - FFC_PCIE_TX_0 : in std_logic; - FFC_PCIE_TX_1 : in std_logic; - FFC_PCIE_TX_2 : in std_logic; - FFC_PCIE_TX_3 : in std_logic; - - FFC_PCIE_RX_0 : in std_logic; - FFC_PCIE_RX_1 : in std_logic; - FFC_PCIE_RX_2 : in std_logic; - FFC_PCIE_RX_3 : in std_logic; - - FFC_SD_0 : in std_logic; - FFC_SD_1 : in std_logic; - FFC_SD_2 : in std_logic; - FFC_SD_3 : in std_logic; - - FFC_EN_CGA_0 : in std_logic; - FFC_EN_CGA_1 : in std_logic; - FFC_EN_CGA_2 : in std_logic; - FFC_EN_CGA_3 : in std_logic; - - FFC_ALIGN_EN_0 : in std_logic; - FFC_ALIGN_EN_1 : in std_logic; - FFC_ALIGN_EN_2 : in std_logic; - FFC_ALIGN_EN_3 : in std_logic; - - FFC_AB_RESET : in std_logic; - FFC_CD_RESET : in std_logic; - - FFS_LS_STATUS_0 : out std_logic; - FFS_LS_STATUS_1 : out std_logic; - FFS_LS_STATUS_2 : out std_logic; - FFS_LS_STATUS_3 : out std_logic; - - FFS_AB_STATUS : out std_logic; - FFS_CD_STATUS : out std_logic; - - FFS_AB_ALIGNED : out std_logic; - FFS_CD_ALIGNED : out std_logic; - - FFS_RLOS_LO0 : out std_logic; - FFS_RLOS_LO1 : out std_logic; - FFS_RLOS_LO2 : out std_logic; - FFS_RLOS_LO3 : out std_logic; - - FFS_AB_FAILED : out std_logic; - FFS_CD_FAILED : out std_logic; - - FFC_FB_LB_0 : in std_logic; - FFC_FB_LB_1 : in std_logic; - FFC_FB_LB_2 : in std_logic; - FFC_FB_LB_3 : in std_logic; - - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - - FFS_CC_ORUN_0 : out std_logic; - FFS_CC_ORUN_1 : out std_logic; - FFS_CC_ORUN_2 : out std_logic; - FFS_CC_ORUN_3 : out std_logic; - - FFS_CC_URUN_0 : out std_logic; - FFS_CC_URUN_1 : out std_logic; - FFS_CC_URUN_2 : out std_logic; - FFS_CC_URUN_3 : out std_logic; - - FFC_CK_CORE_TX : in std_logic; - FFC_CK_CORE_RX : in std_logic; - RDATAO_7 : out std_logic; - RDATAO_6 : out std_logic; - RDATAO_5 : out std_logic; - RDATAO_4 : out std_logic; - RDATAO_3 : out std_logic; - RDATAO_2 : out std_logic; - RDATAO_1 : out std_logic; - RDATAO_0 : out std_logic; - INTO : out std_logic; - - ADDRI_7 : in std_logic; - ADDRI_6 : in std_logic; - ADDRI_5 : in std_logic; - ADDRI_4 : in std_logic; - ADDRI_3 : in std_logic; - ADDRI_2 : in std_logic; - ADDRI_1 : in std_logic; - ADDRI_0 : in std_logic; - WDATAI_7 : in std_logic; - WDATAI_6 : in std_logic; - WDATAI_5 : in std_logic; - WDATAI_4 : in std_logic; - WDATAI_3 : in std_logic; - WDATAI_2 : in std_logic; - WDATAI_1 : in std_logic; - WDATAI_0 : in std_logic; - RDI : in std_logic; - WSTBI : in std_logic; - - CS_CHIF_0 : in std_logic; - CS_CHIF_1 : in std_logic; - CS_CHIF_2 : in std_logic; - CS_CHIF_3 : in std_logic; - CS_QIF : in std_logic; - - QUAD_ID_1 : in std_logic; - QUAD_ID_0 : in std_logic; - - FF_SYSCLK_P1 : out std_logic; - - FF_SYSCLK0 : out std_logic; - FF_SYSCLK1 : out std_logic; - FF_SYSCLK2 : out std_logic; - FF_SYSCLK3 : out std_logic; - - FF_RXCLK_P1 : out std_logic; - FF_RXCLK_P2 : out std_logic; - - FF_RXCLK0 : out std_logic; - FF_RXCLK1 : out std_logic; - FF_RXCLK2 : out std_logic; - FF_RXCLK3 : out std_logic; - - QUAD_CLK : out std_logic; - - GRP_CLK_P1_3 : in std_logic; - GRP_CLK_P1_2 : in std_logic; - GRP_CLK_P1_1 : in std_logic; - GRP_CLK_P1_0 : in std_logic; - - GRP_CLK_P2_3 : in std_logic; - GRP_CLK_P2_2 : in std_logic; - GRP_CLK_P2_1 : in std_logic; - GRP_CLK_P2_0 : in std_logic; - - GRP_START_3 : in std_logic; - GRP_START_2 : in std_logic; - GRP_START_1 : in std_logic; - GRP_START_0 : in std_logic; - - GRP_DONE_3 : in std_logic; - GRP_DONE_2 : in std_logic; - GRP_DONE_1 : in std_logic; - GRP_DONE_0 : in std_logic; - - GRP_DESKEW_ERROR_3 : in std_logic; - GRP_DESKEW_ERROR_2 : in std_logic; - GRP_DESKEW_ERROR_1 : in std_logic; - GRP_DESKEW_ERROR_0 : in std_logic; - - IQA_START_LS : out std_logic; - IQA_DONE_LS : out std_logic; - IQA_AND_FP1_LS : out std_logic; - IQA_AND_FP0_LS : out std_logic; - IQA_OR_FP1_LS : out std_logic; - IQA_OR_FP0_LS : out std_logic; - IQA_RST_N : out std_logic; - - FF_TCLK0 : in std_logic; - FF_TCLK1 : in std_logic; - FF_TCLK2 : in std_logic; - FF_TCLK3 : in std_logic; - - FF_RCLK0 : in std_logic; - FF_RCLK1 : in std_logic; - FF_RCLK2 : in std_logic; - FF_RCLK3 : in std_logic; - TCK_FMACP : in std_logic; - - FF_TXD_0_23 : in std_logic; - FF_TXD_0_22 : in std_logic; - FF_TXD_0_21 : in std_logic; - FF_TXD_0_20 : in std_logic; - FF_TXD_0_19 : in std_logic; - FF_TXD_0_18 : in std_logic; - FF_TXD_0_17 : in std_logic; - FF_TXD_0_16 : in std_logic; - FF_TXD_0_15 : in std_logic; - FF_TXD_0_14 : in std_logic; - FF_TXD_0_13 : in std_logic; - FF_TXD_0_12 : in std_logic; - FF_TXD_0_11 : in std_logic; - FF_TXD_0_10 : in std_logic; - FF_TXD_0_9 : in std_logic; - FF_TXD_0_8 : in std_logic; - FF_TXD_0_7 : in std_logic; - FF_TXD_0_6 : in std_logic; - FF_TXD_0_5 : in std_logic; - FF_TXD_0_4 : in std_logic; - FF_TXD_0_3 : in std_logic; - FF_TXD_0_2 : in std_logic; - FF_TXD_0_1 : in std_logic; - FF_TXD_0_0 : in std_logic; - FB_RXD_0_23 : out std_logic; - FB_RXD_0_22 : out std_logic; - FB_RXD_0_21 : out std_logic; - FB_RXD_0_20 : out std_logic; - FB_RXD_0_19 : out std_logic; - FB_RXD_0_18 : out std_logic; - FB_RXD_0_17 : out std_logic; - FB_RXD_0_16 : out std_logic; - FB_RXD_0_15 : out std_logic; - FB_RXD_0_14 : out std_logic; - FB_RXD_0_13 : out std_logic; - FB_RXD_0_12 : out std_logic; - FB_RXD_0_11 : out std_logic; - FB_RXD_0_10 : out std_logic; - FB_RXD_0_9 : out std_logic; - FB_RXD_0_8 : out std_logic; - FB_RXD_0_7 : out std_logic; - FB_RXD_0_6 : out std_logic; - FB_RXD_0_5 : out std_logic; - FB_RXD_0_4 : out std_logic; - FB_RXD_0_3 : out std_logic; - FB_RXD_0_2 : out std_logic; - FB_RXD_0_1 : out std_logic; - FB_RXD_0_0 : out std_logic; - FF_TXD_1_23 : in std_logic; - FF_TXD_1_22 : in std_logic; - FF_TXD_1_21 : in std_logic; - FF_TXD_1_20 : in std_logic; - FF_TXD_1_19 : in std_logic; - FF_TXD_1_18 : in std_logic; - FF_TXD_1_17 : in std_logic; - FF_TXD_1_16 : in std_logic; - FF_TXD_1_15 : in std_logic; - FF_TXD_1_14 : in std_logic; - FF_TXD_1_13 : in std_logic; - FF_TXD_1_12 : in std_logic; - FF_TXD_1_11 : in std_logic; - FF_TXD_1_10 : in std_logic; - FF_TXD_1_9 : in std_logic; - FF_TXD_1_8 : in std_logic; - FF_TXD_1_7 : in std_logic; - FF_TXD_1_6 : in std_logic; - FF_TXD_1_5 : in std_logic; - FF_TXD_1_4 : in std_logic; - FF_TXD_1_3 : in std_logic; - FF_TXD_1_2 : in std_logic; - FF_TXD_1_1 : in std_logic; - FF_TXD_1_0 : in std_logic; - FB_RXD_1_23 : out std_logic; - FB_RXD_1_22 : out std_logic; - FB_RXD_1_21 : out std_logic; - FB_RXD_1_20 : out std_logic; - FB_RXD_1_19 : out std_logic; - FB_RXD_1_18 : out std_logic; - FB_RXD_1_17 : out std_logic; - FB_RXD_1_16 : out std_logic; - FB_RXD_1_15 : out std_logic; - FB_RXD_1_14 : out std_logic; - FB_RXD_1_13 : out std_logic; - FB_RXD_1_12 : out std_logic; - FB_RXD_1_11 : out std_logic; - FB_RXD_1_10 : out std_logic; - FB_RXD_1_9 : out std_logic; - FB_RXD_1_8 : out std_logic; - FB_RXD_1_7 : out std_logic; - FB_RXD_1_6 : out std_logic; - FB_RXD_1_5 : out std_logic; - FB_RXD_1_4 : out std_logic; - FB_RXD_1_3 : out std_logic; - FB_RXD_1_2 : out std_logic; - FB_RXD_1_1 : out std_logic; - FB_RXD_1_0 : out std_logic; - FF_TXD_2_23 : in std_logic; - FF_TXD_2_22 : in std_logic; - FF_TXD_2_21 : in std_logic; - FF_TXD_2_20 : in std_logic; - FF_TXD_2_19 : in std_logic; - FF_TXD_2_18 : in std_logic; - FF_TXD_2_17 : in std_logic; - FF_TXD_2_16 : in std_logic; - FF_TXD_2_15 : in std_logic; - FF_TXD_2_14 : in std_logic; - FF_TXD_2_13 : in std_logic; - FF_TXD_2_12 : in std_logic; - FF_TXD_2_11 : in std_logic; - FF_TXD_2_10 : in std_logic; - FF_TXD_2_9 : in std_logic; - FF_TXD_2_8 : in std_logic; - FF_TXD_2_7 : in std_logic; - FF_TXD_2_6 : in std_logic; - FF_TXD_2_5 : in std_logic; - FF_TXD_2_4 : in std_logic; - FF_TXD_2_3 : in std_logic; - FF_TXD_2_2 : in std_logic; - FF_TXD_2_1 : in std_logic; - FF_TXD_2_0 : in std_logic; - FB_RXD_2_23 : out std_logic; - FB_RXD_2_22 : out std_logic; - FB_RXD_2_21 : out std_logic; - FB_RXD_2_20 : out std_logic; - FB_RXD_2_19 : out std_logic; - FB_RXD_2_18 : out std_logic; - FB_RXD_2_17 : out std_logic; - FB_RXD_2_16 : out std_logic; - FB_RXD_2_15 : out std_logic; - FB_RXD_2_14 : out std_logic; - FB_RXD_2_13 : out std_logic; - FB_RXD_2_12 : out std_logic; - FB_RXD_2_11 : out std_logic; - FB_RXD_2_10 : out std_logic; - FB_RXD_2_9 : out std_logic; - FB_RXD_2_8 : out std_logic; - FB_RXD_2_7 : out std_logic; - FB_RXD_2_6 : out std_logic; - FB_RXD_2_5 : out std_logic; - FB_RXD_2_4 : out std_logic; - FB_RXD_2_3 : out std_logic; - FB_RXD_2_2 : out std_logic; - FB_RXD_2_1 : out std_logic; - FB_RXD_2_0 : out std_logic; - FF_TXD_3_23 : in std_logic; - FF_TXD_3_22 : in std_logic; - FF_TXD_3_21 : in std_logic; - FF_TXD_3_20 : in std_logic; - FF_TXD_3_19 : in std_logic; - FF_TXD_3_18 : in std_logic; - FF_TXD_3_17 : in std_logic; - FF_TXD_3_16 : in std_logic; - FF_TXD_3_15 : in std_logic; - FF_TXD_3_14 : in std_logic; - FF_TXD_3_13 : in std_logic; - FF_TXD_3_12 : in std_logic; - FF_TXD_3_11 : in std_logic; - FF_TXD_3_10 : in std_logic; - FF_TXD_3_9 : in std_logic; - FF_TXD_3_8 : in std_logic; - FF_TXD_3_7 : in std_logic; - FF_TXD_3_6 : in std_logic; - FF_TXD_3_5 : in std_logic; - FF_TXD_3_4 : in std_logic; - FF_TXD_3_3 : in std_logic; - FF_TXD_3_2 : in std_logic; - FF_TXD_3_1 : in std_logic; - FF_TXD_3_0 : in std_logic; - FB_RXD_3_23 : out std_logic; - FB_RXD_3_22 : out std_logic; - FB_RXD_3_21 : out std_logic; - FB_RXD_3_20 : out std_logic; - FB_RXD_3_19 : out std_logic; - FB_RXD_3_18 : out std_logic; - FB_RXD_3_17 : out std_logic; - FB_RXD_3_16 : out std_logic; - FB_RXD_3_15 : out std_logic; - FB_RXD_3_14 : out std_logic; - FB_RXD_3_13 : out std_logic; - FB_RXD_3_12 : out std_logic; - FB_RXD_3_11 : out std_logic; - FB_RXD_3_10 : out std_logic; - FB_RXD_3_9 : out std_logic; - FB_RXD_3_8 : out std_logic; - FB_RXD_3_7 : out std_logic; - FB_RXD_3_6 : out std_logic; - FB_RXD_3_5 : out std_logic; - FB_RXD_3_4 : out std_logic; - FB_RXD_3_3 : out std_logic; - FB_RXD_3_2 : out std_logic; - FB_RXD_3_1 : out std_logic; - FB_RXD_3_0 : out std_logic; - TCK_FMAC : out std_logic; - BS4PAD_0 : out std_logic; - BS4PAD_1 : out std_logic; - BS4PAD_2 : out std_logic; - BS4PAD_3 : out std_logic; - COUT_21 : out std_logic; - COUT_20 : out std_logic; - COUT_19 : out std_logic; - COUT_18 : out std_logic; - COUT_17 : out std_logic; - COUT_16 : out std_logic; - COUT_15 : out std_logic; - COUT_14 : out std_logic; - COUT_13 : out std_logic; - COUT_12 : out std_logic; - COUT_11 : out std_logic; - COUT_10 : out std_logic; - COUT_9 : out std_logic; - COUT_8 : out std_logic; - COUT_7 : out std_logic; - COUT_6 : out std_logic; - COUT_5 : out std_logic; - COUT_4 : out std_logic; - COUT_3 : out std_logic; - COUT_2 : out std_logic; - COUT_1 : out std_logic; - COUT_0 : out std_logic; - CIN_12 : in std_logic; - CIN_11 : in std_logic; - CIN_10 : in std_logic; - CIN_9 : in std_logic; - CIN_8 : in std_logic; - CIN_7 : in std_logic; - CIN_6 : in std_logic; - CIN_5 : in std_logic; - CIN_4 : in std_logic; - CIN_3 : in std_logic; - CIN_2 : in std_logic; - CIN_1 : in std_logic; - CIN_0 : in std_logic; - TESTCLK_MACO : in std_logic -); - -end PCSA; - -architecture PCSA_arch of PCSA is - -component PCSA_sim -GENERIC( - CONFIG_FILE : String - ); -port ( - HDINP0 : in std_logic; - HDINN0 : in std_logic; - HDINP1 : in std_logic; - HDINN1 : in std_logic; - HDINP2 : in std_logic; - HDINN2 : in std_logic; - HDINP3 : in std_logic; - HDINN3 : in std_logic; - HDOUTP0 : out std_logic; - HDOUTN0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTP3 : out std_logic; - HDOUTN3 : out std_logic; - REFCLKP : in std_logic; - REFCLKN : in std_logic; - RXREFCLKP : in std_logic; - RXREFCLKN : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_MACRO_RST : in std_logic; - - FFC_LANE_TX_RST0 : in std_logic; - FFC_LANE_TX_RST1 : in std_logic; - FFC_LANE_TX_RST2 : in std_logic; - FFC_LANE_TX_RST3 : in std_logic; - - FFC_LANE_RX_RST0 : in std_logic; - FFC_LANE_RX_RST1 : in std_logic; - FFC_LANE_RX_RST2 : in std_logic; - FFC_LANE_RX_RST3 : in std_logic; - - FFC_PCIE_EI_EN_0 : in std_logic; - FFC_PCIE_EI_EN_1 : in std_logic; - FFC_PCIE_EI_EN_2 : in std_logic; - FFC_PCIE_EI_EN_3 : in std_logic; - - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - - FFC_PCIE_TX_0 : in std_logic; - FFC_PCIE_TX_1 : in std_logic; - FFC_PCIE_TX_2 : in std_logic; - FFC_PCIE_TX_3 : in std_logic; - - FFC_PCIE_RX_0 : in std_logic; - FFC_PCIE_RX_1 : in std_logic; - FFC_PCIE_RX_2 : in std_logic; - FFC_PCIE_RX_3 : in std_logic; - - FFC_SD_0 : in std_logic; - FFC_SD_1 : in std_logic; - FFC_SD_2 : in std_logic; - FFC_SD_3 : in std_logic; - - FFC_EN_CGA_0 : in std_logic; - FFC_EN_CGA_1 : in std_logic; - FFC_EN_CGA_2 : in std_logic; - FFC_EN_CGA_3 : in std_logic; - - FFC_ALIGN_EN_0 : in std_logic; - FFC_ALIGN_EN_1 : in std_logic; - FFC_ALIGN_EN_2 : in std_logic; - FFC_ALIGN_EN_3 : in std_logic; - - FFC_AB_RESET : in std_logic; - FFC_CD_RESET : in std_logic; - - FFS_LS_STATUS_0 : out std_logic; - FFS_LS_STATUS_1 : out std_logic; - FFS_LS_STATUS_2 : out std_logic; - FFS_LS_STATUS_3 : out std_logic; - - FFS_AB_STATUS : out std_logic; - FFS_CD_STATUS : out std_logic; - - FFS_AB_ALIGNED : out std_logic; - FFS_CD_ALIGNED : out std_logic; - - FFS_AB_FAILED : out std_logic; - FFS_CD_FAILED : out std_logic; - - FFS_RLOS_LO0 : out std_logic; - FFS_RLOS_LO1 : out std_logic; - FFS_RLOS_LO2 : out std_logic; - FFS_RLOS_LO3 : out std_logic; - - FFC_FB_LB_0 : in std_logic; - FFC_FB_LB_1 : in std_logic; - FFC_FB_LB_2 : in std_logic; - FFC_FB_LB_3 : in std_logic; - - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - - FFS_CC_ORUN_0 : out std_logic; - FFS_CC_ORUN_1 : out std_logic; - FFS_CC_ORUN_2 : out std_logic; - FFS_CC_ORUN_3 : out std_logic; - - FFS_CC_URUN_0 : out std_logic; - FFS_CC_URUN_1 : out std_logic; - FFS_CC_URUN_2 : out std_logic; - FFS_CC_URUN_3 : out std_logic; - - FFC_CK_CORE_TX : in std_logic; - FFC_CK_CORE_RX : in std_logic; - RDATAO_7 : out std_logic; - RDATAO_6 : out std_logic; - RDATAO_5 : out std_logic; - RDATAO_4 : out std_logic; - RDATAO_3 : out std_logic; - RDATAO_2 : out std_logic; - RDATAO_1 : out std_logic; - RDATAO_0 : out std_logic; - INTO : out std_logic; - - ADDRI_7 : in std_logic; - ADDRI_6 : in std_logic; - ADDRI_5 : in std_logic; - ADDRI_4 : in std_logic; - ADDRI_3 : in std_logic; - ADDRI_2 : in std_logic; - ADDRI_1 : in std_logic; - ADDRI_0 : in std_logic; - WDATAI_7 : in std_logic; - WDATAI_6 : in std_logic; - WDATAI_5 : in std_logic; - WDATAI_4 : in std_logic; - WDATAI_3 : in std_logic; - WDATAI_2 : in std_logic; - WDATAI_1 : in std_logic; - WDATAI_0 : in std_logic; - RDI : in std_logic; - WSTBI : in std_logic; - - CS_CHIF_0 : in std_logic; - CS_CHIF_1 : in std_logic; - CS_CHIF_2 : in std_logic; - CS_CHIF_3 : in std_logic; - CS_QIF : in std_logic; - - QUAD_ID_1 : in std_logic; - QUAD_ID_0 : in std_logic; - - FF_SYSCLK_P1 : out std_logic; - - FF_SYSCLK0 : out std_logic; - FF_SYSCLK1 : out std_logic; - FF_SYSCLK2 : out std_logic; - FF_SYSCLK3 : out std_logic; - - FF_RXCLK_P1 : out std_logic; - FF_RXCLK_P2 : out std_logic; - - FF_RXCLK0 : out std_logic; - FF_RXCLK1 : out std_logic; - FF_RXCLK2 : out std_logic; - FF_RXCLK3 : out std_logic; - - QUAD_CLK : out std_logic; - - GRP_CLK_P1_3 : in std_logic; - GRP_CLK_P1_2 : in std_logic; - GRP_CLK_P1_1 : in std_logic; - GRP_CLK_P1_0 : in std_logic; - - GRP_CLK_P2_3 : in std_logic; - GRP_CLK_P2_2 : in std_logic; - GRP_CLK_P2_1 : in std_logic; - GRP_CLK_P2_0 : in std_logic; - - GRP_START_3 : in std_logic; - GRP_START_2 : in std_logic; - GRP_START_1 : in std_logic; - GRP_START_0 : in std_logic; - - GRP_DONE_3 : in std_logic; - GRP_DONE_2 : in std_logic; - GRP_DONE_1 : in std_logic; - GRP_DONE_0 : in std_logic; - - GRP_DESKEW_ERROR_3 : in std_logic; - GRP_DESKEW_ERROR_2 : in std_logic; - GRP_DESKEW_ERROR_1 : in std_logic; - GRP_DESKEW_ERROR_0 : in std_logic; - - IQA_START_LS : out std_logic; - IQA_DONE_LS : out std_logic; - IQA_AND_FP1_LS : out std_logic; - IQA_AND_FP0_LS : out std_logic; - IQA_OR_FP1_LS : out std_logic; - IQA_OR_FP0_LS : out std_logic; - IQA_RST_N : out std_logic; - - FF_TCLK0 : in std_logic; - FF_TCLK1 : in std_logic; - FF_TCLK2 : in std_logic; - FF_TCLK3 : in std_logic; - - FF_RCLK0 : in std_logic; - FF_RCLK1 : in std_logic; - FF_RCLK2 : in std_logic; - FF_RCLK3 : in std_logic; - TCK_FMACP : in std_logic; - - FF_TXD_0_23 : in std_logic; - FF_TXD_0_22 : in std_logic; - FF_TXD_0_21 : in std_logic; - FF_TXD_0_20 : in std_logic; - FF_TXD_0_19 : in std_logic; - FF_TXD_0_18 : in std_logic; - FF_TXD_0_17 : in std_logic; - FF_TXD_0_16 : in std_logic; - FF_TXD_0_15 : in std_logic; - FF_TXD_0_14 : in std_logic; - FF_TXD_0_13 : in std_logic; - FF_TXD_0_12 : in std_logic; - FF_TXD_0_11 : in std_logic; - FF_TXD_0_10 : in std_logic; - FF_TXD_0_9 : in std_logic; - FF_TXD_0_8 : in std_logic; - FF_TXD_0_7 : in std_logic; - FF_TXD_0_6 : in std_logic; - FF_TXD_0_5 : in std_logic; - FF_TXD_0_4 : in std_logic; - FF_TXD_0_3 : in std_logic; - FF_TXD_0_2 : in std_logic; - FF_TXD_0_1 : in std_logic; - FF_TXD_0_0 : in std_logic; - FB_RXD_0_23 : out std_logic; - FB_RXD_0_22 : out std_logic; - FB_RXD_0_21 : out std_logic; - FB_RXD_0_20 : out std_logic; - FB_RXD_0_19 : out std_logic; - FB_RXD_0_18 : out std_logic; - FB_RXD_0_17 : out std_logic; - FB_RXD_0_16 : out std_logic; - FB_RXD_0_15 : out std_logic; - FB_RXD_0_14 : out std_logic; - FB_RXD_0_13 : out std_logic; - FB_RXD_0_12 : out std_logic; - FB_RXD_0_11 : out std_logic; - FB_RXD_0_10 : out std_logic; - FB_RXD_0_9 : out std_logic; - FB_RXD_0_8 : out std_logic; - FB_RXD_0_7 : out std_logic; - FB_RXD_0_6 : out std_logic; - FB_RXD_0_5 : out std_logic; - FB_RXD_0_4 : out std_logic; - FB_RXD_0_3 : out std_logic; - FB_RXD_0_2 : out std_logic; - FB_RXD_0_1 : out std_logic; - FB_RXD_0_0 : out std_logic; - FF_TXD_1_23 : in std_logic; - FF_TXD_1_22 : in std_logic; - FF_TXD_1_21 : in std_logic; - FF_TXD_1_20 : in std_logic; - FF_TXD_1_19 : in std_logic; - FF_TXD_1_18 : in std_logic; - FF_TXD_1_17 : in std_logic; - FF_TXD_1_16 : in std_logic; - FF_TXD_1_15 : in std_logic; - FF_TXD_1_14 : in std_logic; - FF_TXD_1_13 : in std_logic; - FF_TXD_1_12 : in std_logic; - FF_TXD_1_11 : in std_logic; - FF_TXD_1_10 : in std_logic; - FF_TXD_1_9 : in std_logic; - FF_TXD_1_8 : in std_logic; - FF_TXD_1_7 : in std_logic; - FF_TXD_1_6 : in std_logic; - FF_TXD_1_5 : in std_logic; - FF_TXD_1_4 : in std_logic; - FF_TXD_1_3 : in std_logic; - FF_TXD_1_2 : in std_logic; - FF_TXD_1_1 : in std_logic; - FF_TXD_1_0 : in std_logic; - FB_RXD_1_23 : out std_logic; - FB_RXD_1_22 : out std_logic; - FB_RXD_1_21 : out std_logic; - FB_RXD_1_20 : out std_logic; - FB_RXD_1_19 : out std_logic; - FB_RXD_1_18 : out std_logic; - FB_RXD_1_17 : out std_logic; - FB_RXD_1_16 : out std_logic; - FB_RXD_1_15 : out std_logic; - FB_RXD_1_14 : out std_logic; - FB_RXD_1_13 : out std_logic; - FB_RXD_1_12 : out std_logic; - FB_RXD_1_11 : out std_logic; - FB_RXD_1_10 : out std_logic; - FB_RXD_1_9 : out std_logic; - FB_RXD_1_8 : out std_logic; - FB_RXD_1_7 : out std_logic; - FB_RXD_1_6 : out std_logic; - FB_RXD_1_5 : out std_logic; - FB_RXD_1_4 : out std_logic; - FB_RXD_1_3 : out std_logic; - FB_RXD_1_2 : out std_logic; - FB_RXD_1_1 : out std_logic; - FB_RXD_1_0 : out std_logic; - FF_TXD_2_23 : in std_logic; - FF_TXD_2_22 : in std_logic; - FF_TXD_2_21 : in std_logic; - FF_TXD_2_20 : in std_logic; - FF_TXD_2_19 : in std_logic; - FF_TXD_2_18 : in std_logic; - FF_TXD_2_17 : in std_logic; - FF_TXD_2_16 : in std_logic; - FF_TXD_2_15 : in std_logic; - FF_TXD_2_14 : in std_logic; - FF_TXD_2_13 : in std_logic; - FF_TXD_2_12 : in std_logic; - FF_TXD_2_11 : in std_logic; - FF_TXD_2_10 : in std_logic; - FF_TXD_2_9 : in std_logic; - FF_TXD_2_8 : in std_logic; - FF_TXD_2_7 : in std_logic; - FF_TXD_2_6 : in std_logic; - FF_TXD_2_5 : in std_logic; - FF_TXD_2_4 : in std_logic; - FF_TXD_2_3 : in std_logic; - FF_TXD_2_2 : in std_logic; - FF_TXD_2_1 : in std_logic; - FF_TXD_2_0 : in std_logic; - FB_RXD_2_23 : out std_logic; - FB_RXD_2_22 : out std_logic; - FB_RXD_2_21 : out std_logic; - FB_RXD_2_20 : out std_logic; - FB_RXD_2_19 : out std_logic; - FB_RXD_2_18 : out std_logic; - FB_RXD_2_17 : out std_logic; - FB_RXD_2_16 : out std_logic; - FB_RXD_2_15 : out std_logic; - FB_RXD_2_14 : out std_logic; - FB_RXD_2_13 : out std_logic; - FB_RXD_2_12 : out std_logic; - FB_RXD_2_11 : out std_logic; - FB_RXD_2_10 : out std_logic; - FB_RXD_2_9 : out std_logic; - FB_RXD_2_8 : out std_logic; - FB_RXD_2_7 : out std_logic; - FB_RXD_2_6 : out std_logic; - FB_RXD_2_5 : out std_logic; - FB_RXD_2_4 : out std_logic; - FB_RXD_2_3 : out std_logic; - FB_RXD_2_2 : out std_logic; - FB_RXD_2_1 : out std_logic; - FB_RXD_2_0 : out std_logic; - FF_TXD_3_23 : in std_logic; - FF_TXD_3_22 : in std_logic; - FF_TXD_3_21 : in std_logic; - FF_TXD_3_20 : in std_logic; - FF_TXD_3_19 : in std_logic; - FF_TXD_3_18 : in std_logic; - FF_TXD_3_17 : in std_logic; - FF_TXD_3_16 : in std_logic; - FF_TXD_3_15 : in std_logic; - FF_TXD_3_14 : in std_logic; - FF_TXD_3_13 : in std_logic; - FF_TXD_3_12 : in std_logic; - FF_TXD_3_11 : in std_logic; - FF_TXD_3_10 : in std_logic; - FF_TXD_3_9 : in std_logic; - FF_TXD_3_8 : in std_logic; - FF_TXD_3_7 : in std_logic; - FF_TXD_3_6 : in std_logic; - FF_TXD_3_5 : in std_logic; - FF_TXD_3_4 : in std_logic; - FF_TXD_3_3 : in std_logic; - FF_TXD_3_2 : in std_logic; - FF_TXD_3_1 : in std_logic; - FF_TXD_3_0 : in std_logic; - FB_RXD_3_23 : out std_logic; - FB_RXD_3_22 : out std_logic; - FB_RXD_3_21 : out std_logic; - FB_RXD_3_20 : out std_logic; - FB_RXD_3_19 : out std_logic; - FB_RXD_3_18 : out std_logic; - FB_RXD_3_17 : out std_logic; - FB_RXD_3_16 : out std_logic; - FB_RXD_3_15 : out std_logic; - FB_RXD_3_14 : out std_logic; - FB_RXD_3_13 : out std_logic; - FB_RXD_3_12 : out std_logic; - FB_RXD_3_11 : out std_logic; - FB_RXD_3_10 : out std_logic; - FB_RXD_3_9 : out std_logic; - FB_RXD_3_8 : out std_logic; - FB_RXD_3_7 : out std_logic; - FB_RXD_3_6 : out std_logic; - FB_RXD_3_5 : out std_logic; - FB_RXD_3_4 : out std_logic; - FB_RXD_3_3 : out std_logic; - FB_RXD_3_2 : out std_logic; - FB_RXD_3_1 : out std_logic; - FB_RXD_3_0 : out std_logic; - TCK_FMAC : out std_logic; - BS4PAD_0 : out std_logic; - BS4PAD_1 : out std_logic; - BS4PAD_2 : out std_logic; - BS4PAD_3 : out std_logic; - COUT_21 : out std_logic; - COUT_20 : out std_logic; - COUT_19 : out std_logic; - COUT_18 : out std_logic; - COUT_17 : out std_logic; - COUT_16 : out std_logic; - COUT_15 : out std_logic; - COUT_14 : out std_logic; - COUT_13 : out std_logic; - COUT_12 : out std_logic; - COUT_11 : out std_logic; - COUT_10 : out std_logic; - COUT_9 : out std_logic; - COUT_8 : out std_logic; - COUT_7 : out std_logic; - COUT_6 : out std_logic; - COUT_5 : out std_logic; - COUT_4 : out std_logic; - COUT_3 : out std_logic; - COUT_2 : out std_logic; - COUT_1 : out std_logic; - COUT_0 : out std_logic; - CIN_12 : in std_logic; - CIN_11 : in std_logic; - CIN_10 : in std_logic; - CIN_9 : in std_logic; - CIN_8 : in std_logic; - CIN_7 : in std_logic; - CIN_6 : in std_logic; - CIN_5 : in std_logic; - CIN_4 : in std_logic; - CIN_3 : in std_logic; - CIN_2 : in std_logic; - CIN_1 : in std_logic; - CIN_0 : in std_logic; - TESTCLK_MACO : in std_logic -); -end component; - -begin - -PCSA_sim_inst : PCSA_sim -generic map ( - CONFIG_FILE => CONFIG_FILE) -port map ( - HDINP0 => HDINP0, - HDINN0 => HDINN0, - HDINP1 => HDINP1, - HDINN1 => HDINN1, - HDINP2 => HDINP2, - HDINN2 => HDINN2, - HDINP3 => HDINP3, - HDINN3 => HDINN3, - HDOUTP0 => HDOUTP0, - HDOUTN0 => HDOUTN0, - HDOUTP1 => HDOUTP1, - HDOUTN1 => HDOUTN1, - HDOUTP2 => HDOUTP2, - HDOUTN2 => HDOUTN2, - HDOUTP3 => HDOUTP3, - HDOUTN3 => HDOUTN3, - REFCLKP => REFCLKP, - REFCLKN => REFCLKN, - RXREFCLKP => RXREFCLKP, - RXREFCLKN => RXREFCLKN, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_LANE_TX_RST0 => FFC_LANE_TX_RST0, - FFC_LANE_TX_RST1 => FFC_LANE_TX_RST1, - FFC_LANE_TX_RST2 => FFC_LANE_TX_RST2, - FFC_LANE_TX_RST3 => FFC_LANE_TX_RST3, - FFC_LANE_RX_RST0 => FFC_LANE_RX_RST0, - FFC_LANE_RX_RST1 => FFC_LANE_RX_RST1, - FFC_LANE_RX_RST2 => FFC_LANE_RX_RST2, - FFC_LANE_RX_RST3 => FFC_LANE_RX_RST3, - FFC_PCIE_EI_EN_0 => FFC_PCIE_EI_EN_0, - FFC_PCIE_EI_EN_1 => FFC_PCIE_EI_EN_1, - FFC_PCIE_EI_EN_2 => FFC_PCIE_EI_EN_2, - FFC_PCIE_EI_EN_3 => FFC_PCIE_EI_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFC_PCIE_TX_0 => FFC_PCIE_TX_0, - FFC_PCIE_TX_1 => FFC_PCIE_TX_1, - FFC_PCIE_TX_2 => FFC_PCIE_TX_2, - FFC_PCIE_TX_3 => FFC_PCIE_TX_3, - FFC_PCIE_RX_0 => FFC_PCIE_RX_0, - FFC_PCIE_RX_1 => FFC_PCIE_RX_1, - FFC_PCIE_RX_2 => FFC_PCIE_RX_2, - FFC_PCIE_RX_3 => FFC_PCIE_RX_3, - FFC_SD_0 => FFC_SD_0, - FFC_SD_1 => FFC_SD_1, - FFC_SD_2 => FFC_SD_2, - FFC_SD_3 => FFC_SD_3, - FFC_EN_CGA_0 => FFC_EN_CGA_0, - FFC_EN_CGA_1 => FFC_EN_CGA_1, - FFC_EN_CGA_2 => FFC_EN_CGA_2, - FFC_EN_CGA_3 => FFC_EN_CGA_3, - FFC_ALIGN_EN_0 => FFC_ALIGN_EN_0, - FFC_ALIGN_EN_1 => FFC_ALIGN_EN_1, - FFC_ALIGN_EN_2 => FFC_ALIGN_EN_2, - FFC_ALIGN_EN_3 => FFC_ALIGN_EN_3, - FFC_AB_RESET => FFC_AB_RESET, - FFC_CD_RESET => FFC_CD_RESET, - FFS_LS_STATUS_0 => FFS_LS_STATUS_0, - FFS_LS_STATUS_1 => FFS_LS_STATUS_1, - FFS_LS_STATUS_2 => FFS_LS_STATUS_2, - FFS_LS_STATUS_3 => FFS_LS_STATUS_3, - FFS_AB_STATUS => FFS_AB_STATUS, - FFS_CD_STATUS => FFS_CD_STATUS, - FFS_AB_ALIGNED => FFS_AB_ALIGNED, - FFS_CD_ALIGNED => FFS_CD_ALIGNED, - FFS_AB_FAILED => FFS_AB_FAILED, - FFS_CD_FAILED => FFS_CD_FAILED, - FFS_RLOS_LO0 => FFS_RLOS_LO0, - FFS_RLOS_LO1 => FFS_RLOS_LO1, - FFS_RLOS_LO2 => FFS_RLOS_LO2, - FFS_RLOS_LO3 => FFS_RLOS_LO3, - FFC_FB_LB_0 => FFC_FB_LB_0, - FFC_FB_LB_1 => FFC_FB_LB_1, - FFC_FB_LB_2 => FFC_FB_LB_2, - FFC_FB_LB_3 => FFC_FB_LB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFS_CC_ORUN_0 => FFS_CC_ORUN_0, - FFS_CC_ORUN_1 => FFS_CC_ORUN_1, - FFS_CC_ORUN_2 => FFS_CC_ORUN_2, - FFS_CC_ORUN_3 => FFS_CC_ORUN_3, - FFS_CC_URUN_0 => FFS_CC_URUN_0, - FFS_CC_URUN_1 => FFS_CC_URUN_1, - FFS_CC_URUN_2 => FFS_CC_URUN_2, - FFS_CC_URUN_3 => FFS_CC_URUN_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_CK_CORE_RX => FFC_CK_CORE_RX, - BS4PAD_0 => BS4PAD_0, - BS4PAD_1 => BS4PAD_1, - BS4PAD_2 => BS4PAD_2, - BS4PAD_3 => BS4PAD_3, - RDATAO_7 => RDATAO_7, - RDATAO_6 => RDATAO_6, - RDATAO_5 => RDATAO_5, - RDATAO_4 => RDATAO_4, - RDATAO_3 => RDATAO_3, - RDATAO_2 => RDATAO_2, - RDATAO_1 => RDATAO_1, - RDATAO_0 => RDATAO_0, - INTO => INTO, - ADDRI_7 => ADDRI_7, - ADDRI_6 => ADDRI_6, - ADDRI_5 => ADDRI_5, - ADDRI_4 => ADDRI_4, - ADDRI_3 => ADDRI_3, - ADDRI_2 => ADDRI_2, - ADDRI_1 => ADDRI_1, - ADDRI_0 => ADDRI_0, - WDATAI_7 => WDATAI_7, - WDATAI_6 => WDATAI_6, - WDATAI_5 => WDATAI_5, - WDATAI_4 => WDATAI_4, - WDATAI_3 => WDATAI_3, - WDATAI_2 => WDATAI_2, - WDATAI_1 => WDATAI_1, - WDATAI_0 => WDATAI_0, - RDI => RDI, - WSTBI => WSTBI, - CS_CHIF_0 => CS_CHIF_0, - CS_CHIF_1 => CS_CHIF_1, - CS_CHIF_2 => CS_CHIF_2, - CS_CHIF_3 => CS_CHIF_3, - CS_QIF => CS_QIF, - QUAD_ID_1 => QUAD_ID_1, - QUAD_ID_0 => QUAD_ID_0, - FF_SYSCLK_P1 => FF_SYSCLK_P1, - FF_SYSCLK0 => FF_SYSCLK0, - FF_SYSCLK1 => FF_SYSCLK1, - FF_SYSCLK2 => FF_SYSCLK2, - FF_SYSCLK3 => FF_SYSCLK3, - FF_RXCLK_P1 => FF_RXCLK_P1, - FF_RXCLK_P2 => FF_RXCLK_P2, - FF_RXCLK0 => FF_RXCLK0, - FF_RXCLK1 => FF_RXCLK1, - FF_RXCLK2 => FF_RXCLK2, - FF_RXCLK3 => FF_RXCLK3, - QUAD_CLK => QUAD_CLK, - GRP_CLK_P1_3 => GRP_CLK_P1_3, - GRP_CLK_P1_2 => GRP_CLK_P1_2, - GRP_CLK_P1_1 => GRP_CLK_P1_1, - GRP_CLK_P1_0 => GRP_CLK_P1_0, - GRP_CLK_P2_3 => GRP_CLK_P2_3, - GRP_CLK_P2_2 => GRP_CLK_P2_2, - GRP_CLK_P2_1 => GRP_CLK_P2_1, - GRP_CLK_P2_0 => GRP_CLK_P2_0, - GRP_START_3 => GRP_START_3, - GRP_START_2 => GRP_START_2, - GRP_START_1 => GRP_START_1, - GRP_START_0 => GRP_START_0, - GRP_DONE_3 => GRP_DONE_3, - GRP_DONE_2 => GRP_DONE_2, - GRP_DONE_1 => GRP_DONE_1, - GRP_DONE_0 => GRP_DONE_0, - GRP_DESKEW_ERROR_3 => GRP_DESKEW_ERROR_3, - GRP_DESKEW_ERROR_2 => GRP_DESKEW_ERROR_2, - GRP_DESKEW_ERROR_1 => GRP_DESKEW_ERROR_1, - GRP_DESKEW_ERROR_0 => GRP_DESKEW_ERROR_0, - IQA_START_LS => IQA_START_LS, - IQA_DONE_LS => IQA_DONE_LS, - IQA_AND_FP1_LS => IQA_AND_FP1_LS, - IQA_AND_FP0_LS => IQA_AND_FP0_LS, - IQA_OR_FP1_LS => IQA_OR_FP1_LS, - IQA_OR_FP0_LS => IQA_OR_FP0_LS, - IQA_RST_N => IQA_RST_N, - FF_TCLK0 => FF_TCLK0, - FF_TCLK1 => FF_TCLK1, - FF_TCLK2 => FF_TCLK2, - FF_TCLK3 => FF_TCLK3, - FF_RCLK0 => FF_RCLK0, - FF_RCLK1 => FF_RCLK1, - FF_RCLK2 => FF_RCLK2, - FF_RCLK3 => FF_RCLK3, - TCK_FMACP => TCK_FMACP, - FF_TXD_0_23 => FF_TXD_0_23, - FF_TXD_0_22 => FF_TXD_0_22, - FF_TXD_0_21 => FF_TXD_0_21, - FF_TXD_0_20 => FF_TXD_0_20, - FF_TXD_0_19 => FF_TXD_0_19, - FF_TXD_0_18 => FF_TXD_0_18, - FF_TXD_0_17 => FF_TXD_0_17, - FF_TXD_0_16 => FF_TXD_0_16, - FF_TXD_0_15 => FF_TXD_0_15, - FF_TXD_0_14 => FF_TXD_0_14, - FF_TXD_0_13 => FF_TXD_0_13, - FF_TXD_0_12 => FF_TXD_0_12, - FF_TXD_0_11 => FF_TXD_0_11, - FF_TXD_0_10 => FF_TXD_0_10, - FF_TXD_0_9 => FF_TXD_0_9, - FF_TXD_0_8 => FF_TXD_0_8, - FF_TXD_0_7 => FF_TXD_0_7, - FF_TXD_0_6 => FF_TXD_0_6, - FF_TXD_0_5 => FF_TXD_0_5, - FF_TXD_0_4 => FF_TXD_0_4, - FF_TXD_0_3 => FF_TXD_0_3, - FF_TXD_0_2 => FF_TXD_0_2, - FF_TXD_0_1 => FF_TXD_0_1, - FF_TXD_0_0 => FF_TXD_0_0, - FB_RXD_0_23 => FB_RXD_0_23, - FB_RXD_0_22 => FB_RXD_0_22, - FB_RXD_0_21 => FB_RXD_0_21, - FB_RXD_0_20 => FB_RXD_0_20, - FB_RXD_0_19 => FB_RXD_0_19, - FB_RXD_0_18 => FB_RXD_0_18, - FB_RXD_0_17 => FB_RXD_0_17, - FB_RXD_0_16 => FB_RXD_0_16, - FB_RXD_0_15 => FB_RXD_0_15, - FB_RXD_0_14 => FB_RXD_0_14, - FB_RXD_0_13 => FB_RXD_0_13, - FB_RXD_0_12 => FB_RXD_0_12, - FB_RXD_0_11 => FB_RXD_0_11, - FB_RXD_0_10 => FB_RXD_0_10, - FB_RXD_0_9 => FB_RXD_0_9, - FB_RXD_0_8 => FB_RXD_0_8, - FB_RXD_0_7 => FB_RXD_0_7, - FB_RXD_0_6 => FB_RXD_0_6, - FB_RXD_0_5 => FB_RXD_0_5, - FB_RXD_0_4 => FB_RXD_0_4, - FB_RXD_0_3 => FB_RXD_0_3, - FB_RXD_0_2 => FB_RXD_0_2, - FB_RXD_0_1 => FB_RXD_0_1, - FB_RXD_0_0 => FB_RXD_0_0, - FF_TXD_1_23 => FF_TXD_1_23, - FF_TXD_1_22 => FF_TXD_1_22, - FF_TXD_1_21 => FF_TXD_1_21, - FF_TXD_1_20 => FF_TXD_1_20, - FF_TXD_1_19 => FF_TXD_1_19, - FF_TXD_1_18 => FF_TXD_1_18, - FF_TXD_1_17 => FF_TXD_1_17, - FF_TXD_1_16 => FF_TXD_1_16, - FF_TXD_1_15 => FF_TXD_1_15, - FF_TXD_1_14 => FF_TXD_1_14, - FF_TXD_1_13 => FF_TXD_1_13, - FF_TXD_1_12 => FF_TXD_1_12, - FF_TXD_1_11 => FF_TXD_1_11, - FF_TXD_1_10 => FF_TXD_1_10, - FF_TXD_1_9 => FF_TXD_1_9, - FF_TXD_1_8 => FF_TXD_1_8, - FF_TXD_1_7 => FF_TXD_1_7, - FF_TXD_1_6 => FF_TXD_1_6, - FF_TXD_1_5 => FF_TXD_1_5, - FF_TXD_1_4 => FF_TXD_1_4, - FF_TXD_1_3 => FF_TXD_1_3, - FF_TXD_1_2 => FF_TXD_1_2, - FF_TXD_1_1 => FF_TXD_1_1, - FF_TXD_1_0 => FF_TXD_1_0, - FB_RXD_1_23 => FB_RXD_1_23, - FB_RXD_1_22 => FB_RXD_1_22, - FB_RXD_1_21 => FB_RXD_1_21, - FB_RXD_1_20 => FB_RXD_1_20, - FB_RXD_1_19 => FB_RXD_1_19, - FB_RXD_1_18 => FB_RXD_1_18, - FB_RXD_1_17 => FB_RXD_1_17, - FB_RXD_1_16 => FB_RXD_1_16, - FB_RXD_1_15 => FB_RXD_1_15, - FB_RXD_1_14 => FB_RXD_1_14, - FB_RXD_1_13 => FB_RXD_1_13, - FB_RXD_1_12 => FB_RXD_1_12, - FB_RXD_1_11 => FB_RXD_1_11, - FB_RXD_1_10 => FB_RXD_1_10, - FB_RXD_1_9 => FB_RXD_1_9, - FB_RXD_1_8 => FB_RXD_1_8, - FB_RXD_1_7 => FB_RXD_1_7, - FB_RXD_1_6 => FB_RXD_1_6, - FB_RXD_1_5 => FB_RXD_1_5, - FB_RXD_1_4 => FB_RXD_1_4, - FB_RXD_1_3 => FB_RXD_1_3, - FB_RXD_1_2 => FB_RXD_1_2, - FB_RXD_1_1 => FB_RXD_1_1, - FB_RXD_1_0 => FB_RXD_1_0, - FF_TXD_2_23 => FF_TXD_2_23, - FF_TXD_2_22 => FF_TXD_2_22, - FF_TXD_2_21 => FF_TXD_2_21, - FF_TXD_2_20 => FF_TXD_2_20, - FF_TXD_2_19 => FF_TXD_2_19, - FF_TXD_2_18 => FF_TXD_2_18, - FF_TXD_2_17 => FF_TXD_2_17, - FF_TXD_2_16 => FF_TXD_2_16, - FF_TXD_2_15 => FF_TXD_2_15, - FF_TXD_2_14 => FF_TXD_2_14, - FF_TXD_2_13 => FF_TXD_2_13, - FF_TXD_2_12 => FF_TXD_2_12, - FF_TXD_2_11 => FF_TXD_2_11, - FF_TXD_2_10 => FF_TXD_2_10, - FF_TXD_2_9 => FF_TXD_2_9, - FF_TXD_2_8 => FF_TXD_2_8, - FF_TXD_2_7 => FF_TXD_2_7, - FF_TXD_2_6 => FF_TXD_2_6, - FF_TXD_2_5 => FF_TXD_2_5, - FF_TXD_2_4 => FF_TXD_2_4, - FF_TXD_2_3 => FF_TXD_2_3, - FF_TXD_2_2 => FF_TXD_2_2, - FF_TXD_2_1 => FF_TXD_2_1, - FF_TXD_2_0 => FF_TXD_2_0, - FB_RXD_2_23 => FB_RXD_2_23, - FB_RXD_2_22 => FB_RXD_2_22, - FB_RXD_2_21 => FB_RXD_2_21, - FB_RXD_2_20 => FB_RXD_2_20, - FB_RXD_2_19 => FB_RXD_2_19, - FB_RXD_2_18 => FB_RXD_2_18, - FB_RXD_2_17 => FB_RXD_2_17, - FB_RXD_2_16 => FB_RXD_2_16, - FB_RXD_2_15 => FB_RXD_2_15, - FB_RXD_2_14 => FB_RXD_2_14, - FB_RXD_2_13 => FB_RXD_2_13, - FB_RXD_2_12 => FB_RXD_2_12, - FB_RXD_2_11 => FB_RXD_2_11, - FB_RXD_2_10 => FB_RXD_2_10, - FB_RXD_2_9 => FB_RXD_2_9, - FB_RXD_2_8 => FB_RXD_2_8, - FB_RXD_2_7 => FB_RXD_2_7, - FB_RXD_2_6 => FB_RXD_2_6, - FB_RXD_2_5 => FB_RXD_2_5, - FB_RXD_2_4 => FB_RXD_2_4, - FB_RXD_2_3 => FB_RXD_2_3, - FB_RXD_2_2 => FB_RXD_2_2, - FB_RXD_2_1 => FB_RXD_2_1, - FB_RXD_2_0 => FB_RXD_2_0, - FF_TXD_3_23 => FF_TXD_3_23, - FF_TXD_3_22 => FF_TXD_3_22, - FF_TXD_3_21 => FF_TXD_3_21, - FF_TXD_3_20 => FF_TXD_3_20, - FF_TXD_3_19 => FF_TXD_3_19, - FF_TXD_3_18 => FF_TXD_3_18, - FF_TXD_3_17 => FF_TXD_3_17, - FF_TXD_3_16 => FF_TXD_3_16, - FF_TXD_3_15 => FF_TXD_3_15, - FF_TXD_3_14 => FF_TXD_3_14, - FF_TXD_3_13 => FF_TXD_3_13, - FF_TXD_3_12 => FF_TXD_3_12, - FF_TXD_3_11 => FF_TXD_3_11, - FF_TXD_3_10 => FF_TXD_3_10, - FF_TXD_3_9 => FF_TXD_3_9, - FF_TXD_3_8 => FF_TXD_3_8, - FF_TXD_3_7 => FF_TXD_3_7, - FF_TXD_3_6 => FF_TXD_3_6, - FF_TXD_3_5 => FF_TXD_3_5, - FF_TXD_3_4 => FF_TXD_3_4, - FF_TXD_3_3 => FF_TXD_3_3, - FF_TXD_3_2 => FF_TXD_3_2, - FF_TXD_3_1 => FF_TXD_3_1, - FF_TXD_3_0 => FF_TXD_3_0, - FB_RXD_3_23 => FB_RXD_3_23, - FB_RXD_3_22 => FB_RXD_3_22, - FB_RXD_3_21 => FB_RXD_3_21, - FB_RXD_3_20 => FB_RXD_3_20, - FB_RXD_3_19 => FB_RXD_3_19, - FB_RXD_3_18 => FB_RXD_3_18, - FB_RXD_3_17 => FB_RXD_3_17, - FB_RXD_3_16 => FB_RXD_3_16, - FB_RXD_3_15 => FB_RXD_3_15, - FB_RXD_3_14 => FB_RXD_3_14, - FB_RXD_3_13 => FB_RXD_3_13, - FB_RXD_3_12 => FB_RXD_3_12, - FB_RXD_3_11 => FB_RXD_3_11, - FB_RXD_3_10 => FB_RXD_3_10, - FB_RXD_3_9 => FB_RXD_3_9, - FB_RXD_3_8 => FB_RXD_3_8, - FB_RXD_3_7 => FB_RXD_3_7, - FB_RXD_3_6 => FB_RXD_3_6, - FB_RXD_3_5 => FB_RXD_3_5, - FB_RXD_3_4 => FB_RXD_3_4, - FB_RXD_3_3 => FB_RXD_3_3, - FB_RXD_3_2 => FB_RXD_3_2, - FB_RXD_3_1 => FB_RXD_3_1, - FB_RXD_3_0 => FB_RXD_3_0, - TCK_FMAC => TCK_FMAC, - COUT_21 => COUT_21, - COUT_20 => COUT_20, - COUT_19 => COUT_19, - COUT_18 => COUT_18, - COUT_17 => COUT_17, - COUT_16 => COUT_16, - COUT_15 => COUT_15, - COUT_14 => COUT_14, - COUT_13 => COUT_13, - COUT_12 => COUT_12, - COUT_11 => COUT_11, - COUT_10 => COUT_10, - COUT_9 => COUT_9, - COUT_8 => COUT_8, - COUT_7 => COUT_7, - COUT_6 => COUT_6, - COUT_5 => COUT_5, - COUT_4 => COUT_4, - COUT_3 => COUT_3, - COUT_2 => COUT_2, - COUT_1 => COUT_1, - COUT_0 => COUT_0, - CIN_12 => CIN_12, - CIN_11 => CIN_11, - CIN_10 => CIN_10, - CIN_9 => CIN_9, - CIN_8 => CIN_8, - CIN_7 => CIN_7, - CIN_6 => CIN_6, - CIN_5 => CIN_5, - CIN_4 => CIN_4, - CIN_3 => CIN_3, - CIN_2 => CIN_2, - CIN_1 => CIN_1, - CIN_0 => CIN_0, - TESTCLK_MACO => TESTCLK_MACO -); - -end PCSA_arch; - ---synopsys translate_on - ---synopsys translate_off -library SC; -use SC.components.all; ---synopsys translate_on - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - - -entity serdes_fpga_ref_clk is - GENERIC (USER_CONFIG_FILE : String := "serdes_fpga_ref_clk.txt"); - port ( --- serdes clk pins -- - rxrefclk, refclk : in std_logic; - rxa_pclk, rxb_pclk : out std_logic; - hdinp_0, hdinn_0 : in std_logic; - hdoutp_0, hdoutn_0 : out std_logic; - tclk_0, rclk_0 : in std_logic; - tx_rst_0, rx_rst_0 : in std_logic; - ref_0_sclk, rx_0_sclk : out std_logic; - txd_0 : in std_logic_vector (15 downto 0); - tx_k_0, tx_force_disp_0, tx_disp_sel_0 : in std_logic_vector (1 downto 0); - rxd_0 : out std_logic_vector (15 downto 0); - rx_k_0, rx_disp_err_detect_0, rx_cv_detect_0 : out std_logic_vector (1 downto 0); - tx_crc_init_0 : in std_logic_vector (1 downto 0); - rx_crc_eop_0 : out std_logic_vector (1 downto 0); - word_align_en_0, mca_align_en_0, felb_0 : in std_logic; - lsm_en_0 : in std_logic; - lsm_status_0 : out std_logic; - - hdinp_1, hdinn_1 : in std_logic; - hdoutp_1, hdoutn_1 : out std_logic; - tclk_1, rclk_1 : in std_logic; - tx_rst_1, rx_rst_1 : in std_logic; - ref_1_sclk, rx_1_sclk : out std_logic; - txd_1 : in std_logic_vector (15 downto 0); - tx_k_1, tx_force_disp_1, tx_disp_sel_1 : in std_logic_vector (1 downto 0); - rxd_1 : out std_logic_vector (15 downto 0); - rx_k_1, rx_disp_err_detect_1, rx_cv_detect_1 : out std_logic_vector (1 downto 0); - tx_crc_init_1 : in std_logic_vector (1 downto 0); - rx_crc_eop_1 : out std_logic_vector (1 downto 0); - word_align_en_1, mca_align_en_1, felb_1 : in std_logic; - lsm_en_1 : in std_logic; - lsm_status_1 : out std_logic; - - hdinp_2, hdinn_2 : in std_logic; - hdoutp_2, hdoutn_2 : out std_logic; - tclk_2, rclk_2 : in std_logic; - tx_rst_2, rx_rst_2 : in std_logic; - ref_2_sclk, rx_2_sclk : out std_logic; - txd_2 : in std_logic_vector (15 downto 0); - tx_k_2, tx_force_disp_2, tx_disp_sel_2 : in std_logic_vector (1 downto 0); - rxd_2 : out std_logic_vector (15 downto 0); - rx_k_2, rx_disp_err_detect_2, rx_cv_detect_2 : out std_logic_vector (1 downto 0); - tx_crc_init_2 : in std_logic_vector (1 downto 0); - rx_crc_eop_2 : out std_logic_vector (1 downto 0); - word_align_en_2, mca_align_en_2, felb_2 : in std_logic; - lsm_en_2 : in std_logic; - lsm_status_2 : out std_logic; - - hdinp_3, hdinn_3 : in std_logic; - hdoutp_3, hdoutn_3 : out std_logic; - tclk_3, rclk_3 : in std_logic; - tx_rst_3, rx_rst_3 : in std_logic; - ref_3_sclk, rx_3_sclk : out std_logic; - txd_3 : in std_logic_vector (15 downto 0); - tx_k_3, tx_force_disp_3, tx_disp_sel_3 : in std_logic_vector (1 downto 0); - rxd_3 : out std_logic_vector (15 downto 0); - rx_k_3, rx_disp_err_detect_3, rx_cv_detect_3 : out std_logic_vector (1 downto 0); - tx_crc_init_3 : in std_logic_vector (1 downto 0); - rx_crc_eop_3 : out std_logic_vector (1 downto 0); - word_align_en_3, mca_align_en_3, felb_3 : in std_logic; - lsm_en_3 : in std_logic; - lsm_status_3 : out std_logic; - mca_resync_01 : in std_logic; - mca_aligned_01, mca_inskew_01, mca_outskew_01 : out std_logic; - mca_resync_23 : in std_logic; - mca_aligned_23, mca_inskew_23, mca_outskew_23 : out std_logic; - quad_rst, serdes_rst : in std_logic; - ref_pclk : out std_logic); - -end serdes_fpga_ref_clk; - -architecture serdes_fpga_ref_clk_arch of serdes_fpga_ref_clk is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - -component PCSA ---synopsys translate_off -GENERIC( - CONFIG_FILE : String - ); ---synopsys translate_on -port ( - HDINP0 : in std_logic; - HDINN0 : in std_logic; - HDINP1 : in std_logic; - HDINN1 : in std_logic; - HDINP2 : in std_logic; - HDINN2 : in std_logic; - HDINP3 : in std_logic; - HDINN3 : in std_logic; - HDOUTP0 : out std_logic; - HDOUTN0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTP3 : out std_logic; - HDOUTN3 : out std_logic; - REFCLKP : in std_logic; - REFCLKN : in std_logic; - RXREFCLKP : in std_logic; - RXREFCLKN : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_MACRO_RST : in std_logic; - - FFC_LANE_TX_RST0 : in std_logic; - FFC_LANE_TX_RST1 : in std_logic; - FFC_LANE_TX_RST2 : in std_logic; - FFC_LANE_TX_RST3 : in std_logic; - - FFC_LANE_RX_RST0 : in std_logic; - FFC_LANE_RX_RST1 : in std_logic; - FFC_LANE_RX_RST2 : in std_logic; - FFC_LANE_RX_RST3 : in std_logic; - - FFC_PCIE_EI_EN_0 : in std_logic; - FFC_PCIE_EI_EN_1 : in std_logic; - FFC_PCIE_EI_EN_2 : in std_logic; - FFC_PCIE_EI_EN_3 : in std_logic; - - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - - FFC_PCIE_TX_0 : in std_logic; - FFC_PCIE_TX_1 : in std_logic; - FFC_PCIE_TX_2 : in std_logic; - FFC_PCIE_TX_3 : in std_logic; - - FFC_PCIE_RX_0 : in std_logic; - FFC_PCIE_RX_1 : in std_logic; - FFC_PCIE_RX_2 : in std_logic; - FFC_PCIE_RX_3 : in std_logic; - - FFC_SD_0 : in std_logic; - FFC_SD_1 : in std_logic; - FFC_SD_2 : in std_logic; - FFC_SD_3 : in std_logic; - - FFC_EN_CGA_0 : in std_logic; - FFC_EN_CGA_1 : in std_logic; - FFC_EN_CGA_2 : in std_logic; - FFC_EN_CGA_3 : in std_logic; - - FFC_ALIGN_EN_0 : in std_logic; - FFC_ALIGN_EN_1 : in std_logic; - FFC_ALIGN_EN_2 : in std_logic; - FFC_ALIGN_EN_3 : in std_logic; - - FFC_AB_RESET : in std_logic; - FFC_CD_RESET : in std_logic; - - FFS_LS_STATUS_0 : out std_logic; - FFS_LS_STATUS_1 : out std_logic; - FFS_LS_STATUS_2 : out std_logic; - FFS_LS_STATUS_3 : out std_logic; - - FFS_AB_STATUS : out std_logic; - FFS_CD_STATUS : out std_logic; - - FFS_AB_ALIGNED : out std_logic; - FFS_CD_ALIGNED : out std_logic; - - FFS_AB_FAILED : out std_logic; - FFS_CD_FAILED : out std_logic; - - FFS_RLOS_LO0 : out std_logic; - FFS_RLOS_LO1 : out std_logic; - FFS_RLOS_LO2 : out std_logic; - FFS_RLOS_LO3 : out std_logic; - - FFC_FB_LB_0 : in std_logic; - FFC_FB_LB_1 : in std_logic; - FFC_FB_LB_2 : in std_logic; - FFC_FB_LB_3 : in std_logic; - - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - - FFS_CC_ORUN_0 : out std_logic; - FFS_CC_ORUN_1 : out std_logic; - FFS_CC_ORUN_2 : out std_logic; - FFS_CC_ORUN_3 : out std_logic; - - FFS_CC_URUN_0 : out std_logic; - FFS_CC_URUN_1 : out std_logic; - FFS_CC_URUN_2 : out std_logic; - FFS_CC_URUN_3 : out std_logic; - - FFC_CK_CORE_TX : in std_logic; - FFC_CK_CORE_RX : in std_logic; - RDATAO_7 : out std_logic; - RDATAO_6 : out std_logic; - RDATAO_5 : out std_logic; - RDATAO_4 : out std_logic; - RDATAO_3 : out std_logic; - RDATAO_2 : out std_logic; - RDATAO_1 : out std_logic; - RDATAO_0 : out std_logic; - INTO : out std_logic; - - ADDRI_7 : in std_logic; - ADDRI_6 : in std_logic; - ADDRI_5 : in std_logic; - ADDRI_4 : in std_logic; - ADDRI_3 : in std_logic; - ADDRI_2 : in std_logic; - ADDRI_1 : in std_logic; - ADDRI_0 : in std_logic; - WDATAI_7 : in std_logic; - WDATAI_6 : in std_logic; - WDATAI_5 : in std_logic; - WDATAI_4 : in std_logic; - WDATAI_3 : in std_logic; - WDATAI_2 : in std_logic; - WDATAI_1 : in std_logic; - WDATAI_0 : in std_logic; - RDI : in std_logic; - WSTBI : in std_logic; - - CS_CHIF_0 : in std_logic; - CS_CHIF_1 : in std_logic; - CS_CHIF_2 : in std_logic; - CS_CHIF_3 : in std_logic; - CS_QIF : in std_logic; - - QUAD_ID_1 : in std_logic; - QUAD_ID_0 : in std_logic; - - FF_SYSCLK_P1 : out std_logic; - - FF_SYSCLK0 : out std_logic; - FF_SYSCLK1 : out std_logic; - FF_SYSCLK2 : out std_logic; - FF_SYSCLK3 : out std_logic; - - FF_RXCLK_P1 : out std_logic; - FF_RXCLK_P2 : out std_logic; - - FF_RXCLK0 : out std_logic; - FF_RXCLK1 : out std_logic; - FF_RXCLK2 : out std_logic; - FF_RXCLK3 : out std_logic; - - QUAD_CLK : out std_logic; - - GRP_CLK_P1_3 : in std_logic; - GRP_CLK_P1_2 : in std_logic; - GRP_CLK_P1_1 : in std_logic; - GRP_CLK_P1_0 : in std_logic; - - GRP_CLK_P2_3 : in std_logic; - GRP_CLK_P2_2 : in std_logic; - GRP_CLK_P2_1 : in std_logic; - GRP_CLK_P2_0 : in std_logic; - - GRP_START_3 : in std_logic; - GRP_START_2 : in std_logic; - GRP_START_1 : in std_logic; - GRP_START_0 : in std_logic; - - GRP_DONE_3 : in std_logic; - GRP_DONE_2 : in std_logic; - GRP_DONE_1 : in std_logic; - GRP_DONE_0 : in std_logic; - - GRP_DESKEW_ERROR_3 : in std_logic; - GRP_DESKEW_ERROR_2 : in std_logic; - GRP_DESKEW_ERROR_1 : in std_logic; - GRP_DESKEW_ERROR_0 : in std_logic; - - IQA_START_LS : out std_logic; - IQA_DONE_LS : out std_logic; - IQA_AND_FP1_LS : out std_logic; - IQA_AND_FP0_LS : out std_logic; - IQA_OR_FP1_LS : out std_logic; - IQA_OR_FP0_LS : out std_logic; - IQA_RST_N : out std_logic; - - FF_TCLK0 : in std_logic; - FF_TCLK1 : in std_logic; - FF_TCLK2 : in std_logic; - FF_TCLK3 : in std_logic; - - FF_RCLK0 : in std_logic; - FF_RCLK1 : in std_logic; - FF_RCLK2 : in std_logic; - FF_RCLK3 : in std_logic; - TCK_FMACP : in std_logic; - - FF_TXD_0_23 : in std_logic; - FF_TXD_0_22 : in std_logic; - FF_TXD_0_21 : in std_logic; - FF_TXD_0_20 : in std_logic; - FF_TXD_0_19 : in std_logic; - FF_TXD_0_18 : in std_logic; - FF_TXD_0_17 : in std_logic; - FF_TXD_0_16 : in std_logic; - FF_TXD_0_15 : in std_logic; - FF_TXD_0_14 : in std_logic; - FF_TXD_0_13 : in std_logic; - FF_TXD_0_12 : in std_logic; - FF_TXD_0_11 : in std_logic; - FF_TXD_0_10 : in std_logic; - FF_TXD_0_9 : in std_logic; - FF_TXD_0_8 : in std_logic; - FF_TXD_0_7 : in std_logic; - FF_TXD_0_6 : in std_logic; - FF_TXD_0_5 : in std_logic; - FF_TXD_0_4 : in std_logic; - FF_TXD_0_3 : in std_logic; - FF_TXD_0_2 : in std_logic; - FF_TXD_0_1 : in std_logic; - FF_TXD_0_0 : in std_logic; - FB_RXD_0_23 : out std_logic; - FB_RXD_0_22 : out std_logic; - FB_RXD_0_21 : out std_logic; - FB_RXD_0_20 : out std_logic; - FB_RXD_0_19 : out std_logic; - FB_RXD_0_18 : out std_logic; - FB_RXD_0_17 : out std_logic; - FB_RXD_0_16 : out std_logic; - FB_RXD_0_15 : out std_logic; - FB_RXD_0_14 : out std_logic; - FB_RXD_0_13 : out std_logic; - FB_RXD_0_12 : out std_logic; - FB_RXD_0_11 : out std_logic; - FB_RXD_0_10 : out std_logic; - FB_RXD_0_9 : out std_logic; - FB_RXD_0_8 : out std_logic; - FB_RXD_0_7 : out std_logic; - FB_RXD_0_6 : out std_logic; - FB_RXD_0_5 : out std_logic; - FB_RXD_0_4 : out std_logic; - FB_RXD_0_3 : out std_logic; - FB_RXD_0_2 : out std_logic; - FB_RXD_0_1 : out std_logic; - FB_RXD_0_0 : out std_logic; - FF_TXD_1_23 : in std_logic; - FF_TXD_1_22 : in std_logic; - FF_TXD_1_21 : in std_logic; - FF_TXD_1_20 : in std_logic; - FF_TXD_1_19 : in std_logic; - FF_TXD_1_18 : in std_logic; - FF_TXD_1_17 : in std_logic; - FF_TXD_1_16 : in std_logic; - FF_TXD_1_15 : in std_logic; - FF_TXD_1_14 : in std_logic; - FF_TXD_1_13 : in std_logic; - FF_TXD_1_12 : in std_logic; - FF_TXD_1_11 : in std_logic; - FF_TXD_1_10 : in std_logic; - FF_TXD_1_9 : in std_logic; - FF_TXD_1_8 : in std_logic; - FF_TXD_1_7 : in std_logic; - FF_TXD_1_6 : in std_logic; - FF_TXD_1_5 : in std_logic; - FF_TXD_1_4 : in std_logic; - FF_TXD_1_3 : in std_logic; - FF_TXD_1_2 : in std_logic; - FF_TXD_1_1 : in std_logic; - FF_TXD_1_0 : in std_logic; - FB_RXD_1_23 : out std_logic; - FB_RXD_1_22 : out std_logic; - FB_RXD_1_21 : out std_logic; - FB_RXD_1_20 : out std_logic; - FB_RXD_1_19 : out std_logic; - FB_RXD_1_18 : out std_logic; - FB_RXD_1_17 : out std_logic; - FB_RXD_1_16 : out std_logic; - FB_RXD_1_15 : out std_logic; - FB_RXD_1_14 : out std_logic; - FB_RXD_1_13 : out std_logic; - FB_RXD_1_12 : out std_logic; - FB_RXD_1_11 : out std_logic; - FB_RXD_1_10 : out std_logic; - FB_RXD_1_9 : out std_logic; - FB_RXD_1_8 : out std_logic; - FB_RXD_1_7 : out std_logic; - FB_RXD_1_6 : out std_logic; - FB_RXD_1_5 : out std_logic; - FB_RXD_1_4 : out std_logic; - FB_RXD_1_3 : out std_logic; - FB_RXD_1_2 : out std_logic; - FB_RXD_1_1 : out std_logic; - FB_RXD_1_0 : out std_logic; - FF_TXD_2_23 : in std_logic; - FF_TXD_2_22 : in std_logic; - FF_TXD_2_21 : in std_logic; - FF_TXD_2_20 : in std_logic; - FF_TXD_2_19 : in std_logic; - FF_TXD_2_18 : in std_logic; - FF_TXD_2_17 : in std_logic; - FF_TXD_2_16 : in std_logic; - FF_TXD_2_15 : in std_logic; - FF_TXD_2_14 : in std_logic; - FF_TXD_2_13 : in std_logic; - FF_TXD_2_12 : in std_logic; - FF_TXD_2_11 : in std_logic; - FF_TXD_2_10 : in std_logic; - FF_TXD_2_9 : in std_logic; - FF_TXD_2_8 : in std_logic; - FF_TXD_2_7 : in std_logic; - FF_TXD_2_6 : in std_logic; - FF_TXD_2_5 : in std_logic; - FF_TXD_2_4 : in std_logic; - FF_TXD_2_3 : in std_logic; - FF_TXD_2_2 : in std_logic; - FF_TXD_2_1 : in std_logic; - FF_TXD_2_0 : in std_logic; - FB_RXD_2_23 : out std_logic; - FB_RXD_2_22 : out std_logic; - FB_RXD_2_21 : out std_logic; - FB_RXD_2_20 : out std_logic; - FB_RXD_2_19 : out std_logic; - FB_RXD_2_18 : out std_logic; - FB_RXD_2_17 : out std_logic; - FB_RXD_2_16 : out std_logic; - FB_RXD_2_15 : out std_logic; - FB_RXD_2_14 : out std_logic; - FB_RXD_2_13 : out std_logic; - FB_RXD_2_12 : out std_logic; - FB_RXD_2_11 : out std_logic; - FB_RXD_2_10 : out std_logic; - FB_RXD_2_9 : out std_logic; - FB_RXD_2_8 : out std_logic; - FB_RXD_2_7 : out std_logic; - FB_RXD_2_6 : out std_logic; - FB_RXD_2_5 : out std_logic; - FB_RXD_2_4 : out std_logic; - FB_RXD_2_3 : out std_logic; - FB_RXD_2_2 : out std_logic; - FB_RXD_2_1 : out std_logic; - FB_RXD_2_0 : out std_logic; - FF_TXD_3_23 : in std_logic; - FF_TXD_3_22 : in std_logic; - FF_TXD_3_21 : in std_logic; - FF_TXD_3_20 : in std_logic; - FF_TXD_3_19 : in std_logic; - FF_TXD_3_18 : in std_logic; - FF_TXD_3_17 : in std_logic; - FF_TXD_3_16 : in std_logic; - FF_TXD_3_15 : in std_logic; - FF_TXD_3_14 : in std_logic; - FF_TXD_3_13 : in std_logic; - FF_TXD_3_12 : in std_logic; - FF_TXD_3_11 : in std_logic; - FF_TXD_3_10 : in std_logic; - FF_TXD_3_9 : in std_logic; - FF_TXD_3_8 : in std_logic; - FF_TXD_3_7 : in std_logic; - FF_TXD_3_6 : in std_logic; - FF_TXD_3_5 : in std_logic; - FF_TXD_3_4 : in std_logic; - FF_TXD_3_3 : in std_logic; - FF_TXD_3_2 : in std_logic; - FF_TXD_3_1 : in std_logic; - FF_TXD_3_0 : in std_logic; - FB_RXD_3_23 : out std_logic; - FB_RXD_3_22 : out std_logic; - FB_RXD_3_21 : out std_logic; - FB_RXD_3_20 : out std_logic; - FB_RXD_3_19 : out std_logic; - FB_RXD_3_18 : out std_logic; - FB_RXD_3_17 : out std_logic; - FB_RXD_3_16 : out std_logic; - FB_RXD_3_15 : out std_logic; - FB_RXD_3_14 : out std_logic; - FB_RXD_3_13 : out std_logic; - FB_RXD_3_12 : out std_logic; - FB_RXD_3_11 : out std_logic; - FB_RXD_3_10 : out std_logic; - FB_RXD_3_9 : out std_logic; - FB_RXD_3_8 : out std_logic; - FB_RXD_3_7 : out std_logic; - FB_RXD_3_6 : out std_logic; - FB_RXD_3_5 : out std_logic; - FB_RXD_3_4 : out std_logic; - FB_RXD_3_3 : out std_logic; - FB_RXD_3_2 : out std_logic; - FB_RXD_3_1 : out std_logic; - FB_RXD_3_0 : out std_logic; - TCK_FMAC : out std_logic; - BS4PAD_0 : out std_logic; - BS4PAD_1 : out std_logic; - BS4PAD_2 : out std_logic; - BS4PAD_3 : out std_logic; - COUT_21 : out std_logic; - COUT_20 : out std_logic; - COUT_19 : out std_logic; - COUT_18 : out std_logic; - COUT_17 : out std_logic; - COUT_16 : out std_logic; - COUT_15 : out std_logic; - COUT_14 : out std_logic; - COUT_13 : out std_logic; - COUT_12 : out std_logic; - COUT_11 : out std_logic; - COUT_10 : out std_logic; - COUT_9 : out std_logic; - COUT_8 : out std_logic; - COUT_7 : out std_logic; - COUT_6 : out std_logic; - COUT_5 : out std_logic; - COUT_4 : out std_logic; - COUT_3 : out std_logic; - COUT_2 : out std_logic; - COUT_1 : out std_logic; - COUT_0 : out std_logic; - CIN_12 : in std_logic; - CIN_11 : in std_logic; - CIN_10 : in std_logic; - CIN_9 : in std_logic; - CIN_8 : in std_logic; - CIN_7 : in std_logic; - CIN_6 : in std_logic; - CIN_5 : in std_logic; - CIN_4 : in std_logic; - CIN_3 : in std_logic; - CIN_2 : in std_logic; - CIN_1 : in std_logic; - CIN_0 : in std_logic; - TESTCLK_MACO : in std_logic -); -end component; - attribute IS_ASB: string; - attribute IS_ASB of PCSA_INST : label is "or5s00/data/or5s00.acd"; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSA_INST : label is USER_CONFIG_FILE; - attribute CH0_RX_MAXRATE: string; - attribute CH0_RX_MAXRATE of PCSA_INST : label is "RXF3"; - attribute CH1_RX_MAXRATE: string; - attribute CH1_RX_MAXRATE of PCSA_INST : label is "RXF3"; - attribute CH2_RX_MAXRATE: string; - attribute CH2_RX_MAXRATE of PCSA_INST : label is "RXF3"; - attribute CH3_RX_MAXRATE: string; - attribute CH3_RX_MAXRATE of PCSA_INST : label is "RXF3"; - attribute CH0_TX_MAXRATE: string; - attribute CH0_TX_MAXRATE of PCSA_INST : label is "TXF2"; - attribute CH1_TX_MAXRATE: string; - attribute CH1_TX_MAXRATE of PCSA_INST : label is "TXF2"; - attribute CH2_TX_MAXRATE: string; - attribute CH2_TX_MAXRATE of PCSA_INST : label is "TXF2"; - attribute CH3_TX_MAXRATE: string; - attribute CH3_TX_MAXRATE of PCSA_INST : label is "TXF2"; - attribute AMP_BOOST: string; - attribute AMP_BOOST of PCSA_INST : label is "DISABLED"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSA : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN, RXREFCLKP, RXREFCLKN"; - -signal fpsc_vlo : std_logic := '0'; - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); - --- pcs_quad instance -PCSA_INST : PCSA ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - RXREFCLKP => fpsc_vlo, - RXREFCLKN => fpsc_vlo, - FFC_CK_CORE_RX => rxrefclk, - FFC_CK_CORE_TX => refclk, - CS_CHIF_0 => fpsc_vlo, - CS_CHIF_1 => fpsc_vlo, - CS_CHIF_2 => fpsc_vlo, - CS_CHIF_3 => fpsc_vlo, - CS_QIF => fpsc_vlo, - QUAD_ID_0 => fpsc_vlo, - QUAD_ID_1 => fpsc_vlo, - ADDRI_0 => fpsc_vlo, - ADDRI_1 => fpsc_vlo, - ADDRI_2 => fpsc_vlo, - ADDRI_3 => fpsc_vlo, - ADDRI_4 => fpsc_vlo, - ADDRI_5 => fpsc_vlo, - ADDRI_6 => fpsc_vlo, - ADDRI_7 => fpsc_vlo, - WDATAI_0 => fpsc_vlo, - WDATAI_1 => fpsc_vlo, - WDATAI_2 => fpsc_vlo, - WDATAI_3 => fpsc_vlo, - WDATAI_4 => fpsc_vlo, - WDATAI_5 => fpsc_vlo, - WDATAI_6 => fpsc_vlo, - WDATAI_7 => fpsc_vlo, - RDI => fpsc_vlo, - WSTBI => fpsc_vlo, - GRP_CLK_P1_0 => fpsc_vlo, - GRP_CLK_P1_1 => fpsc_vlo, - GRP_CLK_P1_2 => fpsc_vlo, - GRP_CLK_P1_3 => fpsc_vlo, - GRP_CLK_P2_0 => fpsc_vlo, - GRP_CLK_P2_1 => fpsc_vlo, - GRP_CLK_P2_2 => fpsc_vlo, - GRP_CLK_P2_3 => fpsc_vlo, - GRP_START_0 => fpsc_vlo, - GRP_START_1 => fpsc_vlo, - GRP_START_2 => fpsc_vlo, - GRP_START_3 => fpsc_vlo, - GRP_DONE_0 => fpsc_vlo, - GRP_DONE_1 => fpsc_vlo, - GRP_DONE_2 => fpsc_vlo, - GRP_DONE_3 => fpsc_vlo, - GRP_DESKEW_ERROR_0 => fpsc_vlo, - GRP_DESKEW_ERROR_1 => fpsc_vlo, - GRP_DESKEW_ERROR_2 => fpsc_vlo, - GRP_DESKEW_ERROR_3 => fpsc_vlo, --- to sysbusa - RDATAO_0 => open, - RDATAO_1 => open, - RDATAO_2 => open, - RDATAO_3 => open, - RDATAO_4 => open, - RDATAO_5 => open, - RDATAO_6 => open, - RDATAO_7 => open, - INTO => open, - QUAD_CLK => open, - IQA_START_LS => open, - IQA_DONE_LS => open, - IQA_AND_FP1_LS => open, - IQA_AND_FP0_LS => open, - IQA_OR_FP1_LS => open, - IQA_OR_FP0_LS => open, - IQA_RST_N => open, - - FF_TXD_0_19 => txd_0(15), - FF_TXD_0_18 => txd_0(14), - FF_TXD_0_17 => txd_0(13), - FF_TXD_0_16 => txd_0(12), - FF_TXD_0_15 => txd_0(11), - FF_TXD_0_14 => txd_0(10), - FF_TXD_0_13 => txd_0(9), - FF_TXD_0_12 => txd_0(8), - FF_TXD_0_7 => txd_0(7), - FF_TXD_0_6 => txd_0(6), - FF_TXD_0_5 => txd_0(5), - FF_TXD_0_4 => txd_0(4), - FF_TXD_0_3 => txd_0(3), - FF_TXD_0_2 => txd_0(2), - FF_TXD_0_1 => txd_0(1), - FF_TXD_0_0 => txd_0(0), - FB_RXD_0_19 => rxd_0(15), - FB_RXD_0_18 => rxd_0(14), - FB_RXD_0_17 => rxd_0(13), - FB_RXD_0_16 => rxd_0(12), - FB_RXD_0_15 => rxd_0(11), - FB_RXD_0_14 => rxd_0(10), - FB_RXD_0_13 => rxd_0(9), - FB_RXD_0_12 => rxd_0(8), - FB_RXD_0_7 => rxd_0(7), - FB_RXD_0_6 => rxd_0(6), - FB_RXD_0_5 => rxd_0(5), - FB_RXD_0_4 => rxd_0(4), - FB_RXD_0_3 => rxd_0(3), - FB_RXD_0_2 => rxd_0(2), - FB_RXD_0_1 => rxd_0(1), - FB_RXD_0_0 => rxd_0(0), - - FF_TXD_0_20 => tx_k_0(1), - FF_TXD_0_8 => tx_k_0(0), - FB_RXD_0_20 => rx_k_0(1), - FB_RXD_0_8 => rx_k_0(0), - - FF_TXD_0_21 => tx_force_disp_0(1), - FF_TXD_0_9 => tx_force_disp_0(0), - - FF_TXD_0_22 => tx_disp_sel_0(1), - FF_TXD_0_10 => tx_disp_sel_0(0), - - FF_TXD_0_23 => tx_crc_init_0(1), - FF_TXD_0_11 => tx_crc_init_0(0), - - FB_RXD_0_21 => rx_disp_err_detect_0(1), - FB_RXD_0_9 => rx_disp_err_detect_0(0), - - FB_RXD_0_22 => rx_cv_detect_0(1), - FB_RXD_0_10 => rx_cv_detect_0(0), - - FB_RXD_0_23 => rx_crc_eop_0(1), - FB_RXD_0_11 => rx_crc_eop_0(0), - - FF_TXD_1_19 => txd_1(15), - FF_TXD_1_18 => txd_1(14), - FF_TXD_1_17 => txd_1(13), - FF_TXD_1_16 => txd_1(12), - FF_TXD_1_15 => txd_1(11), - FF_TXD_1_14 => txd_1(10), - FF_TXD_1_13 => txd_1(9), - FF_TXD_1_12 => txd_1(8), - FF_TXD_1_7 => txd_1(7), - FF_TXD_1_6 => txd_1(6), - FF_TXD_1_5 => txd_1(5), - FF_TXD_1_4 => txd_1(4), - FF_TXD_1_3 => txd_1(3), - FF_TXD_1_2 => txd_1(2), - FF_TXD_1_1 => txd_1(1), - FF_TXD_1_0 => txd_1(0), - FB_RXD_1_19 => rxd_1(15), - FB_RXD_1_18 => rxd_1(14), - FB_RXD_1_17 => rxd_1(13), - FB_RXD_1_16 => rxd_1(12), - FB_RXD_1_15 => rxd_1(11), - FB_RXD_1_14 => rxd_1(10), - FB_RXD_1_13 => rxd_1(9), - FB_RXD_1_12 => rxd_1(8), - FB_RXD_1_7 => rxd_1(7), - FB_RXD_1_6 => rxd_1(6), - FB_RXD_1_5 => rxd_1(5), - FB_RXD_1_4 => rxd_1(4), - FB_RXD_1_3 => rxd_1(3), - FB_RXD_1_2 => rxd_1(2), - FB_RXD_1_1 => rxd_1(1), - FB_RXD_1_0 => rxd_1(0), - - FF_TXD_1_20 => tx_k_1(1), - FF_TXD_1_8 => tx_k_1(0), - FB_RXD_1_20 => rx_k_1(1), - FB_RXD_1_8 => rx_k_1(0), - - FF_TXD_1_21 => tx_force_disp_1(1), - FF_TXD_1_9 => tx_force_disp_1(0), - - FF_TXD_1_22 => tx_disp_sel_1(1), - FF_TXD_1_10 => tx_disp_sel_1(0), - FF_TXD_1_23 => tx_crc_init_1(1), - FF_TXD_1_11 => tx_crc_init_1(0), - - FB_RXD_1_21 => rx_disp_err_detect_1(1), - FB_RXD_1_9 => rx_disp_err_detect_1(0), - - FB_RXD_1_22 => rx_cv_detect_1(1), - FB_RXD_1_10 => rx_cv_detect_1(0), - - FB_RXD_1_23 => rx_crc_eop_1(1), - FB_RXD_1_11 => rx_crc_eop_1(0), - - FF_TXD_2_19 => txd_2(15), - FF_TXD_2_18 => txd_2(14), - FF_TXD_2_17 => txd_2(13), - FF_TXD_2_16 => txd_2(12), - FF_TXD_2_15 => txd_2(11), - FF_TXD_2_14 => txd_2(10), - FF_TXD_2_13 => txd_2(9), - FF_TXD_2_12 => txd_2(8), - FF_TXD_2_7 => txd_2(7), - FF_TXD_2_6 => txd_2(6), - FF_TXD_2_5 => txd_2(5), - FF_TXD_2_4 => txd_2(4), - FF_TXD_2_3 => txd_2(3), - FF_TXD_2_2 => txd_2(2), - FF_TXD_2_1 => txd_2(1), - FF_TXD_2_0 => txd_2(0), - FB_RXD_2_19 => rxd_2(15), - FB_RXD_2_18 => rxd_2(14), - FB_RXD_2_17 => rxd_2(13), - FB_RXD_2_16 => rxd_2(12), - FB_RXD_2_15 => rxd_2(11), - FB_RXD_2_14 => rxd_2(10), - FB_RXD_2_13 => rxd_2(9), - FB_RXD_2_12 => rxd_2(8), - FB_RXD_2_7 => rxd_2(7), - FB_RXD_2_6 => rxd_2(6), - FB_RXD_2_5 => rxd_2(5), - FB_RXD_2_4 => rxd_2(4), - FB_RXD_2_3 => rxd_2(3), - FB_RXD_2_2 => rxd_2(2), - FB_RXD_2_1 => rxd_2(1), - FB_RXD_2_0 => rxd_2(0), - - FF_TXD_2_20 => tx_k_2(1), - FF_TXD_2_8 => tx_k_2(0), - FB_RXD_2_20 => rx_k_2(1), - FB_RXD_2_8 => rx_k_2(0), - - FF_TXD_2_21 => tx_force_disp_2(1), - FF_TXD_2_9 => tx_force_disp_2(0), - - FF_TXD_2_22 => tx_disp_sel_2(1), - FF_TXD_2_10 => tx_disp_sel_2(0), - FF_TXD_2_23 => tx_crc_init_2(1), - FF_TXD_2_11 => tx_crc_init_2(0), - - FB_RXD_2_21 => rx_disp_err_detect_2(1), - FB_RXD_2_9 => rx_disp_err_detect_2(0), - - FB_RXD_2_22 => rx_cv_detect_2(1), - FB_RXD_2_10 => rx_cv_detect_2(0), - - FB_RXD_2_23 => rx_crc_eop_2(1), - FB_RXD_2_11 => rx_crc_eop_2(0), - - FF_TXD_3_19 => txd_3(15), - FF_TXD_3_18 => txd_3(14), - FF_TXD_3_17 => txd_3(13), - FF_TXD_3_16 => txd_3(12), - FF_TXD_3_15 => txd_3(11), - FF_TXD_3_14 => txd_3(10), - FF_TXD_3_13 => txd_3(9), - FF_TXD_3_12 => txd_3(8), - FF_TXD_3_7 => txd_3(7), - FF_TXD_3_6 => txd_3(6), - FF_TXD_3_5 => txd_3(5), - FF_TXD_3_4 => txd_3(4), - FF_TXD_3_3 => txd_3(3), - FF_TXD_3_2 => txd_3(2), - FF_TXD_3_1 => txd_3(1), - FF_TXD_3_0 => txd_3(0), - FB_RXD_3_19 => rxd_3(15), - FB_RXD_3_18 => rxd_3(14), - FB_RXD_3_17 => rxd_3(13), - FB_RXD_3_16 => rxd_3(12), - FB_RXD_3_15 => rxd_3(11), - FB_RXD_3_14 => rxd_3(10), - FB_RXD_3_13 => rxd_3(9), - FB_RXD_3_12 => rxd_3(8), - FB_RXD_3_7 => rxd_3(7), - FB_RXD_3_6 => rxd_3(6), - FB_RXD_3_5 => rxd_3(5), - FB_RXD_3_4 => rxd_3(4), - FB_RXD_3_3 => rxd_3(3), - FB_RXD_3_2 => rxd_3(2), - FB_RXD_3_1 => rxd_3(1), - FB_RXD_3_0 => rxd_3(0), - - FF_TXD_3_20 => tx_k_3(1), - FF_TXD_3_8 => tx_k_3(0), - FB_RXD_3_20 => rx_k_3(1), - FB_RXD_3_8 => rx_k_3(0), - - FF_TXD_3_21 => tx_force_disp_3(1), - FF_TXD_3_9 => tx_force_disp_3(0), - - FF_TXD_3_22 => tx_disp_sel_3(1), - FF_TXD_3_10 => tx_disp_sel_3(0), - FF_TXD_3_23 => tx_crc_init_3(1), - FF_TXD_3_11 => tx_crc_init_3(0), - - FB_RXD_3_21 => rx_disp_err_detect_3(1), - FB_RXD_3_9 => rx_disp_err_detect_3(0), - - FB_RXD_3_22 => rx_cv_detect_3(1), - FB_RXD_3_10 => rx_cv_detect_3(0), - - FB_RXD_3_23 => rx_crc_eop_3(1), - FB_RXD_3_11 => rx_crc_eop_3(0), - - HDINP0 => hdinp_0, - HDINN0 => hdinn_0, - HDOUTP0 => hdoutp_0, - HDOUTN0 => hdoutn_0, - FF_SYSCLK0 => ref_0_sclk, - FF_RXCLK0 => rx_0_sclk, - FFC_LANE_TX_RST0 => tx_rst_0, - FFC_LANE_RX_RST0 => rx_rst_0, - FF_TCLK0 => tclk_0, - FF_RCLK0 => rclk_0, - HDINP1 => hdinp_1, - HDINN1 => hdinn_1, - HDOUTP1 => hdoutp_1, - HDOUTN1 => hdoutn_1, - FF_SYSCLK1 => ref_1_sclk, - FF_RXCLK1 => rx_1_sclk, - FFC_LANE_TX_RST1 => tx_rst_1, - FFC_LANE_RX_RST1 => rx_rst_1, - FF_TCLK1 => tclk_1, - FF_RCLK1 => rclk_1, - HDINP2 => hdinp_2, - HDINN2 => hdinn_2, - HDOUTP2 => hdoutp_2, - HDOUTN2 => hdoutn_2, - FF_SYSCLK2 => ref_2_sclk, - FF_RXCLK2 => rx_2_sclk, - FFC_LANE_TX_RST2 => tx_rst_2, - FFC_LANE_RX_RST2 => rx_rst_2, - FF_TCLK2 => tclk_2, - FF_RCLK2 => rclk_2, - HDINP3 => hdinp_3, - HDINN3 => hdinn_3, - HDOUTP3 => hdoutp_3, - HDOUTN3 => hdoutn_3, - FF_SYSCLK3 => ref_3_sclk, - FF_RXCLK3 => rx_3_sclk, - FFC_LANE_TX_RST3 => tx_rst_3, - FFC_LANE_RX_RST3 => rx_rst_3, - FF_TCLK3 => tclk_3, - FF_RCLK3 => rclk_3, - - FFC_PCIE_EI_EN_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCIE_TX_0 => fpsc_vlo, - FFC_PCIE_RX_0 => fpsc_vlo, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFC_PCIE_EI_EN_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCIE_TX_1 => fpsc_vlo, - FFC_PCIE_RX_1 => fpsc_vlo, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFC_PCIE_EI_EN_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCIE_TX_2 => fpsc_vlo, - FFC_PCIE_RX_2 => fpsc_vlo, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFC_PCIE_EI_EN_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCIE_TX_3 => fpsc_vlo, - FFC_PCIE_RX_3 => fpsc_vlo, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - - FFC_SD_0 => lsm_en_0, - FFC_SD_1 => lsm_en_1, - FFC_SD_2 => lsm_en_2, - FFC_SD_3 => lsm_en_3, - - FFC_EN_CGA_0 => word_align_en_0, - FFC_EN_CGA_1 => word_align_en_1, - FFC_EN_CGA_2 => word_align_en_2, - FFC_EN_CGA_3 => word_align_en_3, - - FFC_ALIGN_EN_0 => mca_align_en_0, - FFC_ALIGN_EN_1 => mca_align_en_1, - FFC_ALIGN_EN_2 => mca_align_en_2, - FFC_ALIGN_EN_3 => mca_align_en_3, - - FFC_FB_LB_0 => felb_0, - FFC_FB_LB_1 => felb_1, - FFC_FB_LB_2 => felb_2, - FFC_FB_LB_3 => felb_3, - - FFS_LS_STATUS_0 => lsm_status_0, - FFS_LS_STATUS_1 => lsm_status_1, - FFS_LS_STATUS_2 => lsm_status_2, - FFS_LS_STATUS_3 => lsm_status_3, - - FFS_CC_ORUN_0 => open, - FFS_CC_URUN_0 => open, - FFS_CC_ORUN_1 => open, - FFS_CC_URUN_1 => open, - FFS_CC_ORUN_2 => open, - FFS_CC_URUN_2 => open, - FFS_CC_ORUN_3 => open, - FFS_CC_URUN_3 => open, - - FFC_AB_RESET => mca_resync_01, - - FFS_AB_STATUS => mca_aligned_01, - FFS_AB_ALIGNED => mca_inskew_01, - FFS_AB_FAILED => mca_outskew_01, - - FFC_CD_RESET => mca_resync_23, - FFS_CD_STATUS => mca_aligned_23, - - FFS_CD_ALIGNED => mca_inskew_23, - FFS_CD_FAILED => mca_outskew_23, - BS4PAD_0 => open, - BS4PAD_1 => open, - BS4PAD_2 => open, - BS4PAD_3 => open, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - TCK_FMAC => open, - TCK_FMACP => fpsc_vlo, - FF_SYSCLK_P1 => ref_pclk, - FF_RXCLK_P1 => rxa_pclk, - FF_RXCLK_P2 => rxb_pclk, - FFC_QUAD_RST => quad_rst, - FFS_RLOS_LO0 => open, - FFS_RLOS_LO1 => open, - FFS_RLOS_LO2 => open, - FFS_RLOS_LO3 => open, - COUT_21 => open, - COUT_20 => open, - COUT_19 => open, - COUT_18 => open, - COUT_17 => open, - COUT_16 => open, - COUT_15 => open, - COUT_14 => open, - COUT_13 => open, - COUT_12 => open, - COUT_11 => open, - COUT_10 => open, - COUT_9 => open, - COUT_8 => open, - COUT_7 => open, - COUT_6 => open, - COUT_5 => open, - COUT_4 => open, - COUT_3 => open, - COUT_2 => open, - COUT_1 => open, - COUT_0 => open, - CIN_12 => fpsc_vlo, - CIN_11 => fpsc_vlo, - CIN_10 => fpsc_vlo, - CIN_9 => fpsc_vlo, - CIN_8 => fpsc_vlo, - CIN_7 => fpsc_vlo, - CIN_6 => fpsc_vlo, - CIN_5 => fpsc_vlo, - CIN_4 => fpsc_vlo, - CIN_3 => fpsc_vlo, - CIN_2 => fpsc_vlo, - CIN_1 => fpsc_vlo, - CIN_0 => fpsc_vlo, - TESTCLK_MACO => fpsc_vlo, - FFC_MACRO_RST => serdes_rst); - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on - -end serdes_fpga_ref_clk_arch ; diff --git a/setup_env b/setup_env deleted file mode 100755 index 8b7b31e..0000000 --- a/setup_env +++ /dev/null @@ -1,28 +0,0 @@ -export ISPLEVER_PATH=/opt/lattice/isplever7.0/isptools - -export ISPCPLD=$ISPLEVER_PATH/ispcpld -export ISPJTOOLS=$ISPLEVER_PATH/ispjtools -export PDSPLUS=$ISPLEVER_PATH/ispcomp -export ISPFPGA=$ISPLEVER_PATH/ispfpga -export ISPVM_DIR=$ISPLEVER_PATH/ispvmsystem -export INI_FILE=lsc_7_0.ini -export MWHOME=$ISPCPLD/mw -export MWUSER_DIRECTORY=$HOME/isplever_lin_window -export MWREGISTRY=:$MWUSER_DIRECTORY/hklm_linux.bin -#unexport LD_LIBRARY_PATH -#source $MWHOME/setmwruntime.csh -export COMSPEC=/bin/csh -export PATH=$PATH:$ISPCPLD/bin:$PDSPLUS/bin:$ISPVM_DIR -export LD_LIBRARY_PATH=$ISPCPLD/bin:$PDSPLUS/bin:$ISPCPLD/../ispvmsystem/lib:$ISPFPGA/bin/lin:$ISPJTOOLS/vm15/lib/i386:$ISPJTOOLS/vm15/lib/i386/client:$ISPCPLD/tcltk/linux-ix86/lib:$LD_LIBRARY_PATH -export WINHELPDIR=$ISPCPLD/bin -export WINHELPPATH=$ISPCPLD/bin -export ABEL5DEV=$ISPCPLD/lib5 -#export LD_ASSUME_KERNEL 2.4.0 -export MWRT_MODE=professional - -export LM_LICENSE_FILE=$ISPCPLD/../license/license.dat:$LM_LICENSE_FILE - -sed -e "s?home_dir?$HOME/isplever_lin_window?" -e "s?bin_dir?$ISPLEVER_PATH/ispcpld/bin?" -e "s?isptool_dir?$ISPLEVER_PATH?" $ISPCPLD/config/$INI_FILE > $ISPLEVER_PATH/$INI_FILE -export LSC_INI_PATH=$ISPLEVER_PATH -export LSC_INI_FILE=$LSC_INI_PATH/$INI_FILE - diff --git a/simpleupcounter_16bit.vhd b/simpleupcounter_16bit.vhd deleted file mode 100644 index 4dd2e34..0000000 --- a/simpleupcounter_16bit.vhd +++ /dev/null @@ -1,40 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following lines to use the declarations that are --- provided for instantiating Xilinx primitive components. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity simpleupcounter_16bit is - Port ( QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); -end simpleupcounter_16bit; - -architecture simpleupcounter_16bit of simpleupcounter_16bit is - -signal counter: std_logic_vector (15 downto 0); - -begin - - process (CLR, UP, CLK) - - begin - if CLR = '1' then - counter <= "0000000000000000"; - elsif clk'event and clk = '1' then - if UP = '1' then - counter <= counter + 1; - else - counter <= counter; - end if; -end if; -end process; - -QOUT <= counter; - -end simpleupcounter_16bit; diff --git a/simpleupcounter_32bit.vhd b/simpleupcounter_32bit.vhd deleted file mode 100644 index 4bc7f93..0000000 --- a/simpleupcounter_32bit.vhd +++ /dev/null @@ -1,40 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following lines to use the declarations that are --- provided for instantiating Xilinx primitive components. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity simpleupcounter_32bit is - Port ( QOUT : out std_logic_vector(31 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); -end simpleupcounter_32bit; - -architecture simpleupcounter_32bit of simpleupcounter_32bit is - -signal counter: std_logic_vector (31 downto 0); - -begin - - process (CLR, UP, CLK) - - begin - if CLR = '1' then - counter <= "00000000000000000000000000000000"; - elsif clk'event and clk = '1' then - if UP = '1' then - counter <= counter + 1; - else - counter <= counter; - end if; -end if; -end process; - -QOUT <= counter; - -end simpleupcounter_32bit; diff --git a/simpleupcounter_8bit.vhd b/simpleupcounter_8bit.vhd deleted file mode 100644 index aa07751..0000000 --- a/simpleupcounter_8bit.vhd +++ /dev/null @@ -1,40 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following lines to use the declarations that are --- provided for instantiating Xilinx primitive components. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity simpleupcounter_8bit is - Port ( QOUT : out std_logic_vector(7 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); -end simpleupcounter_8bit; - -architecture Behavioral of simpleupcounter_8bit is - -signal counter: std_logic_vector (7 downto 0); - -begin - - process (CLR, UP, CLK) - - begin - if CLR = '1' then - counter <= ( others => '0'); - elsif clk'event and clk = '1' then - if UP = '1' then - counter <= counter + 1; - else - counter <= counter; - end if; -end if; -end process; - -QOUT <= counter; - -end Behavioral;