From: Jan Michel <j.michel@gsi.de>
Date: Thu, 23 Jul 2020 14:28:55 +0000 (+0200)
Subject: correct polarity of JIN inputs
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f8533e0a65bf7e20c6ffc99a4b9a3247b7fccdb1;p=trb3.git

correct polarity of JIN inputs
---

diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index 3ab183f..c80467c 100644
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -575,12 +575,14 @@ architecture trb3_central_arch of trb3_central is
 
    signal reboot_from_gbe : std_logic;
 
-   signal fwd_data : std_logic_vector(4 * 8 - 1 downto 0);
-   signal fwd_dv, fwd_sop, fwd_eop, fwd_ready, fwd_full : std_logic_vector(3 downto 0);
-   signal fwd_mac : std_logic_vector(4 * 48 - 1 downto 0);
-   signal fwd_ip : std_logic_vector(4 * 32 - 1 downto 0);
-   signal fwd_udp : std_logic_vector(4 * 16 - 1 downto 0);
+--    signal fwd_data : std_logic_vector(4 * 8 - 1 downto 0);
+--    signal fwd_dv, fwd_sop, fwd_eop, fwd_ready, fwd_full : std_logic_vector(3 downto 0);
+--    signal fwd_mac : std_logic_vector(4 * 48 - 1 downto 0);
+--    signal fwd_ip : std_logic_vector(4 * 32 - 1 downto 0);
+--    signal fwd_udp : std_logic_vector(4 * 16 - 1 downto 0);
 
+   signal jin1_corrected, jin2_corrected : std_logic_vector(3 downto 0);
+   
    component OSCF is
       port (
          OSC : out std_logic
@@ -766,19 +768,23 @@ begin
         FEE_DATA_FINISHED_OUT  => cts_rdo_finished
         );   
 
+   jin1_corrected <= JIN1(3) & JIN1(2) & not JIN1(1) & JIN1(0);
+   jin2_corrected <= JIN2(3) & JIN2(2) & not JIN2(1) & not JIN2(0);
+        
+        
 gen_trigger_in_nombsmaster : if INCLUDE_MBS_MASTER = c_NO and USE_CLKRJ_AS_OUTMUX = c_NO generate      
     cts_addon_triggers_in(1 downto 0) <= CLK_EXT;  -- former trigger inputs
 end generate;    
     cts_addon_triggers_in(3 downto 2) <= TRIGGER_EXT_3 & TRIGGER_EXT_2;  -- former trigger inputs
 
     cts_addon_triggers_in(7 downto 4)   <= ECL_IN;
-    cts_addon_triggers_in(11 downto 8)  <= JIN1;
-    cts_addon_triggers_in(15 downto 12) <= JIN2;
+    cts_addon_triggers_in(11 downto 8)  <= jin1_corrected;
+    cts_addon_triggers_in(15 downto 12) <= jin2_corrected;
     cts_addon_triggers_in(17 downto 16) <= NIM_IN;
 
     cts_addon_triggers_in(18)           <= or_all(ECL_IN);
-    cts_addon_triggers_in(19)           <= or_all(JIN1);
-    cts_addon_triggers_in(20)           <= or_all(JIN2);
+    cts_addon_triggers_in(19)           <= or_all(jin1_corrected);
+    cts_addon_triggers_in(20)           <= or_all(jin2_corrected);
     cts_addon_triggers_in(21)           <= or_all(NIM_IN);
     cts_addon_triggers_in(37 downto 22) <= JTTL;