From: Ludwig Maier Date: Tue, 10 Feb 2015 20:13:13 +0000 (+0100) Subject: ADCM: new compile script X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f885a43c8cb7bf4f5c4c1e4d13bdbff74f328eee;p=adcm.git ADCM: new compile script --- diff --git a/adcmv3.lpf b/adcmv3.lpf index c701a7c..9b69a65 100755 --- a/adcmv3.lpf +++ b/adcmv3.lpf @@ -238,22 +238,22 @@ LOCATE COMP "EXT_IN_0" SITE "AB28" ; # alternative, if needed # LOCATE COMP "EXT_IN_0" SITE "P28" ; IOBUF PORT "EXT_IN_0" IO_TYPE=LVTTL33 ; -# LOCATE COMP "DBG_EXP_41" SITE "T27" ; -# LOCATE COMP "DBG_EXP_39" SITE "T26" ; -# LOCATE COMP "DBG_EXP_37" SITE "U26" ; -# LOCATE COMP "DBG_EXP_35" SITE "V25" ; -# LOCATE COMP "DBG_EXP_33" SITE "W25" ; -# LOCATE COMP "DBG_EXP_31" SITE "W26" ; -# LOCATE COMP "DBG_EXP_29" SITE "Y26" ; -# LOCATE COMP "DBG_EXP_27" SITE "Y27" ; -# LOCATE COMP "DBG_EXP_25" SITE "AB26" ; -# LOCATE COMP "DBG_EXP_23" SITE "AC27" ; -# LOCATE COMP "DBG_EXP_21" SITE "U25" ; -# LOCATE COMP "DBG_EXP_19" SITE "U28" ; -# LOCATE COMP "DBG_EXP_17" SITE "U27" ; -# LOCATE COMP "DBG_EXP_5" SITE "R28" ; -# LOCATE COMP "DBG_EXP_3" SITE "R27" ; -# LOCATE COMP "DBG_EXP_1" SITE "T28" ; +LOCATE COMP "DBG_EXP_41" SITE "T27" ; +LOCATE COMP "DBG_EXP_39" SITE "T26" ; +LOCATE COMP "DBG_EXP_37" SITE "U26" ; +LOCATE COMP "DBG_EXP_35" SITE "V25" ; +LOCATE COMP "DBG_EXP_33" SITE "W25" ; +LOCATE COMP "DBG_EXP_31" SITE "W26" ; +LOCATE COMP "DBG_EXP_29" SITE "Y26" ; +LOCATE COMP "DBG_EXP_27" SITE "Y27" ; +LOCATE COMP "DBG_EXP_25" SITE "AB26" ; +LOCATE COMP "DBG_EXP_23" SITE "AC27" ; +LOCATE COMP "DBG_EXP_21" SITE "U25" ; +LOCATE COMP "DBG_EXP_19" SITE "U28" ; +LOCATE COMP "DBG_EXP_17" SITE "U27" ; +LOCATE COMP "DBG_EXP_5" SITE "R28" ; +LOCATE COMP "DBG_EXP_3" SITE "R27" ; +LOCATE COMP "DBG_EXP_1" SITE "T28" ; LOCATE COMP "UC_REBOOT" SITE "Y28" ; # was UC_FPGA3 IOBUF PORT "UC_REBOOT" IO_TYPE=LVTTL33 ; # LOCATE COMP "UC_FPGA_2" SITE "W27" ; @@ -311,34 +311,34 @@ IOBUF PORT "UC_RESET" IO_TYPE=LVTTL33 ; # I/O bank 2 - 3.30V # SFP control, LEDs, 1Wire ID, debug pins (SMC50) ###################################################################### -# LOCATE COMP "DBG_EXP_43" SITE "R26" ; -# LOCATE COMP "DBG_EXP_42" SITE "P25" ; -# LOCATE COMP "DBG_EXP_40" SITE "P26" ; -# LOCATE COMP "DBG_EXP_38" SITE "N25" ; -# LOCATE COMP "DBG_EXP_36" SITE "M25" ; -# LOCATE COMP "DBG_EXP_34" SITE "M26" ; -# LOCATE COMP "DBG_EXP_32" SITE "L25" ; -# LOCATE COMP "DBG_EXP_30" SITE "L26" ; -# LOCATE COMP "DBG_EXP_28" SITE "K25" ; -# LOCATE COMP "DBG_EXP_26" SITE "J26" ; -# LOCATE COMP "DBG_EXP_24" SITE "H25" ; -# LOCATE COMP "DBG_EXP_22" SITE "H26" ; -# LOCATE COMP "DBG_EXP_20" SITE "H24" ; -# LOCATE COMP "DBG_EXP_18" SITE "G26" ; -# LOCATE COMP "DBG_EXP_16" SITE "G25" ; -# LOCATE COMP "DBG_EXP_15" SITE "L27" ; -# LOCATE COMP "DBG_EXP_14" SITE "L28" ; -# LOCATE COMP "DBG_EXP_13" SITE "M28" ; -# LOCATE COMP "DBG_EXP_12" SITE "K24" ; -# LOCATE COMP "DBG_EXP_11" SITE "M27" ; -# LOCATE COMP "DBG_EXP_10" SITE "M30" ; -# LOCATE COMP "DBG_EXP_9" SITE "N26" ; -# LOCATE COMP "DBG_EXP_8" SITE "M29" ; -# LOCATE COMP "DBG_EXP_7" SITE "P27" ; -# LOCATE COMP "DBG_EXP_6" SITE "L30" ; -# LOCATE COMP "DBG_EXP_4" SITE "L29" ; -# LOCATE COMP "DBG_EXP_2" SITE "K30" ; -# LOCATE COMP "DBG_EXP_0" SITE "K29" ; +LOCATE COMP "DBG_EXP_43" SITE "R26" ; +LOCATE COMP "DBG_EXP_42" SITE "P25" ; +LOCATE COMP "DBG_EXP_40" SITE "P26" ; +LOCATE COMP "DBG_EXP_38" SITE "N25" ; +LOCATE COMP "DBG_EXP_36" SITE "M25" ; +LOCATE COMP "DBG_EXP_34" SITE "M26" ; +LOCATE COMP "DBG_EXP_32" SITE "L25" ; +LOCATE COMP "DBG_EXP_30" SITE "L26" ; +LOCATE COMP "DBG_EXP_28" SITE "K25" ; +LOCATE COMP "DBG_EXP_26" SITE "J26" ; +LOCATE COMP "DBG_EXP_24" SITE "H25" ; +LOCATE COMP "DBG_EXP_22" SITE "H26" ; +LOCATE COMP "DBG_EXP_20" SITE "H24" ; +LOCATE COMP "DBG_EXP_18" SITE "G26" ; +LOCATE COMP "DBG_EXP_16" SITE "G25" ; +LOCATE COMP "DBG_EXP_15" SITE "L27" ; +LOCATE COMP "DBG_EXP_14" SITE "L28" ; +LOCATE COMP "DBG_EXP_13" SITE "M28" ; +LOCATE COMP "DBG_EXP_12" SITE "K24" ; +LOCATE COMP "DBG_EXP_11" SITE "M27" ; +LOCATE COMP "DBG_EXP_10" SITE "M30" ; +LOCATE COMP "DBG_EXP_9" SITE "N26" ; +LOCATE COMP "DBG_EXP_8" SITE "M29" ; +LOCATE COMP "DBG_EXP_7" SITE "P27" ; +LOCATE COMP "DBG_EXP_6" SITE "L30" ; +LOCATE COMP "DBG_EXP_4" SITE "L29" ; +LOCATE COMP "DBG_EXP_2" SITE "K30" ; +LOCATE COMP "DBG_EXP_0" SITE "K29" ; LOCATE COMP "FPGA_LED_6" SITE "G28" ; IOBUF PORT "FPGA_LED_6" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; LOCATE COMP "FPGA_LED_5" SITE "G27" ; @@ -444,8 +444,8 @@ IOBUF PORT "BP_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ; # simplify IO definitions ###################################################################### # Debug header (50pin SMC connector) -# DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ; -# IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=4 SLEWRATE=FAST ; +DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ; +IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN SLEWRATE=FAST ; # LED drivers # DEFINE PORT GROUP "led_output_group" "FPGA_LED*" ; diff --git a/adcmv3.prj b/adcmv3.prj index 8f2b6ed..23224e7 100644 --- a/adcmv3.prj +++ b/adcmv3.prj @@ -8,6 +8,7 @@ add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "source/adcmv3_components.vhd" +add_file -vhdl -lib work "source/adcmv3_components2.vhd" # ADCMv3 design files # Top level entity @@ -58,6 +59,9 @@ add_file -vhdl -lib work "source/slv_ped_thr_mem.vhd" add_file -vhdl -lib work "source/slave_bus.vhd" add_file -vhdl -lib work "source/rich_trb.vhd" +# Addons +add_file -vhdl -lib work "source/debug_multiplexer.vhd" + # Core files add_file -vhdl -lib work "cores/adc_ch_in.vhd" add_file -vhdl -lib work "cores/eds_buffer_dpram.vhd" diff --git a/adcmv3.vhd b/adcmv3.vhd index 518cc63..f8f11da 100644 --- a/adcmv3.vhd +++ b/adcmv3.vhd @@ -83,9 +83,9 @@ port( U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM U_SPI_SCK : out std_logic; -- OK -- clock U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM - U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM + U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM -- Debug connections --- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header + DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header ); end; @@ -215,11 +215,6 @@ type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0); signal adc_ctrl_reg : reg_16bit_t; signal adc_stat_reg : reg_16bit_t; signal raw_buf_dbg : reg_16bit_t; - ---signal debug : std_logic_vector(42 downto 0); ---signal debug_q : std_logic_vector(42 downto 0); ---signal debug_qq : std_logic_vector(42 downto 0); ---signal debug_clk : std_logic; -- LVL1 application interface signal lvl1_trg_type : std_logic_vector(3 downto 0); @@ -292,9 +287,30 @@ signal fe_error : std_logic; signal tick_10s : std_logic; +-- Debug Multiplexer +signal debug_o : std_logic_vector(33 downto 0); + begin +------------------------------------------------------------------------------- +-- Debug Out +------------------------------------------------------------------------------- + + DEBUG: for I in 0 to 15 generate + debug_o(2 * I) <= sysclk; + debug_o(2 * I + 1) <= not sysclk; + end generate DEBUG; + debug_o(32) <= sysclk; + debug_o(33) <= not sysclk; + + DBG_EXP(31 downto 0) <= debug_o(31 downto 0); + DBG_EXP(37 downto 32) <= (others => '0'); + DBG_EXP(38) <= debug_o(32); + DBG_EXP(41 downto 49) <= (others => '0'); + DBG_EXP(42) <= debug_o(33); + DBG_EXP(43) <= '0'; + ---------------------------------------- -- Async reset assignment -- ---------------------------------------- @@ -762,7 +778,6 @@ apv_reset <= apv0_reset or apv1_reset or frontend_reset; GEN_ADC_LVDS_ON: for i in 0 to 15 generate adc_on(i) <= adc_ctrl_reg(i)(0); lvds_on(i) <= adc_ctrl_reg(i)(1); --- adc_stat_reg(i) <= raw_buf_dbg(i); adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4)); broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit apv_error(i) <= buf_data(i)(26); -- APV error frame bit diff --git a/compile.pl b/compile.pl deleted file mode 100755 index c9b4049..0000000 --- a/compile.pl +++ /dev/null @@ -1,218 +0,0 @@ -#!/usr/bin/perl -########################################### -# Script file to run the flow -########################################### - -# You need the tunnels before! - -use Data::Dumper; -use warnings; -use strict; - -# Path settings for ispLEVER tools -my $lattice_path = '/usr/local/opt/synplify/8/isptools'; - -# Path settings for SynplifyPRO -my $synplify_path = '/usr/local/opt/synplify/premier'; -# my $synplify_path = '/scratch/rich/synplify/D-2009.12'; - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}="27000\@localhost"; - -# Design top level entity -my $TOPNAME="adcmv3"; - -# FPGA chip description -my $FAMILYNAME="LATTICEECP2M"; -my $DEVICENAME="LFE2M100E"; -my $PACKAGE="FPBGA900"; -my $SPEEDGRADE="6"; - -# benchmarking -my $CTIME_String = localtime(time); -print "Script started: $CTIME_String\n"; -system("echo $CTIME_String > workdir/benchmark.txt"); - -# cleanup in workdir -system("rm workdir/$TOPNAME.alt"); -system("rm workdir/$TOPNAME.bgn"); -system("rm workdir/$TOPNAME.bit"); -system("rm workdir/$TOPNAME.edf"); -system("rm workdir/$TOPNAME.fse"); -system("rm workdir/$TOPNAME.mrp"); -system("rm workdir/$TOPNAME.ncd"); -system("rm workdir/$TOPNAME.ngd"); -system("rm workdir/$TOPNAME.ngo"); -system("rm workdir/$TOPNAME.ngy"); -system("rm workdir/$TOPNAME.pad"); -system("rm workdir/$TOPNAME.par"); -system("rm workdir/$TOPNAME.sr?"); -system("rm workdir/$TOPNAME.tlg"); -system("rm workdir/$TOPNAME.twr*"); - -# Create full lpf file -#system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); -#system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); -system("cp ./$TOPNAME.lpf workdir/$TOPNAME.lpf"); -system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); - -# Generate timestamp for slowcontrol readback -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -# Run Synplify on the design -system("env| grep LM_"); -my $r = ""; -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; -$r=execute($c, "do_not_exit" ); - -# Check for errors -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - -foreach (@a) -{ - if(/\@E:/) - { - $c="cat $TOPNAME.srr"; - system($c); - print "ERROR_ERROR_ERROR_ERROR_ERROR\n"; - exit 129; - } -} - -# ispLEVER design flow starts here -# new license file must be given -$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; - -# EDIF2NGD -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -# NGDBUILD -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -# MAP -my $tpmap = $TOPNAME . "_map" ; -$c=qq|$lattice_path/ispfpga/bin/lin/map -noinferGSR -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf" -tdm -td_pack|; -execute($c); - -system("rm $TOPNAME.ncd"); - -# MULTIPAR - -my $fh2 = new FileHandle(">$TOPNAME.p2t"); -die "could not open file" if (! defined $fh2); -print $fh2 <close; - -###################################################################### -# -w # overwrite files -# -i 15 # maximum number of routing attempts -# -l 5 # effort level (1-5) -# -n 1 # starting cost table (n=0 loop) -# -y # delay summary report -# -s 12 # number of best results to save -# -t 1 # start placement with cost table X -# -c 1 # number of cost-based cleanup passes of the router -# -e 2 # number of delay-based cleanup passes of the router -# -m nodelist.txt # -# -exp parCDP=1 # -# -exp parCDR=1 # -# -exp parPlcInLimit=0 # -# -exp parPlcInNeighborSize=1 # -# -exp parPathBased=ON # -# -exp parHold=ON # -# -exp parHoldLimit=10000 # -# -exp paruseNBR=1 # -###################################################################### - -# real multipar -$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; -execute($c); - -# IOR IO Timing Report -#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -#execute($c); - -# TWR Timing Report (setup) -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# TWR Timing Report (hold) -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# BitGen -#$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|; -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -chdir ".."; - -$CTIME_String = localtime(time); -print "Script ended: $CTIME_String\n"; -system("echo $CTIME_String >> workdir/benchmark.txt"); - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/compile_munich21.pl b/compile_munich21.pl deleted file mode 100755 index ef644d5..0000000 --- a/compile_munich21.pl +++ /dev/null @@ -1,149 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - - - - -################################################################################### -#Settings for this project -my $TOPNAME = "adcmv3"; #Name of top-level entity -my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.1'; -my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; -my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; -my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; -################################################################################### - - - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - -# FPGA chip description -my $FAMILYNAME="LATTICEECP2M"; -my $DEVICENAME="LFE2M100E"; -my $PACKAGE="FPBGA900"; -my $SPEEDGRADE="6"; - -#create full lpf file -system("cp ./$TOPNAME.lpf workdir/$TOPNAME.lpf"); -system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); -#system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf"); -#system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; - -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - - -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -my $tpmap = $TOPNAME . "_map" ; - -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -execute($c); - -system("rm $TOPNAME.ncd"); - - -$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# IOR IO Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -#$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -#execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; -# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -chdir ".."; - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/compile_munich21.sh b/compile_munich21.sh deleted file mode 100755 index 5b8795e..0000000 --- a/compile_munich21.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -. /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env - -exec ./compile_munich21.pl -#exec ./compile.pl diff --git a/source/rich_trb.vhd b/source/rich_trb.vhd index a58448e..8ebd24a 100644 --- a/source/rich_trb.vhd +++ b/source/rich_trb.vhd @@ -229,7 +229,8 @@ port map( MED_READ_OUT => med_read_out_int, MED_STAT_OP_IN => med_stat_op, MED_CTRL_OP_OUT => med_ctrl_op, - -- LVL1 trigger APL + + -- LVL1 trigger APL LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...) @@ -242,7 +243,8 @@ port map( LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint - -- IPU Port + + -- IPU Port IPU_NUMBER_OUT => IPU_NUMBER_OUT, IPU_READOUT_TYPE_OUT => open, -- 4bit readout type IPU_INFORMATION_OUT => IPU_INFORMATION_OUT, @@ -253,7 +255,8 @@ port map( IPU_READ_OUT => IPU_READ_OUT, IPU_LENGTH_IN => IPU_LENGTH_IN, IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN, - -- Slow Control Data Port + + -- Slow Control Data Port REGIO_COMMON_STAT_REG_IN => common_stat_reg, REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, REGIO_REGISTERS_IN => regio_stat_regs, @@ -262,7 +265,8 @@ port map( COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number STAT_REG_STROBE => open, CTRL_REG_STROBE => open, - --following ports only used when using internal data port + + --following ports only used when using internal data port REGIO_ADDR_OUT => REGIO_ADDR_OUT, REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, @@ -273,7 +277,8 @@ port map( REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, - --IDRAM is used if no 1-wire interface, onewire used otherwise + + --IDRAM is used if no 1-wire interface, onewire used otherwise REGIO_IDRAM_DATA_IN => x"0000", -- not used REGIO_IDRAM_DATA_OUT => open, -- not used REGIO_IDRAM_ADDR_IN => "000", -- not used @@ -281,13 +286,15 @@ port map( REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT, REGIO_ONEWIRE_MONITOR_IN => '1', -- not used REGIO_ONEWIRE_MONITOR_OUT => open, -- not used - -- New stuff + + -- New stuff GLOBAL_TIME_OUT => open, LOCAL_TIME_OUT => open, TIME_SINCE_LAST_TRG_OUT => open, TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks TIMER_TICKS_OUT(0) => open, -- us ticks - -- Status and debug + + -- Status and debug STAT_DEBUG_IPU => open, STAT_DEBUG_1 => stat_debug_1, --open, STAT_DEBUG_2 => open, diff --git a/source/slave_bus.vhd b/source/slave_bus.vhd index be178b9..93b64ca 100644 --- a/source/slave_bus.vhd +++ b/source/slave_bus.vhd @@ -169,13 +169,16 @@ end entity; architecture Behavioral of slave_bus is -- Signals -signal slv_read : std_logic_vector(18-1 downto 0); -signal slv_write : std_logic_vector(18-1 downto 0); +constant NUM_PORTS : integer := 18; +signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); +signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); signal slv_busy : std_logic_vector(18-1 downto 0); -signal slv_ack : std_logic_vector(18-1 downto 0); -signal slv_addr : std_logic_vector(18*16-1 downto 0); -signal slv_data_rd : std_logic_vector(18*32-1 downto 0); -signal slv_data_wr : std_logic_vector(18*32-1 downto 0); +signal slv_no_more_data : std_logic_vector(NUM_PORTS-1 downto 0); +signal slv_ack : std_logic_vector(NUM_PORTS-1 downto 0); +signal slv_addr : std_logic_vector(NUM_PORTS*16-1 downto 0); +signal slv_data_rd : std_logic_vector(NUM_PORTS*32-1 downto 0); +signal slv_data_wr : std_logic_vector(NUM_PORTS*32-1 downto 0); +signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0); -- SPI controller BRAM lines signal spi_bram_addr : std_logic_vector(7 downto 0); @@ -201,7 +204,7 @@ begin -- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus THE_BUS_HANDLER: trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 18, + PORT_NUMBER => NUM_PORTS, PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories 1 => x"a800", -- threshold memories 2 => x"8040", -- I2C master @@ -239,8 +242,9 @@ generic map( 15 => 4, -- FIFO status registers 16 => 0, -- LVL1 release status register 17 => 0, -- IPU handler status register - others => 0) -) + others => 0), + PORT_MASK_ENABLE => 1 + ) port map( CLK => CLK_IN, RESET => RESET_IN, @@ -254,185 +258,22 @@ port map( DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT, DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT, DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT, - -- pedestal memories - BUS_READ_ENABLE_OUT(0) => slv_read(0), - BUS_WRITE_ENABLE_OUT(0) => slv_write(0), - BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32), - BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32), - BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16), - BUS_TIMEOUT_OUT(0) => open, - BUS_DATAREADY_IN(0) => slv_ack(0), - BUS_WRITE_ACK_IN(0) => slv_ack(0), - BUS_NO_MORE_DATA_IN(0) => slv_busy(0), - BUS_UNKNOWN_ADDR_IN(0) => '0', - -- threshold memories - BUS_READ_ENABLE_OUT(1) => slv_read(1), - BUS_WRITE_ENABLE_OUT(1) => slv_write(1), - BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32), - BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32), - BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16), - BUS_TIMEOUT_OUT(1) => open, - BUS_DATAREADY_IN(1) => slv_ack(1), - BUS_WRITE_ACK_IN(1) => slv_ack(1), - BUS_NO_MORE_DATA_IN(1) => slv_busy(1), - BUS_UNKNOWN_ADDR_IN(1) => '0', - -- I2C master - BUS_READ_ENABLE_OUT(2) => slv_read(2), - BUS_WRITE_ENABLE_OUT(2) => slv_write(2), - BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), - BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), - BUS_ADDR_OUT(2*16+15 downto 2*16) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATAREADY_IN(2) => slv_ack(2), - BUS_WRITE_ACK_IN(2) => slv_ack(2), - BUS_NO_MORE_DATA_IN(2) => slv_busy(2), - BUS_UNKNOWN_ADDR_IN(2) => '0', - -- OneWire master - BUS_READ_ENABLE_OUT(3) => slv_read(3), - BUS_WRITE_ENABLE_OUT(3) => slv_write(3), - BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32), - BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32), - BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16), - BUS_TIMEOUT_OUT(3) => open, - BUS_DATAREADY_IN(3) => slv_ack(3), - BUS_WRITE_ACK_IN(3) => slv_ack(3), - BUS_NO_MORE_DATA_IN(3) => slv_busy(3), - BUS_UNKNOWN_ADDR_IN(3) => '0', - -- SPI control registers - BUS_READ_ENABLE_OUT(4) => slv_read(4), - BUS_WRITE_ENABLE_OUT(4) => slv_write(4), - BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32), - BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), - BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16), - BUS_TIMEOUT_OUT(4) => open, - BUS_DATAREADY_IN(4) => slv_ack(4), - BUS_WRITE_ACK_IN(4) => slv_ack(4), - BUS_NO_MORE_DATA_IN(4) => slv_busy(4), - BUS_UNKNOWN_ADDR_IN(4) => '0', - -- SPI data memory - BUS_READ_ENABLE_OUT(5) => slv_read(5), - BUS_WRITE_ENABLE_OUT(5) => slv_write(5), - BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32), - BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32), - BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16), - BUS_TIMEOUT_OUT(5) => open, - BUS_DATAREADY_IN(5) => slv_ack(5), - BUS_WRITE_ACK_IN(5) => slv_ack(5), - BUS_NO_MORE_DATA_IN(5) => slv_busy(5), - BUS_UNKNOWN_ADDR_IN(5) => '0', - -- ADC 0 SPI control registers - BUS_READ_ENABLE_OUT(6) => slv_read(6), - BUS_WRITE_ENABLE_OUT(6) => slv_write(6), - BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32), - BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32), - BUS_ADDR_OUT(6*16+15 downto 6*16) => open, - BUS_TIMEOUT_OUT(6) => open, - BUS_DATAREADY_IN(6) => slv_ack(6), - BUS_WRITE_ACK_IN(6) => slv_ack(6), - BUS_NO_MORE_DATA_IN(6) => slv_busy(6), - BUS_UNKNOWN_ADDR_IN(6) => '0', - -- ADC 1 SPI control registers - BUS_READ_ENABLE_OUT(7) => slv_read(7), - BUS_WRITE_ENABLE_OUT(7) => slv_write(7), - BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32), - BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32), - BUS_ADDR_OUT(7*16+15 downto 7*16) => open, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATAREADY_IN(7) => slv_ack(7), - BUS_WRITE_ACK_IN(7) => slv_ack(7), - BUS_NO_MORE_DATA_IN(7) => slv_busy(7), - BUS_UNKNOWN_ADDR_IN(7) => '0', - -- APV control / status registers - BUS_READ_ENABLE_OUT(8) => slv_read(8), - BUS_WRITE_ENABLE_OUT(8) => slv_write(8), - BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32), - BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32), - BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16), - BUS_TIMEOUT_OUT(8) => open, - BUS_DATAREADY_IN(8) => slv_ack(8), - BUS_WRITE_ACK_IN(8) => slv_ack(8), - BUS_NO_MORE_DATA_IN(8) => slv_busy(8), - BUS_UNKNOWN_ADDR_IN(8) => '0', - -- ADC / PLL / trigger ctrl register - BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9), - BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9), - BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32), - BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32), - BUS_ADDR_OUT(11*16+15 downto 9*16) => open, - BUS_TIMEOUT_OUT(11 downto 9) => open, - BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9), - BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9), - BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9), - BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'), - -- ADC0 snooper - BUS_READ_ENABLE_OUT(12) => slv_read(12), - BUS_WRITE_ENABLE_OUT(12) => slv_write(12), - BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32), - BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32), - BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16), - BUS_TIMEOUT_OUT(12) => open, - BUS_DATAREADY_IN(12) => slv_ack(12), - BUS_WRITE_ACK_IN(12) => slv_ack(12), - BUS_NO_MORE_DATA_IN(12) => slv_busy(12), - BUS_UNKNOWN_ADDR_IN(12) => '0', - -- ADC1 snooper - BUS_READ_ENABLE_OUT(13) => slv_read(13), - BUS_WRITE_ENABLE_OUT(13) => slv_write(13), - BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32), - BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32), - BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16), - BUS_TIMEOUT_OUT(13) => open, - BUS_DATAREADY_IN(13) => slv_ack(13), - BUS_WRITE_ACK_IN(13) => slv_ack(13), - BUS_NO_MORE_DATA_IN(13) => slv_busy(13), - BUS_UNKNOWN_ADDR_IN(13) => '0', - -- Test register - BUS_READ_ENABLE_OUT(14) => slv_read(14), - BUS_WRITE_ENABLE_OUT(14) => slv_write(14), - BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32), - BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32), - BUS_ADDR_OUT(14*16+15 downto 14*16) => open, - BUS_TIMEOUT_OUT(14) => open, - BUS_DATAREADY_IN(14) => slv_ack(14), - BUS_WRITE_ACK_IN(14) => slv_ack(14), - BUS_NO_MORE_DATA_IN(14) => slv_busy(14), - BUS_UNKNOWN_ADDR_IN(14) => '0', - -- data buffer status registers - BUS_READ_ENABLE_OUT(15) => slv_read(15), - BUS_WRITE_ENABLE_OUT(15) => slv_write(15), - BUS_DATA_OUT(15*32+31 downto 15*32) => slv_data_wr(15*32+31 downto 15*32), - BUS_DATA_IN(15*32+31 downto 15*32) => slv_data_rd(15*32+31 downto 15*32), - BUS_ADDR_OUT(15*16+15 downto 15*16) => slv_addr(15*16+15 downto 15*16), - BUS_TIMEOUT_OUT(15) => open, - BUS_DATAREADY_IN(15) => slv_ack(15), - BUS_WRITE_ACK_IN(15) => slv_ack(15), - BUS_NO_MORE_DATA_IN(15) => slv_busy(15), - BUS_UNKNOWN_ADDR_IN(15) => '0', - -- LVL1 release status register - BUS_READ_ENABLE_OUT(16) => slv_read(16), - BUS_WRITE_ENABLE_OUT(16) => slv_write(16), - BUS_DATA_OUT(16*32+31 downto 16*32) => slv_data_wr(16*32+31 downto 16*32), - BUS_DATA_IN(16*32+31 downto 16*32) => slv_data_rd(16*32+31 downto 16*32), - BUS_ADDR_OUT(16*16+15 downto 16*16) => slv_addr(16*16+15 downto 16*16), - BUS_TIMEOUT_OUT(16) => open, - BUS_DATAREADY_IN(16) => slv_ack(16), - BUS_WRITE_ACK_IN(16) => slv_ack(16), - BUS_NO_MORE_DATA_IN(16) => slv_busy(16), - BUS_UNKNOWN_ADDR_IN(16) => '0', - -- IPU handler status register - BUS_READ_ENABLE_OUT(17) => slv_read(17), - BUS_WRITE_ENABLE_OUT(17) => slv_write(17), - BUS_DATA_OUT(17*32+31 downto 17*32) => slv_data_wr(17*32+31 downto 17*32), - BUS_DATA_IN(17*32+31 downto 17*32) => slv_data_rd(17*32+31 downto 17*32), - BUS_ADDR_OUT(17*16+15 downto 17*16) => slv_addr(17*16+15 downto 17*16), - BUS_TIMEOUT_OUT(17) => open, - BUS_DATAREADY_IN(17) => slv_ack(17), - BUS_WRITE_ACK_IN(17) => slv_ack(17), - BUS_NO_MORE_DATA_IN(17) => slv_busy(17), - BUS_UNKNOWN_ADDR_IN(17) => '0', + + -- All Slow Control Ports + BUS_READ_ENABLE_OUT => slv_read, + BUS_WRITE_ENABLE_OUT => slv_write, + BUS_DATA_OUT => slv_data_wr, + BUS_DATA_IN => slv_data_rd, + BUS_ADDR_OUT => slv_addr, + BUS_TIMEOUT_OUT => open, + BUS_DATAREADY_IN => slv_ack, + BUS_WRITE_ACK_IN => slv_ack, + BUS_NO_MORE_DATA_IN => slv_no_more_data, + BUS_UNKNOWN_ADDR_IN => slv_unknown_addr, + -- debug - STAT_DEBUG => stat -); + STAT_DEBUG => stat + ); ------------------------------------------------------------------------------------ @@ -472,7 +313,7 @@ port map( MEM_15_D_OUT => PED_DATA_15_OUT, -- Status lines STAT => open -); + ); slv_busy(0) <= '0'; ------------------------------------------------------------------------------------ @@ -954,8 +795,6 @@ port map( ); - - -- unusable pins debug(63 downto 43) <= (others => '0'); -- connected pins