From: Thomas Gessler Date: Thu, 3 Sep 2020 09:20:55 +0000 (+0200) Subject: Fix Xilinx FIFO counts, remove unused FIFOs X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f9cec9b914b31a71a2530a87b6d99117309ce36e;p=trbnet.git Fix Xilinx FIFO counts, remove unused FIFOs --- diff --git a/xilinx/xcku/fifo_1024x9x18_oreg_wcnt.vhd b/xilinx/xcku/fifo_1024x9x18_oreg_wcnt.vhd deleted file mode 100644 index 515a2dc..0000000 --- a/xilinx/xcku/fifo_1024x9x18_oreg_wcnt.vhd +++ /dev/null @@ -1,54 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity fifo_1024x9x18_oreg_wcnt is - port ( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(17 downto 0); - WCNT : out std_logic_vector(9 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic - ); -end entity fifo_1024x9x18_oreg_wcnt; - -architecture structural of fifo_1024x9x18_oreg_wcnt is - component fifo_1024x9x18_oreg_wcnt_xcku - port ( - rst : in std_logic; - wr_clk : in std_logic; - rd_clk : in std_logic; - din : in std_logic_vector(8 downto 0); - wr_en : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(17 downto 0); - full : out std_logic; - almost_full : out std_logic; - empty : out std_logic; - almost_empty : out std_logic; - wr_data_count : out std_logic_vector(9 downto 0) - ); - end component; -begin - fifo : fifo_1024x9x18_oreg_wcnt_xcku - port map ( - rst => Reset, - wr_clk => WrClock, - rd_clk => RdClock, - din => Data, - wr_en => WrEn, - rd_en => RdEn, - dout => Q, - full => Full, - almost_full => AlmostFull, - empty => Empty, - almost_empty => AlmostEmpty, - wr_data_count => WCNT - ); -end architecture structural; diff --git a/xilinx/xcku/fifo_1024x9x18_oreg_wcnt_xcku/fifo_1024x9x18_oreg_wcnt_xcku.xci b/xilinx/xcku/fifo_1024x9x18_oreg_wcnt_xcku/fifo_1024x9x18_oreg_wcnt_xcku.xci deleted file mode 100644 index 651bf34..0000000 --- a/xilinx/xcku/fifo_1024x9x18_oreg_wcnt_xcku/fifo_1024x9x18_oreg_wcnt_xcku.xci +++ /dev/null @@ -1,569 +0,0 @@ - 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STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_ar_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_full_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_empty_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_wr_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_rd_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_r_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axis_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - - - C_COMMON_CLOCK - 0 - - - C_SELECT_XPM - 0 - - - C_COUNT_TYPE - 0 - - - C_DATA_COUNT_WIDTH - 10 - - - C_DEFAULT_VALUE - BlankString - - - C_DIN_WIDTH - 9 - - - C_DOUT_RST_VAL - 0 - - - C_DOUT_WIDTH - 18 - - - C_ENABLE_RLOCS - 0 - - - C_FAMILY - kintexu - - - C_FULL_FLAGS_RST_VAL - 1 - - - C_HAS_ALMOST_EMPTY - 1 - - - C_HAS_ALMOST_FULL - 1 - - - C_HAS_BACKUP - 0 - - - C_HAS_DATA_COUNT - 0 - - - C_HAS_INT_CLK - 0 - - - C_HAS_MEMINIT_FILE - 0 - - - C_HAS_OVERFLOW - 0 - - - C_HAS_RD_DATA_COUNT - 0 - - - C_HAS_RD_RST - 0 - - - C_HAS_RST - 1 - - - C_HAS_SRST - 0 - - - C_HAS_UNDERFLOW - 0 - - - C_HAS_VALID - 0 - - - C_HAS_WR_ACK - 0 - - - C_HAS_WR_DATA_COUNT - 1 - - - C_HAS_WR_RST - 0 - - - C_IMPLEMENTATION_TYPE - 2 - - - C_INIT_WR_PNTR_VAL - 0 - - - C_MEMORY_TYPE - 1 - - - C_MIF_FILE_NAME - BlankString - - - C_OPTIMIZATION_MODE - 0 - - - C_OVERFLOW_LOW - 0 - - - C_PRELOAD_LATENCY - 2 - - - C_PRELOAD_REGS - 1 - - - C_PRIM_FIFO_TYPE - 1kx18 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL - 2 - - - C_PROG_EMPTY_THRESH_NEGATE_VAL - 3 - - - C_PROG_EMPTY_TYPE - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL - 1021 - - - C_PROG_FULL_THRESH_NEGATE_VAL - 1020 - - - C_PROG_FULL_TYPE - 0 - - - C_RD_DATA_COUNT_WIDTH - 9 - - - C_RD_DEPTH - 512 - - - C_RD_FREQ - 1 - - - C_RD_PNTR_WIDTH - 9 - - - C_UNDERFLOW_LOW - 0 - - - C_USE_DOUT_RST - 1 - - - C_USE_ECC - 0 - - - C_USE_EMBEDDED_REG - 1 - - - C_USE_PIPELINE_REG - 0 - - - C_POWER_SAVING_MODE - 0 - - - C_USE_FIFO16_FLAGS - 0 - - - C_USE_FWFT_DATA_COUNT - 0 - - - C_VALID_LOW - 0 - - - C_WR_ACK_LOW - 0 - - - C_WR_DATA_COUNT_WIDTH - 10 - - - C_WR_DEPTH - 1024 - - - C_WR_FREQ - 1 - - - C_WR_PNTR_WIDTH - 10 - - - C_WR_RESPONSE_LATENCY - 1 - - - C_MSGON_VAL - 1 - - - C_ENABLE_RST_SYNC - 1 - - - C_EN_SAFETY_CKT - 0 - - - C_ERROR_INJECTION_TYPE - 0 - - - C_SYNCHRONIZER_STAGE - 2 - - - C_INTERFACE_TYPE - 0 - - - C_AXI_TYPE - 1 - - - C_HAS_AXI_WR_CHANNEL - 1 - - - C_HAS_AXI_RD_CHANNEL - 1 - - - C_HAS_SLAVE_CE - 0 - - - C_HAS_MASTER_CE - 0 - - - C_ADD_NGC_CONSTRAINT - 0 - - - C_USE_COMMON_OVERFLOW - 0 - - - C_USE_COMMON_UNDERFLOW - 0 - - - C_USE_DEFAULT_SETTINGS - 0 - - - C_AXI_ID_WIDTH - 1 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_DATA_WIDTH - 64 - - - C_AXI_LEN_WIDTH - 8 - - - C_AXI_LOCK_WIDTH - 1 - - - C_HAS_AXI_ID - 0 - - - C_HAS_AXI_AWUSER - 0 - - - C_HAS_AXI_WUSER - 0 - - - C_HAS_AXI_BUSER - 0 - - - C_HAS_AXI_ARUSER - 0 - - - C_HAS_AXI_RUSER - 0 - - - C_AXI_ARUSER_WIDTH - 1 - - - C_AXI_AWUSER_WIDTH - 1 - - - C_AXI_WUSER_WIDTH - 1 - - - C_AXI_BUSER_WIDTH - 1 - - - C_AXI_RUSER_WIDTH - 1 - - - C_HAS_AXIS_TDATA - 1 - - - C_HAS_AXIS_TID - 0 - - - C_HAS_AXIS_TDEST - 0 - - - C_HAS_AXIS_TUSER - 1 - - - C_HAS_AXIS_TREADY - 1 - - - C_HAS_AXIS_TLAST - 0 - - - C_HAS_AXIS_TSTRB - 0 - - - C_HAS_AXIS_TKEEP - 0 - - - C_AXIS_TDATA_WIDTH - 8 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 4 - - - C_AXIS_TSTRB_WIDTH - 1 - - - C_AXIS_TKEEP_WIDTH - 1 - - - C_WACH_TYPE - 0 - - - C_WDCH_TYPE - 0 - - - C_WRCH_TYPE - 0 - - - C_RACH_TYPE - 0 - - - C_RDCH_TYPE - 0 - - - C_AXIS_TYPE - 0 - - - C_IMPLEMENTATION_TYPE_WACH - 1 - - - C_IMPLEMENTATION_TYPE_WDCH - 1 - - - C_IMPLEMENTATION_TYPE_WRCH - 1 - - - C_IMPLEMENTATION_TYPE_RACH - 1 - - - C_IMPLEMENTATION_TYPE_RDCH - 1 - - - C_IMPLEMENTATION_TYPE_AXIS - 1 - - - C_APPLICATION_TYPE_WACH - 0 - - - C_APPLICATION_TYPE_WDCH - 0 - - - C_APPLICATION_TYPE_WRCH - 0 - - - C_APPLICATION_TYPE_RACH - 0 - - - C_APPLICATION_TYPE_RDCH - 0 - - - C_APPLICATION_TYPE_AXIS - 0 - - - C_PRIM_FIFO_TYPE_WACH - 512x36 - - - C_PRIM_FIFO_TYPE_WDCH - 512x72 - - - C_PRIM_FIFO_TYPE_WRCH - 512x36 - - - C_PRIM_FIFO_TYPE_RACH - 512x36 - - - C_PRIM_FIFO_TYPE_RDCH - 512x72 - - - C_PRIM_FIFO_TYPE_AXIS - 1kx18 - - - C_USE_ECC_WACH - 0 - - - C_USE_ECC_WDCH - 0 - - - C_USE_ECC_WRCH - 0 - - - C_USE_ECC_RACH - 0 - - - C_USE_ECC_RDCH - 0 - - - C_USE_ECC_AXIS - 0 - - - C_ERROR_INJECTION_TYPE_WACH - 0 - - - C_ERROR_INJECTION_TYPE_WDCH - 0 - - - C_ERROR_INJECTION_TYPE_WRCH - 0 - - - C_ERROR_INJECTION_TYPE_RACH - 0 - - - C_ERROR_INJECTION_TYPE_RDCH - 0 - - - C_ERROR_INJECTION_TYPE_AXIS - 0 - - - C_DIN_WIDTH_WACH - 1 - - - C_DIN_WIDTH_WDCH - 64 - - - C_DIN_WIDTH_WRCH - 2 - - - C_DIN_WIDTH_RACH - 32 - - - C_DIN_WIDTH_RDCH - 64 - - - C_DIN_WIDTH_AXIS - 1 - - - C_WR_DEPTH_WACH - 16 - - - C_WR_DEPTH_WDCH - 1024 - - - C_WR_DEPTH_WRCH - 16 - - - C_WR_DEPTH_RACH - 16 - - - C_WR_DEPTH_RDCH - 1024 - - - C_WR_DEPTH_AXIS - 1024 - - - C_WR_PNTR_WIDTH_WACH - 4 - - - C_WR_PNTR_WIDTH_WDCH - 10 - - - C_WR_PNTR_WIDTH_WRCH - 4 - - - C_WR_PNTR_WIDTH_RACH - 4 - - - C_WR_PNTR_WIDTH_RDCH - 10 - - - C_WR_PNTR_WIDTH_AXIS - 10 - - - C_HAS_DATA_COUNTS_WACH - 0 - - - C_HAS_DATA_COUNTS_WDCH - 0 - - - C_HAS_DATA_COUNTS_WRCH - 0 - - - C_HAS_DATA_COUNTS_RACH - 0 - - - C_HAS_DATA_COUNTS_RDCH - 0 - - - C_HAS_DATA_COUNTS_AXIS - 0 - - - C_HAS_PROG_FLAGS_WACH - 0 - - - C_HAS_PROG_FLAGS_WDCH - 0 - - - C_HAS_PROG_FLAGS_WRCH - 0 - - - C_HAS_PROG_FLAGS_RACH - 0 - - - C_HAS_PROG_FLAGS_RDCH - 0 - - - C_HAS_PROG_FLAGS_AXIS - 0 - - - C_PROG_FULL_TYPE_WACH - 0 - - - C_PROG_FULL_TYPE_WDCH - 0 - - - C_PROG_FULL_TYPE_WRCH - 0 - - - C_PROG_FULL_TYPE_RACH - 0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_165ed04b - 64 - - - choice_list_26900833 - 9 - 18 - 36 - 72 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_26bda4ef - Asynchronous_Reset - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_1024x9x18_oreg_wcnt_xcku - - - - true - - - - - - Fifo_Implementation - Independent_Clocks_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - true - - - - true - - - - - - Input_Data_Width - 9 - - - - true - - - - - - Input_Depth - 1024 - - - - true - - - - - - Output_Data_Width - 18 - - - - true - - - - - - Output_Depth - 512 - - - - false - - - - - - Enable_ECC - false - - - - false - - - - - - Use_Embedded_Registers - true - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - true - - - - - - Reset_Type - Asynchronous_Reset - - - - false - - - - - - Full_Flags_Reset_Value - 1 - - - - true - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - true - - - - true - - - - - - Almost_Empty_Flag - true - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - false - - - - false - - - - - - Data_Count_Width - 10 - - - - false - - - - - - Write_Data_Count - true - - - - true - - - - - - Write_Data_Count_Width - 10 - - - - true - - - - - - Read_Data_Count - false - - - - true - - - - - - Read_Data_Count_Width - 9 - - - - false - - - - - - Disable_Timing_Violations - false - - - - true - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - No_Programmable_Full_Threshold - - - - true - - - - - - Full_Threshold_Assert_Value - 1021 - - - - false - - - - - - Full_Threshold_Negate_Value - 1020 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wach - false - - - - false - - - - - - Inject_Sbit_Error_wach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wach - false - - - - false - - - - - - Input_Depth_wach - 16 - - - - true - - - - - - Enable_Data_Counts_wach - false - - - - false - - - - - - Programmable_Full_Type_wach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wdch - false - - - - false - - - - - - Inject_Sbit_Error_wdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wdch - false - - - - false - - - - - - Input_Depth_wdch - 1024 - - - - true - - - - - - Enable_Data_Counts_wdch - false - - - - false - - - - - - Programmable_Full_Type_wdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wrch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wrch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wrch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wrch - false - - - - false - - - - - - Inject_Sbit_Error_wrch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wrch - false - - - - false - - - - - - Input_Depth_wrch - 16 - - - - true - - - - - - Enable_Data_Counts_wrch - false - - - - false - - - - - - Programmable_Full_Type_wrch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wrch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wrch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wrch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rach - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rach - false - - - - false - - - - - - Inject_Sbit_Error_rach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rach - false - - - - false - - - - - - Input_Depth_rach - 16 - - - - true - - - - - - Enable_Data_Counts_rach - false - - - - false - - - - - - Programmable_Full_Type_rach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rdch - false - - - - false - - - - - - Inject_Sbit_Error_rdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rdch - false - - - - false - - - - - - Input_Depth_rdch - 1024 - - - - true - - - - - - Enable_Data_Counts_rdch - false - - - - false - - - - - - Programmable_Full_Type_rdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - axis_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_axis - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_axis - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_axis - false - - - - false - - - - - - Inject_Sbit_Error_axis - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_axis - Double Bit Error Injection - false - - - - false - - - - - - Input_Depth_axis - 1024 - - - - true - - - - - - Enable_Data_Counts_axis - false - - - - false - - - - - - Programmable_Full_Type_axis - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_axis - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_axis - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_axis - Empty Threshold Assert Value - 1022 - - - - false - - - - - - Register_Slice_Mode_wach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wrch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_axis - Register Slice Options - Fully_Registered - - - - true - - - - - - Underflow_Flag_AXI - Underflow Flag - false - - - - false - - - - - - Underflow_Sense_AXI - Underflow (Read Error) - Active_High - - - - false - - - - - - Overflow_Flag_AXI - Overflow Flag - false - - - - false - - - - - - Overflow_Sense_AXI - Overflow (Write Error) - Active_High - - - - false - - - - - - Disable_Timing_Violations_AXI - false - - - - true - - - - - - Add_NGC_Constraint_AXI - false - - - - true - - - - - - Enable_Common_Underflow - false - - - - true - - - - - - Enable_Common_Overflow - false - - - - true - - - - - - enable_read_pointer_increment_by2 - false - - - - true - - - - - - Use_Embedded_Registers_axis - false - - - - false - - - - - - enable_low_latency - false - - - - false - - - - - - use_dout_register - false - - - - false - - - - - - Master_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Slave_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - true - - - - - - Enable_Safety_Circuit - false - - - - true - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/xilinx/xcku/fifo_16x18x9_oreg.vhd b/xilinx/xcku/fifo_16x18x9_oreg.vhd deleted file mode 100644 index 8feddd6..0000000 --- a/xilinx/xcku/fifo_16x18x9_oreg.vhd +++ /dev/null @@ -1,51 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity fifo_16x18x9_oreg is - port ( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic - ); -end entity fifo_16x18x9_oreg; - -architecture structural of fifo_16x18x9_oreg is - component fifo_16x18x9_oreg_xcku - port ( - rst : in std_logic; - wr_clk : in std_logic; - rd_clk : in std_logic; - din : in std_logic_vector(17 downto 0); - wr_en : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(8 downto 0); - full : out std_logic; - almost_full : out std_logic; - empty : out std_logic; - almost_empty : out std_logic - ); - end component; -begin - fifo : fifo_16x18x9_oreg_xcku - port map ( - rst => Reset, - wr_clk => WrClock, - rd_clk => RdClock, - din => Data, - wr_en => WrEn, - rd_en => RdEn, - dout => Q, - full => Full, - almost_full => AlmostFull, - empty => Empty, - almost_empty => AlmostEmpty - ); -end architecture structural; diff --git a/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xci b/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xci deleted file mode 100644 index f2f10c9..0000000 --- a/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xci +++ /dev/null @@ -1,571 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fifo_16x18x9_oreg_xcku - - - - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - - - 100000000 - 0 - 0.000 - - 100000000 - 0 - 0.000 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - - - 100000000 - 0 - 0.000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 1 - 1 - 1 - 1 - 4 - 0 - 32 - 1 - 1 - 1 - 64 - 1 - 8 - 1 - 1 - 1 - 1 - 0 - 0 - 4 - BlankString - 18 - 1 - 32 - 64 - 1 - 64 - 2 - 0 - 9 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - kintexu - 1 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - BlankString - 1 - 0 - 0 - 0 - 2 - 1 - 512x36 - 1kx18 - 512x36 - 512x72 - 512x36 - 512x72 - 512x36 - 2 - 1022 - 1022 - 1022 - 1022 - 1022 - 1022 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 13 - 1023 - 1023 - 1023 - 1023 - 1023 - 1023 - 12 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 5 - 32 - 1 - 5 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 4 - 16 - 1024 - 16 - 1024 - 16 - 1024 - 16 - 1 - 4 - 10 - 4 - 10 - 4 - 10 - 4 - 1 - 32 - 0 - 0 - false - true - true - 0 - 0 - Slave_Interface_Clock_Enable - Common_Clock - fifo_16x18x9_oreg_xcku - 64 - false - 4 - false - false - 0 - 2 - 1022 - 1022 - 1022 - 1022 - 1022 - 1022 - 3 - false - false - false - false - false - false - false - false - false - Hard_ECC - false - false - false - false - false - false - true - false - false - true - Data_FIFO - Data_FIFO - Data_FIFO - Data_FIFO - Data_FIFO - Data_FIFO - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Independent_Clocks_Block_RAM - 1 - 13 - 1023 - 1023 - 1023 - 1023 - 1023 - 1023 - 12 - false - false - false - 0 - Native - false - false - false - false - false - false - false - false - false - false - false - false - false - false - 18 - 16 - 1024 - 16 - 1024 - 16 - 1024 - 16 - false - 9 - 32 - Embedded_Reg - false - false - Active_High - Active_High - AXI4 - Standard_FIFO - No_Programmable_Empty_Threshold - No_Programmable_Empty_Threshold - No_Programmable_Empty_Threshold - No_Programmable_Empty_Threshold - No_Programmable_Empty_Threshold - No_Programmable_Empty_Threshold - No_Programmable_Empty_Threshold - No_Programmable_Full_Threshold - No_Programmable_Full_Threshold - No_Programmable_Full_Threshold - No_Programmable_Full_Threshold - No_Programmable_Full_Threshold - No_Programmable_Full_Threshold - No_Programmable_Full_Threshold - READ_WRITE - 0 - 1 - false - 5 - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - true - Asynchronous_Reset - false - 1 - 0 - 0 - 1 - 1 - 4 - false - false - Active_High - Active_High - true - true - false - false - false - Active_High - 0 - false - Active_High - 1 - false - 4 - true - FIFO - false - false - false - false - FIFO - FIFO - 2 - 2 - false - FIFO - FIFO - FIFO - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xml b/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xml deleted file mode 100644 index 18d23e6..0000000 --- a/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xml +++ /dev/null @@ -1,10745 +0,0 @@ - - - xilinx.com - customized_ip - fifo_16x18x9_oreg_xcku - 1.0 - - - M_AXIS - - - - - - - TDATA - - - m_axis_tdata - - - - - TDEST - - - m_axis_tdest - - - - - TID - - - m_axis_tid - - - - - TKEEP - - - m_axis_tkeep - - - - - TLAST - - - m_axis_tlast - - - - - TREADY - - - m_axis_tready - - - - - TSTRB - - - m_axis_tstrb - - - - - TUSER - - - m_axis_tuser - - - - - TVALID - - - m_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXIS - - - - - - - TDATA - - - s_axis_tdata - - - - - TDEST - - - s_axis_tdest - - - - - TID - - - s_axis_tid - - - - - TKEEP - - - s_axis_tkeep - - - - - TLAST - - - s_axis_tlast - - - - - TREADY - - - s_axis_tready - - - - - TSTRB - - - s_axis_tstrb - - - - - TUSER - - - s_axis_tuser - - - - - TVALID - - - s_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXI - - - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - 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1 - - - C_IMPLEMENTATION_TYPE_WRCH - 1 - - - C_IMPLEMENTATION_TYPE_RACH - 1 - - - C_IMPLEMENTATION_TYPE_RDCH - 1 - - - C_IMPLEMENTATION_TYPE_AXIS - 1 - - - C_APPLICATION_TYPE_WACH - 0 - - - C_APPLICATION_TYPE_WDCH - 0 - - - C_APPLICATION_TYPE_WRCH - 0 - - - C_APPLICATION_TYPE_RACH - 0 - - - C_APPLICATION_TYPE_RDCH - 0 - - - C_APPLICATION_TYPE_AXIS - 0 - - - C_PRIM_FIFO_TYPE_WACH - 512x36 - - - C_PRIM_FIFO_TYPE_WDCH - 512x72 - - - C_PRIM_FIFO_TYPE_WRCH - 512x36 - - - C_PRIM_FIFO_TYPE_RACH - 512x36 - - - C_PRIM_FIFO_TYPE_RDCH - 512x72 - - - C_PRIM_FIFO_TYPE_AXIS - 1kx18 - - - C_USE_ECC_WACH - 0 - - - C_USE_ECC_WDCH - 0 - - - C_USE_ECC_WRCH - 0 - - - C_USE_ECC_RACH - 0 - - - C_USE_ECC_RDCH - 0 - - - C_USE_ECC_AXIS - 0 - - - C_ERROR_INJECTION_TYPE_WACH - 0 - - - C_ERROR_INJECTION_TYPE_WDCH - 0 - - - C_ERROR_INJECTION_TYPE_WRCH - 0 - - - C_ERROR_INJECTION_TYPE_RACH - 0 - - - C_ERROR_INJECTION_TYPE_RDCH - 0 - - - C_ERROR_INJECTION_TYPE_AXIS - 0 - - - C_DIN_WIDTH_WACH - 1 - - - C_DIN_WIDTH_WDCH - 64 - - - C_DIN_WIDTH_WRCH - 2 - - - C_DIN_WIDTH_RACH - 32 - - - C_DIN_WIDTH_RDCH - 64 - - - C_DIN_WIDTH_AXIS - 1 - - - C_WR_DEPTH_WACH - 16 - - - C_WR_DEPTH_WDCH - 1024 - - - C_WR_DEPTH_WRCH - 16 - - - C_WR_DEPTH_RACH - 16 - - - C_WR_DEPTH_RDCH - 1024 - - - C_WR_DEPTH_AXIS - 1024 - - - C_WR_PNTR_WIDTH_WACH - 4 - - - C_WR_PNTR_WIDTH_WDCH - 10 - - - C_WR_PNTR_WIDTH_WRCH - 4 - - - C_WR_PNTR_WIDTH_RACH - 4 - - - C_WR_PNTR_WIDTH_RDCH - 10 - - - C_WR_PNTR_WIDTH_AXIS - 10 - - - C_HAS_DATA_COUNTS_WACH - 0 - - - C_HAS_DATA_COUNTS_WDCH - 0 - - - C_HAS_DATA_COUNTS_WRCH - 0 - - - C_HAS_DATA_COUNTS_RACH - 0 - - - C_HAS_DATA_COUNTS_RDCH - 0 - - - C_HAS_DATA_COUNTS_AXIS - 0 - - - C_HAS_PROG_FLAGS_WACH - 0 - - - C_HAS_PROG_FLAGS_WDCH - 0 - - - C_HAS_PROG_FLAGS_WRCH - 0 - - - C_HAS_PROG_FLAGS_RACH - 0 - - - C_HAS_PROG_FLAGS_RDCH - 0 - - - C_HAS_PROG_FLAGS_AXIS - 0 - - - C_PROG_FULL_TYPE_WACH - 0 - - - C_PROG_FULL_TYPE_WDCH - 0 - - - C_PROG_FULL_TYPE_WRCH - 0 - - - C_PROG_FULL_TYPE_RACH - 0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_165ed04b - 64 - - - choice_list_537e964c - 9 - 18 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_26bda4ef - Asynchronous_Reset - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_16x18x9_oreg_xcku - - - - true - - - - - - Fifo_Implementation - Independent_Clocks_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - true - - - - true - - - - - - Input_Data_Width - 18 - - - - true - - - - - - Input_Depth - 16 - - - - true - - - - - - Output_Data_Width - 9 - - - - true - - - - - - Output_Depth - 32 - - - - false - - - - - - Enable_ECC - false - - - - false - - - - - - Use_Embedded_Registers - true - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - true - - - - - - Reset_Type - Asynchronous_Reset - - - - false - - - - - - Full_Flags_Reset_Value - 1 - - - - true - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - true - - - - true - - - - - - Almost_Empty_Flag - true - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - false - - - - false - - - - - - Data_Count_Width - 4 - - - - false - - - - - - Write_Data_Count - false - - - - true - - - - - - Write_Data_Count_Width - 4 - - - - false - - - - - - Read_Data_Count - false - - - - true - - - - - - Read_Data_Count_Width - 5 - - - - false - - - - - - Disable_Timing_Violations - false - - - - true - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - No_Programmable_Full_Threshold - - - - true - - - - - - Full_Threshold_Assert_Value - 13 - - - - false - - - - - - Full_Threshold_Negate_Value - 12 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wach - false - - - - false - - - - - - Inject_Sbit_Error_wach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wach - false - - - - false - - - - - - Input_Depth_wach - 16 - - - - true - - - - - - Enable_Data_Counts_wach - false - - - - false - - - - - - Programmable_Full_Type_wach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wdch - false - - - - false - - - - - - Inject_Sbit_Error_wdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wdch - false - - - - false - - - - - - Input_Depth_wdch - 1024 - - - - true - - - - - - Enable_Data_Counts_wdch - false - - - - false - - - - - - Programmable_Full_Type_wdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wrch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wrch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wrch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wrch - false - - - - false - - - - - - Inject_Sbit_Error_wrch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wrch - false - - - - false - - - - - - Input_Depth_wrch - 16 - - - - true - - - - - - Enable_Data_Counts_wrch - false - - - - false - - - - - - Programmable_Full_Type_wrch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wrch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wrch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wrch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rach - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rach - false - - - - false - - - - - - Inject_Sbit_Error_rach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rach - false - - - - false - - - - - - Input_Depth_rach - 16 - - - - true - - - - - - Enable_Data_Counts_rach - false - - - - false - - - - - - Programmable_Full_Type_rach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rdch - false - - - - false - - - - - - Inject_Sbit_Error_rdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rdch - false - - - - false - - - - - - Input_Depth_rdch - 1024 - - - - true - - - - - - Enable_Data_Counts_rdch - false - - - - false - - - - - - Programmable_Full_Type_rdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - axis_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_axis - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_axis - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_axis - false - - - - false - - - - - - Inject_Sbit_Error_axis - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_axis - Double Bit Error Injection - false - - - - false - - - - - - Input_Depth_axis - 1024 - - - - true - - - - - - Enable_Data_Counts_axis - false - - - - false - - - - - - Programmable_Full_Type_axis - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_axis - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_axis - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_axis - Empty Threshold Assert Value - 1022 - - - - false - - - - - - Register_Slice_Mode_wach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wrch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_axis - Register Slice Options - Fully_Registered - - - - true - - - - - - Underflow_Flag_AXI - Underflow Flag - false - - - - false - - - - - - Underflow_Sense_AXI - Underflow (Read Error) - Active_High - - - - false - - - - - - Overflow_Flag_AXI - Overflow Flag - false - - - - false - - - - - - Overflow_Sense_AXI - Overflow (Write Error) - Active_High - - - - false - - - - - - Disable_Timing_Violations_AXI - false - - - - true - - - - - - Add_NGC_Constraint_AXI - false - - - - true - - - - - - Enable_Common_Underflow - false - - - - true - - - - - - Enable_Common_Overflow - false - - - - true - - - - - - enable_read_pointer_increment_by2 - false - - - - true - - - - - - Use_Embedded_Registers_axis - false - - - - false - - - - - - enable_low_latency - false - - - - false - - - - - - use_dout_register - false - - - - false - - - - - - Master_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Slave_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - true - - - - - - Enable_Safety_Circuit - false - - - - true - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/xilinx/xcku/fifo_18x512_oreg.vhd b/xilinx/xcku/fifo_18x512_oreg.vhd index 18a841c..3b4f44e 100644 --- a/xilinx/xcku/fifo_18x512_oreg.vhd +++ b/xilinx/xcku/fifo_18x512_oreg.vhd @@ -35,6 +35,8 @@ architecture structural of fifo_18x512_oreg is rd_rst_busy : out std_logic ); end component; + + signal full_i : std_logic; begin fifo : fifo_18x512_oreg_xcku port map ( @@ -45,7 +47,7 @@ begin rd_en => RdEn, prog_full_thresh => AmFullThresh, dout => Q, - full => Full, + full => full_i, empty => Empty, data_count => WCNT(8 downto 0), prog_full => AlmostFull, @@ -53,6 +55,6 @@ begin rd_rst_busy => open ); - -- TODO: Check impact of different count values - WCNT(9) <= '0'; + WCNT(9) <= full_i; + Full <= full_i; end architecture structural; diff --git a/xilinx/xcku/fifo_19x16.vhd b/xilinx/xcku/fifo_19x16.vhd index 030c808..8c85f44 100644 --- a/xilinx/xcku/fifo_19x16.vhd +++ b/xilinx/xcku/fifo_19x16.vhd @@ -33,6 +33,8 @@ architecture structural of fifo_19x16 is rd_rst_busy : out std_logic ); end component; + + signal full_i : std_logic; begin fifo : fifo_19x16_xcku port map ( @@ -42,7 +44,7 @@ begin wr_en => WrEn, rd_en => RdEn, dout => Q, - full => Full, + full => full_i, empty => Empty, data_count => WCNT(3 downto 0), prog_full => AlmostFull, @@ -50,6 +52,6 @@ begin rd_rst_busy => open ); - -- TODO: Check impact of different count values - WCNT(4) <= '0'; + WCNT(4) <= full_i; + Full <= full_i; end architecture structural; diff --git a/xilinx/xcku/fifo_19x16_obuf.vhd b/xilinx/xcku/fifo_19x16_obuf.vhd index 77914a0..6a8ce37 100644 --- a/xilinx/xcku/fifo_19x16_obuf.vhd +++ b/xilinx/xcku/fifo_19x16_obuf.vhd @@ -35,6 +35,8 @@ architecture structural of fifo_19x16_obuf is rd_rst_busy : out std_logic ); end component; + + signal full_i : std_logic; begin fifo : fifo_19x16_obuf_xcku port map ( @@ -45,7 +47,7 @@ begin rd_en => RdEn, prog_full_thresh => AmFullThresh, dout => Q, - full => Full, + full => full_i, empty => Empty, data_count => WCNT(3 downto 0), prog_full => AlmostFull, @@ -53,6 +55,6 @@ begin rd_rst_busy => open ); - -- TODO: Check impact of different count values - WCNT(4) <= '0'; + WCNT(4) <= full_i; + Full <= full_i; end architecture structural; diff --git a/xilinx/xcku/fifo_36x512_oreg.vhd b/xilinx/xcku/fifo_36x512_oreg.vhd index 622b7d9..bcfe5a1 100644 --- a/xilinx/xcku/fifo_36x512_oreg.vhd +++ b/xilinx/xcku/fifo_36x512_oreg.vhd @@ -35,6 +35,8 @@ architecture structural of fifo_36x512_oreg is rd_rst_busy : out std_logic ); end component; + + signal full_i : std_logic; begin fifo : fifo_36x512_oreg_xcku port map ( @@ -45,7 +47,7 @@ begin rd_en => RdEn, prog_full_thresh => AmFullThresh, dout => Q, - full => Full, + full => full_i, empty => Empty, data_count => WCNT(8 downto 0), prog_full => AlmostFull, @@ -53,6 +55,6 @@ begin rd_rst_busy => open ); - -- TODO: Check impact of different count values - WCNT(9) <= '0'; + WCNT(9) <= full_i; + Full <= full_i; end architecture structural; diff --git a/xilinx/xcku/fifo_36x8k_oreg.vhd b/xilinx/xcku/fifo_36x8k_oreg.vhd index 1cefabf..5f25aa1 100644 --- a/xilinx/xcku/fifo_36x8k_oreg.vhd +++ b/xilinx/xcku/fifo_36x8k_oreg.vhd @@ -35,6 +35,8 @@ architecture structural of fifo_36x8k_oreg is rd_rst_busy : out std_logic ); end component; + + signal full_i : std_logic; begin fifo : fifo_36x8k_oreg_xcku port map ( @@ -45,7 +47,7 @@ begin rd_en => RdEn, prog_full_thresh => AmFullThresh, dout => Q, - full => Full, + full => full_i, empty => Empty, data_count => WCNT(12 downto 0), prog_full => AlmostFull, @@ -53,6 +55,6 @@ begin rd_rst_busy => open ); - -- TODO: Check impact of different count values - WCNT(13) <= '0'; + WCNT(13) <= full_i; + Full <= full_i; end architecture structural;