From: Jan Michel Date: Thu, 14 Jun 2018 14:52:17 +0000 (+0200) Subject: some clean-up to signals X-Git-Tag: v2.3~14 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f9f9cb24f8f585e4727a2954574b0d91b82f9dee;p=tdc.git some clean-up to signals --- diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd index e502607..6d4662d 100644 --- a/releases/tdc_v2.3/Channel_200.vhd +++ b/releases/tdc_v2.3/Channel_200.vhd @@ -157,14 +157,6 @@ architecture Channel_200 of Channel_200 is signal trg_win_end_rdo_flag : std_logic := '0'; signal fsm_rd_debug : std_logic_vector(3 downto 0); - ----------------------------------------------------------------------------- - -- debug - signal data_cnt_total : integer range 0 to 2147483647 := 0; - signal data_cnt_event : integer range 0 to 255 := 0; - signal epoch_cnt_total : integer range 0 to 65535 := 0; - signal epoch_cnt_event : integer range 0 to 127 := 0; - ----------------------------------------------------------------------------- - attribute syn_keep : boolean; attribute syn_keep of ff_array_en : signal is true; attribute syn_keep of FSM_RD_STATE : signal is true; @@ -869,10 +861,15 @@ begin -- Channel_200 --CHANNEL_200_DEBUG_OUT(23 downto 19) <= (others => '0'); -- CHANNEL_200_DEBUG_OUT(0) <= ff_array_en; CHANNEL_200_DEBUG_OUT(23 downto 0) <= (others => '0'); - CHANNEL_200_DEBUG_OUT(27 downto 24) <= fsm_rd_debug; - CHANNEL_200_DEBUG_OUT(31 downto 28) <= fsm_wr_debug; + CHANNEL_200_DEBUG_OUT(27 downto 24) <= fsm_rd_debug when rising_edge(CLK_100); + CHANNEL_200_DEBUG_OUT(31 downto 28) <= fsm_wr_debug when rising_edge(CLK_100); gen_SIMULATION : if SIMULATION = c_YES generate + signal data_cnt_total : integer range 0 to 2147483647 := 0; + signal data_cnt_event : integer range 0 to 255 := 0; + signal epoch_cnt_total : integer range 0 to 65535 := 0; + signal epoch_cnt_event : integer range 0 to 127 := 0; + begin -- count data written data_cntr : process begin diff --git a/releases/tdc_v2.3/Encoder_288_Bit.vhd b/releases/tdc_v2.3/Encoder_288_Bit.vhd index 5686b74..45cb2d9 100644 --- a/releases/tdc_v2.3/Encoder_288_Bit.vhd +++ b/releases/tdc_v2.3/Encoder_288_Bit.vhd @@ -38,8 +38,8 @@ entity Encoder_288_Bit is DECIMAL_CODE_OUT : out std_logic_vector(9 downto 0); ENCODER_INFO_OUT : out std_logic; ENCODER_DEBUG : out std_logic_vector(31 downto 0); - CHAIN_VALID_OUT : out std_logic; - CHAIN_DATA_OUT : out std_logic_vector(15 downto 0) + CHAIN_VALID_OUT : out std_logic := '0'; + CHAIN_DATA_OUT : out std_logic_vector(15 downto 0) := (others => '0') ); end Encoder_288_Bit; diff --git a/releases/tdc_v2.3/Readout_record.vhd b/releases/tdc_v2.3/Readout_record.vhd index 9e84741..a82f1ab 100644 --- a/releases/tdc_v2.3/Readout_record.vhd +++ b/releases/tdc_v2.3/Readout_record.vhd @@ -79,13 +79,13 @@ architecture behavioral of Readout_record is signal start_trg_win_cnt : std_logic := '0'; signal start_trg_win_cnt_200_p : std_logic; signal trg_win_cnt : std_logic_vector(11 downto 0); - signal trg_win_end_200 : std_logic := '0'; - signal trg_win_end_200_p : std_logic; - signal trg_win_end_100_p : std_logic; - signal trg_win_end_100_r : std_logic; - signal trg_win_end_100_2r : std_logic; - signal trg_win_end_100_3r : std_logic; - signal trg_win_end_100_4r : std_logic; +-- signal trg_win_end_200 : std_logic := '0'; +-- signal trg_win_end_200_p : std_logic; +-- signal trg_win_end_100_p : std_logic; +-- signal trg_win_end_100_r : std_logic; +-- signal trg_win_end_100_2r : std_logic; +-- signal trg_win_end_100_3r : std_logic; +-- signal trg_win_end_100_4r : std_logic; -- channel signals signal ch_data_r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); signal ch_data_2r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); @@ -122,8 +122,8 @@ architecture behavioral of Readout_record is signal invalid_trg : std_logic; signal unknown_trg_fsm : std_logic; signal unknown_trg : std_logic; - signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER := 0; - signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER-1 := 0; + signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER-1 := 0; signal buf_delay_fsm : integer range 0 to 63 := 0; signal buf_delay : integer range 0 to 63 := 0; signal idle_fsm : std_logic; diff --git a/releases/tdc_v2.3/tdc_components.vhd b/releases/tdc_v2.3/tdc_components.vhd index fcad7f3..d637ed9 100644 --- a/releases/tdc_v2.3/tdc_components.vhd +++ b/releases/tdc_v2.3/tdc_components.vhd @@ -34,7 +34,7 @@ package tdc_components is BUSRDO_RX : in READOUT_RX; BUSRDO_TX : out READOUT_TX; BUS_RX : in CTRLBUS_RX; - BUS_TX : in CTRLBUS_TX; + BUS_TX : out CTRLBUS_TX; INFO_IN : in TIMERS; LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0)); end component TDC_record; diff --git a/releases/tdc_v2.3/unimportant_lines_constraints.lpf b/releases/tdc_v2.3/unimportant_lines_constraints.lpf index 3e7f185..bd14631 100644 --- a/releases/tdc_v2.3/unimportant_lines_constraints.lpf +++ b/releases/tdc_v2.3/unimportant_lines_constraints.lpf @@ -49,11 +49,11 @@ MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/*US_TX.data*" 20 ns; MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x; MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CELL "THE_TDC/*Channe*/Channel200/RingBuffer*FIFO/*" 5x; +MULTICYCLE TO CELL "THE_CLOCK_RESET/send_reset_detect" 20 ns; MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x; MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x; - MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ;