From: Cahit Date: Fri, 17 Apr 2015 09:34:19 +0000 (+0200) Subject: added FIFOs for ecp3 X-Git-Tag: v2.3~85 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f9fb953e9478c8918696249f34ff870770f22cbb;p=tdc.git added FIFOs for ecp3 --- diff --git a/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.edn b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.edn new file mode 100644 index 0000000..f9912f1 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.edn @@ -0,0 +1,1433 @@ +(edif FIFO_36x32_OutReg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 4 17 11 33 22) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 36 -depth 32 -regout -no_enable -pe -1 -pf -1 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell 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+++ b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.jhd b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.jhd new file mode 100644 index 0000000..e69de29 diff --git a/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.lpc b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.lpc new file mode 100644 index 0000000..ae2380c --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=FIFO_36x32_OutReg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/17/2015 +Time=11:33:22 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf -1 diff --git a/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.sort b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.sort new file mode 100644 index 0000000..2c83725 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.sort @@ -0,0 +1 @@ +FIFO_36x32_OutReg.vhd diff --git a/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.srp b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.srp new file mode 100644 index 0000000..7ae80e7 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.srp @@ -0,0 +1,42 @@ +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:33:22 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf -1 + Circuit name : FIFO_36x32_OutReg + Module type : fifoblk + Module Version : 5.0 + Ports : + Inputs : Data[35:0], Clock, WrEn, RdEn, Reset + Outputs : Q[35:0], Empty, Full + I/O buffer : not inserted + EDIF output : FIFO_36x32_OutReg.edn + VHDL output : FIFO_36x32_OutReg.vhd + VHDL template : FIFO_36x32_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_36x32_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_36x32_OutReg.srp + Element Usage : + AGEB2 : 3 + ALEB2 : 3 + AND2 : 3 + CU2 : 6 + CB2 : 3 + FADD2B : 7 + FD1P3DX : 18 + FD1S3BX : 1 + FD1S3DX : 1 + INV : 4 + ROM16X1A : 2 + XOR2 : 1 + PDPW16KC : 1 + Estimated Resource Usage: + LUT : 50 + EBR : 1 + Reg : 20 diff --git a/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd new file mode 100644 index 0000000..91fb52e --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd @@ -0,0 +1,519 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.0 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 36 -depth 32 -regout -no_enable -pe -1 -pf -1 + +-- Fri Apr 17 11:33:22 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_36x32_OutReg is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic); +end FIFO_36x32_OutReg; + +architecture Structure of FIFO_36x32_OutReg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co2: std_logic; + signal cnt_con: std_logic; + signal co1: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co2_1: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co2_2: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x32_OutReg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), + ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2, + ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>scuba_vlo, + ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1, + ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4, + ADR10=>scuba_vlo, ADR11=>scuba_vlo, ADR12=>scuba_vlo, + ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i, + CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), + DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), + DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), + DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), + DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), + DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), + DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), + DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), + DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); + + FF_19: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_18: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_17: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_16: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_15: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_14: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_13: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_12: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_11: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_10: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_9: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_8: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_7: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_6: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_5: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_4: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_3: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_2: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_1: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_0: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i_inv, + CI=>co1_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_1, + NC0=>iwcount_4, NC1=>iwcount_5); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_2, + NC0=>ircount_4, NC1=>ircount_5); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_36x32_OutReg is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/ecp3/FIFO/FIFO_36x32_OutReg_generate.log b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg_generate.log new file mode 100644 index 0000000..a1501b7 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg_generate.log @@ -0,0 +1,48 @@ +Starting process: module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:33:22 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf -1 + Circuit name : FIFO_36x32_OutReg + Module type : fifoblk + Module Version : 5.0 + Ports : + Inputs : Data[35:0], Clock, WrEn, RdEn, Reset + Outputs : Q[35:0], Empty, Full + I/O buffer : not inserted + EDIF output : FIFO_36x32_OutReg.edn + VHDL output : FIFO_36x32_OutReg.vhd + VHDL template : FIFO_36x32_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_36x32_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_36x32_OutReg.srp + Estimated Resource Usage: + LUT : 50 + EBR : 1 + Reg : 20 + +END SCUBA Module Synthesis + +File: FIFO_36x32_OutReg.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/base/cores/ecp3/FIFO/FIFO_36x32_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg_tmpl.vhd new file mode 100644 index 0000000..2265e3c --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x32_OutReg_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.0 +-- Fri Apr 17 11:33:22 2015 + +-- parameterized module component declaration +component FIFO_36x32_OutReg + port (Data: in std_logic_vector(35 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : FIFO_36x32_OutReg + port map (Data(35 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(35 downto 0)=>__, Empty=>__, Full=>__); diff --git a/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.edn b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.edn new file mode 100644 index 0000000..bfa3db0 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.edn @@ -0,0 +1,1528 @@ +(edif FIFO_36x64_OutReg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 4 17 11 33 43) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 36 -depth 64 -regout -no_enable -pe -1 -pf -1 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell AGEB2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port GE + (direction OUTPUT))))) + (cell ALEB2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port LE + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell CU2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT)) + (port PC0 + (direction INPUT)) + (port PC1 + (direction INPUT)) + (port CO + (direction OUTPUT)) + (port NC0 + (direction OUTPUT)) + (port NC1 + (direction OUTPUT))))) + (cell CB2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT)) + (port PC0 + (direction INPUT)) + (port PC1 + (direction INPUT)) + (port CON + (direction INPUT)) + (port CO + (direction OUTPUT)) + (port NC0 + (direction OUTPUT)) + (port NC1 + (direction OUTPUT))))) + (cell FADD2B + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port COUT + (direction OUTPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell PDPW16KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI0 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port DI4 + (direction INPUT)) + (port DI5 + (direction INPUT)) + (port DI6 + (direction INPUT)) + (port DI7 + (direction INPUT)) + (port DI8 + (direction INPUT)) + (port DI9 + (direction INPUT)) + (port DI10 + (direction INPUT)) + (port DI11 + (direction INPUT)) + (port DI12 + (direction INPUT)) + (port DI13 + (direction INPUT)) + (port DI14 + (direction INPUT)) + (port DI15 + (direction INPUT)) + (port DI16 + (direction INPUT)) + (port DI17 + (direction INPUT)) + (port DI18 + (direction INPUT)) + (port DI19 + (direction INPUT)) + (port DI20 + (direction INPUT)) + (port DI21 + (direction INPUT)) + (port DI22 + (direction INPUT)) + (port DI23 + (direction INPUT)) + (port DI24 + (direction INPUT)) + (port DI25 + (direction INPUT)) + (port DI26 + (direction INPUT)) + (port DI27 + (direction INPUT)) + (port DI28 + (direction INPUT)) + (port DI29 + (direction INPUT)) + (port DI30 + (direction INPUT)) + (port DI31 + (direction INPUT)) + (port DI32 + (direction INPUT)) + (port DI33 + (direction INPUT)) + (port DI34 + (direction INPUT)) + (port DI35 + (direction INPUT)) + (port ADW0 + (direction INPUT)) + (port ADW1 + (direction INPUT)) + (port ADW2 + (direction INPUT)) + (port ADW3 + (direction INPUT)) + (port ADW4 + (direction INPUT)) + (port ADW5 + (direction INPUT)) + (port ADW6 + (direction INPUT)) + (port ADW7 + (direction INPUT)) + (port ADW8 + (direction INPUT)) + (port BE0 + (direction INPUT)) + (port BE1 + (direction INPUT)) + (port BE2 + (direction INPUT)) + (port BE3 + (direction INPUT)) + (port CEW + (direction INPUT)) + (port CLKW + (direction INPUT)) + (port CSW0 + (direction INPUT)) + (port CSW1 + (direction INPUT)) + (port CSW2 + (direction INPUT)) + (port ADR0 + (direction INPUT)) + (port ADR1 + (direction INPUT)) + (port ADR2 + (direction INPUT)) + (port ADR3 + (direction INPUT)) + (port ADR4 + (direction INPUT)) + (port ADR5 + (direction INPUT)) + (port ADR6 + (direction INPUT)) + (port ADR7 + (direction INPUT)) + (port ADR8 + (direction INPUT)) + (port ADR9 + (direction INPUT)) + (port ADR10 + (direction INPUT)) + (port ADR11 + (direction INPUT)) + (port ADR12 + (direction INPUT)) + (port ADR13 + (direction INPUT)) + (port CER + (direction INPUT)) + (port CLKR + (direction INPUT)) + (port CSR0 + (direction INPUT)) + (port CSR1 + (direction INPUT)) + (port CSR2 + (direction INPUT)) + (port RST + (direction INPUT)) + (port DO0 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT)) + (port DO4 + (direction OUTPUT)) + (port DO5 + (direction OUTPUT)) + (port DO6 + (direction OUTPUT)) + (port DO7 + (direction OUTPUT)) + (port DO8 + (direction OUTPUT)) + (port DO9 + (direction OUTPUT)) + (port DO10 + (direction OUTPUT)) + (port DO11 + (direction OUTPUT)) + (port DO12 + (direction OUTPUT)) + (port DO13 + (direction OUTPUT)) + (port DO14 + (direction OUTPUT)) + (port DO15 + (direction OUTPUT)) + (port DO16 + (direction OUTPUT)) + (port DO17 + (direction OUTPUT)) + (port DO18 + (direction OUTPUT)) + (port DO19 + (direction OUTPUT)) + (port DO20 + (direction OUTPUT)) + (port DO21 + (direction OUTPUT)) + (port DO22 + (direction OUTPUT)) + (port DO23 + (direction OUTPUT)) + (port DO24 + (direction OUTPUT)) + (port DO25 + (direction OUTPUT)) + (port DO26 + (direction OUTPUT)) + (port DO27 + (direction OUTPUT)) + (port DO28 + (direction OUTPUT)) + (port DO29 + (direction OUTPUT)) + (port DO30 + (direction OUTPUT)) + (port DO31 + (direction OUTPUT)) + (port DO32 + (direction OUTPUT)) + (port DO33 + (direction OUTPUT)) + (port DO34 + (direction OUTPUT)) + (port DO35 + (direction OUTPUT))))) + (cell FIFO_36x64_OutReg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port Clock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t3 + (viewRef view1 + (cellRef AND2))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance AND2_t2 + (viewRef view1 + (cellRef AND2))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance pdp_ram_0_0_0 + (viewRef view1 + (cellRef PDPW16KC)) + (property MEM_LPC_FILE + (string "FIFO_36x64_OutReg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_R + (string "0b001")) + (property CSDECODE_W + (string "0b001")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE + (string "OUTREG")) + (property DATA_WIDTH_R + (string "36")) + (property DATA_WIDTH_W + (string "36"))) + (instance FF_22 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_21 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_20 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_19 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_18 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_17 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_16 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_15 + (viewRef view1 + (cellRef FD1S3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_14 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_13 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_12 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_11 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_10 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_9 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_8 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_7 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_6 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_5 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_4 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_3 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_2 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance bdcnt_bctr_cia + (viewRef view1 + (cellRef FADD2B))) + (instance bdcnt_bctr_0 + (viewRef view1 + (cellRef CB2))) + (instance bdcnt_bctr_1 + (viewRef view1 + (cellRef CB2))) + (instance bdcnt_bctr_2 + (viewRef view1 + (cellRef CB2))) + (instance bdcnt_bctr_3 + (viewRef view1 + (cellRef CB2))) + (instance e_cmp_ci_a + (viewRef view1 + (cellRef FADD2B))) + (instance e_cmp_0 + (viewRef view1 + (cellRef ALEB2))) + (instance e_cmp_1 + (viewRef view1 + (cellRef ALEB2))) + (instance e_cmp_2 + (viewRef view1 + (cellRef ALEB2))) + (instance e_cmp_3 + (viewRef view1 + (cellRef ALEB2))) + (instance a0 + (viewRef view1 + (cellRef FADD2B))) + (instance g_cmp_ci_a + (viewRef view1 + (cellRef FADD2B))) + (instance g_cmp_0 + (viewRef view1 + (cellRef AGEB2))) + (instance g_cmp_1 + (viewRef view1 + (cellRef AGEB2))) + (instance g_cmp_2 + (viewRef view1 + (cellRef AGEB2))) + (instance g_cmp_3 + (viewRef view1 + (cellRef AGEB2))) + (instance a1 + (viewRef view1 + (cellRef FADD2B))) + (instance w_ctr_cia + (viewRef view1 + (cellRef FADD2B))) + (instance w_ctr_0 + (viewRef view1 + (cellRef CU2))) + (instance w_ctr_1 + (viewRef view1 + (cellRef CU2))) + (instance w_ctr_2 + (viewRef view1 + (cellRef CU2))) + (instance w_ctr_3 + (viewRef view1 + (cellRef CU2))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance r_ctr_cia + (viewRef view1 + (cellRef FADD2B))) + (instance r_ctr_0 + (viewRef view1 + (cellRef CU2))) + (instance r_ctr_1 + (viewRef view1 + (cellRef CU2))) + (instance r_ctr_2 + (viewRef view1 + (cellRef CU2))) + (instance r_ctr_3 + (viewRef view1 + (cellRef CU2))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (net invout_1 + (joined + (portRef Z (instanceRef INV_3)) + (portRef B (instanceRef AND2_t3)))) + (net invout_0 + (joined + (portRef Z (instanceRef INV_2)) + (portRef B (instanceRef AND2_t2)))) + (net rden_i_inv + (joined + (portRef Z (instanceRef INV_1)) + (portRef B (instanceRef AND2_t1)))) + (net fcnt_en + (joined + (portRef SP (instanceRef FF_16)) + (portRef Z (instanceRef XOR2_t0)) + (portRef SP (instanceRef FF_22)) + (portRef SP (instanceRef FF_21)) + (portRef SP (instanceRef FF_20)) + (portRef SP (instanceRef FF_19)) + (portRef SP (instanceRef FF_18)) + (portRef SP (instanceRef FF_17)))) + (net empty_d + (joined + (portRef D (instanceRef FF_15)) + (portRef DO0 (instanceRef LUT4_1)))) + (net full_d + (joined + (portRef D (instanceRef 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(net datain19 + (joined + (portRef (member Data 16)) + (portRef DI19 (instanceRef pdp_ram_0_0_0)))) + (net datain18 + (joined + (portRef (member Data 17)) + (portRef DI18 (instanceRef pdp_ram_0_0_0)))) + (net datain17 + (joined + (portRef (member Data 18)) + (portRef DI17 (instanceRef pdp_ram_0_0_0)))) + (net datain16 + (joined + (portRef (member Data 19)) + (portRef DI16 (instanceRef pdp_ram_0_0_0)))) + (net datain15 + (joined + (portRef (member Data 20)) + (portRef DI15 (instanceRef pdp_ram_0_0_0)))) + (net datain14 + (joined + (portRef (member Data 21)) + (portRef DI14 (instanceRef pdp_ram_0_0_0)))) + (net datain13 + (joined + (portRef (member Data 22)) + (portRef DI13 (instanceRef pdp_ram_0_0_0)))) + (net datain12 + (joined + (portRef (member Data 23)) + (portRef DI12 (instanceRef pdp_ram_0_0_0)))) + (net datain11 + (joined + (portRef (member Data 24)) + (portRef DI11 (instanceRef pdp_ram_0_0_0)))) + (net datain10 + (joined + (portRef (member Data 25)) + (portRef DI10 (instanceRef pdp_ram_0_0_0)))) + (net datain9 + (joined + (portRef (member Data 26)) + (portRef DI9 (instanceRef pdp_ram_0_0_0)))) + (net datain8 + (joined + (portRef (member Data 27)) + (portRef DI8 (instanceRef pdp_ram_0_0_0)))) + (net datain7 + (joined + (portRef (member Data 28)) + (portRef DI7 (instanceRef pdp_ram_0_0_0)))) + (net datain6 + (joined + (portRef (member Data 29)) + (portRef DI6 (instanceRef pdp_ram_0_0_0)))) + (net datain5 + (joined + (portRef (member Data 30)) + (portRef DI5 (instanceRef pdp_ram_0_0_0)))) + (net datain4 + (joined + (portRef (member Data 31)) + (portRef DI4 (instanceRef pdp_ram_0_0_0)))) + (net datain3 + (joined + (portRef (member Data 32)) + (portRef DI3 (instanceRef pdp_ram_0_0_0)))) + (net datain2 + (joined + (portRef (member Data 33)) + (portRef DI2 (instanceRef pdp_ram_0_0_0)))) + (net datain1 + (joined + (portRef (member Data 34)) + (portRef DI1 (instanceRef pdp_ram_0_0_0)))) + (net datain0 + (joined + (portRef (member Data 35)) + (portRef DI0 (instanceRef pdp_ram_0_0_0)))))))) + (design FIFO_36x64_OutReg + (cellRef FIFO_36x64_OutReg + (libraryRef ORCLIB))) +) diff --git a/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.ipx b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.ipx new file mode 100644 index 0000000..7e979be --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.jhd b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.jhd new file mode 100644 index 0000000..e69de29 diff --git a/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.lpc b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.lpc new file mode 100644 index 0000000..75dc2d9 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=FIFO_36x64_OutReg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/17/2015 +Time=11:33:43 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=64 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf -1 diff --git a/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.sort b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.sort new file mode 100644 index 0000000..9c51738 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.sort @@ -0,0 +1 @@ +FIFO_36x64_OutReg.vhd diff --git a/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.srp b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.srp new file mode 100644 index 0000000..27533f7 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.srp @@ -0,0 +1,42 @@ +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:33:43 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf -1 + Circuit name : FIFO_36x64_OutReg + Module type : fifoblk + Module Version : 5.0 + Ports : + Inputs : Data[35:0], Clock, WrEn, RdEn, Reset + Outputs : Q[35:0], Empty, Full + I/O buffer : not inserted + EDIF output : FIFO_36x64_OutReg.edn + VHDL output : FIFO_36x64_OutReg.vhd + VHDL template : FIFO_36x64_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_36x64_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_36x64_OutReg.srp + Element Usage : + AGEB2 : 4 + ALEB2 : 4 + AND2 : 3 + CU2 : 8 + CB2 : 4 + FADD2B : 7 + FD1P3DX : 21 + FD1S3BX : 1 + FD1S3DX : 1 + INV : 4 + ROM16X1A : 2 + XOR2 : 1 + PDPW16KC : 1 + Estimated Resource Usage: + LUT : 60 + EBR : 1 + Reg : 23 diff --git a/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd new file mode 100644 index 0000000..fd6dd94 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd @@ -0,0 +1,565 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.0 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 36 -depth 64 -regout -no_enable -pe -1 -pf -1 + +-- Fri Apr 17 11:33:43 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_36x64_OutReg is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic); +end FIFO_36x64_OutReg; + +architecture Structure of FIFO_36x64_OutReg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal co3: std_logic; + signal cnt_con: std_logic; + signal co2: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal wren_i: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_6: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal co3_1: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal co3_2: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x64_OutReg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), + ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2, + ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5, + ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1, + ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4, + ADR10=>rcount_5, ADR11=>scuba_vlo, ADR12=>scuba_vlo, + ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i, + CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), + DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), + DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), + DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), + DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), + DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), + DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), + DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), + DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); + + FF_22: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_21: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_20: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_19: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_18: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_17: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_16: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_15: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_14: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_13: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_12: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_11: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_10: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_9: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_8: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_7: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_6: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_5: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_4: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_3: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_2: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_1: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_0: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>open); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co2_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3_1, + NC0=>iwcount_6, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_2, + NC0=>ircount_6, NC1=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_36x64_OutReg is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/ecp3/FIFO/FIFO_36x64_OutReg_generate.log b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg_generate.log new file mode 100644 index 0000000..c7b3aa2 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg_generate.log @@ -0,0 +1,48 @@ +Starting process: module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:33:43 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf -1 + Circuit name : FIFO_36x64_OutReg + Module type : fifoblk + Module Version : 5.0 + Ports : + Inputs : Data[35:0], Clock, WrEn, RdEn, Reset + Outputs : Q[35:0], Empty, Full + I/O buffer : not inserted + EDIF output : FIFO_36x64_OutReg.edn + VHDL output : FIFO_36x64_OutReg.vhd + VHDL template : FIFO_36x64_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_36x64_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_36x64_OutReg.srp + Estimated Resource Usage: + LUT : 60 + EBR : 1 + Reg : 23 + +END SCUBA Module Synthesis + +File: FIFO_36x64_OutReg.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/base/cores/ecp3/FIFO/FIFO_36x64_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg_tmpl.vhd new file mode 100644 index 0000000..70f135b --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_36x64_OutReg_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.0 +-- Fri Apr 17 11:33:43 2015 + +-- parameterized module component declaration +component FIFO_36x64_OutReg + port (Data: in std_logic_vector(35 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : FIFO_36x64_OutReg + port map (Data(35 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(35 downto 0)=>__, Empty=>__, Full=>__); diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.edn b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.edn new file mode 100644 index 0000000..774c517 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.edn @@ -0,0 +1,2715 @@ +(edif FIFO_DC_36x128_OutReg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 4 17 11 31 2) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe -1 -pf 120 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell AGEB2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port GE + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell CU2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT)) + (port PC0 + (direction INPUT)) + (port PC1 + (direction INPUT)) + (port CO + (direction OUTPUT)) + (port NC0 + (direction OUTPUT)) + (port NC1 + (direction OUTPUT))))) + (cell FADD2B + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port COUT + (direction OUTPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell OR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell PDPW16KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI0 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port DI4 + (direction INPUT)) + (port DI5 + (direction INPUT)) + (port DI6 + (direction INPUT)) + (port DI7 + (direction INPUT)) + (port DI8 + (direction INPUT)) + (port DI9 + (direction INPUT)) + (port DI10 + (direction INPUT)) + (port DI11 + (direction INPUT)) + (port DI12 + (direction INPUT)) + (port DI13 + (direction INPUT)) + (port DI14 + (direction INPUT)) + (port DI15 + (direction INPUT)) + (port DI16 + (direction INPUT)) + (port DI17 + (direction INPUT)) + (port DI18 + (direction INPUT)) + (port DI19 + (direction INPUT)) + (port DI20 + (direction INPUT)) + (port DI21 + (direction INPUT)) + (port DI22 + (direction INPUT)) + (port DI23 + (direction INPUT)) + (port DI24 + (direction INPUT)) + (port DI25 + (direction INPUT)) + (port DI26 + (direction INPUT)) + (port DI27 + (direction INPUT)) + (port DI28 + (direction INPUT)) + (port DI29 + (direction INPUT)) + (port DI30 + (direction INPUT)) + (port DI31 + (direction INPUT)) + (port DI32 + (direction INPUT)) + (port DI33 + (direction INPUT)) + (port DI34 + (direction INPUT)) + (port DI35 + (direction INPUT)) + (port ADW0 + (direction INPUT)) + (port ADW1 + (direction INPUT)) + (port ADW2 + (direction INPUT)) + (port ADW3 + (direction INPUT)) + (port ADW4 + (direction INPUT)) + (port ADW5 + (direction INPUT)) + (port ADW6 + (direction INPUT)) + (port ADW7 + (direction INPUT)) + (port ADW8 + (direction INPUT)) + (port BE0 + (direction INPUT)) + (port BE1 + (direction INPUT)) + (port BE2 + (direction INPUT)) + (port BE3 + (direction INPUT)) + (port CEW + (direction INPUT)) + (port CLKW + (direction INPUT)) + (port CSW0 + (direction INPUT)) + (port CSW1 + (direction INPUT)) + (port CSW2 + (direction INPUT)) + (port ADR0 + (direction INPUT)) + (port ADR1 + (direction INPUT)) + (port ADR2 + (direction INPUT)) + (port ADR3 + (direction INPUT)) + (port ADR4 + (direction INPUT)) + (port ADR5 + (direction INPUT)) + (port ADR6 + (direction INPUT)) + (port ADR7 + (direction INPUT)) + (port ADR8 + (direction INPUT)) + (port ADR9 + (direction INPUT)) + (port ADR10 + (direction INPUT)) + (port ADR11 + (direction INPUT)) + (port ADR12 + (direction INPUT)) + (port ADR13 + (direction INPUT)) + (port CER + (direction INPUT)) + (port CLKR + (direction INPUT)) + (port CSR0 + (direction INPUT)) + (port CSR1 + (direction INPUT)) + (port CSR2 + (direction INPUT)) + (port RST + (direction INPUT)) + (port DO0 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT)) + (port DO4 + (direction OUTPUT)) + (port DO5 + (direction OUTPUT)) + (port DO6 + (direction OUTPUT)) + (port DO7 + (direction OUTPUT)) + (port DO8 + (direction OUTPUT)) + (port DO9 + (direction OUTPUT)) + (port DO10 + (direction OUTPUT)) + (port DO11 + (direction OUTPUT)) + (port DO12 + (direction OUTPUT)) + (port DO13 + (direction OUTPUT)) + (port DO14 + (direction OUTPUT)) + (port DO15 + (direction OUTPUT)) + (port DO16 + (direction OUTPUT)) + (port DO17 + (direction OUTPUT)) + (port DO18 + (direction OUTPUT)) + (port DO19 + (direction OUTPUT)) + (port DO20 + (direction OUTPUT)) + (port DO21 + (direction OUTPUT)) + (port DO22 + (direction OUTPUT)) + (port DO23 + (direction OUTPUT)) + (port DO24 + (direction OUTPUT)) + (port DO25 + (direction OUTPUT)) + (port DO26 + (direction OUTPUT)) + (port DO27 + (direction OUTPUT)) + (port DO28 + (direction OUTPUT)) + (port DO29 + (direction OUTPUT)) + (port DO30 + (direction OUTPUT)) + (port DO31 + (direction OUTPUT)) + (port DO32 + (direction OUTPUT)) + (port DO33 + (direction OUTPUT)) + (port DO34 + (direction OUTPUT)) + (port DO35 + (direction OUTPUT))))) + (cell FIFO_DC_36x128_OutReg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port RPReset + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t16 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance AND2_t15 + (viewRef view1 + (cellRef AND2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance OR2_t14 + (viewRef view1 + (cellRef OR2))) + (instance XOR2_t13 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t12 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t11 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t10 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t9 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t8 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t7 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t6 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t5 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t4 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t3 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t1 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance LUT4_21 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_20 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_19 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_18 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_17 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_16 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_15 + (viewRef view1 + (cellRef ROM16X1A)) + (property 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(property initval + (string "0x0410"))) + (instance LUT4_4 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x1004"))) + (instance LUT4_3 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x0140"))) + (instance LUT4_2 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x4001"))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x4c32"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8001"))) + (instance pdp_ram_0_0_0 + (viewRef view1 + (cellRef PDPW16KC)) + (property MEM_LPC_FILE + (string "FIFO_DC_36x128_OutReg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_R + (string "0b001")) + (property CSDECODE_W + (string "0b001")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE + (string "OUTREG")) + (property DATA_WIDTH_R + (string "36")) + (property DATA_WIDTH_W + (string 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(net datain32 + (joined + (portRef (member Data 3)) + (portRef DI32 (instanceRef pdp_ram_0_0_0)))) + (net datain31 + (joined + (portRef (member Data 4)) + (portRef DI31 (instanceRef pdp_ram_0_0_0)))) + (net datain30 + (joined + (portRef (member Data 5)) + (portRef DI30 (instanceRef pdp_ram_0_0_0)))) + (net datain29 + (joined + (portRef (member Data 6)) + (portRef DI29 (instanceRef pdp_ram_0_0_0)))) + (net datain28 + (joined + (portRef (member Data 7)) + (portRef DI28 (instanceRef pdp_ram_0_0_0)))) + (net datain27 + (joined + (portRef (member Data 8)) + (portRef DI27 (instanceRef pdp_ram_0_0_0)))) + (net datain26 + (joined + (portRef (member Data 9)) + (portRef DI26 (instanceRef pdp_ram_0_0_0)))) + (net datain25 + (joined + (portRef (member Data 10)) + (portRef DI25 (instanceRef pdp_ram_0_0_0)))) + (net datain24 + (joined + (portRef (member Data 11)) + (portRef DI24 (instanceRef pdp_ram_0_0_0)))) + (net datain23 + (joined + (portRef (member Data 12)) + (portRef DI23 (instanceRef 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(portRef DI13 (instanceRef pdp_ram_0_0_0)))) + (net datain12 + (joined + (portRef (member Data 23)) + (portRef DI12 (instanceRef pdp_ram_0_0_0)))) + (net datain11 + (joined + (portRef (member Data 24)) + (portRef DI11 (instanceRef pdp_ram_0_0_0)))) + (net datain10 + (joined + (portRef (member Data 25)) + (portRef DI10 (instanceRef pdp_ram_0_0_0)))) + (net datain9 + (joined + (portRef (member Data 26)) + (portRef DI9 (instanceRef pdp_ram_0_0_0)))) + (net datain8 + (joined + (portRef (member Data 27)) + (portRef DI8 (instanceRef pdp_ram_0_0_0)))) + (net datain7 + (joined + (portRef (member Data 28)) + (portRef DI7 (instanceRef pdp_ram_0_0_0)))) + (net datain6 + (joined + (portRef (member Data 29)) + (portRef DI6 (instanceRef pdp_ram_0_0_0)))) + (net datain5 + (joined + (portRef (member Data 30)) + (portRef DI5 (instanceRef pdp_ram_0_0_0)))) + (net datain4 + (joined + (portRef (member Data 31)) + (portRef DI4 (instanceRef pdp_ram_0_0_0)))) + (net datain3 + (joined + (portRef (member Data 32)) + (portRef DI3 (instanceRef pdp_ram_0_0_0)))) + (net datain2 + (joined + (portRef (member Data 33)) + (portRef DI2 (instanceRef pdp_ram_0_0_0)))) + (net datain1 + (joined + (portRef (member Data 34)) + (portRef DI1 (instanceRef pdp_ram_0_0_0)))) + (net datain0 + (joined + (portRef (member Data 35)) + (portRef DI0 (instanceRef pdp_ram_0_0_0)))))))) + (design FIFO_DC_36x128_OutReg + (cellRef FIFO_DC_36x128_OutReg + (libraryRef ORCLIB))) +) diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.ipx b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.ipx new file mode 100644 index 0000000..6975de0 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.jhd b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.jhd new file mode 100644 index 0000000..e69de29 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.lpc b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.lpc new file mode 100644 index 0000000..8496c32 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=FIFO_DC_36x128_OutReg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/17/2015 +Time=11:31:02 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=128 +Width=36 +RDepth=128 +RWidth=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=120 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n FIFO_DC_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 120 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.sort b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.sort new file mode 100644 index 0000000..a407670 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.sort @@ -0,0 +1 @@ +FIFO_DC_36x128_OutReg.vhd diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.srp b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.srp new file mode 100644 index 0000000..407137a --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.srp @@ -0,0 +1,42 @@ +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:31:02 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 120 + Circuit name : FIFO_DC_36x128_OutReg + Module type : ebfifo + Module Version : 5.7 + Ports : + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[35:0], Empty, Full, AlmostFull + I/O buffer : not inserted + EDIF output : FIFO_DC_36x128_OutReg.edn + VHDL output : FIFO_DC_36x128_OutReg.vhd + VHDL template : FIFO_DC_36x128_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_DC_36x128_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_DC_36x128_OutReg.srp + Element Usage : + AGEB2 : 12 + AND2 : 2 + CU2 : 12 + FADD2B : 9 + FD1P3BX : 4 + FD1P3DX : 52 + FD1S3BX : 1 + FD1S3DX : 34 + INV : 2 + OR2 : 1 + ROM16X1A : 22 + XOR2 : 14 + PDPW16KC : 1 + Estimated Resource Usage: + LUT : 105 + EBR : 1 + Reg : 91 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd new file mode 100644 index 0000000..a8f3c1a --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd @@ -0,0 +1,1149 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe -1 -pf 120 + +-- Fri Apr 17 11:31:02 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_DC_36x128_OutReg is + port ( + Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end FIFO_DC_36x128_OutReg; + +architecture Structure of FIFO_DC_36x128_OutReg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co3: std_logic; + signal co2: std_logic; + signal wcount_7: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co3_1: std_logic; + signal co2_1: std_logic; + signal rcount_7: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_6: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_6: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co1_4: std_logic; + signal iaf_setcount_6: std_logic; + signal iaf_setcount_7: std_logic; + signal co3_2: std_logic; + signal co2_4: std_logic; + signal af_setcount_7: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w5: std_logic; + signal af_setcount_4: std_logic; + signal af_setcount_5: std_logic; + signal co2_5: std_logic; + signal rcount_w6: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_setcount_6: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_DC_36x128_OutReg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t16: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t15: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t14: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t13: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t12: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t11: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t10: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t9: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t8: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t7: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t6: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t5: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t4: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t3: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t2: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t1: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t0: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_0); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>wcount_r6, DO0=>wcount_r3); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>wcount_r5, DO0=>wcount_r2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, + DO0=>r_g2b_xor_cluster_0); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, + DO0=>r_g2b_xor_cluster_1); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>rcount_w6, DO0=>rcount_w3); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>rcount_w5, DO0=>rcount_w2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_5: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_7, AD2=>rcount_7, AD1=>w_gcount_r27, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_4: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_7, AD2=>rcount_7, AD1=>w_gcount_r27, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_3: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_7, AD2=>wcount_7, AD1=>r_gcount_w27, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_7, AD2=>wcount_7, AD1=>r_gcount_w27, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_7, AD2=>wcount_7, AD1=>r_gcount_w27, + AD0=>wptr_7, DO0=>af_set_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_7, AD2=>wcount_7, AD1=>r_gcount_w27, + AD0=>wptr_7, DO0=>af_set_cmp_clr); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, + ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi, + CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), + DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17)); + + FF_90: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_89: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_88: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_87: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_86: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_85: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_84: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_83: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_82: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_81: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_80: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_79: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_78: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_77: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_76: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_75: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_74: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_73: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_72: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_71: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_70: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_69: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_68: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_67: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_66: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_65: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_64: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_63: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_62: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_61: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_60: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_59: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_58: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_57: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_56: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_55: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_54: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_53: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_52: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_51: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_50: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_49: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_48: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_47: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_46: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_45: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_44: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_43: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_42: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_41: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_40: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_39: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_38: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_37: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_36: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_35: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_34: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_33: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_32: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_31: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_30: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_29: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_28: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_27: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_26: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_25: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_24: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_23: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_22: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_21: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_20: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_19: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_18: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_17: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_16: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_15: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_14: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_13: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_12: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_11: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_10: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_9: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_8: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); + + FF_7: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); + + FF_6: FD1P3DX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_2); + + FF_5: FD1P3BX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_4: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_3: FD1P3DX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_5); + + FF_2: FD1P3DX + port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_6); + + FF_1: FD1P3DX + port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_7); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>empty_cmp_set, B0=>wcount_r6, + B1=>empty_cmp_clr, CI=>co2_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>full_cmp_set, B0=>rcount_w6, + B1=>full_cmp_clr, CI=>co2_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, + CO=>co2_4, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); + + af_set_ctr_3: CU2 + port map (CI=>co2_4, PC0=>af_setcount_6, PC1=>af_setcount_7, + CO=>co3_2, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_setcount_4, A1=>af_setcount_5, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w5, CI=>co1_5, GE=>co2_5); + + af_set_cmp_3: AGEB2 + port map (A0=>af_setcount_6, A1=>af_set_cmp_set, B0=>rcount_w6, + B1=>af_set_cmp_clr, CI=>co2_5, GE=>af_set_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_DC_36x128_OutReg is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg_generate.log b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg_generate.log new file mode 100644 index 0000000..821d440 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg_generate.log @@ -0,0 +1,48 @@ +Starting process: module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:31:02 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 120 + Circuit name : FIFO_DC_36x128_OutReg + Module type : ebfifo + Module Version : 5.7 + Ports : + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[35:0], Empty, Full, AlmostFull + I/O buffer : not inserted + EDIF output : FIFO_DC_36x128_OutReg.edn + VHDL output : FIFO_DC_36x128_OutReg.vhd + VHDL template : FIFO_DC_36x128_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_DC_36x128_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_DC_36x128_OutReg.srp + Estimated Resource Usage: + LUT : 105 + EBR : 1 + Reg : 91 + +END SCUBA Module Synthesis + +File: FIFO_DC_36x128_OutReg.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg_tmpl.vhd new file mode 100644 index 0000000..5ef85f0 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +-- Fri Apr 17 11:31:02 2015 + +-- parameterized module component declaration +component FIFO_DC_36x128_OutReg + port (Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; Full: out std_logic; + AlmostFull: out std_logic); +end component; + +-- parameterized module component instance +__ : FIFO_DC_36x128_OutReg + port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(35 downto 0)=>__, Empty=>__, + Full=>__, AlmostFull=>__); diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.edn b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.edn new file mode 100644 index 0000000..d276a5c --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.edn @@ -0,0 +1,2277 @@ +(edif FIFO_DC_36x32_OutReg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 4 17 11 32 6) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 36 -depth 32 -rdata_width 36 -regout -no_enable -pe -1 -pf 24 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell AGEB2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port GE + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell CU2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT)) + (port PC0 + (direction INPUT)) + (port PC1 + (direction INPUT)) + (port CO + (direction OUTPUT)) + (port NC0 + (direction OUTPUT)) + (port NC1 + (direction OUTPUT))))) + (cell FADD2B + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port COUT + (direction OUTPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell OR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell PDPW16KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI0 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port DI4 + (direction INPUT)) + (port DI5 + (direction INPUT)) + (port DI6 + (direction INPUT)) + (port DI7 + (direction INPUT)) + (port DI8 + (direction INPUT)) + (port DI9 + (direction INPUT)) + (port DI10 + (direction INPUT)) + (port DI11 + (direction INPUT)) + (port DI12 + (direction INPUT)) + (port DI13 + (direction INPUT)) + (port DI14 + (direction INPUT)) + (port DI15 + (direction INPUT)) + (port DI16 + (direction INPUT)) + (port DI17 + (direction INPUT)) + (port DI18 + (direction INPUT)) + (port DI19 + (direction INPUT)) + (port DI20 + (direction INPUT)) + (port DI21 + (direction INPUT)) + (port DI22 + (direction INPUT)) + (port DI23 + (direction INPUT)) + (port DI24 + (direction INPUT)) + (port DI25 + (direction INPUT)) + (port DI26 + (direction INPUT)) + (port DI27 + (direction INPUT)) + (port DI28 + (direction INPUT)) + (port DI29 + (direction INPUT)) + (port DI30 + (direction INPUT)) + (port DI31 + (direction INPUT)) + (port DI32 + (direction INPUT)) + (port DI33 + (direction INPUT)) + (port DI34 + (direction INPUT)) + (port DI35 + (direction INPUT)) + (port ADW0 + (direction INPUT)) + (port ADW1 + (direction INPUT)) + (port ADW2 + (direction INPUT)) + (port ADW3 + (direction INPUT)) + (port ADW4 + (direction INPUT)) + (port ADW5 + (direction INPUT)) + (port ADW6 + (direction INPUT)) + (port ADW7 + (direction INPUT)) + (port ADW8 + (direction INPUT)) + (port BE0 + (direction INPUT)) + (port BE1 + (direction INPUT)) + (port BE2 + (direction INPUT)) + (port BE3 + (direction INPUT)) + (port CEW + (direction INPUT)) + (port CLKW + (direction INPUT)) + (port CSW0 + (direction INPUT)) + (port CSW1 + (direction INPUT)) + (port CSW2 + (direction INPUT)) + (port ADR0 + (direction INPUT)) + (port ADR1 + (direction INPUT)) + (port ADR2 + (direction INPUT)) + (port ADR3 + (direction INPUT)) + (port ADR4 + (direction INPUT)) + (port ADR5 + (direction INPUT)) + (port ADR6 + (direction INPUT)) + (port ADR7 + (direction INPUT)) + (port ADR8 + (direction INPUT)) + (port ADR9 + (direction INPUT)) + (port ADR10 + (direction INPUT)) + (port ADR11 + (direction INPUT)) + (port ADR12 + (direction INPUT)) + (port ADR13 + (direction INPUT)) + (port CER + (direction INPUT)) + (port CLKR + (direction INPUT)) + (port CSR0 + (direction INPUT)) + (port CSR1 + (direction INPUT)) + (port CSR2 + (direction INPUT)) + (port RST + (direction INPUT)) + (port DO0 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT)) + (port DO4 + (direction OUTPUT)) + (port DO5 + (direction OUTPUT)) + (port DO6 + (direction OUTPUT)) + (port DO7 + (direction OUTPUT)) + (port DO8 + (direction OUTPUT)) + (port DO9 + (direction OUTPUT)) + (port DO10 + (direction OUTPUT)) + (port DO11 + (direction OUTPUT)) + (port DO12 + (direction OUTPUT)) + (port DO13 + (direction OUTPUT)) + (port DO14 + (direction OUTPUT)) + (port DO15 + (direction OUTPUT)) + (port DO16 + (direction OUTPUT)) + (port DO17 + (direction OUTPUT)) + (port DO18 + (direction OUTPUT)) + (port DO19 + (direction OUTPUT)) + (port DO20 + (direction OUTPUT)) + (port DO21 + (direction OUTPUT)) + (port DO22 + (direction OUTPUT)) + (port DO23 + (direction OUTPUT)) + (port DO24 + (direction OUTPUT)) + (port DO25 + (direction OUTPUT)) + (port DO26 + (direction OUTPUT)) + (port DO27 + (direction OUTPUT)) + (port DO28 + (direction OUTPUT)) + (port DO29 + (direction OUTPUT)) + (port DO30 + (direction OUTPUT)) + (port DO31 + (direction OUTPUT)) + (port DO32 + (direction OUTPUT)) + (port DO33 + (direction OUTPUT)) + (port DO34 + (direction OUTPUT)) + (port DO35 + (direction OUTPUT))))) + (cell FIFO_DC_36x32_OutReg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port RPReset + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t12 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance AND2_t11 + (viewRef view1 + (cellRef AND2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance OR2_t10 + (viewRef view1 + (cellRef OR2))) + (instance XOR2_t9 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t8 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t7 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t6 + (viewRef view1 + (cellRef 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a/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.lpc b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.lpc new file mode 100644 index 0000000..fcaf0cc --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=FIFO_DC_36x32_OutReg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/17/2015 +Time=11:32:06 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32 +Width=36 +RDepth=32 +RWidth=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=24 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n FIFO_DC_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 5 -data_width 36 -num_words 32 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 24 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.sort b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.sort new file mode 100644 index 0000000..c6408cc --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.sort @@ -0,0 +1 @@ +FIFO_DC_36x32_OutReg.vhd diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.srp b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.srp new file mode 100644 index 0000000..8166627 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.srp @@ -0,0 +1,42 @@ +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:32:06 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 5 -data_width 36 -num_words 32 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 24 + Circuit name : FIFO_DC_36x32_OutReg + Module type : ebfifo + Module Version : 5.7 + Ports : + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[35:0], Empty, Full, AlmostFull + I/O buffer : not inserted + EDIF output : FIFO_DC_36x32_OutReg.edn + VHDL output : FIFO_DC_36x32_OutReg.vhd + VHDL template : FIFO_DC_36x32_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_DC_36x32_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_DC_36x32_OutReg.srp + Element Usage : + AGEB2 : 9 + AND2 : 2 + CU2 : 9 + FADD2B : 9 + FD1P3BX : 4 + FD1P3DX : 38 + FD1S3BX : 1 + FD1S3DX : 26 + INV : 2 + OR2 : 1 + ROM16X1A : 16 + XOR2 : 10 + PDPW16KC : 1 + Estimated Resource Usage: + LUT : 83 + EBR : 1 + Reg : 69 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd new file mode 100644 index 0000000..dbf4781 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd @@ -0,0 +1,933 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 36 -depth 32 -rdata_width 36 -regout -no_enable -pe -1 -pf 24 + +-- Fri Apr 17 11:32:06 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_DC_36x32_OutReg is + port ( + Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end FIFO_DC_36x32_OutReg; + +architecture Structure of FIFO_DC_36x32_OutReg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co2: std_logic; + signal co1: std_logic; + signal wcount_5: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co2_1: std_logic; + signal co1_1: std_logic; + signal rcount_5: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_4: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_4: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co2_2: std_logic; + signal co1_4: std_logic; + signal af_setcount_5: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w3: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal rcount_w4: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_setcount_4: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_DC_36x32_OutReg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t12: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t11: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t10: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t9: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t8: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t7: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t6: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t5: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t4: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t3: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t2: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t1: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t0: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_0); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_0); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); + + LUT4_5: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_4: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_3: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_5, AD2=>wcount_5, AD1=>r_gcount_w25, + AD0=>wptr_5, DO0=>af_set_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_5, AD2=>wcount_5, AD1=>r_gcount_w25, + AD0=>wptr_5, DO0=>af_set_cmp_clr); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, + ADW5=>scuba_vlo, ADW6=>scuba_vlo, ADW7=>scuba_vlo, + ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi, + BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, + CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, + ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, + ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, + ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>scuba_vlo, + ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo, + CER=>scuba_vhi, CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), + DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17)); + + FF_68: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_67: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_66: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_65: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_64: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_63: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_62: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_61: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_60: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_59: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_58: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_57: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_56: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_55: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_54: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_53: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_52: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_51: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_50: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_49: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_48: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_47: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_46: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_45: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_44: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_43: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_42: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_41: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_40: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_39: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_38: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_37: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_36: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_35: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_34: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_33: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_32: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_31: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_30: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_29: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_28: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_27: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_26: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_25: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_24: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_23: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_22: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_21: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_20: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_19: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_18: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_17: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_16: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_15: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_14: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_13: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_12: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_11: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_10: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_9: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_8: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_7: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_6: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); + + FF_5: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); + + FF_4: FD1P3DX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_2); + + FF_3: FD1P3BX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_2: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_1: FD1P3DX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_5); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>empty_cmp_set, B0=>wcount_r4, + B1=>empty_cmp_clr, CI=>co1_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>full_cmp_set, B0=>rcount_w4, + B1=>full_cmp_clr, CI=>co1_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, + CO=>co2_2, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_setcount_4, A1=>af_set_cmp_set, B0=>rcount_w4, + B1=>af_set_cmp_clr, CI=>co1_5, GE=>af_set_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_DC_36x32_OutReg is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg_generate.log b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg_generate.log new file mode 100644 index 0000000..83ed55b --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg_generate.log @@ -0,0 +1,48 @@ +Starting process: module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:32:06 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 5 -data_width 36 -num_words 32 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 24 + Circuit name : FIFO_DC_36x32_OutReg + Module type : ebfifo + Module Version : 5.7 + Ports : + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[35:0], Empty, Full, AlmostFull + I/O buffer : not inserted + EDIF output : FIFO_DC_36x32_OutReg.edn + VHDL output : FIFO_DC_36x32_OutReg.vhd + VHDL template : FIFO_DC_36x32_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_DC_36x32_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_DC_36x32_OutReg.srp + Estimated Resource Usage: + LUT : 83 + EBR : 1 + Reg : 69 + +END SCUBA Module Synthesis + +File: FIFO_DC_36x32_OutReg.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg_tmpl.vhd new file mode 100644 index 0000000..f44b8de --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +-- Fri Apr 17 11:32:06 2015 + +-- parameterized module component declaration +component FIFO_DC_36x32_OutReg + port (Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; Full: out std_logic; + AlmostFull: out std_logic); +end component; + +-- parameterized module component instance +__ : FIFO_DC_36x32_OutReg + port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(35 downto 0)=>__, Empty=>__, + Full=>__, AlmostFull=>__); diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.edn b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.edn new file mode 100644 index 0000000..a40368a --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.edn @@ -0,0 +1,2514 @@ +(edif FIFO_DC_36x64_OutReg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 4 17 11 31 34) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 36 -depth 64 -rdata_width 36 -regout -no_enable -pe -1 -pf 56 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell AGEB2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port GE + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell CU2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT)) + (port PC0 + (direction INPUT)) + (port PC1 + (direction INPUT)) + (port CO + (direction OUTPUT)) + (port NC0 + (direction OUTPUT)) + (port NC1 + (direction OUTPUT))))) + (cell FADD2B + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port COUT + (direction OUTPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell OR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell PDPW16KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI0 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port DI4 + (direction INPUT)) + (port DI5 + (direction INPUT)) + (port DI6 + (direction INPUT)) + (port DI7 + (direction INPUT)) + (port DI8 + (direction INPUT)) + (port DI9 + (direction INPUT)) + (port DI10 + (direction INPUT)) + (port DI11 + (direction INPUT)) + (port DI12 + (direction INPUT)) + (port DI13 + (direction INPUT)) + (port DI14 + (direction INPUT)) + (port DI15 + (direction INPUT)) + (port DI16 + (direction INPUT)) + (port DI17 + (direction INPUT)) + (port DI18 + (direction INPUT)) + (port DI19 + (direction INPUT)) + (port DI20 + (direction INPUT)) + (port DI21 + (direction INPUT)) + (port DI22 + (direction INPUT)) + (port DI23 + (direction INPUT)) + (port DI24 + (direction INPUT)) + (port DI25 + (direction INPUT)) + (port DI26 + (direction INPUT)) + (port DI27 + (direction INPUT)) + (port DI28 + (direction INPUT)) + (port DI29 + (direction INPUT)) + (port DI30 + (direction INPUT)) + (port DI31 + (direction INPUT)) + (port DI32 + (direction INPUT)) + (port DI33 + (direction INPUT)) + (port DI34 + (direction INPUT)) + (port DI35 + (direction INPUT)) + (port ADW0 + (direction INPUT)) + (port ADW1 + (direction INPUT)) + (port ADW2 + (direction INPUT)) + (port ADW3 + (direction INPUT)) + (port ADW4 + (direction INPUT)) + (port ADW5 + (direction INPUT)) + (port ADW6 + (direction INPUT)) + (port ADW7 + (direction INPUT)) + (port ADW8 + (direction INPUT)) + (port BE0 + (direction INPUT)) + (port BE1 + (direction INPUT)) + (port BE2 + (direction INPUT)) + (port BE3 + (direction INPUT)) + (port CEW + (direction INPUT)) + (port CLKW + (direction INPUT)) + (port CSW0 + (direction INPUT)) + (port CSW1 + (direction INPUT)) + (port CSW2 + (direction INPUT)) + (port ADR0 + (direction INPUT)) + (port ADR1 + (direction INPUT)) + (port ADR2 + (direction INPUT)) + (port ADR3 + (direction INPUT)) + (port ADR4 + (direction INPUT)) + (port ADR5 + (direction INPUT)) + (port ADR6 + (direction INPUT)) + (port ADR7 + (direction INPUT)) + (port ADR8 + (direction INPUT)) + (port ADR9 + (direction INPUT)) + (port ADR10 + (direction INPUT)) + (port ADR11 + (direction INPUT)) + (port ADR12 + (direction INPUT)) + (port ADR13 + (direction INPUT)) + (port CER + (direction INPUT)) + (port CLKR + (direction INPUT)) + (port CSR0 + (direction INPUT)) + (port CSR1 + (direction INPUT)) + (port CSR2 + (direction INPUT)) + (port RST + (direction INPUT)) + (port DO0 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT)) + (port DO4 + (direction OUTPUT)) + (port DO5 + (direction OUTPUT)) + (port DO6 + (direction OUTPUT)) + (port DO7 + (direction OUTPUT)) + (port DO8 + (direction OUTPUT)) + (port DO9 + (direction OUTPUT)) + (port DO10 + (direction OUTPUT)) + (port DO11 + (direction OUTPUT)) + (port DO12 + (direction OUTPUT)) + (port DO13 + (direction OUTPUT)) + (port DO14 + (direction OUTPUT)) + (port DO15 + (direction OUTPUT)) + (port DO16 + (direction OUTPUT)) + (port DO17 + (direction OUTPUT)) + (port DO18 + (direction OUTPUT)) + (port DO19 + (direction OUTPUT)) + (port DO20 + (direction OUTPUT)) + (port DO21 + (direction OUTPUT)) + (port DO22 + (direction OUTPUT)) + (port DO23 + (direction OUTPUT)) + (port DO24 + (direction OUTPUT)) + (port DO25 + (direction OUTPUT)) + (port DO26 + (direction OUTPUT)) + (port DO27 + (direction OUTPUT)) + (port DO28 + (direction OUTPUT)) + (port DO29 + (direction OUTPUT)) + (port DO30 + (direction OUTPUT)) + (port DO31 + (direction OUTPUT)) + (port DO32 + (direction OUTPUT)) + (port DO33 + (direction OUTPUT)) + (port DO34 + (direction OUTPUT)) + (port DO35 + (direction OUTPUT))))) + (cell FIFO_DC_36x64_OutReg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port RPReset + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t14 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance AND2_t13 + (viewRef view1 + (cellRef AND2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance OR2_t12 + (viewRef view1 + (cellRef OR2))) + (instance XOR2_t11 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t10 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t9 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t8 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t7 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t6 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t5 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t4 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t3 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t1 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance LUT4_17 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_16 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_15 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_14 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_13 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_12 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_11 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_10 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_9 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_8 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_7 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_6 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_5 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x0410"))) + (instance LUT4_4 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x1004"))) + (instance LUT4_3 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x0140"))) + (instance LUT4_2 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x4001"))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x4c32"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8001"))) + (instance pdp_ram_0_0_0 + (viewRef view1 + (cellRef PDPW16KC)) + (property MEM_LPC_FILE + (string "FIFO_DC_36x64_OutReg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_R + (string "0b001")) + (property CSDECODE_W + (string "0b001")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE + (string "OUTREG")) + (property DATA_WIDTH_R + (string "36")) + (property DATA_WIDTH_W + (string "36"))) + (instance FF_79 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_78 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_77 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_76 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_75 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_74 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_73 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_72 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_71 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_70 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_69 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_68 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_67 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_66 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_65 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_64 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_63 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_62 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_61 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_60 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_59 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_58 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_57 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_56 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_55 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_54 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_53 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_52 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_51 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_50 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_49 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_48 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_47 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_46 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_45 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_44 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_43 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_42 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_41 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_40 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_39 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_38 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_37 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_36 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_35 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_34 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_33 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_32 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_31 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_30 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_29 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_28 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_27 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_26 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_25 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_24 + (viewRef view1 + (cellRef FD1S3DX)) + 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(instanceRef FF_59)) + (portRef CK (instanceRef FF_30)) + (portRef CK (instanceRef FF_29)) + (portRef CK (instanceRef FF_28)) + (portRef CK (instanceRef FF_27)) + (portRef CK (instanceRef FF_26)) + (portRef CK (instanceRef FF_25)) + (portRef CK (instanceRef FF_24)) + (portRef CK (instanceRef FF_16)) + (portRef CK (instanceRef FF_15)) + (portRef CK (instanceRef FF_14)) + (portRef CK (instanceRef FF_13)) + (portRef CK (instanceRef FF_12)) + (portRef CK (instanceRef FF_11)) + (portRef CK (instanceRef FF_10)) + (portRef CK (instanceRef FF_8)) + (portRef CK (instanceRef FF_7)) + (portRef CK (instanceRef FF_6)) + (portRef CK (instanceRef FF_5)) + (portRef CK (instanceRef FF_4)) + (portRef CK (instanceRef FF_3)) + (portRef CK (instanceRef FF_2)) + (portRef CK (instanceRef FF_1)) + (portRef CK (instanceRef FF_0)))) + (net datain35 + (joined + (portRef (member Data 0)) + (portRef DI35 (instanceRef pdp_ram_0_0_0)))) + (net datain34 + (joined + (portRef (member Data 1)) + (portRef DI34 (instanceRef pdp_ram_0_0_0)))) + (net datain33 + (joined + (portRef (member Data 2)) + (portRef DI33 (instanceRef pdp_ram_0_0_0)))) + (net datain32 + (joined + (portRef (member Data 3)) + (portRef DI32 (instanceRef pdp_ram_0_0_0)))) + (net datain31 + (joined + (portRef (member Data 4)) + (portRef DI31 (instanceRef pdp_ram_0_0_0)))) + (net datain30 + (joined + (portRef (member Data 5)) + (portRef DI30 (instanceRef pdp_ram_0_0_0)))) + (net datain29 + (joined + (portRef (member Data 6)) + (portRef DI29 (instanceRef pdp_ram_0_0_0)))) + (net datain28 + (joined + (portRef (member Data 7)) + (portRef DI28 (instanceRef pdp_ram_0_0_0)))) + (net datain27 + (joined + (portRef (member Data 8)) + (portRef DI27 (instanceRef pdp_ram_0_0_0)))) + (net datain26 + (joined + (portRef (member Data 9)) + (portRef DI26 (instanceRef pdp_ram_0_0_0)))) + (net datain25 + (joined + (portRef (member Data 10)) + (portRef DI25 (instanceRef pdp_ram_0_0_0)))) + (net datain24 + (joined + (portRef (member Data 11)) + (portRef DI24 (instanceRef pdp_ram_0_0_0)))) + (net datain23 + (joined + (portRef (member Data 12)) + (portRef DI23 (instanceRef pdp_ram_0_0_0)))) + (net datain22 + (joined + (portRef (member Data 13)) + (portRef DI22 (instanceRef pdp_ram_0_0_0)))) + (net datain21 + (joined + (portRef (member Data 14)) + (portRef DI21 (instanceRef pdp_ram_0_0_0)))) + (net datain20 + (joined + (portRef (member Data 15)) + (portRef DI20 (instanceRef pdp_ram_0_0_0)))) + (net datain19 + (joined + (portRef (member Data 16)) + (portRef DI19 (instanceRef pdp_ram_0_0_0)))) + (net datain18 + (joined + (portRef (member Data 17)) + (portRef DI18 (instanceRef pdp_ram_0_0_0)))) + (net datain17 + (joined + (portRef (member Data 18)) + (portRef DI17 (instanceRef pdp_ram_0_0_0)))) + (net datain16 + (joined + (portRef (member Data 19)) + (portRef DI16 (instanceRef pdp_ram_0_0_0)))) + (net datain15 + (joined + (portRef (member Data 20)) + (portRef DI15 (instanceRef pdp_ram_0_0_0)))) + (net datain14 + (joined + (portRef (member Data 21)) + (portRef DI14 (instanceRef pdp_ram_0_0_0)))) + (net datain13 + (joined + (portRef (member Data 22)) + (portRef DI13 (instanceRef pdp_ram_0_0_0)))) + (net datain12 + (joined + (portRef (member Data 23)) + (portRef DI12 (instanceRef pdp_ram_0_0_0)))) + (net datain11 + (joined + (portRef (member Data 24)) + (portRef DI11 (instanceRef pdp_ram_0_0_0)))) + (net datain10 + (joined + (portRef (member Data 25)) + (portRef DI10 (instanceRef pdp_ram_0_0_0)))) + (net datain9 + (joined + (portRef (member Data 26)) + (portRef DI9 (instanceRef pdp_ram_0_0_0)))) + (net datain8 + (joined + (portRef (member Data 27)) + (portRef DI8 (instanceRef pdp_ram_0_0_0)))) + (net datain7 + (joined + (portRef (member Data 28)) + (portRef DI7 (instanceRef pdp_ram_0_0_0)))) + (net datain6 + (joined + (portRef (member Data 29)) + (portRef DI6 (instanceRef pdp_ram_0_0_0)))) + (net datain5 + (joined + (portRef (member Data 30)) + (portRef DI5 (instanceRef pdp_ram_0_0_0)))) + (net datain4 + (joined + (portRef (member Data 31)) + (portRef DI4 (instanceRef pdp_ram_0_0_0)))) + (net datain3 + (joined + (portRef (member Data 32)) + (portRef DI3 (instanceRef pdp_ram_0_0_0)))) + (net datain2 + (joined + (portRef (member Data 33)) + (portRef DI2 (instanceRef pdp_ram_0_0_0)))) + (net datain1 + (joined + (portRef (member Data 34)) + (portRef DI1 (instanceRef pdp_ram_0_0_0)))) + (net datain0 + (joined + (portRef (member Data 35)) + (portRef DI0 (instanceRef pdp_ram_0_0_0)))))))) + (design FIFO_DC_36x64_OutReg + (cellRef FIFO_DC_36x64_OutReg + (libraryRef ORCLIB))) +) diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.ipx b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.ipx new file mode 100644 index 0000000..b317471 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.jhd b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.jhd new file mode 100644 index 0000000..e69de29 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.lpc b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.lpc new file mode 100644 index 0000000..801d66d --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=FIFO_DC_36x64_OutReg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/17/2015 +Time=11:31:34 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=64 +Width=36 +RDepth=64 +RWidth=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=56 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n FIFO_DC_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 6 -data_width 36 -num_words 64 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 56 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.sort b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.sort new file mode 100644 index 0000000..762a807 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.sort @@ -0,0 +1 @@ +FIFO_DC_36x64_OutReg.vhd diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.srp b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.srp new file mode 100644 index 0000000..fdf3f09 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.srp @@ -0,0 +1,42 @@ +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:31:34 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 6 -data_width 36 -num_words 64 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 56 + Circuit name : FIFO_DC_36x64_OutReg + Module type : ebfifo + Module Version : 5.7 + Ports : + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[35:0], Empty, Full, AlmostFull + I/O buffer : not inserted + EDIF output : FIFO_DC_36x64_OutReg.edn + VHDL output : FIFO_DC_36x64_OutReg.vhd + VHDL template : FIFO_DC_36x64_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_DC_36x64_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_DC_36x64_OutReg.srp + Element Usage : + AGEB2 : 12 + AND2 : 2 + CU2 : 12 + FADD2B : 9 + FD1P3BX : 4 + FD1P3DX : 45 + FD1S3BX : 1 + FD1S3DX : 30 + INV : 2 + OR2 : 1 + ROM16X1A : 18 + XOR2 : 12 + PDPW16KC : 1 + Estimated Resource Usage: + LUT : 99 + EBR : 1 + Reg : 80 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd new file mode 100644 index 0000000..831549f --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd @@ -0,0 +1,1049 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 36 -depth 64 -rdata_width 36 -regout -no_enable -pe -1 -pf 56 + +-- Fri Apr 17 11:31:34 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_DC_36x64_OutReg is + port ( + Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end FIFO_DC_36x64_OutReg; + +architecture Structure of FIFO_DC_36x64_OutReg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal co3: std_logic; + signal co2: std_logic; + signal wcount_6: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal co3_1: std_logic; + signal co2_1: std_logic; + signal rcount_6: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co1_4: std_logic; + signal iaf_setcount_6: std_logic; + signal co3_2: std_logic; + signal co2_4: std_logic; + signal af_setcount_6: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal rcount_w2: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal af_setcount_4: std_logic; + signal af_setcount_5: std_logic; + signal co2_5: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_DC_36x64_OutReg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t14: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t13: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t12: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t11: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t10: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t9: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t8: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t7: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t6: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t4: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t3: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t2: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t1: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t0: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_gcount_r26, + DO0=>w_g2b_xor_cluster_0); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>wcount_r5, DO0=>wcount_r2); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r0); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_0); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>rcount_w5, DO0=>rcount_w2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0); + + LUT4_5: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_4: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_3: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_6, AD2=>wcount_6, AD1=>r_gcount_w26, + AD0=>wptr_6, DO0=>af_set_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_6, AD2=>wcount_6, AD1=>r_gcount_w26, + AD0=>wptr_6, DO0=>af_set_cmp_clr); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, + ADW5=>wptr_5, ADW6=>scuba_vlo, ADW7=>scuba_vlo, + ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi, + BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, + CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, + ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, + ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, + ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, + ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo, + CER=>scuba_vhi, CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), + DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17)); + + FF_79: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_78: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_77: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_76: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_75: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_74: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_73: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_72: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_71: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_70: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_69: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_68: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_67: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_66: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_65: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_64: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_63: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_62: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_61: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_60: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_59: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_58: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_57: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_56: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_55: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_54: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_53: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_52: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_51: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_50: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_49: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_48: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_47: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_46: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_45: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_44: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_43: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_42: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_41: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_40: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_39: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_38: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_37: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_36: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_35: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_34: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_33: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_32: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_31: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_30: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_29: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_28: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_27: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_26: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_25: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_24: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_23: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_22: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_21: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_20: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_19: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_18: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_17: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_16: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_15: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_14: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_13: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_12: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_11: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_10: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_9: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_8: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_7: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); + + FF_6: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); + + FF_5: FD1P3DX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_2); + + FF_4: FD1P3BX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_3: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_2: FD1P3DX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_5); + + FF_1: FD1P3DX + port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_6); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3, + NC0=>iwcount_6, NC1=>open); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_1, + NC0=>ircount_6, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>w_g2b_xor_cluster_0, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co2_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>r_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co2_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, + CO=>co2_4, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); + + af_set_ctr_3: CU2 + port map (CI=>co2_4, PC0=>af_setcount_6, PC1=>scuba_vlo, + CO=>co3_2, NC0=>iaf_setcount_6, NC1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>r_g2b_xor_cluster_0, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_5, GE=>co2_5); + + af_set_cmp_3: AGEB2 + port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr, + B1=>scuba_vlo, CI=>co2_5, GE=>af_set_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_DC_36x64_OutReg is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg_generate.log b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg_generate.log new file mode 100644 index 0000000..3e9aa2a --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg_generate.log @@ -0,0 +1,48 @@ +Starting process: module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 17 11:31:34 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 6 -data_width 36 -num_words 64 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 56 + Circuit name : FIFO_DC_36x64_OutReg + Module type : ebfifo + Module Version : 5.7 + Ports : + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[35:0], Empty, Full, AlmostFull + I/O buffer : not inserted + EDIF output : FIFO_DC_36x64_OutReg.edn + VHDL output : FIFO_DC_36x64_OutReg.vhd + VHDL template : FIFO_DC_36x64_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_DC_36x64_OutReg_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : FIFO_DC_36x64_OutReg.srp + Estimated Resource Usage: + LUT : 99 + EBR : 1 + Reg : 80 + +END SCUBA Module Synthesis + +File: FIFO_DC_36x64_OutReg.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg_tmpl.vhd new file mode 100644 index 0000000..0770222 --- /dev/null +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +-- Fri Apr 17 11:31:34 2015 + +-- parameterized module component declaration +component FIFO_DC_36x64_OutReg + port (Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; Full: out std_logic; + AlmostFull: out std_logic); +end component; + +-- parameterized module component instance +__ : FIFO_DC_36x64_OutReg + port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(35 downto 0)=>__, Empty=>__, + Full=>__, AlmostFull=>__); diff --git a/base/cores/ecp3/FIFO/generate_core.tcl b/base/cores/ecp3/FIFO/generate_core.tcl index 1480465..a774abe 100644 --- a/base/cores/ecp3/FIFO/generate_core.tcl +++ b/base/cores/ecp3/FIFO/generate_core.tcl @@ -85,7 +85,7 @@ set Para(install_dir) $env(TOOLRTF) set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set scuba "$Para(FPGAPath)/scuba" -set modulename "FIFO_36x128_OutReg" +set modulename "FIFO_36x64_OutReg" set lang "vhdl" set lpcfile "$Para(sbp_path)/$modulename.lpc" set arch "ep5c00" diff --git a/base/cores/ecp3/FIFO/generate_ngd.tcl b/base/cores/ecp3/FIFO/generate_ngd.tcl index ccb3988..b25353c 100644 --- a/base/cores/ecp3/FIFO/generate_ngd.tcl +++ b/base/cores/ecp3/FIFO/generate_ngd.tcl @@ -50,7 +50,7 @@ set Para(install_dir) $env(TOOLRTF) set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" -set Para(ModuleName) "FIFO_36x128_OutReg" +set Para(ModuleName) "FIFO_36x64_OutReg" set Para(Module) "FIFO" set Para(libname) latticeecp3 set Para(arch_name) ep5c00 diff --git a/base/cores/ecp3/FIFO/msg_file.log b/base/cores/ecp3/FIFO/msg_file.log index 454a544..9e909af 100644 --- a/base/cores/ecp3/FIFO/msg_file.log +++ b/base/cores/ecp3/FIFO/msg_file.log @@ -1,5 +1,5 @@ SCUBA, Version Diamond (64-bit) 3.4.0.80 -Mon Apr 13 14:41:29 2015 +Fri Apr 17 11:33:43 2015 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -9,25 +9,25 @@ Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf -1 - Circuit name : FIFO_36x128_OutReg + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf -1 + Circuit name : FIFO_36x64_OutReg Module type : fifoblk Module Version : 5.0 Ports : Inputs : Data[35:0], Clock, WrEn, RdEn, Reset Outputs : Q[35:0], Empty, Full I/O buffer : not inserted - EDIF output : FIFO_36x128_OutReg.edn - VHDL output : FIFO_36x128_OutReg.vhd - VHDL template : FIFO_36x128_OutReg_tmpl.vhd - VHDL testbench : tb_FIFO_36x128_OutReg_tmpl.vhd + EDIF output : FIFO_36x64_OutReg.edn + VHDL output : FIFO_36x64_OutReg.vhd + VHDL template : FIFO_36x64_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_36x64_OutReg_tmpl.vhd VHDL purpose : for synthesis and simulation Bus notation : big endian - Report output : FIFO_36x128_OutReg.srp + Report output : FIFO_36x64_OutReg.srp Estimated Resource Usage: LUT : 60 EBR : 1 - Reg : 26 + Reg : 23 END SCUBA Module Synthesis diff --git a/base/cores/ecp3/FIFO/tb_FIFO_36x32_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/tb_FIFO_36x32_OutReg_tmpl.vhd new file mode 100644 index 0000000..91bff45 --- /dev/null +++ b/base/cores/ecp3/FIFO/tb_FIFO_36x32_OutReg_tmpl.vhd @@ -0,0 +1,89 @@ +-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80 +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +use IEEE.math_real.all; + +use IEEE.numeric_std.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component FIFO_36x32_OutReg + port (Data : in std_logic_vector(35 downto 0); + Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; Q : out std_logic_vector(35 downto 0); + Empty: out std_logic; Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(35 downto 0) := (others => '0'); + signal Clock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal Q : std_logic_vector(35 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : FIFO_36x32_OutReg + port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn, + Reset => Reset, Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + for i in 0 to 36 loop + wait until Clock'event and Clock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + Clock <= not Clock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 36 loop + wait until Clock'event and Clock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 34 loop + wait until Clock'event and Clock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/base/cores/ecp3/FIFO/tb_FIFO_36x64_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/tb_FIFO_36x64_OutReg_tmpl.vhd new file mode 100644 index 0000000..094836a --- /dev/null +++ b/base/cores/ecp3/FIFO/tb_FIFO_36x64_OutReg_tmpl.vhd @@ -0,0 +1,89 @@ +-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80 +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +use IEEE.math_real.all; + +use IEEE.numeric_std.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component FIFO_36x64_OutReg + port (Data : in std_logic_vector(35 downto 0); + Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; Q : out std_logic_vector(35 downto 0); + Empty: out std_logic; Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(35 downto 0) := (others => '0'); + signal Clock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal Q : std_logic_vector(35 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : FIFO_36x64_OutReg + port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn, + Reset => Reset, Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + for i in 0 to 68 loop + wait until Clock'event and Clock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + Clock <= not Clock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 68 loop + wait until Clock'event and Clock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 66 loop + wait until Clock'event and Clock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/base/cores/ecp3/FIFO/tb_FIFO_DC_36x128_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/tb_FIFO_DC_36x128_OutReg_tmpl.vhd new file mode 100644 index 0000000..a520c17 --- /dev/null +++ b/base/cores/ecp3/FIFO/tb_FIFO_DC_36x128_OutReg_tmpl.vhd @@ -0,0 +1,107 @@ +-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80 +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +use IEEE.math_real.all; + +use IEEE.numeric_std.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component FIFO_DC_36x128_OutReg + port (Data : in std_logic_vector(35 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(35 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostFull: out std_logic + ); + end component; + + signal Data : std_logic_vector(35 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(35 downto 0); + signal Empty: std_logic; + signal Full: std_logic; + signal AlmostFull: std_logic; +begin + u1 : FIFO_DC_36x128_OutReg + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full, AlmostFull => AlmostFull + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 131 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 131 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 131 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/base/cores/ecp3/FIFO/tb_FIFO_DC_36x32_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/tb_FIFO_DC_36x32_OutReg_tmpl.vhd new file mode 100644 index 0000000..865fdaf --- /dev/null +++ b/base/cores/ecp3/FIFO/tb_FIFO_DC_36x32_OutReg_tmpl.vhd @@ -0,0 +1,107 @@ +-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80 +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +use IEEE.math_real.all; + +use IEEE.numeric_std.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component FIFO_DC_36x32_OutReg + port (Data : in std_logic_vector(35 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(35 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostFull: out std_logic + ); + end component; + + signal Data : std_logic_vector(35 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(35 downto 0); + signal Empty: std_logic; + signal Full: std_logic; + signal AlmostFull: std_logic; +begin + u1 : FIFO_DC_36x32_OutReg + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full, AlmostFull => AlmostFull + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 35 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 35 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 35 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/base/cores/ecp3/FIFO/tb_FIFO_DC_36x64_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/tb_FIFO_DC_36x64_OutReg_tmpl.vhd new file mode 100644 index 0000000..f0a29c8 --- /dev/null +++ b/base/cores/ecp3/FIFO/tb_FIFO_DC_36x64_OutReg_tmpl.vhd @@ -0,0 +1,107 @@ +-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80 +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +use IEEE.math_real.all; + +use IEEE.numeric_std.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component FIFO_DC_36x64_OutReg + port (Data : in std_logic_vector(35 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(35 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostFull: out std_logic + ); + end component; + + signal Data : std_logic_vector(35 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(35 downto 0); + signal Empty: std_logic; + signal Full: std_logic; + signal AlmostFull: std_logic; +begin + u1 : FIFO_DC_36x64_OutReg + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full, AlmostFull => AlmostFull + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 67 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 67 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 67 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test;