From: hadeshyp Date: Mon, 9 Aug 2010 08:58:59 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~195 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=fa363815754b797130e82ffe06498eeb44f269f0;p=trbnet.git *** empty log message *** --- diff --git a/basics/pulse_sync.vhd b/basics/pulse_sync.vhd new file mode 100644 index 0000000..e56efeb --- /dev/null +++ b/basics/pulse_sync.vhd @@ -0,0 +1,72 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; + + +entity pulse_sync is +port( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic +); +end; + +architecture behavioral of pulse_sync is + +-- normal signals +signal toggle_ff : std_logic; +signal sync_q : std_logic; +signal sync_qq : std_logic; +signal sync_qqq : std_logic; +signal pulse_b : std_logic; + +begin + +-- toggle flip flop in clock domain A +THE_TOGGLE_FF_PROC: process( clk_a_in ) +begin + if( rising_edge(clk_a_in) ) then + if ( reset_a_in = '1' ) then + toggle_ff <= '0'; + elsif( pulse_a_in = '1' ) then + toggle_ff <= not toggle_ff; + end if; + end if; +end process THE_TOGGLE_FF_PROC; + +-- synchronizing stage for clock domain B +THE_SYNC_STAGE_PROC: process( clk_b_in ) +begin + if( rising_edge(clk_b_in) ) then + if( reset_b_in = '1' ) then + sync_q <= '0'; sync_qq <= '0'; sync_qqq <= '0'; + else + sync_qqq <= sync_qq; + sync_qq <= sync_q; + sync_q <= toggle_ff; + end if; + end if; +end process THE_SYNC_STAGE_PROC; + +-- output pulse registering +THE_OUTPUT_PULSE_PROC: process( clk_b_in ) +begin + if( rising_edge(clk_b_in) ) then + if( reset_b_in = '1' ) then + pulse_b <= '0'; + else + pulse_b <= sync_qqq xor sync_qq; + end if; + end if; +end process THE_OUTPUT_PULSE_PROC; + +-- output signals +pulse_b_out <= pulse_b; + +end behavioral; diff --git a/lattice/ecp2m/lattice_ecp2m_fifo_16x16_dualport.lpc b/lattice/ecp2m/lattice_ecp2m_fifo_16x16_dualport.lpc new file mode 100644 index 0000000..ea2b0c7 --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo_16x16_dualport.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=lattice_ecp2m_fifo_16x16_dualport +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=08/09/2010 +Time=10:10:58 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=16 +Width=16 +RDepth=16 +RWidth=16 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=7 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/lattice/ecp2m/lattice_ecp2m_fifo_16x16_dualport.vhd b/lattice/ecp2m/lattice_ecp2m_fifo_16x16_dualport.vhd new file mode 100644 index 0000000..e08eff5 --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo_16x16_dualport.vhd @@ -0,0 +1,1171 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20) +-- Module Version: 5.4 +--/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 16 -depth 16 -rdata_width 16 -no_enable -pe -1 -pf 7 -e + +-- Mon Aug 9 10:10:58 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity lattice_ecp2m_fifo_16x16_dualport is + port ( + Data: in std_logic_vector(15 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(15 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end lattice_ecp2m_fifo_16x16_dualport; + +architecture Structure of lattice_ecp2m_fifo_16x16_dualport is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal wptr_4: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal rptr_4: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal co2: std_logic; + signal wcount_4: std_logic; + signal co1: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal co2_1: std_logic; + signal rcount_4: std_logic; + signal co1_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal co2_2: std_logic; + signal af_setcount_4: std_logic; + signal co1_4: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vlo: std_logic; + signal rdataout15: std_logic; + signal rdataout14: std_logic; + signal rdataout13: std_logic; + signal rdataout12: std_logic; + signal rdataout11: std_logic; + signal rdataout10: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rptr_3: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal rptr_0: std_logic; + signal dec0_wre3: std_logic; + signal wptr_3: std_logic; + signal wptr_2: std_logic; + signal wptr_1: std_logic; + signal wptr_0: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4A + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + attribute initval : string; + attribute GSR : string; + attribute initval of LUT4_14 : label is "0x8000"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x0410"; + attribute initval of LUT4_4 : label is "0x1004"; + attribute initval of LUT4_3 : label is "0x0140"; + attribute initval of LUT4_2 : label is "0x4001"; + attribute initval of LUT4_1 : label is "0x4c32"; + attribute initval of LUT4_0 : label is "0x8001"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t10: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t9: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t8: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t7: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t6: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t5: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t4: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t3: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t2: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t0: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8000") + -- synopsys translate_on + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_0); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_0); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4c32") + -- synopsys translate_on + port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>wptr_4, DO0=>af_set_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8001") + -- synopsys translate_on + port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>wptr_4, DO0=>af_set_cmp_clr); + + FF_73: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_58: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_49: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_48: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_47: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_46: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_45: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_44: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_43: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(0)); + + FF_42: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(1)); + + FF_41: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(2)); + + FF_40: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(3)); + + FF_39: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(4)); + + FF_38: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(5)); + + FF_37: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(6)); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(7)); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(8)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(9)); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(10)); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(11)); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(12)); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(13)); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(14)); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(15)); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_7: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_0); + + FF_4: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_1); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_2); + + FF_2: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2, + NC0=>iwcount_4, NC1=>open); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>ircount_4, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co1_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co1_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>scuba_vlo, + CO=>co2_2, NC0=>iaf_setcount_4, NC1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr, + B1=>scuba_vlo, CI=>co1_5, GE=>af_set_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + fifo_pfu_0_0: DPR16X4A + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12, + DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15); + + fifo_pfu_0_1: DPR16X4A + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8, + DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11); + + fifo_pfu_0_2: DPR16X4A + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5, + DO2=>rdataout6, DO3=>rdataout7); + + fifo_pfu_0_3: DPR16X4A + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1, + DO2=>rdataout2, DO3=>rdataout3); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of lattice_ecp2m_fifo_16x16_dualport is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/lattice_ecp2m_fifo_16x8_dualport.lpc b/lattice/ecp2m/lattice_ecp2m_fifo_16x8_dualport.lpc new file mode 100644 index 0000000..a917b4c --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo_16x8_dualport.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=lattice_ecp2m_fifo_16x8_dualport +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=08/09/2010 +Time=10:09:29 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=16 +Width=16 +RDepth=16 +RWidth=16 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=7 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/lattice/ecp2m/lattice_ecp2m_fifo_16x8_dualport.vhd b/lattice/ecp2m/lattice_ecp2m_fifo_16x8_dualport.vhd new file mode 100644 index 0000000..c0786c7 --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo_16x8_dualport.vhd @@ -0,0 +1,1171 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20) +-- Module Version: 5.4 +--/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 16 -depth 16 -rdata_width 16 -no_enable -pe -1 -pf 7 -e + +-- Mon Aug 9 10:09:29 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity lattice_ecp2m_fifo_16x8_dualport is + port ( + Data: in std_logic_vector(15 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(15 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end lattice_ecp2m_fifo_16x8_dualport; + +architecture Structure of lattice_ecp2m_fifo_16x8_dualport is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal wptr_4: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal rptr_4: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal co2: std_logic; + signal wcount_4: std_logic; + signal co1: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal co2_1: std_logic; + signal rcount_4: std_logic; + signal co1_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal co2_2: std_logic; + signal af_setcount_4: std_logic; + signal co1_4: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vlo: std_logic; + signal rdataout15: std_logic; + signal rdataout14: std_logic; + signal rdataout13: std_logic; + signal rdataout12: std_logic; + signal rdataout11: std_logic; + signal rdataout10: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rptr_3: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal rptr_0: std_logic; + signal dec0_wre3: std_logic; + signal wptr_3: std_logic; + signal wptr_2: std_logic; + signal wptr_1: std_logic; + signal wptr_0: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4A + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + attribute initval : string; + attribute GSR : string; + attribute initval of LUT4_14 : label is "0x8000"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x0410"; + attribute initval of LUT4_4 : label is "0x1004"; + attribute initval of LUT4_3 : label is "0x0140"; + attribute initval of LUT4_2 : label is "0x4001"; + attribute initval of LUT4_1 : label is "0x4c32"; + attribute initval of LUT4_0 : label is "0x8001"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t10: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t9: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t8: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t7: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t6: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t5: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t4: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t3: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t2: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t0: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8000") + -- synopsys translate_on + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_0); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_0); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4c32") + -- synopsys translate_on + port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>wptr_4, DO0=>af_set_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8001") + -- synopsys translate_on + port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>wptr_4, DO0=>af_set_cmp_clr); + + FF_73: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_58: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_49: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_48: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_47: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_46: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_45: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_44: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_43: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(0)); + + FF_42: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(1)); + + FF_41: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(2)); + + FF_40: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(3)); + + FF_39: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(4)); + + FF_38: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(5)); + + FF_37: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(6)); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(7)); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(8)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(9)); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(10)); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(11)); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(12)); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(13)); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(14)); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>Q(15)); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_7: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_0); + + FF_4: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_1); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_2); + + FF_2: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2, + NC0=>iwcount_4, NC1=>open); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>ircount_4, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co1_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co1_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>scuba_vlo, + CO=>co2_2, NC0=>iaf_setcount_4, NC1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr, + B1=>scuba_vlo, CI=>co1_5, GE=>af_set_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + fifo_pfu_0_0: DPR16X4A + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12, + DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15); + + fifo_pfu_0_1: DPR16X4A + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8, + DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11); + + fifo_pfu_0_2: DPR16X4A + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5, + DO2=>rdataout6, DO3=>rdataout7); + + fifo_pfu_0_3: DPR16X4A + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1, + DO2=>rdataout2, DO3=>rdataout3); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of lattice_ecp2m_fifo_16x8_dualport is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/media_interfaces/trb_net16_rx_control.vhd b/media_interfaces/trb_net16_rx_control.vhd new file mode 100644 index 0000000..d4b7d20 --- /dev/null +++ b/media_interfaces/trb_net16_rx_control.vhd @@ -0,0 +1,366 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +--use work.trb_net_components.all; + +entity trb_net16_rx_control is +port( + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- raw data from SerDes receive path + CLK_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + RX_CV_IN : in std_logic; + RX_ALLOW_IN : in std_logic; + -- media interface + SYSCLK_IN : in std_logic; -- 100MHz master clock + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + -- request retransmission in case of error while receiving + REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse + REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- command decoding + START_RETRANSMIT_OUT : out std_logic; + START_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Status signals + PACKET_TIMEOUT_OUT : out std_logic; + -- Debugging + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture arch of trb_net16_rx_control is + +-- components +component trb_net16_rx_full_packets is +port( + -- Resets & clocks + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + -- FIFO signals + FIFO_READ_OUT : out std_logic; + FIFO_RCNT_IN : in std_logic_vector(8 downto 0); + FIFO_RESET_OUT : out std_logic; + -- Media Interface + MED_READ_IN : in std_logic; + MED_DATAREADY_OUT : out std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + UPDATE_OUT : out std_logic; + PKT_IN_TRANSIT_OUT : out std_logic; + -- Status signals + RX_ALLOW_IN : in std_logic; + RX_LD_DATA_CTR_IN : in std_logic; + RX_DATA_CTR_VAL_IN : in std_logic_vector(7 downto 0); + RX_DATA_CTR_OUT : out std_logic_vector(7 downto 0); + PACKET_TIMEOUT_OUT : out std_logic; + -- Debug signals + BSM_OUT : out std_logic_vector(3 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component trb_net16_rx_full_packets; + +component trb_net_fifo_8bit_16bit_bram_dualport is +port( + READ_CLOCK_IN : in std_logic; + WRITE_CLOCK_IN : in std_logic; + READ_ENABLE_IN : in std_logic; + WRITE_ENABLE_IN : in std_logic; + FIFO_GSR_IN : in std_logic; + WRITE_DATA_IN : in std_logic_vector(7 downto 0); + READ_DATA_OUT : out std_logic_vector(15 downto 0); + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic; + WCNT_OUT : out std_logic_vector(9 downto 0); + RCNT_OUT : out std_logic_vector(8 downto 0) +); +end component trb_net_fifo_8bit_16bit_bram_dualport; + +component pulse_sync is +port( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic +); +end component pulse_sync; + +-- state declarations +type STATES is (IDLE, CHK_PKT, RX_FAIL); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- normal signals +signal update : std_logic; +signal med_dataready : std_logic; +signal med_data : std_logic_vector(15 downto 0); +signal med_packet_num : std_logic_vector(2 downto 0); +signal packet_timeout : std_logic; +signal debug_rfp : std_logic_vector(15 downto 0); + +signal buf_rx_data : std_logic_vector(7 downto 0); +signal buf_rx_k : std_logic; +signal buf_rx_cv : std_logic; + +signal fifo_wr_en : std_logic; +signal fifo_rd_en : std_logic; +signal fifo_wr_data : std_logic_vector(7 downto 0); +signal fifo_rd_data : std_logic_vector(15 downto 0); +signal fifo_reset : std_logic; +signal fifo_rcnt : std_logic_vector(8 downto 0); +signal fifo_rst : std_logic; + +signal is_idle_word : std_logic; +signal rx_starting : std_logic; +signal send_reset_words : std_logic; +signal make_trbnet_reset : std_logic; +signal reset_word_cnt : unsigned(4 downto 0); + +signal comma_idle_x : std_logic; +signal comma_idle : std_logic; -- 0xBC +signal comma_reset_x : std_logic; +signal comma_reset : std_logic; -- 0xFE +signal comma_errordetd_x : std_logic; +signal comma_errordetd : std_logic; -- 0xF7 +signal comma_startoftx_x : std_logic; +signal comma_startoftx : std_logic; -- 0xFB +signal comma_invalid_x : std_logic; +signal comma_invalid : std_logic; -- all other commas are invalid! + +signal request_position : std_logic_vector(7 downto 0); + +signal start_retransmit : std_logic; +signal start_position : std_logic_vector(7 downto 0); + +signal ld_rx_position : std_logic; +signal rx_position : std_logic_vector(7 downto 0); + +signal pkt_in_transit : std_logic; + +signal debug : std_logic_vector(31 downto 0); + +begin + +---------------------------------------------------------------------- +-- decoding of raw commas +---------------------------------------------------------------------- +comma_idle_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"bc") ) else '0'; +comma_reset_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"fe") ) else '0'; +comma_errordetd_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"f7") ) else '0'; +comma_startoftx_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"fb") ) else '0'; +comma_invalid_x <= '1' when ( ( (buf_rx_k = '1') and + (comma_idle ='0') and (comma_reset = '0') and + (comma_errordetd = '0') and (comma_startoftx = '0') ) or + (buf_rx_cv = '1') ) + else '0'; + +---------------------------------------------------------------------- +-- StartOfTransmission comma handling +---------------------------------------------------------------------- +-- store the RX position raw data +THE_RX_POSITION_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( comma_startoftx = '1' ) then + rx_position <= buf_rx_data; + end if; + end if; +end process THE_RX_POSITION_PROC; + +-- clock domain transfer for internal RX data counter +THE_LD_PULSE_SYNC: pulse_sync +port map( + CLK_A_IN => CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => comma_startoftx, + CLK_B_IN => SYSCLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => ld_rx_position +); + +---------------------------------------------------------------------- +-- ErrorDetected comma handling +---------------------------------------------------------------------- + +-- store the RX position raw data +THE_START_POSITION_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( comma_errordetd = '1' ) then + start_position <= buf_rx_data; + end if; + end if; +end process THE_START_POSITION_PROC; + +-- clock domain transfer for internal RX data counter +THE_RT_PULSE_SYNC: pulse_sync +port map( + CLK_A_IN => CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => comma_errordetd, + CLK_B_IN => SYSCLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => start_retransmit +); + +---------------------------------------------------------------------- +-- FIFO write process, only data bytes are stored (Jan's work) +---------------------------------------------------------------------- +THE_WRITE_RX_FIFO_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + -- pipeline comma detection + comma_idle <= comma_idle_x; + comma_reset <= comma_reset_x; + comma_errordetd <= comma_errordetd_x; + comma_startoftx <= comma_startoftx_x; + -- pipeline data + buf_rx_data <= RX_DATA_IN; + buf_rx_k <= RX_K_IN; + buf_rx_cv <= RX_CV_IN; + if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then + fifo_wr_en <= '0'; + is_idle_word <= '1'; + rx_starting <= '1'; + else + fifo_wr_data <= buf_rx_data; + if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then + fifo_wr_en <= '1'; + else + fifo_wr_en <= '0'; + end if; + if ( buf_rx_k = '1' ) then + is_idle_word <= '1'; + rx_starting <= '0'; + elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then + is_idle_word <= '0'; + end if; + end if; + end if; +end process THE_WRITE_RX_FIFO_PROC; + +---------------------------------------------------------------------- +-- TRBnet reset handling (handles 0xFE comma) +---------------------------------------------------------------------- +THE_CNT_RESET_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + reset_word_cnt <= (others => '0'); + else + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + if( comma_reset = '1' ) then + if( reset_word_cnt(4) = '0' ) then + reset_word_cnt <= reset_word_cnt + 1; + else + send_reset_words <= '1'; + end if; + else + reset_word_cnt <= (others => '0'); + make_trbnet_reset <= reset_word_cnt(4); + end if; + end if; + end if; +end process; + +---------------------------------------------------------------------- +-- the RX FIFO itself +---------------------------------------------------------------------- +THE_RX_FIFO: trb_net_fifo_8bit_16bit_bram_dualport +port map( + READ_CLOCK_IN => SYSCLK_IN, + WRITE_CLOCK_IN => CLK_IN, + READ_ENABLE_IN => fifo_rd_en, + WRITE_ENABLE_IN => fifo_wr_en, + FIFO_GSR_IN => fifo_reset, + WRITE_DATA_IN => fifo_wr_data, + READ_DATA_OUT => fifo_rd_data, + FULL_OUT => open, + EMPTY_OUT => open, + WCNT_OUT => open, -- not needed + RCNT_OUT => fifo_rcnt +); + +fifo_reset <= RESET_IN or QUAD_RST_IN or not RX_ALLOW_IN or fifo_rst; + +---------------------------------------------------------------------- +-- RX packet state machine +---------------------------------------------------------------------- +THE_RX_FULL_PACKETS: trb_net16_rx_full_packets +port map( + -- Resets & clocks + SYSCLK_IN => SYSCLK_IN, + RESET_IN => RESET_IN, + -- FIFO signals + FIFO_READ_OUT => fifo_rd_en, + FIFO_RCNT_IN => fifo_rcnt, + FIFO_RESET_OUT => fifo_rst, + -- Media Interface + MED_READ_IN => MED_READ_IN, + MED_DATAREADY_OUT => med_dataready, + MED_PACKET_NUM_OUT => med_packet_num, + UPDATE_OUT => update, + PKT_IN_TRANSIT_OUT => pkt_in_transit, -- BUG + -- Status signals + RX_ALLOW_IN => RX_ALLOW_IN, + RX_LD_DATA_CTR_IN => ld_rx_position, + RX_DATA_CTR_VAL_IN => rx_position, + RX_DATA_CTR_OUT => request_position, + PACKET_TIMEOUT_OUT => packet_timeout, + -- Debug signals + BSM_OUT => open, + DBG_OUT => debug_rfp +); + +THE_SYNC_SYSCLK_PROC: process( SYSCLK_IN ) +begin + if( rising_edge(SYSCLK_IN) ) then + if( update = '1' ) then + med_data <= fifo_rd_data; + end if; + end if; +end process THE_SYNC_SYSCLK_PROC; + +---------------------------------------------------------------------- +-- Debug signals +---------------------------------------------------------------------- +debug(31 downto 16) <= debug_rfp; +debug(15 downto 1) <= (others => '0'); +debug(0) <= pkt_in_transit; + +---------------------------------------------------------------------- +-- Output signals +---------------------------------------------------------------------- +SEND_RESET_WORDS_OUT <= send_reset_words; +MAKE_TRBNET_RESET_OUT <= make_trbnet_reset; +PACKET_TIMEOUT_OUT <= packet_timeout; + +MED_DATAREADY_OUT <= med_dataready; +MED_DATA_OUT <= med_data; +MED_PACKET_NUM_OUT <= med_packet_num; + +-- used by internal logic +REQUEST_RETRANSMIT_OUT <= '0'; +REQUEST_POSITION_OUT <= request_position; + +-- forwarding of retransmit request +START_RETRANSMIT_OUT <= start_retransmit; +START_POSITION_OUT <= start_position; + +DEBUG_OUT <= debug; + +end architecture; \ No newline at end of file diff --git a/media_interfaces/trb_net16_rx_full_packets.vhd b/media_interfaces/trb_net16_rx_full_packets.vhd new file mode 100644 index 0000000..3d2de70 --- /dev/null +++ b/media_interfaces/trb_net16_rx_full_packets.vhd @@ -0,0 +1,377 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +--use work.trb_net_components.all; + +entity trb_net16_rx_full_packets is +port( + -- Resets & clocks + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + -- FIFO signals + FIFO_READ_OUT : out std_logic; + FIFO_RCNT_IN : in std_logic_vector(8 downto 0); + FIFO_RESET_OUT : out std_logic; + -- Media Interface + MED_READ_IN : in std_logic; + MED_DATAREADY_OUT : out std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + UPDATE_OUT : out std_logic; + PKT_IN_TRANSIT_OUT : out std_logic; -- full packet received and in transmission to media interface + -- Status signals + RX_ALLOW_IN : in std_logic; + RX_LD_DATA_CTR_IN : in std_logic; + RX_DATA_CTR_VAL_IN : in std_logic_vector(7 downto 0); + RX_DATA_CTR_OUT : out std_logic_vector(7 downto 0); + PACKET_TIMEOUT_OUT : out std_logic; + -- Debug signals + BSM_OUT : out std_logic_vector(3 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end entity trb_net16_rx_full_packets; + + +architecture behavioral of trb_net16_rx_full_packets is + +-- State description: +-- +-- IDLE: wait for any data to be written into the FIFO +-- RD1 : first word prefetch +-- RD2 : first word output reg, second word prefetch, wait state for full packet in FIFO +-- RDI : generates initial dataready_out, wait state for handshake of first data word +-- RD3 : second word output reg, third word prefetch, wait state for handshake of second data word +-- RD4 : third word output reg, fourth word prefetch, wait state for handshake of third data word +-- RD5 : fourth word output reg, fifth word prefetch, wait state for handshake of forth data word +-- => decision: continous data stream or stalling as FIFO runs empty! +-- RDO : fifth word output reg, wait state for handshake of fifth data word, can also resume transmission +-- if new data is available in FIFO +-- RDW : fifth word output reg, first word prefetch, wait state for handshake of fifth data word, +-- continue data stream or stall if for complete packet + +-- state declarations +type STATES is (IDLE, RD1, RD2, RDI, RD3, RD4, RD5, RDO, RDW, TOC, CLEAN); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- normal signals +signal bsm_x : std_logic_vector(3 downto 0); +signal bsm : std_logic_vector(3 downto 0); +signal update_x : std_logic; +signal med_dataready_x : std_logic; +signal med_dataready : std_logic; +signal pkt_timeout_x : std_logic; +signal pkt_timeout : std_logic; +signal inc_data_x : std_logic; +signal inc_data : std_logic; +signal transit_x : std_logic; +signal transit : std_logic; + +signal fifo_rd_en_x : std_logic; +signal fifo_rcnt : unsigned(8 downto 0); +signal fifo_rst_x : std_logic; +signal fifo_rst : std_logic; + +signal rx_counter : unsigned(2 downto 0); + +signal timeout_ctr : unsigned(9 downto 0); +signal rst_toc_x : std_logic; +signal rst_toc : std_logic; +signal ce_toc_x : std_logic; +signal ce_toc : std_logic; +signal toc_done_x : std_logic; +signal toc_done : std_logic; + +signal rx_data_ctr : unsigned(7 downto 0); + +signal debug : std_logic_vector(15 downto 0); + +begin + +---------------------------------------------------------------------- +-- convert RCNT to unsigned for state machine +---------------------------------------------------------------------- +fifo_rcnt <= unsigned(FIFO_RCNT_IN); + +---------------------------------------------------------------------- +-- data counter for retransmission +---------------------------------------------------------------------- +THE_DATA_CTR_PROC: process( SYSCLK_IN ) +begin + if( rising_edge(SYSCLK_IN) ) then + if ( RESET_IN = '1' ) then + rx_data_ctr <= (others => '0'); + elsif( RX_LD_DATA_CTR_IN = '1' ) then + rx_data_ctr <= unsigned(RX_DATA_CTR_VAL_IN); + elsif( inc_data = '1' ) then + rx_data_ctr <= rx_data_ctr + 5; + end if; + end if; +end process THE_DATA_CTR_PROC; + +---------------------------------------------------------------------- +-- RX packet state machine +---------------------------------------------------------------------- +-- state registers +STATE_MEM: process( SYSCLK_IN ) +begin + if( rising_edge(SYSCLK_IN) ) then + if( RESET_IN = '1' ) then + CURRENT_STATE <= IDLE; + med_dataready <= '0'; + ce_toc <= '0'; + rst_toc <= '0'; + fifo_rst <= '0'; + inc_data <= '0'; + transit <= '0'; + pkt_timeout <= '0'; + bsm <= (others => '0'); + else + CURRENT_STATE <= NEXT_STATE; + med_dataready <= med_dataready_x; + ce_toc <= ce_toc_x; + rst_toc <= rst_toc_x; + fifo_rst <= fifo_rst_x; + inc_data <= inc_data_x; + transit <= transit_x; + pkt_timeout <= pkt_timeout_x; + bsm <= bsm_x; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, fifo_rcnt, MED_READ_IN, med_dataready, toc_done ) +begin + NEXT_STATE <= IDLE; -- avoid latches + fifo_rd_en_x <= '0'; + med_dataready_x <= '0'; + update_x <= '0'; + ce_toc_x <= '0'; + rst_toc_x <= '0'; + fifo_rst_x <= '0'; + inc_data_x <= '0'; + transit_x <= '0'; + pkt_timeout_x <= '0'; + case CURRENT_STATE is + when IDLE => + if( fifo_rcnt > 0 ) then + -- we have at least one data word in FIFO, so we prefetch it + NEXT_STATE <= RD1; + fifo_rd_en_x <= '1'; + ce_toc_x <= '1'; + else + NEXT_STATE <= IDLE; + end if; + when RD1 => + if ( fifo_rcnt > 1 ) then -- was 0 + -- second data word is available in FIFO, so we prefetch it and + -- forward the first word to the output register + NEXT_STATE <= RD2; + fifo_rd_en_x <= '1'; + update_x <= '1'; + ce_toc_x <= '1'; + elsif( toc_done = '1' ) then + NEXT_STATE <= TOC; + pkt_timeout_x <= '1'; + rst_toc_x <= '1'; + fifo_rst_x <= '1'; + else + NEXT_STATE <= RD1; + ce_toc_x <= '1'; + end if; + when RD2 => + if ( fifo_rcnt > 2 ) then + -- at least all three missing words in FIFO... so we go ahead and notify full packet availability + NEXT_STATE <= RDI; + med_dataready_x <= '1'; + inc_data_x <= '1'; + rst_toc_x <= '1'; + transit_x <= '1'; + elsif( toc_done = '1' ) then + NEXT_STATE <= TOC; + pkt_timeout_x <= '1'; + rst_toc_x <= '1'; + fifo_rst_x <= '1'; + else + NEXT_STATE <= RD2; + ce_toc_x <= '1'; + end if; + when RDI => + med_dataready_x <= '1'; + transit_x <= '1'; + if( MED_READ_IN = '1' ) then + -- first word of packet has been transfered, update output register and prefetch next data word + NEXT_STATE <= RD3; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= RDI; + end if; + when RD3 => + med_dataready_x <= '1'; + transit_x <= '1'; + if( MED_READ_IN = '1' ) then + -- second word of packet has been transfered, update output register and prefetch next data word + NEXT_STATE <= RD4; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= RD3; + end if; + when RD4 => + med_dataready_x <= '1'; + transit_x <= '1'; + -- third word of packet has been transfered, update output register and prefetch next data word + if( MED_READ_IN = '1' ) then + NEXT_STATE <= RD5; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= RD4; + end if; + when RD5 => + med_dataready_x <= '1'; + -- DANGER. This is the key state for decisions here. + -- There are many ways to do it the wrong way, depending on the FIFO fill level. + if ( (MED_READ_IN = '1') and (fifo_rcnt < 3) ) then -- was 2, changed due to RCNT latency + -- fourth word of packet has been transfered, and FIFO has not seen any new packet word. + -- so we update output register only, no prefetch + NEXT_STATE <= RDO; + update_x <= '1'; + elsif( (MED_READ_IN = '1') and (fifo_rcnt > 2) ) then -- was 1, changed due to RCNT latency + -- fourth word of packet DONE, new packet data already in the FIFO + -- so we can prefetch on data word already and update the output register + NEXT_STATE <= RDW; + fifo_rd_en_x <= '1'; + update_x <= '1'; + transit_x <= '1'; + else + NEXT_STATE <= RD5; + end if; + when RDO => + if ( (MED_READ_IN = '1') and (fifo_rcnt = 0) ) then + -- last word of packet has been transfered, and no new data words to handle. + -- we keep the last transfered word in the output register and wait for new packets to arrive. + NEXT_STATE <= IDLE; + elsif( (MED_READ_IN = '1') and (fifo_rcnt > 0) ) then + -- last word of packet has been transfered, and a new packet data available. + -- so we enter the prefetch phase again. + NEXT_STATE <= RD1; + fifo_rd_en_x <= '1'; + else + NEXT_STATE <= RDO; + med_dataready_x <= '1'; + end if; + when RDW => + if ( (MED_READ_IN = '1') and (fifo_rcnt > 3) ) then + -- last word of packet has been transfered, complete packet in FIFO, so we can go ahead. + NEXT_STATE <= RDI; + fifo_rd_en_x <= '1'; + update_x <= '1'; + med_dataready_x <= '1'; + transit_x <= '1'; + elsif( (MED_READ_IN = '1') and (fifo_rcnt < 4 ) ) then + -- last word of packet has been transfered, but new packet not complete yet. + NEXT_STATE <= RD2; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= RDW; + med_dataready_x <= '1'; + end if; + when TOC => + NEXT_STATE <= CLEAN; + pkt_timeout_x <= '1'; + fifo_rst_x <= '1'; + when CLEAN => + NEXT_STATE <= IDLE; + + when others => + NEXT_STATE <= IDLE; + end case; +end process STATE_TRANSFORM; + +-- just for debugging +THE_DECODE_PROC: process( NEXT_STATE ) +begin + case NEXT_STATE is + when IDLE => bsm_x <= x"0"; + when RD1 => bsm_x <= x"1"; + when RD2 => bsm_x <= x"2"; + when RDI => bsm_x <= x"3"; + when RD3 => bsm_x <= x"4"; + when RD4 => bsm_x <= x"5"; + when RD5 => bsm_x <= x"6"; + when RDO => bsm_x <= x"7"; + when RDW => bsm_x <= x"8"; + when TOC => bsm_x <= x"9"; + when CLEAN => bsm_x <= x"a"; + when others => bsm_x <= x"f"; + end case; +end process THE_DECODE_PROC; + +---------------------------------------------------------------------- +-- RX packet counter +---------------------------------------------------------------------- +THE_RX_PACKETS_PROC: process( SYSCLK_IN ) +begin + if( rising_edge(SYSCLK_IN) ) then + if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') or (pkt_timeout = '1') ) then + rx_counter <= unsigned(c_H0); + else + if( (med_dataready = '1') and (MED_READ_IN = '1') ) then -- modified + if( rx_counter = unsigned(c_max_word_number) ) then + rx_counter <= (others => '0'); + else + rx_counter <= rx_counter + 1; + end if; + end if; + end if; + end if; +end process THE_RX_PACKETS_PROC; + +---------------------------------------------------------------------- +-- Timeout counter +---------------------------------------------------------------------- +THE_TOC_PROC: process( SYSCLK_IN ) +begin + if( rising_edge(SYSCLK_IN) ) then + toc_done <= toc_done_x; + if ( (RESET_IN = '1') or (rst_toc = '1') ) then + timeout_ctr <= (others => '0'); + elsif( (ce_toc = '1') and (toc_done = '0') ) then + timeout_ctr <= timeout_ctr + 1; + end if; + end if; +end process THE_TOC_PROC; + +toc_done_x <= '1' when ( timeout_ctr(9 downto 2) = b"11_1111_11" ) else '0'; + +---------------------------------------------------------------------- +-- Debug signals +---------------------------------------------------------------------- +debug(15 downto 12) <= bsm; +debug(11) <= toc_done; +debug(10) <= ce_toc; +debug(9) <= rst_toc; +debug(8 downto 0) <= (others => '0'); + +---------------------------------------------------------------------- +-- Output signals +---------------------------------------------------------------------- +UPDATE_OUT <= update_x; +FIFO_READ_OUT <= fifo_rd_en_x; +FIFO_RESET_OUT <= fifo_rst; +RX_DATA_CTR_OUT <= std_logic_vector(rx_data_ctr); +PACKET_TIMEOUT_OUT <= pkt_timeout; +PKT_IN_TRANSIT_OUT <= transit; + +MED_DATAREADY_OUT <= med_dataready; +MED_PACKET_NUM_OUT <= std_logic_vector(rx_counter); + +BSM_OUT <= bsm; +DBG_OUT <= debug; + +end behavioral; \ No newline at end of file diff --git a/media_interfaces/trb_net16_tx_control.vhd b/media_interfaces/trb_net16_tx_control.vhd new file mode 100644 index 0000000..5b6eb2e --- /dev/null +++ b/media_interfaces/trb_net16_tx_control.vhd @@ -0,0 +1,374 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity trb_net16_tx_control is +port( + TXCLK_IN : in std_logic; + RXCLK_IN : in std_logic; + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + + TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_WRITE_IN : in std_logic; + TX_READ_OUT : out std_logic; + + TX_DATA_OUT : out std_logic_vector( 7 downto 0); + TX_K_OUT : out std_logic; + + REQUEST_RETRANSMIT_IN : in std_logic; + REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0); + + START_RETRANSMIT_IN : in std_logic; + START_POSITION_IN : in std_logic_vector( 7 downto 0); + + SEND_LINK_RESET_IN : in std_logic; + TX_ALLOW_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture arch of trb_net16_tx_control is + + component lattice_ecp2m_fifo_16x16_dualport + port ( + Data: in std_logic_vector(15 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(15 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic + ); + end component; + + type state_t is (SLEEP, SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, + SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H, + SEND_RESET); + signal current_state : state_t; + + type ram_t is array(0 to 255) of std_logic_vector(15 downto 0); + signal ram : ram_t; + + signal ram_write : std_logic; + signal ram_write_addr : unsigned(7 downto 0); + signal ram_read : std_logic; + signal ram_read_addr : unsigned(7 downto 0); + signal ram_dout : std_logic_vector(15 downto 0); + signal ram_fill_level : unsigned(7 downto 0); + signal ram_empty : std_logic; + signal ram_afull : std_logic; + + signal request_position_q : std_logic_vector( 7 downto 0); + signal restart_position_q : std_logic_vector( 7 downto 0); + signal request_position_i : std_logic_vector( 7 downto 0); + signal restart_position_i : std_logic_vector( 7 downto 0); + signal make_request_i : std_logic; + signal make_restart_i : std_logic; + signal load_read_pointer_i : std_logic; + + signal start_retransmit_i : std_logic; + signal request_retransmit_i : std_logic; + + signal tx_data_25_i : std_logic_vector(15 downto 0); + signal tx_allow_qtx : std_logic; + signal send_link_reset_qtx : std_logic; + signal ct_fifo_empty : std_logic; + signal ct_fifo_write : std_logic; + signal ct_fifo_read : std_logic; + signal ct_fifo_full : std_logic; + signal ct_fifo_afull : std_logic; + +begin + +---------------------------------------------------------------------- +-- Clock Domain Transfer +---------------------------------------------------------------------- + THE_CT_FIFO : lattice_ecp2m_fifo_16x16_dualport + port map( + Data => TX_DATA_IN, + WrClock => SYSCLK_IN, + RdClock => TXCLK_IN, + WrEn => ct_fifo_write, + RdEn => ct_fifo_read, + Reset => RESET_IN, + RPReset => RESET_IN, + Q => tx_data_25_i, + Empty => ct_fifo_empty, + Full => ct_fifo_full, + AlmostFull => ct_fifo_afull + ); + +TX_READ_OUT <= TX_ALLOW_IN and not ct_fifo_afull ; +ct_fifo_write<= TX_ALLOW_IN and not ct_fifo_afull and TX_WRITE_IN; +ct_fifo_read <= tx_allow_qtx and not ram_afull; + +---------------------------------------------------------------------- +-- RAM +---------------------------------------------------------------------- + + +THE_RAM_WR_PROC : process(TXCLK_IN) + begin + if rising_edge(TXCLK_IN) then + ram_write <= ct_fifo_read and not ct_fifo_empty; + end if; + end process; + +--RAM + THE_RAM_PROC : process(TXCLK_IN) + begin + if rising_edge(TXCLK_IN) then + if ram_write = '1' then + ram((to_integer(ram_write_addr))) <= tx_data_25_i; + end if; + ram_dout <= ram(to_integer(ram_read_addr)); + end if; + end process; + +--RAM read pointer + THE_READ_CNT : process(TXCLK_IN) + begin + if rising_edge(TXCLK_IN) then + if RESET_IN = '1' then + ram_read_addr <= (others => '0'); + elsif load_read_pointer_i = '1' then + ram_read_addr <= unsigned(restart_position_i); + elsif ram_read = '1' then + ram_read_addr <= ram_read_addr + to_unsigned(1,1); + end if; + end if; + end process; + +--RAM write pointer + THE_WRITE_CNT : process(TXCLK_IN) + begin + if rising_edge(TXCLK_IN) then + if RESET_IN = '1' then + ram_write_addr <= (others => '0'); + elsif ram_write = '1' then + ram_write_addr <= ram_write_addr + to_unsigned(1,1); + end if; + end if; + end process; + + +--RAM fill level counter + THE_FILL_CNT : process(TXCLK_IN) + begin + if rising_edge(TXCLK_IN) then + if RESET_IN = '1' then + ram_fill_level <= (others => '0'); + else + ram_fill_level <= ram_write_addr - ram_read_addr; + end if; + end if; + end process; + + +--RAM empty + ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)); + ram_afull <= '1' when ram_fill_level > 5 else '0'; + + + +---------------------------------------------------------------------- +-- TX control state machine +---------------------------------------------------------------------- + + THE_DATA_CONTROL_FSM : process(TXCLK_IN) + begin + if rising_edge(TXCLK_IN) then + if RESET_IN = '1' then + null; + else + ram_read <= '0'; + + case current_state is + when SLEEP => + TX_DATA_OUT <= x"BC"; + TX_K_OUT <= '1'; + current_state <= SEND_IDLE_L; + + when SEND_DATA_L => + TX_DATA_OUT <= ram_dout(7 downto 0); + TX_K_OUT <= '0'; + current_state <= SEND_DATA_H; + + when SEND_DATA_H => + TX_DATA_OUT <= ram_dout(15 downto 8); + TX_K_OUT <= '0'; + --current_state <= see below + + when SEND_IDLE_L => + TX_DATA_OUT <= x"BC"; + TX_K_OUT <= '1'; + current_state <= SEND_IDLE_H; + + when SEND_IDLE_H => + TX_DATA_OUT <= x"50"; + TX_K_OUT <= '0'; + --current_state <= see below + + when SEND_START_L => + TX_DATA_OUT <= x"FB"; + TX_K_OUT <= '1'; + current_state <= SEND_START_H; + + when SEND_START_H => + TX_DATA_OUT <= std_logic_vector(ram_read_addr); + TX_K_OUT <= '0'; + --current_state <= see below + + when SEND_REQUEST_L => + TX_DATA_OUT <= x"F7"; + TX_K_OUT <= '1'; + current_state <= SEND_REQUEST_H; + + when SEND_REQUEST_H => + TX_DATA_OUT <= request_position_i; + TX_K_OUT <= '0'; + --current_state <= see below + + when SEND_RESET => + TX_DATA_OUT <= x"FE"; + TX_K_OUT <= '1'; + if SEND_LINK_RESET_IN = '0' then + current_state <= SEND_IDLE_L; + end if; + + when others => + current_state <= SEND_IDLE_L; + end case; + + if current_state = SEND_START_H or + current_state = SEND_IDLE_H or + current_state = SEND_DATA_H or + current_state = SEND_REQUEST_H then + if send_link_reset_qtx = '1' then + current_state <= SEND_RESET; + elsif make_request_i = '1' then + current_state <= SEND_REQUEST_L; + elsif make_restart_i = '1' then + current_state <= SEND_START_L; + elsif ram_empty = '0' and tx_allow_qtx = '1' then + ram_read <= '1'; + current_state <= SEND_DATA_L; + else + current_state <= SEND_IDLE_L; + end if; + + end if; + end if; + end if; + end process; + +---------------------------------------------------------------------- +-- +---------------------------------------------------------------------- + + THE_SYS_TO_TX_SYNC : signal_sync + generic map( + WIDTH => 2, + DEPTH => 2 + ) + port map( + RESET => RESET_IN, + CLK0 => TXCLK_IN, + CLK1 => TXCLK_IN, + D_IN(0) => TX_ALLOW_IN, + D_IN(1) => SEND_LINK_RESET_IN, + D_OUT(0) => tx_allow_qtx, + D_OUT(1) => send_link_reset_qtx + ); + + + THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync + port map( + CLK_A_IN => SYSCLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => REQUEST_RETRANSMIT_IN, + CLK_B_IN => TXCLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => request_retransmit_i + ); + + THE_RETRANSMIT_PULSE_SYNC_2 : pulse_sync + port map( + CLK_A_IN => SYSCLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => START_RETRANSMIT_IN, + CLK_B_IN => TXCLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => start_retransmit_i + ); + + THE_POSITION_REG : process(SYSCLK_IN) + begin + if rising_edge(SYSCLK_IN) then + if REQUEST_RETRANSMIT_IN = '1' then + request_position_q <= REQUEST_POSITION_IN; + end if; + if START_RETRANSMIT_IN = '1' then + restart_position_q <= START_POSITION_IN; + end if; + end if; + end process; + + +--Store Request Retransmit position + THE_STORE_REQUEST_PROC : process(TXCLK_IN) + begin + if rising_edge(TXCLK_IN) then + if RESET_IN = '1' then + make_request_i <= '0'; + request_position_i <= (others => '0'); + elsif request_retransmit_i = '1' then + make_request_i <= '1'; + request_position_i <= request_position_q; + elsif current_state = SEND_REQUEST_H then + make_request_i <= '0'; + request_position_i <= (others => '0'); + end if; + end if; + end process; + + +--Store Restart position + THE_STORE_RESTART_PROC : process(TXCLK_IN) + begin + if rising_edge(TXCLK_IN) then + if RESET_IN = '1' then + make_restart_i <= '0'; + restart_position_i <= (others => '0'); + elsif start_retransmit_i = '1' then + make_restart_i <= '1'; + restart_position_i <= restart_position_q; + elsif current_state = SEND_START_L then + make_restart_i <= '0'; + elsif current_state = SEND_START_H then + restart_position_i <= (others => '0'); + end if; + end if; + end process; + + load_read_pointer_i <= '1' when current_state = SEND_START_L else '0'; + + +---------------------------------------------------------------------- +-- Debug +---------------------------------------------------------------------- + + +end architecture; \ No newline at end of file diff --git a/testbenches/tb_trb_net16_tx_control.vhd b/testbenches/tb_trb_net16_tx_control.vhd new file mode 100644 index 0000000..07c90be --- /dev/null +++ b/testbenches/tb_trb_net16_tx_control.vhd @@ -0,0 +1,238 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +--use work.trb_net_components.all; + +entity txtb is +end entity; + +architecture arch of txtb is + + component trb_net16_tx_control is + port( + TXCLK_IN : in std_logic; + RXCLK_IN : in std_logic; + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + + TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_WRITE_IN : in std_logic; + TX_READ_OUT : out std_logic; + + TX_DATA_OUT : out std_logic_vector( 7 downto 0); + TX_K_OUT : out std_logic; + + REQUEST_RETRANSMIT_IN : in std_logic; + REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0); + + START_RETRANSMIT_IN : in std_logic; + START_POSITION_IN : in std_logic_vector( 7 downto 0); + + SEND_LINK_RESET_IN : in std_logic; + TX_ALLOW_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + signal clk : std_logic := '1'; + signal clk25 : std_logic := '1'; + signal reset : std_logic := '1'; + + signal tx_data_in : std_logic_vector(15 downto 0); + signal tx_write_in : std_logic; + signal tx_read_out : std_logic; + + signal tx_data_out : std_logic_vector( 7 downto 0); + signal tx_k_out : std_logic; + signal request_retransmit_in : std_logic; + signal request_position_in : std_logic_vector( 7 downto 0); + signal start_retransmit_in : std_logic; + signal start_position_in : std_logic_vector( 7 downto 0); + signal send_link_reset_in : std_logic; + signal tx_allow_in : std_logic; + + +begin + + proc_clk25 : process + begin + wait for 20 ns; + clk25 <= not clk25; + end process; + + + proc_clk : process + begin + wait for 5 ns; + clk <= not clk; + end process; + + proc_reset : process + begin + reset <= '1'; + wait for 105 ns; + reset <= '0'; + wait; + end process; + + uut : trb_net16_tx_control + port map( + TXCLK_IN => clk25, + RXCLK_IN => clk25, + SYSCLK_IN => clk, + RESET_IN => reset, + + TX_DATA_IN => tx_data_in, + TX_WRITE_IN => tx_write_in, + TX_READ_OUT => tx_read_out, + + TX_DATA_OUT => tx_data_out, + TX_K_OUT => tx_k_out, + + REQUEST_RETRANSMIT_IN => request_retransmit_in, + REQUEST_POSITION_IN => request_position_in, + + START_RETRANSMIT_IN => start_retransmit_in, + START_POSITION_IN => start_position_in, + + SEND_LINK_RESET_IN => send_link_reset_in, + TX_ALLOW_IN => tx_allow_in, + + DEBUG_OUT => open + ); + +--Data input + process + begin + tx_data_in <= (others => '0'); + tx_write_in <= '0'; + wait for 300 ns; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"1001"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"2002"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_write_in <= '0'; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"3003"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"4004"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_write_in <= '0'; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"5005"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"6006"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"7007"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"8008"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"9009"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"a00a"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"b00b"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"c00c"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"d00d"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"e00e"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= x"f00f"; + tx_write_in <= '1'; + if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx_data_in <= (others => '0'); + tx_write_in <= '0'; + wait; + end process; + + +--request from RX + process + begin + request_retransmit_in <= '0'; + request_position_in <= (others => '0'); + wait for 300 ns; + wait until rising_edge(clk); wait for 1 ns; + request_retransmit_in <= '0'; + request_position_in <= (others => '0'); + wait; + end process; + + +--restart from RX + process + begin + start_retransmit_in <= '0'; + start_position_in <= (others => '0'); + wait for 650 ns; + wait until rising_edge(clk); wait for 1 ns; + start_retransmit_in <= '1'; + start_position_in <= std_logic_vector(to_unsigned(5,8)); + wait until rising_edge(clk); wait for 1 ns; + start_retransmit_in <= '0'; + start_position_in <= (others => '0'); + wait for 1050 ns; + wait until rising_edge(clk); wait for 1 ns; + start_retransmit_in <= '1'; + start_position_in <= std_logic_vector(to_unsigned(15,8)); + wait until rising_edge(clk); wait for 1 ns; + start_retransmit_in <= '0'; + start_position_in <= (others => '0'); + wait; + end process; + +--control from LSM + process + begin + tx_allow_in <= '0'; + send_link_reset_in <= '0'; + wait for 350 ns; + wait until rising_edge(clk); wait for 1 ns; + tx_allow_in <= '1'; + send_link_reset_in <= '0'; + wait; + end process; + + + + +end architecture; + + + diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 7294d08..8a390f9 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -289,8 +289,14 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full begin - reset_no_link <= MED_STAT_OP_IN(14) or RESET; - reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1); + process(CLK) + begin + if rising_edge(CLK) then + reset_no_link <= MED_STAT_OP_IN(14) or RESET; + reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1); + end if; + end process; + --MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15); MED_CTRL_OP_OUT(15 downto 0) <= (others => '0'); MED_STAT_OP <= MED_STAT_OP_IN; @@ -873,7 +879,7 @@ begin -- - THE_CMS_SYNC : signal_sync + THE_TRG_SYNC : signal_sync generic map( DEPTH => 2, WIDTH => 1 diff --git a/trb_net16_rx_packets.vhd b/trb_net16_rx_packets.vhd index bb8a53d..f486659 100755 --- a/trb_net16_rx_packets.vhd +++ b/trb_net16_rx_packets.vhd @@ -8,28 +8,28 @@ use work.trb_net_std.all; entity trb_net16_rx_packets is port( - -- Resets - RESET_IN : in std_logic; - QUAD_RST_IN : in std_logic; - -- data stream from SerDes - CLK_IN : in std_logic; -- SerDes RX clock - RX_ALLOW_IN : in std_logic; - RX_DATA_IN : in std_logic_vector(7 downto 0); - RX_K_IN : in std_logic; - -- media interface - SYSCLK_IN : in std_logic; -- 100MHz master clock - MED_DATA_OUT : out std_logic_vector(15 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - -- reset handling - SEND_RESET_WORDS_OUT : out std_logic; - MAKE_TRBNET_RESET_OUT : out std_logic; - -- Status signals - PACKET_TIMEOUT_OUT : out std_logic; - -- Debug signals - BSM_OUT : out std_logic_vector(3 downto 0); - DBG_OUT : out std_logic_vector(15 downto 0) + -- Resets + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- data stream from SerDes + CLK_IN : in std_logic; -- SerDes RX clock + RX_ALLOW_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + -- media interface + SYSCLK_IN : in std_logic; -- 100MHz master clock + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Status signals + PACKET_TIMEOUT_OUT : out std_logic; + -- Debug signals + BSM_OUT : out std_logic_vector(3 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) ); end entity trb_net16_rx_packets; @@ -39,17 +39,17 @@ architecture behavioral of trb_net16_rx_packets is -- components component trb_net_fifo_8bit_16bit_bram_dualport is port( - READ_CLOCK_IN : in std_logic; - WRITE_CLOCK_IN : in std_logic; - READ_ENABLE_IN : in std_logic; - WRITE_ENABLE_IN : in std_logic; - FIFO_GSR_IN : in std_logic; - WRITE_DATA_IN : in std_logic_vector(7 downto 0); - READ_DATA_OUT : out std_logic_vector(15 downto 0); - FULL_OUT : out std_logic; - EMPTY_OUT : out std_logic; - WCNT_OUT : out std_logic_vector(9 downto 0); - RCNT_OUT : out std_logic_vector(8 downto 0) + READ_CLOCK_IN : in std_logic; + WRITE_CLOCK_IN : in std_logic; + READ_ENABLE_IN : in std_logic; + WRITE_ENABLE_IN : in std_logic; + FIFO_GSR_IN : in std_logic; + WRITE_DATA_IN : in std_logic_vector(7 downto 0); + READ_DATA_OUT : out std_logic_vector(15 downto 0); + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic; + WCNT_OUT : out std_logic_vector(9 downto 0); + RCNT_OUT : out std_logic_vector(8 downto 0) ); end component trb_net_fifo_8bit_16bit_bram_dualport; @@ -118,28 +118,28 @@ begin ---------------------------------------------------------------------- THE_WRITE_RX_FIFO_PROC: process( CLK_IN ) begin - if( rising_edge(CLK_IN) ) then - buf_rx_data <= RX_DATA_IN; - buf_rx_k <= RX_K_IN; - if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then - fifo_wr_en <= '0'; - is_idle_word <= '1'; - rx_starting <= '1'; - else - fifo_wr_data <= buf_rx_data; - if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then - fifo_wr_en <= '1'; - else - fifo_wr_en <= '0'; - end if; - if ( buf_rx_k = '1' ) then - is_idle_word <= '1'; - rx_starting <= '0'; - elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then - is_idle_word <= '0'; - end if; - end if; - end if; + if( rising_edge(CLK_IN) ) then + buf_rx_data <= RX_DATA_IN; + buf_rx_k <= RX_K_IN; + if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then + fifo_wr_en <= '0'; + is_idle_word <= '1'; + rx_starting <= '1'; + else + fifo_wr_data <= buf_rx_data; + if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then + fifo_wr_en <= '1'; + else + fifo_wr_en <= '0'; + end if; + if ( buf_rx_k = '1' ) then + is_idle_word <= '1'; + rx_starting <= '0'; + elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then + is_idle_word <= '0'; + end if; + end if; + end if; end process THE_WRITE_RX_FIFO_PROC; ---------------------------------------------------------------------- @@ -147,26 +147,26 @@ end process THE_WRITE_RX_FIFO_PROC; ---------------------------------------------------------------------- THE_CNT_RESET_PROC: process( CLK_IN ) begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - send_reset_words <= '0'; - make_trbnet_reset <= '0'; - reset_word_cnt <= (others => '0'); - else - send_reset_words <= '0'; - make_trbnet_reset <= '0'; - if( (buf_rx_data = x"FE") and (buf_rx_k = '1') ) then - if( reset_word_cnt(4) = '0' ) then - reset_word_cnt <= reset_word_cnt + 1; - else - send_reset_words <= '1'; - end if; - else - reset_word_cnt <= (others => '0'); - make_trbnet_reset <= reset_word_cnt(4); - end if; - end if; - end if; + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + reset_word_cnt <= (others => '0'); + else + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + if( (buf_rx_data = x"FE") and (buf_rx_k = '1') ) then + if( reset_word_cnt(4) = '0' ) then + reset_word_cnt <= reset_word_cnt + 1; + else + send_reset_words <= '1'; + end if; + else + reset_word_cnt <= (others => '0'); + make_trbnet_reset <= reset_word_cnt(4); + end if; + end if; + end if; end process; ---------------------------------------------------------------------- @@ -174,17 +174,17 @@ end process; ---------------------------------------------------------------------- THE_RX_FIFO: trb_net_fifo_8bit_16bit_bram_dualport port map( - READ_CLOCK_IN => SYSCLK_IN, - WRITE_CLOCK_IN => CLK_IN, - READ_ENABLE_IN => fifo_rd_en_x, - WRITE_ENABLE_IN => fifo_wr_en, - FIFO_GSR_IN => fifo_reset, - WRITE_DATA_IN => fifo_wr_data, - READ_DATA_OUT => fifo_rd_data, - FULL_OUT => open, - EMPTY_OUT => open, - WCNT_OUT => open, -- not needed - RCNT_OUT => fifo_rcnt_stdlv + READ_CLOCK_IN => SYSCLK_IN, + WRITE_CLOCK_IN => CLK_IN, + READ_ENABLE_IN => fifo_rd_en_x, + WRITE_ENABLE_IN => fifo_wr_en, + FIFO_GSR_IN => fifo_reset, + WRITE_DATA_IN => fifo_wr_data, + READ_DATA_OUT => fifo_rd_data, + FULL_OUT => open, + EMPTY_OUT => open, + WCNT_OUT => open, -- not needed + RCNT_OUT => fifo_rcnt_stdlv ); fifo_reset <= RESET_IN or QUAD_RST_IN or not RX_ALLOW_IN or fifo_rst; @@ -197,178 +197,178 @@ fifo_rcnt <= unsigned(fifo_rcnt_stdlv); -- state registers STATE_MEM: process( SYSCLK_IN ) begin - if( rising_edge(SYSCLK_IN) ) then - if( RESET_IN = '1' ) then - CURRENT_STATE <= IDLE; - med_dataready <= '0'; - ce_toc <= '0'; - rst_toc <= '0'; - fifo_rst <= '0'; - bsm <= (others => '0'); - else - CURRENT_STATE <= NEXT_STATE; - med_dataready <= med_dataready_x; - ce_toc <= ce_toc_x; - rst_toc <= rst_toc_x; - fifo_rst <= fifo_rst_x; - bsm <= bsm_x; - end if; - end if; + if( rising_edge(SYSCLK_IN) ) then + if( RESET_IN = '1' ) then + CURRENT_STATE <= IDLE; + med_dataready <= '0'; + ce_toc <= '0'; + rst_toc <= '0'; + fifo_rst <= '0'; + bsm <= (others => '0'); + else + CURRENT_STATE <= NEXT_STATE; + med_dataready <= med_dataready_x; + ce_toc <= ce_toc_x; + rst_toc <= rst_toc_x; + fifo_rst <= fifo_rst_x; + bsm <= bsm_x; + end if; + end if; end process STATE_MEM; -- state transitions STATE_TRANSFORM: process( CURRENT_STATE, fifo_rcnt, MED_READ_IN, med_dataready, toc_done ) begin - NEXT_STATE <= IDLE; -- avoid latches - fifo_rd_en_x <= '0'; - med_dataready_x <= '0'; - update_x <= '0'; - ce_toc_x <= '0'; - rst_toc_x <= '0'; - fifo_rst_x <= '0'; - case CURRENT_STATE is - when IDLE => if( fifo_rcnt > 0 ) then - -- we have at least one data word in FIFO, so we prefetch it - NEXT_STATE <= RD1; - fifo_rd_en_x <= '1'; - ce_toc_x <= '1'; - else - NEXT_STATE <= IDLE; - end if; - when RD1 => if ( fifo_rcnt > 1 ) then -- was 0 - -- second data word is available in FIFO, so we prefetch it and - -- forward the first word to the output register - NEXT_STATE <= RD2; - fifo_rd_en_x <= '1'; - update_x <= '1'; - ce_toc_x <= '1'; - elsif( toc_done = '1' ) then - NEXT_STATE <= TOC; - rst_toc_x <= '1'; - fifo_rst_x <= '1'; - else - NEXT_STATE <= RD1; - ce_toc_x <= '1'; - end if; - when RD2 => if ( fifo_rcnt > 2 ) then - -- at least all three missing words in FIFO... so we go ahead and notify full packet availability - NEXT_STATE <= RDI; - med_dataready_x <= '1'; - rst_toc_x <= '1'; - elsif( toc_done = '1' ) then - NEXT_STATE <= TOC; - rst_toc_x <= '1'; - fifo_rst_x <= '1'; - else - NEXT_STATE <= RD2; - ce_toc_x <= '1'; - end if; - when RDI => med_dataready_x <= '1'; - if( MED_READ_IN = '1' ) then - -- first word of packet has been transfered, update output register and prefetch next data word - NEXT_STATE <= RD3; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RDI; - end if; - when RD3 => med_dataready_x <= '1'; - if( MED_READ_IN = '1' ) then - -- second word of packet has been transfered, update output register and prefetch next data word - NEXT_STATE <= RD4; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RD3; - end if; - when RD4 => med_dataready_x <= '1'; - -- third word of packet has been transfered, update output register and prefetch next data word - if( MED_READ_IN = '1' ) then - NEXT_STATE <= RD5; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RD4; - end if; - when RD5 => med_dataready_x <= '1'; - -- DANGER. This is the key state for decisions here. - -- There are many ways to do it the wrong way, depending on the FIFO fill level. - if ( (MED_READ_IN = '1') and (fifo_rcnt < 3) ) then -- was 2, changed due to RCNT latency - -- fourth word of packet has been transfered, and FIFO has not seen any new packet word. - -- so we update output register only, no prefetch - NEXT_STATE <= RDO; - update_x <= '1'; - elsif( (MED_READ_IN = '1') and (fifo_rcnt > 2) ) then -- was 1, changed due to RCNT latency - -- fourth word of packet DONE, new packet data already in the FIFO - -- so we can prefetch on data word already and update the output register - NEXT_STATE <= RDW; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RD5; - end if; - when RDO => if ( (MED_READ_IN = '1') and (fifo_rcnt = 0) ) then - -- last word of packet has been transfered, and no new data words to handle. - -- we keep the last transfered word in the output register and wait for new packets to arrive. - NEXT_STATE <= IDLE; - elsif( (MED_READ_IN = '1') and (fifo_rcnt > 0) ) then - -- last word of packet has been transfered, and a new packet data available. - -- so we enter the prefetch phase again. - NEXT_STATE <= RD1; - fifo_rd_en_x <= '1'; - else - NEXT_STATE <= RDO; - med_dataready_x <= '1'; - end if; - when RDW => if ( (MED_READ_IN = '1') and (fifo_rcnt > 3) ) then - -- last word of packet has been transfered, complete packet in FIFO, so we can go ahead. - NEXT_STATE <= RDI; - fifo_rd_en_x <= '1'; - update_x <= '1'; - med_dataready_x <= '1'; - elsif( (MED_READ_IN = '1') and (fifo_rcnt < 4 ) ) then - -- last word of packet has been transfered, but new packet not complete yet. - NEXT_STATE <= RD2; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RDW; - med_dataready_x <= '1'; - end if; - when TOC => NEXT_STATE <= CLEAN; - fifo_rst_x <= '1'; - when CLEAN => NEXT_STATE <= IDLE; - - when others => NEXT_STATE <= IDLE; - end case; + NEXT_STATE <= IDLE; -- avoid latches + fifo_rd_en_x <= '0'; + med_dataready_x <= '0'; + update_x <= '0'; + ce_toc_x <= '0'; + rst_toc_x <= '0'; + fifo_rst_x <= '0'; + case CURRENT_STATE is + when IDLE => if( fifo_rcnt > 0 ) then + -- we have at least one data word in FIFO, so we prefetch it + NEXT_STATE <= RD1; + fifo_rd_en_x <= '1'; + ce_toc_x <= '1'; + else + NEXT_STATE <= IDLE; + end if; + when RD1 => if ( fifo_rcnt > 1 ) then -- was 0 + -- second data word is available in FIFO, so we prefetch it and + -- forward the first word to the output register + NEXT_STATE <= RD2; + fifo_rd_en_x <= '1'; + update_x <= '1'; + ce_toc_x <= '1'; + elsif( toc_done = '1' ) then + NEXT_STATE <= TOC; + rst_toc_x <= '1'; + fifo_rst_x <= '1'; + else + NEXT_STATE <= RD1; + ce_toc_x <= '1'; + end if; + when RD2 => if ( fifo_rcnt > 2 ) then + -- at least all three missing words in FIFO... so we go ahead and notify full packet availability + NEXT_STATE <= RDI; + med_dataready_x <= '1'; + rst_toc_x <= '1'; + elsif( toc_done = '1' ) then + NEXT_STATE <= TOC; + rst_toc_x <= '1'; + fifo_rst_x <= '1'; + else + NEXT_STATE <= RD2; + ce_toc_x <= '1'; + end if; + when RDI => med_dataready_x <= '1'; + if( MED_READ_IN = '1' ) then + -- first word of packet has been transfered, update output register and prefetch next data word + NEXT_STATE <= RD3; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= RDI; + end if; + when RD3 => med_dataready_x <= '1'; + if( MED_READ_IN = '1' ) then + -- second word of packet has been transfered, update output register and prefetch next data word + NEXT_STATE <= RD4; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= RD3; + end if; + when RD4 => med_dataready_x <= '1'; + -- third word of packet has been transfered, update output register and prefetch next data word + if( MED_READ_IN = '1' ) then + NEXT_STATE <= RD5; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= RD4; + end if; + when RD5 => med_dataready_x <= '1'; + -- DANGER. This is the key state for decisions here. + -- There are many ways to do it the wrong way, depending on the FIFO fill level. + if ( (MED_READ_IN = '1') and (fifo_rcnt < 3) ) then -- was 2, changed due to RCNT latency + -- fourth word of packet has been transfered, and FIFO has not seen any new packet word. + -- so we update output register only, no prefetch + NEXT_STATE <= RDO; + update_x <= '1'; + elsif( (MED_READ_IN = '1') and (fifo_rcnt > 2) ) then -- was 1, changed due to RCNT latency + -- fourth word of packet DONE, new packet data already in the FIFO + -- so we can prefetch on data word already and update the output register + NEXT_STATE <= RDW; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= RD5; + end if; + when RDO => if ( (MED_READ_IN = '1') and (fifo_rcnt = 0) ) then + -- last word of packet has been transfered, and no new data words to handle. + -- we keep the last transfered word in the output register and wait for new packets to arrive. + NEXT_STATE <= IDLE; + elsif( (MED_READ_IN = '1') and (fifo_rcnt > 0) ) then + -- last word of packet has been transfered, and a new packet data available. + -- so we enter the prefetch phase again. + NEXT_STATE <= RD1; + fifo_rd_en_x <= '1'; + else + NEXT_STATE <= RDO; + med_dataready_x <= '1'; + end if; + when RDW => if ( (MED_READ_IN = '1') and (fifo_rcnt > 3) ) then + -- last word of packet has been transfered, complete packet in FIFO, so we can go ahead. + NEXT_STATE <= RDI; + fifo_rd_en_x <= '1'; + update_x <= '1'; + med_dataready_x <= '1'; + elsif( (MED_READ_IN = '1') and (fifo_rcnt < 4 ) ) then + -- last word of packet has been transfered, but new packet not complete yet. + NEXT_STATE <= RD2; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= RDW; + med_dataready_x <= '1'; + end if; + when TOC => NEXT_STATE <= CLEAN; + fifo_rst_x <= '1'; + when CLEAN => NEXT_STATE <= IDLE; + + when others => NEXT_STATE <= IDLE; + end case; end process STATE_TRANSFORM; -- just for debugging THE_DECODE_PROC: process( NEXT_STATE ) begin - case NEXT_STATE is - when IDLE => bsm_x <= x"0"; - when RD1 => bsm_x <= x"1"; - when RD2 => bsm_x <= x"2"; - when RDI => bsm_x <= x"3"; - when RD3 => bsm_x <= x"4"; - when RD4 => bsm_x <= x"5"; - when RD5 => bsm_x <= x"6"; - when RDO => bsm_x <= x"7"; - when RDW => bsm_x <= x"8"; - when TOC => bsm_x <= x"9"; - when CLEAN => bsm_x <= x"a"; - when others => bsm_x <= x"f"; - end case; + case NEXT_STATE is + when IDLE => bsm_x <= x"0"; + when RD1 => bsm_x <= x"1"; + when RD2 => bsm_x <= x"2"; + when RDI => bsm_x <= x"3"; + when RD3 => bsm_x <= x"4"; + when RD4 => bsm_x <= x"5"; + when RD5 => bsm_x <= x"6"; + when RDO => bsm_x <= x"7"; + when RDW => bsm_x <= x"8"; + when TOC => bsm_x <= x"9"; + when CLEAN => bsm_x <= x"a"; + when others => bsm_x <= x"f"; + end case; end process THE_DECODE_PROC; THE_SYNC_PROC: process( SYSCLK_IN ) begin - if( rising_edge(SYSCLK_IN) ) then - if( update_x = '1' ) then - med_data <= fifo_rd_data; - end if; - end if; + if( rising_edge(SYSCLK_IN) ) then + if( update_x = '1' ) then + med_data <= fifo_rd_data; + end if; + end if; end process THE_SYNC_PROC; ---------------------------------------------------------------------- @@ -376,19 +376,19 @@ end process THE_SYNC_PROC; ---------------------------------------------------------------------- THE_RX_PACKETS_PROC: process( SYSCLK_IN ) begin - if( rising_edge(SYSCLK_IN) ) then - if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then - rx_counter <= unsigned(c_H0); - else - if( (med_dataready = '1') and (MED_READ_IN = '1') ) then -- modified - if( rx_counter = unsigned(c_max_word_number) ) then - rx_counter <= (others => '0'); - else - rx_counter <= rx_counter + 1; - end if; - end if; - end if; - end if; + if( rising_edge(SYSCLK_IN) ) then + if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then + rx_counter <= unsigned(c_H0); + else + if( (med_dataready = '1') and (MED_READ_IN = '1') ) then -- modified + if( rx_counter = unsigned(c_max_word_number) ) then + rx_counter <= (others => '0'); + else + rx_counter <= rx_counter + 1; + end if; + end if; + end if; + end if; end process THE_RX_PACKETS_PROC; ---------------------------------------------------------------------- @@ -396,14 +396,14 @@ end process THE_RX_PACKETS_PROC; ---------------------------------------------------------------------- THE_TOC_PROC: process( SYSCLK_IN ) begin - if( rising_edge(SYSCLK_IN) ) then - toc_done <= toc_done_x; - if ( (RESET_IN = '1') or (rst_toc = '1') ) then - timeout_ctr <= (others => '0'); - elsif( (ce_toc = '1') and (toc_done = '0') ) then - timeout_ctr <= timeout_ctr + 1; - end if; - end if; + if( rising_edge(SYSCLK_IN) ) then + toc_done <= toc_done_x; + if ( (RESET_IN = '1') or (rst_toc = '1') ) then + timeout_ctr <= (others => '0'); + elsif( (ce_toc = '1') and (toc_done = '0') ) then + timeout_ctr <= timeout_ctr + 1; + end if; + end if; end process THE_TOC_PROC; toc_done_x <= '1' when ( timeout_ctr(9 downto 2) = b"11_1111_11" ) else '0'; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 3894bda..470de94 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -2092,7 +2092,16 @@ end component; - + component pulse_sync is + port( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic + ); + end component;