From: Tobias Weber Date: Fri, 6 Jul 2018 07:29:19 +0000 (+0200) Subject: making the new code synthesis. Still not working and two bugs need fixing. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=fa92c8ab921c51bab1c7cbc968f5f6140b295882;p=trb3.git making the new code synthesis. Still not working and two bugs need fixing. --- diff --git a/mupix/Mupix8/cores/serdes_fifo.ipx b/mupix/Mupix8/cores/serdes_fifo.ipx index a61cc0f..9d999af 100644 --- a/mupix/Mupix8/cores/serdes_fifo.ipx +++ b/mupix/Mupix8/cores/serdes_fifo.ipx @@ -1,9 +1,9 @@ - + - - - - + + + + diff --git a/mupix/Mupix8/cores/serdes_fifo.lpc b/mupix/Mupix8/cores/serdes_fifo.lpc index 21abe9d..89ec340 100644 --- a/mupix/Mupix8/cores/serdes_fifo.lpc +++ b/mupix/Mupix8/cores/serdes_fifo.lpc @@ -16,8 +16,8 @@ CoreRevision=5.8 ModuleName=serdes_fifo SourceFormat=VHDL ParameterFileVersion=1.0 -Date=01/11/2018 -Time=13:46:44 +Date=06/22/2018 +Time=12:16:11 [Parameters] Verilog=0 @@ -28,10 +28,10 @@ Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 FIFOImp=EBR Based -Depth=2048 -Width=8 -RDepth=512 -RWidth=32 +Depth=1024 +Width=40 +RDepth=1024 +RWidth=40 regout=0 CtrlByRdEn=0 EmpFlg=0 @@ -47,4 +47,4 @@ WDataCount=0 EnECC=0 [Command] -cmd_line= -w -n serdes_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 32 -no_enable -pe -1 -pf -1 -rfill +cmd_line= -w -n serdes_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 10 -data_width 40 -num_words 1024 -rdata_width 40 -no_enable -pe -1 -pf -1 -rfill diff --git a/mupix/Mupix8/cores/serdes_fifo.vhd b/mupix/Mupix8/cores/serdes_fifo.vhd index d422d7f..04f52d9 100644 --- a/mupix/Mupix8/cores/serdes_fifo.vhd +++ b/mupix/Mupix8/cores/serdes_fifo.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4 +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502 -- Module Version: 5.8 ---/home/soft/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n serdes_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 32 -no_enable -pe -1 -pf -1 -rfill +--/home/soft/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n serdes_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 40 -depth 1024 -rdata_width 40 -no_enable -pe -1 -pf -1 -rfill --- Thu Jan 11 13:46:45 2018 +-- Fri Jun 22 12:16:11 2018 library IEEE; use IEEE.std_logic_1164.all; @@ -13,15 +13,15 @@ use ecp3.components.all; entity serdes_fifo is port ( - Data: in std_logic_vector(7 downto 0); + Data: in std_logic_vector(39 downto 0); WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(31 downto 0); - RCNT: out std_logic_vector(9 downto 0); + Q: out std_logic_vector(39 downto 0); + RCNT: out std_logic_vector(10 downto 0); Empty: out std_logic; Full: out std_logic); end serdes_fifo; @@ -31,11 +31,9 @@ architecture Structure of serdes_fifo is -- internal signal declarations signal invout_1: std_logic; signal invout_0: std_logic; - signal wcount_r1: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal wcount_r0: std_logic; signal w_g2b_xor_cluster_2: std_logic; signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; signal r_g2b_xor_cluster_1: std_logic; signal w_gdata_0: std_logic; signal w_gdata_1: std_logic; @@ -47,7 +45,6 @@ architecture Structure of serdes_fifo is signal w_gdata_7: std_logic; signal w_gdata_8: std_logic; signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; signal wptr_0: std_logic; signal wptr_1: std_logic; signal wptr_2: std_logic; @@ -59,7 +56,6 @@ architecture Structure of serdes_fifo is signal wptr_8: std_logic; signal wptr_9: std_logic; signal wptr_10: std_logic; - signal wptr_11: std_logic; signal r_gdata_0: std_logic; signal r_gdata_1: std_logic; signal r_gdata_2: std_logic; @@ -69,7 +65,8 @@ architecture Structure of serdes_fifo is signal r_gdata_6: std_logic; signal r_gdata_7: std_logic; signal r_gdata_8: std_logic; - signal rptr_9: std_logic; + signal r_gdata_9: std_logic; + signal rptr_10: std_logic; signal w_gcount_0: std_logic; signal w_gcount_1: std_logic; signal w_gcount_2: std_logic; @@ -81,7 +78,6 @@ architecture Structure of serdes_fifo is signal w_gcount_8: std_logic; signal w_gcount_9: std_logic; signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; signal r_gcount_0: std_logic; signal r_gcount_1: std_logic; signal r_gcount_2: std_logic; @@ -92,6 +88,7 @@ architecture Structure of serdes_fifo is signal r_gcount_7: std_logic; signal r_gcount_8: std_logic; signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; signal w_gcount_r20: std_logic; signal w_gcount_r0: std_logic; signal w_gcount_r21: std_logic; @@ -114,8 +111,6 @@ architecture Structure of serdes_fifo is signal w_gcount_r9: std_logic; signal w_gcount_r210: std_logic; signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; signal r_gcount_w20: std_logic; signal r_gcount_w0: std_logic; signal r_gcount_w21: std_logic; @@ -136,6 +131,8 @@ architecture Structure of serdes_fifo is signal r_gcount_w8: std_logic; signal r_gcount_w29: std_logic; signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; signal empty_i: std_logic; signal rRst: std_logic; signal full_i: std_logic; @@ -155,10 +152,9 @@ architecture Structure of serdes_fifo is signal iwcount_9: std_logic; signal co3: std_logic; signal iwcount_10: std_logic; - signal iwcount_11: std_logic; signal co5: std_logic; signal co4: std_logic; - signal wcount_11: std_logic; + signal wcount_10: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; signal r_gctr_ci: std_logic; @@ -173,9 +169,11 @@ architecture Structure of serdes_fifo is signal co2_1: std_logic; signal ircount_8: std_logic; signal ircount_9: std_logic; - signal co4_1: std_logic; signal co3_1: std_logic; - signal rcount_9: std_logic; + signal ircount_10: std_logic; + signal co5_1: std_logic; + signal co4_1: std_logic; + signal rcount_10: std_logic; signal rfill_sub_0: std_logic; signal precin: std_logic; signal rptr_0: std_logic; @@ -201,64 +199,71 @@ architecture Structure of serdes_fifo is signal rptr_7: std_logic; signal rptr_8: std_logic; signal rfill_sub_9: std_logic; + signal rfill_sub_10: std_logic; signal co4_2: std_logic; + signal rptr_9: std_logic; signal rfill_sub_msb: std_logic; + signal co5_2d: std_logic; + signal co5_2: std_logic; signal rden_i: std_logic; signal cmp_ci: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; signal rcount_0: std_logic; signal rcount_1: std_logic; signal co0_3: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; signal rcount_2: std_logic; signal rcount_3: std_logic; signal co1_3: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; signal rcount_4: std_logic; signal rcount_5: std_logic; signal co2_3: std_logic; + signal wcount_r6: std_logic; signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r9: std_logic; signal rcount_6: std_logic; signal rcount_7: std_logic; signal co3_3: std_logic; - signal wcount_r10: std_logic; - signal empty_cmp_clr: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_3: std_logic; + signal empty_cmp_clr: std_logic; signal empty_cmp_set: std_logic; signal empty_d: std_logic; signal empty_d_c: std_logic; signal wren_i: std_logic; signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; signal wcount_0: std_logic; signal wcount_1: std_logic; signal co0_4: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; signal wcount_2: std_logic; signal wcount_3: std_logic; signal co1_4: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; signal wcount_4: std_logic; signal wcount_5: std_logic; signal co2_4: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal r_g2b_xor_cluster_0: std_logic; signal wcount_6: std_logic; signal wcount_7: std_logic; signal co3_4: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; signal wcount_8: std_logic; signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w8: std_logic; + signal co4_4: std_logic; signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; signal full_cmp_set: std_logic; signal full_d: std_logic; signal full_d_c: std_logic; @@ -389,9 +394,16 @@ architecture Structure of serdes_fifo is attribute MEM_INIT_FILE : string; attribute RESETMODE : string; attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "serdes_fifo.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "serdes_fifo.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_2 : label is ""; + attribute RESETMODE of pdp_ram_0_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "serdes_fifo.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_1 : label is ""; + attribute RESETMODE of pdp_ram_0_1_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "serdes_fifo.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is ""; + attribute RESETMODE of pdp_ram_0_2_0 : label is "SYNC"; + attribute GSR of FF_122 : label is "ENABLED"; attribute GSR of FF_121 : label is "ENABLED"; attribute GSR of FF_120 : label is "ENABLED"; attribute GSR of FF_119 : label is "ENABLED"; @@ -566,662 +578,738 @@ begin port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); XOR2_t10: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); XOR2_t9: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); XOR2_t8: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); XOR2_t7: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); XOR2_t6: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); XOR2_t5: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); XOR2_t4: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); XOR2_t3: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); XOR2_t2: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); XOR2_t1: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); LUT4_27: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>w_gcount_r210, DO0=>w_g2b_xor_cluster_0); LUT4_26: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>w_g2b_xor_cluster_1); LUT4_25: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r9); LUT4_24: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>wcount_r8); LUT4_23: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); LUT4_22: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); LUT4_21: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r4); LUT4_20: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r3); LUT4_19: ROM16X1A generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r2); LUT4_18: ROM16X1A generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + AD1=>w_gcount_r21, AD0=>w_gcount_r22, DO0=>wcount_r1); LUT4_17: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2); LUT4_16: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); LUT4_15: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_gcount_w210, + DO0=>r_g2b_xor_cluster_0); LUT4_14: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_1); LUT4_13: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w9); LUT4_12: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8); LUT4_11: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); LUT4_10: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); LUT4_9: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4); LUT4_8: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3); LUT4_7: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2); LUT4_6: ROM16X1A generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); + AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1); LUT4_5: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2); LUT4_4: ROM16X1A generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); XOR2_t0: XOR2 - port map (A=>w_gcount_r211, B=>rptr_9, Z=>rfill_sub_msb); + port map (A=>w_gcount_r210, B=>rptr_10, Z=>rfill_sub_msb); LUT4_3: ROM16X1A generic map (initval=> X"0410") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r211, + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>empty_cmp_set); LUT4_2: ROM16X1A generic map (initval=> X"1004") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r211, + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>empty_cmp_clr); LUT4_1: ROM16X1A generic map (initval=> X"0140") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w29, + port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>full_cmp_set); LUT4_0: ROM16X1A generic map (initval=> X"4001") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w29, + port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>full_cmp_clr); - pdp_ram_0_0_0: DP16KC + pdp_ram_0_0_2: DP16KC generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 36, - DATA_WIDTH_A=> 9) + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo, - ADB4=>scuba_vlo, ADB5=>rptr_0, ADB6=>rptr_1, ADB7=>rptr_2, - ADB8=>rptr_3, ADB9=>rptr_4, ADB10=>rptr_5, ADB11=>rptr_6, - ADB12=>rptr_7, ADB13=>rptr_8, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0), - DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), - DOA6=>Q(6), DOA7=>Q(7), DOA8=>open, DOA9=>Q(8), DOA10=>Q(9), - DOA11=>Q(10), DOA12=>Q(11), DOA13=>Q(12), DOA14=>Q(13), - DOA15=>Q(14), DOA16=>Q(15), DOA17=>open, DOB0=>Q(16), - DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>Q(20), - DOB5=>Q(21), DOB6=>Q(22), DOB7=>Q(23), DOB8=>open, - DOB9=>Q(24), DOB10=>Q(25), DOB11=>Q(26), DOB12=>Q(27), - DOB13=>Q(28), DOB14=>Q(29), DOB15=>Q(30), DOB16=>Q(31), - DOB17=>open); - - FF_121: FD1P3BX + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, + ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, + ADB10=>rptr_6, ADB11=>rptr_7, ADB12=>rptr_8, ADB13=>rptr_9, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), + DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), + DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11), DOB12=>Q(12), + DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15), DOB16=>Q(16), + DOB17=>Q(17)); + + pdp_ram_0_1_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), + DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), + DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), + DIA9=>Data(27), DIA10=>Data(28), DIA11=>Data(29), + DIA12=>Data(30), DIA13=>Data(31), DIA14=>Data(32), + DIA15=>Data(33), DIA16=>Data(34), DIA17=>Data(35), + ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, + ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, + ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, + ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, + ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, + ADB11=>rptr_7, ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, + CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(18), + DOB1=>Q(19), DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), + DOB5=>Q(23), DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), + DOB9=>Q(27), DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), + DOB13=>Q(31), DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), + DOB17=>Q(35)); + + pdp_ram_0_2_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(36), DIA1=>Data(37), DIA2=>Data(38), + DIA3=>Data(39), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, + ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, + ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, + ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, + ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, + ADB11=>rptr_7, ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, + CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(36), + DOB1=>Q(37), DOB2=>Q(38), DOB3=>Q(39), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + FF_122: FD1P3BX port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); - FF_120: FD1P3DX + FF_121: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); - FF_119: FD1P3DX + FF_120: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); - FF_118: FD1P3DX + FF_119: FD1P3DX port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_3); - FF_117: FD1P3DX + FF_118: FD1P3DX port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_4); - FF_116: FD1P3DX + FF_117: FD1P3DX port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_5); - FF_115: FD1P3DX + FF_116: FD1P3DX port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_6); - FF_114: FD1P3DX + FF_115: FD1P3DX port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_7); - FF_113: FD1P3DX + FF_114: FD1P3DX port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_8); - FF_112: FD1P3DX + FF_113: FD1P3DX port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_9); - FF_111: FD1P3DX + FF_112: FD1P3DX port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_10); - FF_110: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_109: FD1P3DX + FF_111: FD1P3DX port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); - FF_108: FD1P3DX + FF_110: FD1P3DX port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); - FF_107: FD1P3DX + FF_109: FD1P3DX port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); - FF_106: FD1P3DX + FF_108: FD1P3DX port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_3); - FF_105: FD1P3DX + FF_107: FD1P3DX port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_4); - FF_104: FD1P3DX + FF_106: FD1P3DX port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_5); - FF_103: FD1P3DX + FF_105: FD1P3DX port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_6); - FF_102: FD1P3DX + FF_104: FD1P3DX port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_7); - FF_101: FD1P3DX + FF_103: FD1P3DX port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_8); - FF_100: FD1P3DX + FF_102: FD1P3DX port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_9); - FF_99: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + FF_101: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_10); - FF_98: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_97: FD1P3DX + FF_100: FD1P3DX port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); - FF_96: FD1P3DX + FF_99: FD1P3DX port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); - FF_95: FD1P3DX + FF_98: FD1P3DX port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); - FF_94: FD1P3DX + FF_97: FD1P3DX port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_3); - FF_93: FD1P3DX + FF_96: FD1P3DX port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_4); - FF_92: FD1P3DX + FF_95: FD1P3DX port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_5); - FF_91: FD1P3DX + FF_94: FD1P3DX port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_6); - FF_90: FD1P3DX + FF_93: FD1P3DX port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_7); - FF_89: FD1P3DX + FF_92: FD1P3DX port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_8); - FF_88: FD1P3DX + FF_91: FD1P3DX port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_9); - FF_87: FD1P3DX + FF_90: FD1P3DX port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_10); - FF_86: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_85: FD1P3BX + FF_89: FD1P3BX port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); - FF_84: FD1P3DX + FF_88: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); - FF_83: FD1P3DX + FF_87: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); - FF_82: FD1P3DX + FF_86: FD1P3DX port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_3); - FF_81: FD1P3DX + FF_85: FD1P3DX port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_4); - FF_80: FD1P3DX + FF_84: FD1P3DX port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_5); - FF_79: FD1P3DX + FF_83: FD1P3DX port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_6); - FF_78: FD1P3DX + FF_82: FD1P3DX port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_7); - FF_77: FD1P3DX + FF_81: FD1P3DX port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_8); - FF_76: FD1P3DX + FF_80: FD1P3DX port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_9); - FF_75: FD1P3DX + FF_79: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_78: FD1P3DX port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); - FF_74: FD1P3DX + FF_77: FD1P3DX port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); - FF_73: FD1P3DX + FF_76: FD1P3DX port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); - FF_72: FD1P3DX + FF_75: FD1P3DX port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_3); - FF_71: FD1P3DX + FF_74: FD1P3DX port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_4); - FF_70: FD1P3DX + FF_73: FD1P3DX port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_5); - FF_69: FD1P3DX + FF_72: FD1P3DX port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_6); - FF_68: FD1P3DX + FF_71: FD1P3DX port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_7); - FF_67: FD1P3DX + FF_70: FD1P3DX port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_8); - FF_66: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + FF_69: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_9); - FF_65: FD1P3DX + FF_68: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_67: FD1P3DX port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); - FF_64: FD1P3DX + FF_66: FD1P3DX port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); - FF_63: FD1P3DX + FF_65: FD1P3DX port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); - FF_62: FD1P3DX + FF_64: FD1P3DX port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_3); - FF_61: FD1P3DX + FF_63: FD1P3DX port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_4); - FF_60: FD1P3DX + FF_62: FD1P3DX port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_5); - FF_59: FD1P3DX + FF_61: FD1P3DX port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_6); - FF_58: FD1P3DX + FF_60: FD1P3DX port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_7); - FF_57: FD1P3DX + FF_59: FD1P3DX port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_8); - FF_56: FD1P3DX + FF_58: FD1P3DX port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_9); - FF_55: FD1S3DX + FF_57: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_56: FD1S3DX port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - FF_54: FD1S3DX + FF_55: FD1S3DX port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - FF_53: FD1S3DX + FF_54: FD1S3DX port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - FF_52: FD1S3DX + FF_53: FD1S3DX port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - FF_51: FD1S3DX + FF_52: FD1S3DX port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - FF_50: FD1S3DX + FF_51: FD1S3DX port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - FF_49: FD1S3DX + FF_50: FD1S3DX port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - FF_48: FD1S3DX + FF_49: FD1S3DX port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - FF_47: FD1S3DX + FF_48: FD1S3DX port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - FF_46: FD1S3DX + FF_47: FD1S3DX port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - FF_45: FD1S3DX + FF_46: FD1S3DX port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, Q=>w_gcount_r10); + FF_45: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + FF_44: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); FF_43: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); FF_42: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); FF_41: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); FF_40: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); FF_39: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); FF_38: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); FF_37: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); FF_36: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); FF_35: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); FF_34: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_33: FD1S3DX port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r20); - FF_32: FD1S3DX + FF_33: FD1S3DX port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r21); - FF_31: FD1S3DX + FF_32: FD1S3DX port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r22); - FF_30: FD1S3DX + FF_31: FD1S3DX port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r23); - FF_29: FD1S3DX + FF_30: FD1S3DX port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r24); - FF_28: FD1S3DX + FF_29: FD1S3DX port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r25); - FF_27: FD1S3DX + FF_28: FD1S3DX port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r26); - FF_26: FD1S3DX + FF_27: FD1S3DX port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r27); - FF_25: FD1S3DX + FF_26: FD1S3DX port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r28); - FF_24: FD1S3DX + FF_25: FD1S3DX port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r29); - FF_23: FD1S3DX + FF_24: FD1S3DX port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, Q=>w_gcount_r210); + FF_23: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + FF_22: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); FF_21: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); FF_20: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); FF_19: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); FF_18: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); FF_17: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); FF_16: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); FF_15: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); FF_14: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); FF_13: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); FF_12: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); FF_11: FD1S3DX - port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); + port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); FF_10: FD1S3DX - port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); + port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); FF_9: FD1S3DX - port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); + port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); FF_8: FD1S3DX - port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); + port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); FF_7: FD1S3DX - port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); + port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); FF_6: FD1S3DX - port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); + port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); FF_5: FD1S3DX - port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); + port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); FF_4: FD1S3DX - port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); + port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); FF_3: FD1S3DX - port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); + port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); FF_2: FD1S3DX - port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); + port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); FF_1: FD1S3BX port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); @@ -1255,8 +1343,8 @@ begin NC0=>iwcount_8, NC1=>iwcount_9); w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); + port map (CI=>co4, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5, + NC0=>iwcount_10, NC1=>open); r_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, @@ -1283,7 +1371,11 @@ begin port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, NC0=>ircount_8, NC1=>ircount_9); - precin_inst276: FADD2B + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1, + NC0=>ircount_10, NC1=>open); + + precin_inst317: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, S1=>open); @@ -1292,55 +1384,63 @@ begin port map (Z=>scuba_vhi); rfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo, + port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, B1=>rptr_0, BI=>precin, BOUT=>co0_2, S0=>open, S1=>rfill_sub_0); rfill_1: FSUB2B - port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_1, B1=>rptr_2, + port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rptr_1, B1=>rptr_2, BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2); rfill_2: FSUB2B - port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rptr_3, B1=>rptr_4, + port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_3, B1=>rptr_4, BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4); rfill_3: FSUB2B - port map (A0=>wcount_r7, A1=>w_g2b_xor_cluster_0, B0=>rptr_5, - B1=>rptr_6, BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5, - S1=>rfill_sub_6); + port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rptr_5, B1=>rptr_6, + BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5, S1=>rfill_sub_6); rfill_4: FSUB2B - port map (A0=>wcount_r9, A1=>wcount_r10, B0=>rptr_7, B1=>rptr_8, - BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8); + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r8, B0=>rptr_7, + B1=>rptr_8, BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, + S1=>rfill_sub_8); rfill_5: FSUB2B - port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>rfill_sub_9, - S1=>open); + port map (A0=>wcount_r9, A1=>rfill_sub_msb, B0=>rptr_9, + B1=>scuba_vlo, BI=>co4_2, BOUT=>co5_2, S0=>rfill_sub_9, + S1=>rfill_sub_10); + + rfilld: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co5_2, COUT=>open, S0=>co5_2d, S1=>open); empty_cmp_ci_a: FADD2B port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2, - B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3); + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3); empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4, - B1=>wcount_r5, CI=>co0_3, GE=>co1_3); + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_3, GE=>co1_3); empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6, - B1=>wcount_r7, CI=>co1_3, GE=>co2_3); + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_3, GE=>co2_3); empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r9, CI=>co2_3, GE=>co3_3); + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>w_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3); empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r10, - B1=>empty_cmp_clr, CI=>co3_3, GE=>empty_d_c); + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_3, GE=>co4_3); + + empty_cmp_5: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co4_3, GE=>empty_d_c); a0: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -1352,28 +1452,28 @@ begin CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4); + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4); full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0, - B1=>rcount_w1, CI=>co0_4, GE=>co1_4); + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_4, GE=>co1_4); full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2, - B1=>rcount_w3, CI=>co1_4, GE=>co2_4); + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_4, GE=>co2_4); full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4, - B1=>rcount_w5, CI=>co2_4, GE=>co3_4); + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>r_g2b_xor_cluster_0, CI=>co2_4, GE=>co3_4); full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co3_4, GE=>co4_3); + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_4, GE=>co4_4); full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co4_4, GE=>full_d_c); scuba_vlo_inst: VLO port map (Z=>scuba_vlo); diff --git a/mupix/Mupix8/cores/serdes_fifo_large.ipx b/mupix/Mupix8/cores/serdes_fifo_large.ipx deleted file mode 100644 index 6807f6c..0000000 --- a/mupix/Mupix8/cores/serdes_fifo_large.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/mupix/Mupix8/cores/serdes_fifo_large.lpc b/mupix/Mupix8/cores/serdes_fifo_large.lpc deleted file mode 100644 index bd8733b..0000000 --- a/mupix/Mupix8/cores/serdes_fifo_large.lpc +++ /dev/null @@ -1,50 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN672C -SpeedGrade=8 -Package=FPBGA672 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.8 -ModuleName=serdes_fifo_large -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=01/11/2018 -Time=13:50:20 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=4096 -Width=8 -RDepth=1024 -RWidth=32 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=1 -WDataCount=0 -EnECC=0 - -[Command] -cmd_line= -w -n serdes_fifo_large -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 8 -num_words 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -rfill diff --git a/mupix/Mupix8/cores/serdes_fifo_large.vhd b/mupix/Mupix8/cores/serdes_fifo_large.vhd deleted file mode 100644 index 7ae36c1..0000000 --- a/mupix/Mupix8/cores/serdes_fifo_large.vhd +++ /dev/null @@ -1,1571 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4 --- Module Version: 5.8 ---/home/soft/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n serdes_fifo_large -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 8 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -rfill - --- Thu Jan 11 13:50:20 2018 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity serdes_fifo_large is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(31 downto 0); - RCNT: out std_logic_vector(10 downto 0); - Empty: out std_logic; - Full: out std_logic); -end serdes_fifo_large; - -architecture Structure of serdes_fifo_large is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal wcount_r1: std_logic; - signal wcount_r0: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal rptr_10: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal co6: std_logic; - signal co5: std_logic; - signal wcount_12: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal co5_1: std_logic; - signal co4_1: std_logic; - signal rcount_10: std_logic; - signal rfill_sub_0: std_logic; - signal precin: std_logic; - signal rptr_0: std_logic; - signal scuba_vhi: std_logic; - signal rfill_sub_1: std_logic; - signal rfill_sub_2: std_logic; - signal co0_2: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rfill_sub_3: std_logic; - signal rfill_sub_4: std_logic; - signal co1_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rfill_sub_5: std_logic; - signal rfill_sub_6: std_logic; - signal co2_2: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rfill_sub_7: std_logic; - signal rfill_sub_8: std_logic; - signal co3_2: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rfill_sub_9: std_logic; - signal rfill_sub_10: std_logic; - signal co4_2: std_logic; - signal rptr_9: std_logic; - signal rfill_sub_msb: std_logic; - signal co5_2d: std_logic; - signal co5_2: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_3: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_3: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_3: std_logic; - signal wcount_r8: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_3: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_3: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_4: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_4: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_4: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_4: std_logic; - signal rcount_w6: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_4: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "serdes_fifo_large.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "serdes_fifo_large.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - AND2_t25: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t24: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t23: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t22: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t21: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t20: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t19: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t18: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t17: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t16: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t15: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t14: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t13: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t12: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t11: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>r_gcount_w210, - DO0=>r_g2b_xor_cluster_0); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, - DO0=>r_g2b_xor_cluster_1); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - XOR2_t0: XOR2 - port map (A=>w_gcount_r212, B=>rptr_10, Z=>rfill_sub_msb); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w210, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w210, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, - ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, - ADB11=>rptr_7, ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, - CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(8), DOB5=>Q(9), - DOB6=>Q(10), DOB7=>Q(11), DOB8=>open, DOB9=>Q(16), - DOB10=>Q(17), DOB11=>Q(18), DOB12=>Q(19), DOB13=>Q(24), - DOB14=>Q(25), DOB15=>Q(26), DOB16=>Q(27), DOB17=>open); - - pdp_ram_0_1_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), - DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, - ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, - ADB11=>rptr_7, ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, - CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), - DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>Q(12), DOB5=>Q(13), - DOB6=>Q(14), DOB7=>Q(15), DOB8=>open, DOB9=>Q(20), - DOB10=>Q(21), DOB11=>Q(22), DOB12=>Q(23), DOB13=>Q(28), - DOB14=>Q(29), DOB15=>Q(30), DOB16=>Q(31), DOB17=>open); - - FF_132: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_131: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_130: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_129: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_128: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_127: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_126: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_125: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_124: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_123: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_122: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_121: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_120: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_119: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_118: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_117: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_116: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_115: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_114: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_113: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_112: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_111: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_110: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_109: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_108: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_107: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_106: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_105: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_104: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_103: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_102: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_101: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_100: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_99: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_98: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_97: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_96: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_95: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_94: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_93: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_92: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_91: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_90: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_89: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_88: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_87: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_86: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_85: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_84: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_83: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_82: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_81: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_80: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_79: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_78: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_77: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_76: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_75: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_74: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_73: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_72: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_71: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_70: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_69: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_68: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_67: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_66: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_65: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_64: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_63: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_62: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_61: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_60: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_59: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_58: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_57: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_56: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_55: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_54: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_53: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_52: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_51: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_50: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_49: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_48: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_47: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_46: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_45: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_44: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_43: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_42: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_41: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_40: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_39: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_38: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_37: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_36: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_35: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_34: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_33: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_32: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_31: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_30: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_29: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_28: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_27: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_26: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_25: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_24: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_23: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_22: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_21: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_20: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_19: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_18: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_17: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_16: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_15: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_14: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_13: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_12: FD1S3DX - port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); - - FF_11: FD1S3DX - port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); - - FF_10: FD1S3DX - port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); - - FF_9: FD1S3DX - port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); - - FF_8: FD1S3DX - port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); - - FF_7: FD1S3DX - port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); - - FF_6: FD1S3DX - port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); - - FF_5: FD1S3DX - port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); - - FF_4: FD1S3DX - port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); - - FF_3: FD1S3DX - port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); - - FF_2: FD1S3DX - port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1, - NC0=>ircount_10, NC1=>open); - - precin_inst297: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, - S1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - rfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo, - B1=>rptr_0, BI=>precin, BOUT=>co0_2, S0=>open, - S1=>rfill_sub_0); - - rfill_1: FSUB2B - port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_1, B1=>rptr_2, - BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2); - - rfill_2: FSUB2B - port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rptr_3, B1=>rptr_4, - BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4); - - rfill_3: FSUB2B - port map (A0=>wcount_r7, A1=>wcount_r8, B0=>rptr_5, B1=>rptr_6, - BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5, S1=>rfill_sub_6); - - rfill_4: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r10, B0=>rptr_7, - B1=>rptr_8, BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, - S1=>rfill_sub_8); - - rfill_5: FSUB2B - port map (A0=>wcount_r11, A1=>rfill_sub_msb, B0=>rptr_9, - B1=>scuba_vlo, BI=>co4_2, BOUT=>co5_2, S0=>rfill_sub_9, - S1=>rfill_sub_10); - - rfilld: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co5_2, COUT=>open, S0=>co5_2d, S1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2, - B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4, - B1=>wcount_r5, CI=>co0_3, GE=>co1_3); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6, - B1=>wcount_r7, CI=>co1_3, GE=>co2_3); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r10, - B1=>wcount_r11, CI=>co3_3, GE=>co4_3); - - empty_cmp_5: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co4_3, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0, - B1=>rcount_w1, CI=>co0_4, GE=>co1_4); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2, - B1=>rcount_w3, CI=>co1_4, GE=>co2_4); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4, - B1=>rcount_w5, CI=>co2_4, GE=>co3_4); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w6, - B1=>r_g2b_xor_cluster_0, CI=>co3_4, GE=>co4_4); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w8, - B1=>rcount_w9, CI=>co4_4, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of serdes_fifo_large is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FSUB2B use entity ecp3.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/mupix/Mupix8/sources/DataMuxWithConversion.vhd b/mupix/Mupix8/sources/DataMuxWithConversion.vhd index f8d7f6b..80d5a8c 100644 --- a/mupix/Mupix8/sources/DataMuxWithConversion.vhd +++ b/mupix/Mupix8/sources/DataMuxWithConversion.vhd @@ -39,7 +39,7 @@ end entity FiFoDataMuxWithConversion; architecture RTL of FiFoDataMuxWithConversion is signal ticks_counter : unsigned(f_log2(g_clockspeed) - 1 downto 0) := (others => '0'); - signal inword_counter : t_counter_array(0 to g_inputs - 1) := (others => (others => '0')); + signal inword_counter : t_counter32_array(0 to g_inputs - 1) := (others => (others => '0')); signal increase_counter : std_logic_vector(g_inputs - 1 downto 0) := (others => '0'); signal fifo_full_i : std_logic; @@ -115,8 +115,6 @@ begin else if increase_counter(fifo_sel_reg) = '1' then inword_counter(fifo_sel_reg) <= inword_counter(fifo_sel_reg) + 1; - else - inword_counter(fifo_sel_reg) <= inword_counter(fifo_sel_reg); end if; if ticks_counter = g_clockspeed - 1 then inword_counter <= (others => (others => '0')); diff --git a/mupix/Mupix8/sources/GrayCounter2.vhd b/mupix/Mupix8/sources/GrayCounter2.vhd index 79c9c3f..89d988b 100644 --- a/mupix/Mupix8/sources/GrayCounter2.vhd +++ b/mupix/Mupix8/sources/GrayCounter2.vhd @@ -18,7 +18,7 @@ entity Graycounter2 is inc_en : in std_logic; -- increment counter enable counter : out std_logic_vector(COUNTWIDTH - 1 downto 0) -- counter ); -end Graycounter; +end Graycounter2; architecture rtl of Graycounter2 is diff --git a/mupix/Mupix8/sources/LinkSynchronizer.vhd b/mupix/Mupix8/sources/LinkSynchronizer.vhd index dde4142..43f9435 100644 --- a/mupix/Mupix8/sources/LinkSynchronizer.vhd +++ b/mupix/Mupix8/sources/LinkSynchronizer.vhd @@ -31,7 +31,7 @@ architecture rtl of LinkSynchronizer is signal sync_fsm : sync_state_type := idle; signal look_counter : integer range 0 to look_counter_max - 1 := 0; - signal comma_counter : integer range 0 to 2**32 - 1 := 0; + signal comma_counter : integer range 0 to 2**16 - 1 := 0; signal look_enable : std_logic := '0'; signal comma_seen : std_logic := '0'; signal link_sync_i : std_logic := '0'; @@ -133,7 +133,7 @@ begin -- architecture rtl end if; end process sync_proc; - comma_counter_out <= std_logic_vector(to_unsigned(comma_counter, 16)); + comma_counter_out <= std_logic_vector(to_unsigned(comma_counter, 32)); link_sync_out <= link_sync_i; end architecture rtl; diff --git a/mupix/Mupix8/sources/MuPixDataLink_new.vhd b/mupix/Mupix8/sources/MuPixDataLink_new.vhd index 08bfea7..35d7c04 100644 --- a/mupix/Mupix8/sources/MuPixDataLink_new.vhd +++ b/mupix/Mupix8/sources/MuPixDataLink_new.vhd @@ -202,8 +202,6 @@ architecture rtl of MupixDataLinkWithUnpacker is signal rx_dataerror_sync : std_logic_vector(3 downto 0); signal rx_data_sync : std_logic_vector(4*8 - 1 downto 0); signal rx_komma_sync : std_logic_vector(3 downto 0); - signal rx_disp_err_sync : std_logic_vector(3 downto 0); - signal rx_dataerror_sync : std_logic_vector(3 downto 0); -- fifo signals signal fifo_data_oi : std_logic_vector(c_links*c_mupixhitsize - 1 downto 0); @@ -212,18 +210,18 @@ architecture rtl of MupixDataLinkWithUnpacker is signal fifo_full_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); signal fifo_wren_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); signal fifo_rden_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); - constant fifo_depth : integer := 10; -- fifo depth (change when regenerating FIFO IP core) - signal fifo_readcnt_i : std_logic_vector((c_links - 1)*fifo_depth - 1 downto 0); + constant fifo_depth : integer := 11; -- fifo depth (change when regenerating FIFO IP core) + signal fifo_readcnt_i : std_logic_vector(c_links*fifo_depth - 1 downto 0); -- status and error counters - signal serdes_channel_select : integer range 0 to 3 := 0; - signal disp_error_counter : t_counter_array(0 to 3) := (others => (others => '0')); - signal data_error_counter : t_counter_array(0 to 3) := (others => (others => '0')); - signal unpacker_error_counter : t_counter_array(0 to 3) := (others => (others => '0')); + signal serdes_channel_select : integer range 0 to 3 := 0; + signal disp_error_counter : t_vector32_array(0 to 3) := (others => (others => '0')); + signal data_error_counter : t_vector32_array(0 to 3) := (others => (others => '0')); + signal unpacker_error_counter : t_vector32_array(0 to 3) := (others => (others => '0')); -- link synchronizer signals signal link_sync_flag_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); - signal komma_counter : t_counter_array(0 to 3) := (others => (others => '0')); + signal komma_counter : t_vector32_array(0 to 3) := (others => (others => '0')); -- unpacker signals signal unpacker_valid_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); @@ -315,30 +313,37 @@ begin rst_n => reset_serdes_i, -- reset all channels including PCS (active -- low, not documented in maunal -> consult -- vhdl code) - serdes_rst_qd_c => clear_quad_i); -- reset all serdes channels but not PCS (active high) + serdes_rst_qd_c => reset_quad_i); -- reset all serdes channels but not PCS (active high) -- synchronize rx data signals into receive clock domain (maybe not -- necessary, but should not do any harm) - rx_komma_s : InputSynchronizer - generic map (depth => 2, width => 4) - port map (clk => clkrx, rst => rst, input => rx_komma_i, sync_output => rx_komma_sync); - - rx_disp_err_s : InputSynchronizer - generic map (depth => 2, width => 4) - port map (clk => clkrx, rst => rst, input => rx_disp_err_i, sync_output => rx_disp_err_sync); - - rx_dataerror_s : InputSynchronizer - generic map (depth => 2, width => 4) - port map (clk => clkrx, rst => rst, input => rx_dataerror_i, sync_output => rx_dataerror_sync); + rx_komma_gen : for i in 0 to 3 generate + rx_komma_s : InputSynchronizer + generic map (depth => 2, width => 1) + port map (clk => clkrx(i), rst => rst, input(0) => rx_komma_i(i), sync_output(0) => rx_komma_sync(i)); + end generate rx_komma_gen; + + rx_disp_gen : for i in 0 to 3 generate + rx_disp_err_s : InputSynchronizer + generic map (depth => 2, width => 1) + port map (clk => clkrx(i), rst => rst, input(0) => rx_disp_err_i(i), sync_output(0) => rx_disp_err_sync(i)); + end generate rx_disp_gen; + + rx_dataerror_gen : for i in 0 to 3 generate + rx_dataerror_s : InputSynchronizer + generic map (depth => 2, width => 1) + port map (clk => clkrx(i), rst => rst, input(0) => rx_dataerror_i(i), sync_output(0) => rx_dataerror_sync(i)); + end generate rx_dataerror_gen; rx_data_gen : for i in 0 to 3 generate rx_data_s : InputSynchronizer generic map (depth => 2, width => 8) - port map (clk => clkrx, rst => rst, + port map (clk => clkrx(i), rst => rst, input => rx_data_i((i + 1)*8 - 1 downto i*8), - sync_output => rx_data_sync((i + 1)*8 - 1 downto i*8)) - end generate rx_data_s; + sync_output => rx_data_sync((i + 1)*8 - 1 downto i*8)); + end generate rx_data_gen; + -- synchronize status signals into trb clock domain sync_los_low : InputSynchronizer generic map(depth => 2, width => 4) @@ -350,53 +355,53 @@ begin -- component to generate sync signal to serdes based on comma word detection generate_synchronizer : for j in 0 to c_links - 1 generate - entity work.LinkSynchronizer + LinkSynchronizer : entity work.LinkSynchronizer generic map ( clk_speed => 8) port map ( - clk_in => clkrx, + clk_in => clkrx(j), reset_in => rst, comma_in => rx_komma_sync(j), cverr_in => rx_dataerror_sync(j), link_sync_out => align_en_i(j), link_sync_flag => link_sync_flag_i(j), - comma_counter_gray => std_logic_vector(komma_counter(j)), + comma_counter_gray => komma_counter(j), comma_counter_out => open); end generate generate_synchronizer; -- unpacker for mupix data from serdes data stream unpacker_valid_i <= not rx_dataerror_sync and link_sync_flag_i; generate_unpacker : for j in 0 to c_links - 1 generate - entity work.MupixUnpacker + unpacker : entity work.MupixUnpacker generic map ( g_hitsize => c_mupixhitsize, - g_countersize => 31) + g_countersize => 32) port map ( - clk => clkrx, - reset => rst, - data_in => rx_data_sync((j + 1)*8 - 1 downto j*8), - komma => rx_komma_sync(j), - valid => unpacker_valid_i(j), - hit_out => fifo_data_ii((j + 1)*c_mupixhitsize downto j*c_mupixhitsize), - hit_enable => fifo_wren_i(j), - coarsecounter => open, - counter_enable => open, - link_flag => open, - errorcounter_gray => unpacker_error_counter(j) - errorcounter => open); - end generate generate_fifo; + clk => clkrx(j), + reset => rst, + data_in => rx_data_sync((j + 1)*8 - 1 downto j*8), + komma => rx_komma_sync(j), + valid => unpacker_valid_i(j), + hit_out => fifo_data_ii((j + 1)*c_mupixhitsize - 1 downto j*c_mupixhitsize), + hit_enable => fifo_wren_i(j), + coarsecounter => open, + counter_enable => open, + link_flag => open, + errorcounter_gray => unpacker_error_counter(j), + errorcounter => open); + end generate generate_unpacker; generate_fifo : for j in 0 to c_links - 1 generate - entity work.serdes_fifo + fifo : entity work.serdes_fifo port map ( - Data => fifo_data_ii((j + 1)*c_mupixhitsize downto j*c_mupixhitsize), + Data => fifo_data_ii((j + 1)*c_mupixhitsize - 1 downto j*c_mupixhitsize), WrClock => clkrx(j), RdClock => sysclk, WrEn => fifo_wren_i(j), RdEn => fifo_rden_i(j), Reset => reset_fifos_i, RPReset => reset_fifos_i, - Q => fifo_data_oi((j + 1)*c_mupixhitsize downto j*c_mupixhitsize), + Q => fifo_data_oi((j + 1)*c_mupixhitsize - 1 downto j*c_mupixhitsize), RCNT => fifo_readcnt_i((j + 1)*fifo_depth - 1 downto j*fifo_depth), Empty => fifo_empty_i(j), Full => fifo_full_i(j)); @@ -408,21 +413,21 @@ begin disp_err_cnt : Graycounter2 generic map (COUNTWIDTH => 32) port map ( - clk => clkrx, + clk => clkrx(i), reset => rst, inc_en => rx_disp_err_sync(i), - counter => std_logic_vector(disp_error_counter(i))) - end generate disp_err_cnt; + counter => disp_error_counter(i)); + end generate disp_err_cnt_gen; data_err_cnt_gen : for i in 0 to 3 generate data_err_cnt : Graycounter2 generic map (COUNTWIDTH => 32) port map ( - clk => clkrx, + clk => clkrx(i), reset => rst, inc_en => rx_dataerror_sync(i), - counter => std_logic_vector(data_error_counter(i))) - end generate data_error_cnt_gen; + counter => data_error_counter(i)); + end generate data_err_cnt_gen; -- purpose: slow control of data link slowcontrol_proc : process (sysclk) is @@ -441,7 +446,7 @@ begin slv_unknown_addr_out <= '0'; reset_counters_i <= '0'; reset_serdes_i <= '1'; --active low - clear_quad_i <= '0'; + reset_quad_i <= '0'; reset_fifos_i <= '0'; if slv_write_in = '1' then case slv_addr_in is @@ -498,4 +503,4 @@ begin end if; end process slowcontrol_proc; - end architecture; +end architecture; diff --git a/mupix/Mupix8/sources/MuPixUnpacker.vhd b/mupix/Mupix8/sources/MuPixUnpacker.vhd index 3ae0c2a..d4df0a3 100644 --- a/mupix/Mupix8/sources/MuPixUnpacker.vhd +++ b/mupix/Mupix8/sources/MuPixUnpacker.vhd @@ -7,6 +7,8 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; +use work.Constants.all; + entity MupixUnpacker is generic( g_hitsize : integer := 40; @@ -62,8 +64,8 @@ begin generic map ( COUNTWIDTH => 32) port map ( - clk => clk_in, - reset => reset_in, + clk => clk, + reset => reset, inc_en => inc_en_i, counter => errorcounter_gray); diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index 5f5579b..56e7845 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -12,7 +12,7 @@ use work.trb_net_components.all; use work.trb3_components.all; use work.StdTypes.all; -use wirk.Constants.all; +use work.Constants.all; entity MupixBoard8 is port( @@ -208,10 +208,10 @@ architecture Behavioral of MupixBoard8 is rst : in std_logic; fifo_empty : in std_logic_vector(g_mupix_links - 1 downto 0); fifo_full : in std_logic_vector(g_mupix_links - 1 downto 0); - fifo_datain : in std_logic_vector(g_mupix_links*g_datawidth - 1 downto 0); + fifo_datain : in std_logic_vector(g_mupix_links*g_datawidthfifo - 1 downto 0); fifo_rden : out std_logic_vector(g_mupix_links - 1 downto 0); trb_trigger : in std_logic; - dataout : out std_logic_vector(g_datawidth - 1 downto 0); + dataout : out std_logic_vector(g_datawidthtrb - 1 downto 0); data_valid : out std_logic; busy : out std_logic; SLV_READ_IN : in std_logic; @@ -285,7 +285,7 @@ architecture Behavioral of MupixBoard8 is ); end component FrameGeneratorMux; - component MupixDataLink is + component MupixDataLinkWithUnpacker is port( sysclk : in std_logic; dataclk : in std_logic; @@ -293,9 +293,6 @@ architecture Behavioral of MupixBoard8 is clear : in std_logic; rst_fifo : in std_logic; mupix_data : in std_logic_vector(7 downto 0); - refclk2core : out std_logic; - clk_rx_half_out : out std_logic; - clk_rx_full_out : out std_logic; fifo_rden : in std_logic_vector(3 downto 0); fifo_empty : out std_logic_vector(3 downto 0); fifo_full : out std_logic_vector(3 downto 0); @@ -309,7 +306,7 @@ architecture Behavioral of MupixBoard8 is SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic); - end component MupixDataLink; + end component MupixDataLinkWithUnpacker; constant FIFO_DEPTH : positive := 256; --size of pseudo data generator fifos @@ -340,7 +337,7 @@ architecture Behavioral of MupixBoard8 is signal fifo_rden_serdes_i : std_logic_vector(c_links - 1 downto 0); signal fifo_empty_serdes_i : std_logic_vector(c_links - 1 downto 0); signal fifo_full_serdes_i : std_logic_vector(c_links - 1 downto 0); - signal fifo_data_serdes_i : std_logic_vector(c_mupixhitsize*c_links downto 0); + signal fifo_data_serdes_i : std_logic_vector(c_mupixhitsize*c_links - 1 downto 0); begin -- Behavioral @@ -609,9 +606,6 @@ begin -- Behavioral rst => reset, clear => reset, mupix_data => mupix_data, - refclk2core => open, - clk_rx_half_out => open, - clk_rx_full_out => open, fifo_rden => fifo_rden_serdes_i, fifo_empty => fifo_empty_serdes_i, fifo_full => fifo_full_serdes_i, diff --git a/mupix/Mupix8/sources/StdTypes.vhd b/mupix/Mupix8/sources/StdTypes.vhd index 4898b20..c3fbd79 100644 --- a/mupix/Mupix8/sources/StdTypes.vhd +++ b/mupix/Mupix8/sources/StdTypes.vhd @@ -14,10 +14,11 @@ package StdTypes is constant c_mupix_slctrl_init : MupixSlowControl := ('0', '0', '0', '0', '0'); - type t_counter_array is array(integer range <>) of unsigned(31 downto 0); + type t_counter32_array is array(integer range <>) of unsigned(31 downto 0); + type t_vector32_array is array(integer range <>) of std_logic_vector(31 downto 0); function f_log2(x : positive) return natural; - function counter_array_to_stdvec(x : t_counter_array) return std_logic_vector; + function counter_array_to_stdvec(x : t_counter32_array) return std_logic_vector; end package StdTypes; @@ -34,7 +35,7 @@ function f_log2(x : positive) return natural is end function; -function counter_array_to_stdvec(x : t_counter_array) return std_logic_vector is +function counter_array_to_stdvec(x : t_counter32_array) return std_logic_vector is variable tmp : std_logic_vector(32*x'length - 1 downto 0); begin tmp := (others => '0'); diff --git a/mupix/Mupix8/sources/constants.vhd b/mupix/Mupix8/sources/constants.vhd index c29e9d0..a920fb0 100644 --- a/mupix/Mupix8/sources/constants.vhd +++ b/mupix/Mupix8/sources/constants.vhd @@ -4,10 +4,13 @@ use IEEE.numeric_std.all; package Constants is - constant c_links : integer := 4: -- number of links from mupix - constant c_mupixhitsize : integer := 40; -- Link(8) & Row(8) & Col(8) & Charge(7) & TS(9) in hit mode - -- binary counter(24) & link(4) & x"3" & gray counte - constant k28_5 : std_logic_vector(7 downto 0) := x"bc"; - constant k28_0 : std_logic_vector(7 downto 0) := x"1c"; + constant c_links : integer := 4; -- number of links from mupix + constant c_mupixhitsize : integer := 40; -- Link(8) & Row(8) & Col(8) & Charge(7) & TS(9) in hit mode + -- binary counter(24) & link(4) & x"3" & gray counte + constant k28_5 : std_logic_vector(7 downto 0) := x"bc"; + constant k28_0 : std_logic_vector(7 downto 0) := x"1c"; + + constant c_Yes : integer := 1; + constant c_No : integer := 0; end package Constants; diff --git a/mupix/Mupix8/tb/DataMuxTest.vhd b/mupix/Mupix8/tb/DataMuxTest.vhd index cd1d2bc..0fa224a 100644 --- a/mupix/Mupix8/tb/DataMuxTest.vhd +++ b/mupix/Mupix8/tb/DataMuxTest.vhd @@ -9,7 +9,7 @@ end entity DataMuxTest; architecture sim of DataMuxTest is - component FiFoDataMux + component FiFoDataMuxWithConversion generic( g_datawidthfifo : integer := 40; g_datawidthtrb : integer := 32; @@ -29,7 +29,7 @@ architecture sim of DataMuxTest is wordin_freq : out std_logic_vector(32*g_inputs - 1 downto 0); fifo_full_o : out std_logic ); - end component FiFoDataMux; + end component FiFoDataMuxWithConversion; component STD_FIFO generic( @@ -98,7 +98,7 @@ begin ); end generate generate_fifo; - dut : component FiFoDataMux + dut : component FiFoDataMuxWithConversion generic map( g_datawidthfifo => c_datawidthfifo, g_datawidthtrb => c_datawidthtrb, diff --git a/mupix/Mupix8/trb3_periph.prj b/mupix/Mupix8/trb3_periph.prj index 37af33d..2aff52a 100644 --- a/mupix/Mupix8/trb3_periph.prj +++ b/mupix/Mupix8/trb3_periph.prj @@ -170,7 +170,7 @@ add_file -vhdl -lib "work" "sources/ResetHandler.vhd" add_file -vhdl -lib "work" "sources/CircularMemory.vhd" add_file -vhdl -lib "work" "sources/ReadoutController.vhd" add_file -vhdl -lib "work" "sources/MupixTRBReadout.vhd" -add_file -vhdl -lib "work" "sources/MupixDataLink_new.vhd" +add_file -vhdl -lib "work" "sources/MuPixDataLink_new.vhd" add_file -vhdl -lib "work" "sources/TriggerHandler.vhd" add_file -vhdl -lib "work" "sources/Arbiter.vhd" add_file -vhdl -lib "work" "sources/DatasourceSelector.vhd"