From: Benedikt Gutsche Date: Wed, 10 Jan 2024 10:30:16 +0000 (+0100) Subject: renamed files X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=fb3c8e2205757e3d06065159aa8f97fd651132f0;p=trb5sc.git renamed files --- diff --git a/vldb/trb5sc_vldb.lpf b/vldb/trb5sc_vldb.lpf deleted file mode 100644 index 1407584..0000000 --- a/vldb/trb5sc_vldb.lpf +++ /dev/null @@ -1,49 +0,0 @@ - -################################################################# -# Basic Settings -################################################################# - -FREQUENCY PORT CLK_200 200 MHz; -FREQUENCY PORT CLK_125 125 MHz; -FREQUENCY PORT CLK_EXT 200 MHz; - -FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; -FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; -# FREQUENCY NET "med_stat_debug[11]" 200 MHz; - -FREQUENCY NET "med2int_0.clk_full" 200 MHz; -# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; - - -BLOCK PATH TO PORT "LED*"; -BLOCK PATH TO PORT "PROGRAMN"; -BLOCK PATH TO PORT "TEMP_LINE"; -BLOCK PATH FROM PORT "TEMP_LINE"; -BLOCK PATH TO PORT "TEST_LINE*"; - -#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; -#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; -#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; -MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; - -MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; -MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; - -GSR_NET NET "clear_i"; - -# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; - - -REGION "MEDIA" "R81C44D" 13 25; -LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; - - -BLOCK NET "THE_MIMOSIS/THE_IN/reset_i"; -BLOCK NET "THE_MIMOSIS/THE_WORDS/reset_i"; -MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/PROC_REGS.add_re*" 20 ns; -MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/add_re*" 20 ns; -MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/CONF*" 20 ns; -MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.control_re*" 20 ns; - -BLOCK PATH TO CELL "THE_MIMOSIS/THE_IN/PROC_REGS.BUS_TX.dat*"; -BLOCK PATH TO CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.BUS_TX.dat*"; diff --git a/vldb/trb5sc_vldb.prj b/vldb/trb5sc_vldb.prj deleted file mode 100644 index df0bfb1..0000000 --- a/vldb/trb5sc_vldb.prj +++ /dev/null @@ -1,284 +0,0 @@ - -# implementation: "workdir" -impl -add workdir -type fpga - -# device options -set_option -technology ECP5UM -set_option -part LFE5UM_85F -set_option -package BG756C -set_option -speed_grade -8 -set_option -part_companion "" - -# compilation/mapping options -set_option -default_enum_encoding sequential -set_option -symbolic_fsm_compiler 1 -set_option -top_module "trb5sc_mimosis" -set_option -resource_sharing false -set_option -vhdl2008 true - -# map options -set_option -frequency 120 -set_option -fanout_limit 100 -set_option -disable_io_insertion 0 -set_option -retiming 1 -set_option -pipe 1 -set_option -forcegsr false -set_option -fixgatedclocks 3 -set_option -fixgeneratedclocks 3 -set_option -compiler_compatible true -set_option -multi_file_compilation_unit 1 - -set_option -max_parallel_jobs 3 -#set_option -automatic_compile_point 1 -#set_option -continue_on_error 1 -set_option -resolve_multiple_driver 1 - -# simulation options -set_option -write_verilog 0 -set_option -write_vhdl 1 - -# automatic place and route (vendor) options -set_option -write_apr_constraint 0 - -# set result format/file last -project -result_format "edif" -project -result_file "workdir/trb5sc_mimosis.edf" -set_option log_file "workdir/trb5sc_project.srf" -#implementation attributes - -set_option -vlog_std v2001 -set_option -project_relative_includes 1 -impl -active "workdir" - -#################### - -add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" - -#Packages -add_file -vhdl -lib work "workdir/version.vhd" -add_file -vhdl -lib work "config.vhd" -add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" - -#Basic Infrastructure -add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" -add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" -add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" -add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" - - -#Fifos -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd" - - -#Flash & Reload, Tools -add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" -add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" -add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd" -add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" -add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" -add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" -add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" -add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" -add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" -add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" - -#SlowControl files -add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" - -#Media interface -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" - - -######################################### -#channel 0, backplane -#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" -#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" - -#channel 1, SFP -#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" -#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" -########################################## - -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" -add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" - - -#TrbNet Endpoint -add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" -add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" -add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" -add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" -add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" - -add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" -add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" - -add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" -add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" -add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" -add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" - -add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" -add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" -add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" - -add_file -vhdl -lib work "./cores/mimosis_inp.vhd" -add_file -vhdl -lib work "./cores/testout.vhd" -add_file -vhdl -lib work "./code/MimosisInput.vhd" -add_file -vhdl -lib work "./code/InputStage.vhd" -add_file -vhdl -lib work "./code/WordAlign.vhd" -add_file -vhdl -lib work "./cores/pll_200_160/pll_200_160.vhd" - - - -#GbE -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" -add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v" -# Choose your SerDes location here -#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd" - -#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" - - - - - - - - - -add_file -vhdl -lib work "./trb5sc_mimosis.vhd" -#add_file -fpga_constraint "./synplify.fdc" - - - diff --git a/vldb/trb5sc_vldb.vhd b/vldb/trb5sc_vldb.vhd deleted file mode 100644 index 55130db..0000000 --- a/vldb/trb5sc_vldb.vhd +++ /dev/null @@ -1,778 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.version.all; -use work.config.all; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.med_sync_define.all; - -entity trb5sc_mimosis is - port( - CLK_200 : in std_logic; - CLK_125 : in std_logic; - CLK_EXT : in std_logic; - - TRIG_IN_BACKPL : in std_logic; --Reference Time - TRIG_IN_RJ45 : in std_logic; --Reference Time - IN_SELECT_EXT_CLOCK : in std_logic; - - SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 - BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 - - SFP_TX_DIS : out std_logic; - SFP_LOS : in std_logic; - SFP_MOD_0 : in std_logic; - - --AddOn - --FE_GPIO : inout std_logic_vector(11 downto 0); - --FE_CLK : out std_logic_vector( 2 downto 1); - --FE_DIFF : inout std_logic_vector(63 downto 0); - --INP : inout std_logic_vector(63 downto 0); - --LED_ADDON : out std_logic_vector(5 downto 0); - LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); - LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); - LED_ADDON_RJ : out std_logic_vector(1 downto 0); - SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); - SFP_ADDON_LOS : in std_logic_vector(1 downto 0); - - RJ : inout std_logic_vector(3 downto 0); - H1 : inout std_logic_vector(4 downto 0); - H2 : inout std_logic_vector(4 downto 0); - H3 : inout std_logic_vector(4 downto 0); - H4 : inout std_logic_vector(4 downto 0); - H5 : inout std_logic_vector(3 downto 0); - H6 : inout std_logic_vector(4 downto 0); - H7 : inout std_logic_vector(4 downto 0); - - PIN : out std_logic_vector(8 downto 1); - - MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; - - --ADC - ADC_SCLK : out std_logic; - ADC_NCS : out std_logic; - ADC_MOSI : out std_logic; - ADC_MISO : in std_logic; - --Flash, Reload - FLASH_SCLK : out std_logic; - FLASH_NCS : out std_logic; - FLASH_MOSI : out std_logic; - FLASH_MISO : in std_logic; - FLASH_HOLD : out std_logic; - FLASH_WP : out std_logic; - PROGRAMN : out std_logic; - --I2C - I2C_SDA : inout std_logic; - I2C_SCL : inout std_logic; - TMP_ALERT : in std_logic; - - --GBTSCA - SCA_RX : in std_logic(1 downto 0); - SCA_TX : out std_logic(1 downto 0); - SCA_CLK : out std_logic(1 downto 0); - - --LED - LED : out std_logic_vector(8 downto 1); - LED_SFP_YELLOW : out std_logic; - LED_SFP_GREEN : out std_logic; - LED_SFP_RED : out std_logic; - LED_RJ_GREEN : out std_logic_vector(1 downto 0); - LED_RJ_RED : out std_logic_vector(1 downto 0); - LED_EXT_CLOCK : out std_logic; - - --Other Connectors - TEST : inout std_logic_vector(14 downto 1); --on v1 only - --COMMON_SDA, COMMON_SCL : inout std_logic - HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only - ); - - attribute syn_useioff : boolean; - attribute syn_useioff of FLASH_NCS : signal is true; - attribute syn_useioff of FLASH_SCLK : signal is true; - attribute syn_useioff of FLASH_MOSI : signal is true; - attribute syn_useioff of FLASH_MISO : signal is true; - -end entity; - - -architecture arch of trb5sc_mimosis is - - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic; - signal GSR_N : std_logic; - signal reset_i : std_logic; - signal clear_i : std_logic; - signal trigger_in_i : std_logic; - - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - - signal debug_clock_reset : std_logic_vector(31 downto 0); - signal external_clock_lock : std_logic := '0'; - signal debug_tools : std_logic_vector(31 downto 0); - - --Media Interface - signal med2int : med2int_array_t(0 to 0); - signal int2med : int2med_array_t(0 to 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; - - - signal readout_rx : READOUT_RX; - signal readout_tx : readout_tx_array_t(0 to 0); - - signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbtsca_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbtsca_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX; - - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - - signal sed_error_i : std_logic; - signal clock_select : std_logic; - signal bus_master_active : std_logic; - signal flash_ncs_i : std_logic; - - signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); - signal header_io_i : std_logic_vector(10 downto 1); - signal timer : TIMERS; - signal add_reg : std_logic_vector(31 downto 0); - alias led_off : std_logic is add_reg(0); - - signal out_data : std_logic_vector(15 downto 0); - signal out_i : std_logic_vector( 7 downto 0); - signal inp_i : std_logic_vector( 7 downto 0); - signal gbe_status : std_logic_vector(15 downto 0); - - - signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); - signal i2c_reg_2 : std_logic_vector(31 downto 0); - signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); - signal mimosis_scl_drv, mimosis_sda_drv : std_logic; - signal i2c_go_100, i2c_go : std_logic; - signal i2c_reg_5_40 : std_logic_vector(31 downto 0); - signal counter : unsigned(23 downto 0); - - --signal fwd_dst_mac : std_logic_vector(47 downto 0); - --signal fwd_dst_ip : std_logic_vector(31 downto 0); - --signal fwd_dst_port : std_logic_vector(15 downto 0); - --signal fwd_data : std_logic_vector(7 downto 0); - --signal fwd_datavalid : std_logic; - --signal fwd_sop : std_logic; - --signal fwd_eop : std_logic; - --signal fwd_ready : std_logic; - --signal fwd_full : std_logic; - --signal fwd_length : std_logic_vector(15 downto 0); - --signal fwd_do_send : std_logic; - - -- -- GBTSCA - -- -- Clock & reset - -- signal gbtsc_tx_clk_i : in std_logic; --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency - -- signal gbtsc_tx_clk_en : in std_logic := '1'; --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled - -- signal gbtsc_rx_clk_i : in std_logic; --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency - -- signal gbtsc_rx_clk_en : in std_logic := '1'; --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled - -- signal gbtsc_rx_reset_i : in std_logic; --! Reset RX datapath - -- signal gbtsc_tx_reset_i : in std_logic; --! Reset TX datapath - -- -- IC control - -- signal gbtsc_tx_start_write_i : in std_logic; --! Request a write config. to the GBTx (IC) - -- signal gbtsc_tx_start_read_i : in std_logic; --! Request a read config. to the GBTx (IC) - -- -- IC configuration - -- signal gbtsc_tx_GBTx_address_i : in std_logic_vector(7 downto 0); --! I2C address of the GBTx - -- signal gbtsc_tx_register_addr_i : in std_logic_vector(15 downto 0); --! Address of the first register to be accessed - -- signal gbtsc_tx_nb_to_be_read_i : in std_logic_vector(15 downto 0); --! Number of words/bytes to be read (only for read transactions) - -- -- IC FIFO control - -- signal gbtsc_wr_clk_i : in std_logic; --! Fifo's writing clock - -- signal gbtsc_tx_wr_i : in std_logic; --! Request a write operation into the internal FIFO (Data to GBTx) - -- signal gbtsc_tx_data_to_gbtx_i : in std_logic_vector(7 downto 0); --! Data to be written into the internal FIFO - -- signal gbtsc_rd_clk_i : in std_logic; - -- signal gbtsc_rx_rd_i : in std_logic; --! Request a read operation of the internal FIFO (GBTx reply) - -- signal gbtsc_rx_data_from_gbtx_o : out std_logic_vector(7 downto 0); --! Data from the FIFO - -- -- IC Status - -- signal gbtsc_tx_ready_o : out std_logic; --! IC core ready for a transaction - -- signal gbtsc_rx_empty_o : out std_logic; --! Rx FIFO is empty (no reply from GBTx) - -- -- SCA control - -- signal gbtsc_sca_enable_i : in std_logic_vector((g_SCA_COUNT-1) downto 0); --! Enable flag to select SCAs - -- signal gbtsc_start_reset_cmd_i : in std_logic; --! Send a reset command to the enabled SCAs - -- signal gbtsc_start_connect_cmd_i : in std_logic; --! Send a connect command to the enabled SCAs - -- signal gbtsc_start_command_i : in std_logic; --! Send the command set in input to the enabled SCAs - -- signal gbtsc_inject_crc_error : in std_logic; --! Emulate a CRC error - -- -- SCA command - -- signal gbtsc_tx_address_i : in std_logic_vector(7 downto 0); --! Command: address field (According to the SCA manual) - -- signal gbtsc_tx_transID_i : in std_logic_vector(7 downto 0); --! Command: transaction ID field (According to the SCA manual) - -- signal gbtsc_tx_channel_i : in std_logic_vector(7 downto 0); --! Command: channel field (According to the SCA manual) - -- signal gbtsc_tx_command_i : in std_logic_vector(7 downto 0); --! Command: command field (According to the SCA manual) - -- signal gbtsc_tx_data_i : in std_logic_vector(31 downto 0); --! Command: data field (According to the SCA manual) - -- signal gbtsc_rx_received_o : out std_logic_vector((g_SCA_COUNT-1) downto 0); --! Reply received flag (pulse) - -- signal gbtsc_rx_address_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: address field (According to the SCA manual) - -- signal gbtsc_rx_control_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: control field (According to the SCA manual) - -- signal gbtsc_rx_transID_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: transaction ID field (According to the SCA manual) - -- signal gbtsc_rx_channel_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: channel field (According to the SCA manual) - -- signal gbtsc_rx_len_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: len field (According to the SCA manual) - -- signal gbtsc_rx_error_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: error field (According to the SCA manual) - -- signal gbtsc_rx_data_o : out reg32_arr((g_SCA_COUNT-1) downto 0); --! Reply: data field (According to the SCA manual) - -- -- EC line - -- signal gbtsc_ec_data_o : out reg2_arr((g_SCA_COUNT-1) downto 0); --! (TX) Array of bits to be mapped to the TX GBT-Frame - -- signal gbtsc_ec_data_i : in reg2_arr((g_SCA_COUNT-1) downto 0); --! (RX) Array of bits to be mapped to the RX GBT-Frame - -- -- IC lines - -- signal gbtsc_ic_data_o : out std_logic_vector(1 downto 0); --! (TX) Array of bits to be mapped to the TX GBT-Frame (bits 83/84) - -- signal gbtsc_ic_data_i : in std_logic_vector(1 downto 0) --! (RX) Array of bits to be mapped to the RX GBT-Frame (bits 83/84) - - - -- GBT-SCA - variable g_SCA_COUNT : integer := 1; - signal sca_clk : std_logic; --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency - signal sca_reset_i : std_logic := '0'; --! Reset RX datapath - - signal sca_enable_i : std_logic := '0'; --! Enable flag, bit position correspond to the SCA ID ('1': enabled / '0': Disabled) - signal sca_start_reset_cmd_i : std_logic; --! Send a reset command to the enabled SCAs - signal sca_start_connect_cmd_i : std_logic; --! Send a connect command to the enabled SCAs - signal sca_start_command_i : std_logic; --! Send the command set in input to the enabled SCAs - - signal sca_tx_address_i : std_logic_vector(7 downto 0); --! Command: address field (According to the SCA manual) - signal sca_tx_transID_i : std_logic_vector(7 downto 0); --! Command: transaction ID field (According to the SCA manual) - signal sca_tx_channel_i : std_logic_vector(7 downto 0); --! Command: channel field (According to the SCA manual) - signal sca_tx_len_i : std_logic_vector(7 downto 0); --! Command: Len field (not used anymore, fixed to 4 bytes) - signal sca_tx_command_i : std_logic_vector(7 downto 0); --! Command: command field (According to the SCA manual) - signal sca_tx_data_i : std_logic_vector(31 downto 0); --! Command: data field (According to the SCA manual) - - signal sca_rx_received_o : std_logic; --! Reply received flag (pulse), bit position correspond to the SCA ID - signal sca_rx_address_o : std_logic_vector(7 downto 0); --! Reply: address field (According to the SCA manual) - signal sca_rx_control_o : std_logic_vector(7 downto 0); --! Reply: control field (According to the SCA manual) - signal sca_rx_transID_o : std_logic_vector(7 downto 0); --! Reply: transaction ID field (According to the SCA manual) - signal sca_rx_channel_o : std_logic_vector(7 downto 0); --! Reply: channel field (According to the SCA manual) - signal sca_rx_len_o : std_logic_vector(7 downto 0); --! Reply: len field (According to the SCA manual) - signal sca_rx_error_o : std_logic_vector(7 downto 0); --! Reply: error field (According to the SCA manual) - signal sca_rx_data_o : std_logic_vector(31 downto 0); --! Reply: data field (According to the SCA manual) - - signal sca_out : std_logic_vector(1 downto 0); --! (TX) Array of 2 bits to be mapped to the TX GBT-Frame - signal sca_in : std_logic_vector(1 downto 0); --! (RX) Array of 2 bits to be mapped to the RX GBT-Frame - - signal shiftreg2 : std_logic_vector(1 downto 0) := "00"; - -begin - - -trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); - - ---------------------------------------------------------------------------- --- Clock & Reset Handling ---------------------------------------------------------------------------- - THE_CLOCK_RESET : entity work.clock_reset_handler - port map( - CLOCK_IN => CLK_200, - RESET_FROM_NET => med2int(0).stat_op(13), - SEND_RESET_IN => med2int(0).stat_op(15), - - BUS_RX => bustc_rx, - BUS_TX => bustc_tx, - - RESET_OUT => reset_i, - CLEAR_OUT => clear_i, - GSR_OUT => GSR_N, - - REF_CLK_OUT => clk_full, - SYS_CLK_OUT => clk_sys, - RAW_CLK_OUT => clk_full_osc, - - DEBUG_OUT => debug_clock_reset - ); - -THE_160_PLL : entity work.pll_200_160 - port map( - CLKI => clk_full_osc, - CLKOP => clk_160, - CLKOS => clk_320, - CLKOS2=> clk_40 - ); - -H5(3) <= clk_320; -RJ(0) <= clk_40; - - ---------------------------------------------------------------------------- --- TrbNet Uplink ---------------------------------------------------------------------------- - - THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync - generic map( - SERDES_NUM => SERDES_NUM, - USE_NEW_ECP5_RESET => 0, - IS_SYNC_SLAVE => c_YES - ) - port map( - CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - - --SFP Connection - SD_PRSNT_N_IN => sfp_prsnt_i, - SD_LOS_IN => sfp_los_i, - SD_TXDIS_OUT => sfp_txdis_i, - --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, - -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open - ); - - gen_sfp_con : if SERDES_NUM = 1 generate - sfp_los_i <= SFP_LOS; - sfp_prsnt_i <= SFP_MOD_0; - SFP_TX_DIS <= sfp_txdis_i; - end generate; - gen_bpl_con : if SERDES_NUM = 0 generate - sfp_los_i <= BACK_GPIO(1); - sfp_prsnt_i <= BACK_GPIO(1); - BACK_GPIO(0) <= sfp_txdis_i; - end generate; - - ---------------------------------------------------------------------------- --- Endpoint ---------------------------------------------------------------------------- - THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record - generic map ( - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => BROADCAST_BITMASK, - REGIO_INIT_ENDPOINT_ID => x"0001", - REGIO_USE_1WIRE_INTERFACE => c_I2C, - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16, - USE_GBE => USE_GBE - ) - - port map( - -- Misc - CLK => clk_sys, - RESET => reset_i, - CLK_125 => CLK_125, - CLEAR_N => GSR_N, - - -- Media direction port - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, - - READOUT_RX => readout_rx, - READOUT_TX => readout_tx, - - --Slow Control Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - BUS_RX => ctrlbus_rx, - BUS_TX => ctrlbus_tx, - BUS_MASTER_IN => bus_master_in, - BUS_MASTER_OUT => bus_master_out, - BUS_MASTER_ACTIVE => bus_master_active, - - ONEWIRE_INOUT => open, - I2C_SCL => I2C_SCL, - I2C_SDA => I2C_SDA, - --Timing registers - TIMERS_OUT => timer, - STATUS_GBE_OUT=> gbe_status - ); - ---------------------------------------------------------------------------- --- Bus Handler ---------------------------------------------------------------------------- - THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record - generic map( - PORT_NUMBER => 5, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0), - PORT_MASK_ENABLE => 1 - ) - port map( - CLK => clk_sys, - RESET => reset_i, - - REGIO_RX => ctrlbus_rx, - REGIO_TX => ctrlbus_tx, - - BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED - BUS_RX(1) => bussci_rx, --SCI Serdes - BUS_RX(2) => bustc_rx, --Clock switch - BUS_RX(3) => busmimosis_rx, - BUS_RX(4) => busgbtsca_rx, - -- BUS_RX(4) => busi2c_rx, - -- BUS_RX(5) => busgbeip_rx, - -- BUS_RX(6) => busgbereg_rx, - -- BUS_RX(7) => busfwd_rx, - BUS_TX(0) => bustools_tx, - BUS_TX(1) => bussci_tx, - BUS_TX(2) => bustc_tx, - BUS_TX(3) => busmimosis_tx, - BUS_TX(4) => busgbtsca_tx, - -- BUS_TX(4) => busi2c_tx, - -- BUS_TX(5) => busgbeip_tx, - -- BUS_TX(6) => busgbereg_tx, - -- BUS_TX(7) => busfwd_tx, - STAT_DEBUG => open - ); - ---------------------------------------------------------------------------- --- Control Tools ---------------------------------------------------------------------------- - THE_TOOLS : entity work.trb3sc_tools - generic map( - ADC_CMD_1 => x"2c3cb", - ADC_CMD_2 => x"1d5cb", - ADC_CMD_3 => x"1e3cb", - ADC_CMD_4 => x"2f5cb", - ADC_CMD_T => x"1F393" - ) - port map( - CLK => clk_sys, - RESET => reset_i, - - --Flash & Reload - FLASH_CS => flash_ncs_i, - FLASH_CLK => FLASH_SCLK, - FLASH_IN => FLASH_MISO, - FLASH_OUT => FLASH_MOSI, - PROGRAMN => PROGRAMN, - REBOOT_IN => common_ctrl_reg(15), - --SPI - SPI_CS_OUT => spi_cs, - SPI_MOSI_OUT => spi_mosi, - SPI_MISO_IN => spi_miso, - SPI_CLK_OUT => spi_clk, - --Header - --HEADER_IO => open, - HEADER_IO(7) => HDR_IO(6), - HEADER_IO(8) => HDR_IO(7), - ADDITIONAL_REG => add_reg, - --ADC - ADC_CS => ADC_NCS, - ADC_MOSI => ADC_MOSI, - ADC_MISO => ADC_MISO, - ADC_CLK => ADC_SCLK, - --Trigger & Monitor - MONITOR_INPUTS => (others => '0'), - TRIG_GEN_INPUTS => (others => '0'), - TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), - TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), - --SED - SED_ERROR_OUT => sed_error_i, - --Slowcontrol - BUS_RX => bustools_rx, - BUS_TX => bustools_tx, - --Control master for default settings - BUS_MASTER_IN => bus_master_in, - BUS_MASTER_OUT => bus_master_out, - BUS_MASTER_ACTIVE => bus_master_active, - DEBUG_OUT => debug_tools - ); - ---counter <= counter + '1' when rising_edge(clk_sys); ---HDR_IO <= std_logic_vector(counter(15 downto 0)); ---LED <= std_logic_vector(counter(23 downto 16)); - - --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; - --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; - - FLASH_HOLD <= '1'; - FLASH_WP <= '1'; - - ---------------------------------------------------------------------------- --- GBT-SCA ---------------------------------------------------------------------------- --- THE_GBTSCA : entity work.gbtsc_top --- generic map( --- -- IC configuration --- -- g_IC_FIFO_DEPTH => , -- : integer := 20; --! Defines the depth of the FIFO used to handle the Internal control (Max. number of words/bytes can be read/write from/to a GBTx) --- -- g_ToLpGBT => , -- : integer range 0 to 1 := 0; --! 1 to use LpGBT. Otherwise, it should be 0 --- -- g_LPGBT_VERS => , -- : std_logic := '1'; --! Select lpGBT version ('0': 0, '1': 1) - --- -- EC configuration --- g_SCA_COUNT => 1, -- : integer := 1 --! Defines the maximum number of SCA that can be connected to this module --- ) --- port map( --- -- Clock & reset --- tx_clk_i => gbtsc_tx_clk_i, --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency --- tx_clk_en => gbtsc_tx_clk_e, --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled - --- rx_clk_i => gbtsc_rx_clk_i, --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency --- rx_clk_en => gbtsc_rx_clk_e, --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled - --- rx_reset_i => gbtsc_rx_reset_i, --! Reset RX datapath --- tx_reset_i => gbtsc_tx_reset_i, --! Reset TX datapath - --- -- IC control --- tx_start_write_i => gbtsc_tx_start_write_i, --! Request a write config. to the GBTx (IC) --- tx_start_read_i => gbtsc_tx_start_read_i, --! Request a read config. to the GBTx (IC) - --- -- IC configuration --- tx_GBTx_address_i => gbtsc_tx_GBTx_address_i, --! I2C address of the GBTx --- tx_register_addr_i => gbtsc_tx_register_addr_i, --! Address of the first register to be accessed --- tx_nb_to_be_read_i => gbtsc_tx_nb_to_be_read_i, --! Number of words/bytes to be read (only for read transactions) - --- -- IC FIFO control --- wr_clk_i => gbtsc_wr_clk_i, --! Fifo's writing clock --- tx_wr_i => gbtsc_tx_wr_i, --! Request a write operation into the internal FIFO (Data to GBTx) --- tx_data_to_gbtx_i => gbtsc_tx_data_to_gbtx_i, --! Data to be written into the internal FIFO - --- rd_clk_i => gbtsc_rd_clk_i, -- --- rx_rd_i => gbtsc_rx_rd_i, --! Request a read operation of the internal FIFO (GBTx reply) --- rx_data_from_gbtx_o => gbtsc_rx_data_from_gbtx_o, --! Data from the FIFO - --- -- IC Status --- tx_ready_o => gbtsc_tx_ready_o, --! IC core ready for a transaction --- rx_empty_o => gbtsc_rx_empty_o, --! Rx FIFO is empty (no reply from GBTx) - --- -- SCA control --- sca_enable_i => gbtsc_sca_enable_i, --! Enable flag to select SCAs --- start_reset_cmd_i => gbtsc_start_reset_cmd_i, --! Send a reset command to the enabled SCAs --- start_connect_cmd_i => gbtsc_start_connect_cmd_i, --! Send a connect command to the enabled SCAs --- start_command_i => gbtsc_start_command_i, --! Send the command set in input to the enabled SCAs --- inject_crc_error => gbtsc_inject_crc_e, --! Emulate a CRC error - --- -- SCA command --- tx_address_i => gbtsc_tx_address_i, --! Command: address field (According to the SCA manual) --- tx_transID_i => gbtsc_tx_transID_i, --! Command: transaction ID field (According to the SCA manual) --- tx_channel_i => gbtsc_tx_channel_i, --! Command: channel field (According to the SCA manual) --- tx_command_i => gbtsc_tx_command_i, --! Command: command field (According to the SCA manual) --- tx_data_i => gbtsc_tx_data_i, --! Command: data field (According to the SCA manual) - --- rx_received_o => gbtsc_rx_received_o, --! Reply received flag (pulse) --- rx_address_o => gbtsc_rx_address_o, --! Reply: address field (According to the SCA manual) --- rx_control_o => gbtsc_rx_control_o, --! Reply: control field (According to the SCA manual) --- rx_transID_o => gbtsc_rx_transID_o, --! Reply: transaction ID field (According to the SCA manual) --- rx_channel_o => gbtsc_rx_channel_o, --! Reply: channel field (According to the SCA manual) --- rx_len_o => gbtsc_rx_len_o, --! Reply: len field (According to the SCA manual) --- rx_error_o => gbtsc_rx_error_o, --! Reply: error field (According to the SCA manual) --- rx_data_o => gbtsc_rx_data_o, --! Reply: data field (According to the SCA manual) - --- -- EC line --- ec_data_o => gbtsc_ec_data_o, --! (TX) Array of bits to be mapped to the TX GBT-Frame --- ec_data_i => gbtsc_ec_data_i, --! (RX) Array of bits to be mapped to the RX GBT-Frame - --- -- IC lines --- ic_data_o => open, --! (TX) Array of bits to be mapped to the TX GBT-Frame (bits 83/84) --- ic_data_i => "00" --! (RX) Array of bits to be mapped to the RX GBT-Frame (bits 83/84) --- ); - - -PROC_GEN_CLK80 : process begin - wait until rising_edge(clk_160); - sca_clk <= shiftreg2(1); - shiftreg2 = shiftreg2 + 1; -end process - -THE_GBTSCA : entity work.sca_top - generic map( - g_SCA_COUNT => g_SCA_COUNT, --! Number of SCAs to be controlled through the link (up to 41) - ) - port map( - rx_clk_en => '1', --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled - tx_clk_en => '1', --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled - - rx_clk_i => sca_clk, --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency - tx_clk_i => sca_clk, --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency - - rx_reset_i => sca_reset_i, --! Reset RX datapath - tx_reset_i => sca_reset_i, --! Reset TX datapath - - enable_i(0) => sca_enable_i, --! Enable flag, bit position correspond to the SCA ID ('1': enabled / '0': Disabled) - start_reset_cmd_i => sca_start_reset_cmd_i, --! Send a reset command to the enabled SCAs - start_connect_cmd_i => sca_start_connect_cmd_i, --! Send a connect command to the enabled SCAs - start_command_i => sca_start_command_i, --! Send the command set in input to the enabled SCAs - inject_crc_error => '0', --! Emulate a CRC error - - tx_address_i => sca_tx_address_i, --! Command: address field (According to the SCA manual) - tx_transID_i => sca_tx_transID_i, --! Command: transaction ID field (According to the SCA manual) - tx_channel_i => sca_tx_channel_i, --! Command: channel field (According to the SCA manual) - tx_len_i => sca_tx_len_i, --! Command: Len field (not used anymore, fixed to 4 bytes) - tx_command_i => sca_tx_command_i, --! Command: command field (According to the SCA manual) - tx_data_i => sca_tx_data_i, --! Command: data field (According to the SCA manual) - - rx_received_o(0) => sca_rx_received_o, --! Reply received flag (pulse), bit position correspond to the SCA ID - rx_address_o(0) => sca_rx_address_o, --! Reply: address field (According to the SCA manual) - rx_control_o(0) => sca_rx_control_o, --! Reply: control field (According to the SCA manual) - rx_transID_o(0) => sca_rx_transID_o, --! Reply: transaction ID field (According to the SCA manual) - rx_channel_o(0) => sca_rx_channel_o, --! Reply: channel field (According to the SCA manual) - rx_len_o(0) => sca_rx_len_o, --! Reply: len field (According to the SCA manual) - rx_error_o(0) => sca_rx_error_o, --! Reply: error field (According to the SCA manual) - rx_data_o(0) => sca_rx_data_o, --! Reply: data field (According to the SCA manual) - - tx_data_o(0) => sca_out, --! (TX) Array of 2 bits to be mapped to the TX GBT-Frame - rx_data_i(0) => sca_in, --! (RX) Array of 2 bits to be mapped to the RX GBT-Frame - ); - - -PROC_GBTSCA_REGS : process begin - wait until rising_edge(CLK_SYS); - busgbtsca_tx.ack <= '0'; - busgbtsca_tx.unknown <= '0'; - busgbtsca_tx.nack <= '0'; - busgbtsca_tx.data <= (others => '0'); - sca_enable_i <= '0'; - sca_reset_i <= '0'; - - if busgbtsca_rx.write = '1' then - busgbtsca_tx.ack <= '1'; - if busgbtsca_rx.addr(3 downto 0) = x"0" then - sca_tx_address_i <= busgbtsca_rx.data(7 downto 0); - sca_enable_i <= busgbtsca_rx.data(8); - sca_start_reset_cmd_i <= busgbtsca_rx.data(9); - sca_start_connect_i <= busgbtsca_rx.data(10); - sca_reset_i <= busgbtsca_rx.data(11); - elsif busgbtsca_rx.addr(3 downto 0) = x"1" then - sca_tx_transID_i <= busgbtsca_rx.data(7 downto 0); - sca_tx_channel_i <= busgbtsca_rx.data(15 downto 8); - sca_tx_len_i <= busgbtsca_rx.data(23 downto 16); - sca_tx_command_i <= busgbtsca_rx.data(31 downto 24); - elsif busgbtsca_rx.addr(3 downto 0) = x"2" then - sca_tx_data_i <= busgbtsca_rx.data(31 downto 0); - else - busgbtsca_tx.ack <= '0'; - busgbtsca_tx.unknown <= '1'; - end if; - - elsif busgbtsca_rx.read = '1' then - busgbtsca_tx.ack <= '1'; - if busgbtsca_rx.addr(3 downto 0) = x"0" then - busgbtsca_tx.data(7 downto 0) <= sca_rx_address_o; - elsif busgbtsca_rx.addr(3 downto 0) = x"1" then - busgbtsca_tx.data( 7 downto 0 ) <= sca_rx_transID_o; - busgbtsca_tx.data(15 downto 8 ) <= sca_rx_channel_o; - busgbtsca_tx.data(23 downto 16) <= sca_rx_len_o; - -- busgbtsca_tx.data(31 downto 24) <= sca_rx_len_o; - elsif busgbtsca_rx.addr(3 downto 0) = x"2" then - busgbtsca_tx.data(31 downto 0) <= sca_rx_data_o; - elsif busgbtsca_rx.addr(3 downto 0) = x"3" then - busgbtsca_tx.data(7 downto 0) <= sca_rx_control_o; - busgbtsca_tx.data(15 downto 8) <= sca_rx_error_o; - busgbtsca_tx.data(16) <= sca_rx_received_o; - else - busgbtsca_tx.ack <= '0'; - busgbtsca_tx.unknown <= '1'; - end if; - end if; -end process; - -sca_in <= SCA_RX; -SCA_TX <= sca_out; -SCA_CLK <= sca_clk & not sca_clk; - ---------------------------------------------------------------------------- --- LED ---------------------------------------------------------------------------- - - LED_SFP_GREEN <= not med2int(0).stat_op(9); - LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); - LED_SFP_YELLOW <= not med2int(0).stat_op(8); - LED <= x"FF"; - LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used - LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP) - LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used - LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP) - LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used - - TEST(13 downto 1) <= (others => '0'); - TEST(14) <= flash_ncs_i; --for v1 boards - - FLASH_NCS <= flash_ncs_i; - - LED_ADDON_RJ <= "00"; - LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2)); - LED_ADDON_SFP_GREEN(1) <= '0'; - LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4)); - LED_ADDON_SFP_ORANGE(1) <= '0'; - - ---------------------------------------------------------------------------- --- Output stage ---------------------------------------------------------------------------- - THE_OUT : entity work.testout - port map( - clkout => open, - refclk => clk_160, - reset => reset_i, - data => out_data, - data_cflag => open, - data_direction => (others => '0'), - data_loadn => (others => '1'), - data_move => (others => '0'), - dout => out_i - ); - - PROC_OUT : process - variable cnt : integer range 0 to 7; - begin - wait until rising_edge(clk_160); - cnt := cnt + 1; - case cnt is - when 0 => out_data <= x"ffff"; - when 1 => out_data <= x"ffff"; - when 2 => out_data <= x"ffff"; - when 3 => out_data <= x"0000"; - when 4 => out_data <= x"5555"; - when 5 => out_data <= x"5555"; - when 6 => out_data <= x"5555"; - when 7 => out_data <= x"5555"; - end case; - end process; - - H3(3 downto 0) <= out_i(3 downto 0); - H4(3 downto 0) <= out_i(7 downto 4); - - ---------------------------------------------------------------------------- --- Input stage ---------------------------------------------------------------------------- - THE_MIMOSIS : entity work.MimosisInput - port map( - CLK => clk_160, - CLK_SYS => clk_sys, - RESET => reset_i, - - INPUT => inp_i, - - BUSRDO_RX => readout_rx, - BUSRDO_TX => readout_tx(0), - - BUS_RX => busmimosis_rx, - BUS_TX => busmimosis_tx - ); - --- inp_i <= H2(3 downto 0) & H1(3 downto 0); - inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); -------------------------------------------------------------------------------- --- No trigger/data endpoint included -------------------------------------------------------------------------------- --- readout_tx(0).data_finished <= '1'; --- readout_tx(0).data_write <= '0'; --- readout_tx(0).busy_release <= '1'; - -SFP_ADDON_TX_DIS <= (others => '0'); -end architecture; diff --git a/vldb/trb5sc_vldb_OLD.vhd b/vldb/trb5sc_vldb_OLD.vhd deleted file mode 100644 index abac92e..0000000 --- a/vldb/trb5sc_vldb_OLD.vhd +++ /dev/null @@ -1,759 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.version.all; -use work.config.all; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.med_sync_define.all; - -entity trb5sc_mimosis is - port( - CLK_200 : in std_logic; - CLK_125 : in std_logic; - CLK_EXT : in std_logic; - - TRIG_IN_BACKPL : in std_logic; --Reference Time - TRIG_IN_RJ45 : in std_logic; --Reference Time - IN_SELECT_EXT_CLOCK : in std_logic; - - SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 - BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 - - SFP_TX_DIS : out std_logic; - SFP_LOS : in std_logic; - SFP_MOD_0 : in std_logic; - - --AddOn --- FE_GPIO : inout std_logic_vector(11 downto 0); --- FE_CLK : out std_logic_vector( 2 downto 1); --- FE_DIFF : inout std_logic_vector(63 downto 0); - --INP : inout std_logic_vector(63 downto 0); - --LED_ADDON : out std_logic_vector(5 downto 0); - LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); - LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); - LED_ADDON_RJ : out std_logic_vector(1 downto 0); - SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); - SFP_ADDON_LOS : in std_logic_vector(1 downto 0); - - RJ : inout std_logic_vector(3 downto 0); - H1 : inout std_logic_vector(4 downto 0); - H2 : inout std_logic_vector(4 downto 0); - H3 : inout std_logic_vector(4 downto 0); - H4 : inout std_logic_vector(4 downto 0); - H5 : inout std_logic_vector(3 downto 0); - H6 : inout std_logic_vector(4 downto 0); - H7 : inout std_logic_vector(4 downto 0); - - PIN : out std_logic_vector(8 downto 1); - - MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; - - --ADC - ADC_SCLK : out std_logic; - ADC_NCS : out std_logic; - ADC_MOSI : out std_logic; - ADC_MISO : in std_logic; - --Flash, Reload - FLASH_SCLK : out std_logic; - FLASH_NCS : out std_logic; - FLASH_MOSI : out std_logic; - FLASH_MISO : in std_logic; - FLASH_HOLD : out std_logic; - FLASH_WP : out std_logic; - PROGRAMN : out std_logic; - --I2C - I2C_SDA : inout std_logic; - I2C_SCL : inout std_logic; - TMP_ALERT : in std_logic; - - --LED - LED : out std_logic_vector(8 downto 1); - LED_SFP_YELLOW : out std_logic; - LED_SFP_GREEN : out std_logic; - LED_SFP_RED : out std_logic; - LED_RJ_GREEN : out std_logic_vector(1 downto 0); - LED_RJ_RED : out std_logic_vector(1 downto 0); - LED_EXT_CLOCK : out std_logic; - - --Other Connectors - TEST : inout std_logic_vector(14 downto 1); --on v1 only - --COMMON_SDA, COMMON_SCL : inout std_logic - HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only - ); - - - attribute syn_useioff : boolean; - attribute syn_useioff of FLASH_NCS : signal is true; - attribute syn_useioff of FLASH_SCLK : signal is true; - attribute syn_useioff of FLASH_MOSI : signal is true; - attribute syn_useioff of FLASH_MISO : signal is true; - - -end entity; - -architecture arch of trb5sc_mimosis is - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic; - signal GSR_N : std_logic; - signal reset_i : std_logic; - signal clear_i : std_logic; - signal trigger_in_i : std_logic; - - - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - - signal debug_clock_reset : std_logic_vector(31 downto 0); - signal external_clock_lock : std_logic := '0'; - signal debug_tools : std_logic_vector(31 downto 0); - - --Media Interface - signal med2int : med2int_array_t(0 to 0); - signal int2med : int2med_array_t(0 to 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; - - - signal readout_rx : READOUT_RX; - signal readout_tx : readout_tx_array_t(0 to 0); - - signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX; - - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - - signal sed_error_i : std_logic; - signal clock_select : std_logic; - signal bus_master_active : std_logic; - signal flash_ncs_i : std_logic; - - signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); - signal header_io_i : std_logic_vector(10 downto 1); - signal timer : TIMERS; - signal add_reg : std_logic_vector(31 downto 0); - alias led_off : std_logic is add_reg(0); - - signal out_data : std_logic_vector(15 downto 0); - signal out_i : std_logic_vector( 7 downto 0); - signal inp_i : std_logic_vector( 7 downto 0); - signal gbe_status : std_logic_vector(15 downto 0); - - - signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); - signal i2c_reg_2 : std_logic_vector(31 downto 0); - signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); - signal mimosis_scl_drv, mimosis_sda_drv : std_logic; - signal i2c_go_100, i2c_go : std_logic; - signal i2c_reg_5_40 : std_logic_vector(31 downto 0); - signal counter : unsigned(23 downto 0); - --signal fwd_dst_mac : std_logic_vector(47 downto 0); - --signal fwd_dst_ip : std_logic_vector(31 downto 0); - --signal fwd_dst_port : std_logic_vector(15 downto 0); - --signal fwd_data : std_logic_vector(7 downto 0); - --signal fwd_datavalid : std_logic; - --signal fwd_sop : std_logic; - --signal fwd_eop : std_logic; - --signal fwd_ready : std_logic; - --signal fwd_full : std_logic; - --signal fwd_length : std_logic_vector(15 downto 0); - --signal fwd_do_send : std_logic; - -begin - - -trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); - - ---------------------------------------------------------------------------- --- Clock & Reset Handling ---------------------------------------------------------------------------- - THE_CLOCK_RESET : entity work.clock_reset_handler - port map( - CLOCK_IN => CLK_200, - RESET_FROM_NET => med2int(0).stat_op(13), - SEND_RESET_IN => med2int(0).stat_op(15), - - BUS_RX => bustc_rx, - BUS_TX => bustc_tx, - - RESET_OUT => reset_i, - CLEAR_OUT => clear_i, - GSR_OUT => GSR_N, - - REF_CLK_OUT => clk_full, - SYS_CLK_OUT => clk_sys, - RAW_CLK_OUT => clk_full_osc, - - DEBUG_OUT => debug_clock_reset - ); - - - -THE_160_PLL : entity work.pll_200_160 - port map( - CLKI => clk_full_osc, - CLKOP => clk_160, - CLKOS => clk_320, - CLKOS2=> clk_40 - ); - -H5(3) <= clk_320; -RJ(0) <= clk_40; - ---------------------------------------------------------------------------- --- TrbNet Uplink ---------------------------------------------------------------------------- - - THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync - generic map( - SERDES_NUM => SERDES_NUM, - USE_NEW_ECP5_RESET => 0, - IS_SYNC_SLAVE => c_YES - ) - port map( - CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - - --SFP Connection - SD_PRSNT_N_IN => sfp_prsnt_i, - SD_LOS_IN => sfp_los_i, - SD_TXDIS_OUT => sfp_txdis_i, - --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, - -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open - ); - - gen_sfp_con : if SERDES_NUM = 1 generate - sfp_los_i <= SFP_LOS; - sfp_prsnt_i <= SFP_MOD_0; - SFP_TX_DIS <= sfp_txdis_i; - end generate; - gen_bpl_con : if SERDES_NUM = 0 generate - sfp_los_i <= BACK_GPIO(1); - sfp_prsnt_i <= BACK_GPIO(1); - BACK_GPIO(0) <= sfp_txdis_i; - end generate; - - ---------------------------------------------------------------------------- --- Endpoint ---------------------------------------------------------------------------- - THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record - generic map ( - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => BROADCAST_BITMASK, - REGIO_INIT_ENDPOINT_ID => x"0001", - REGIO_USE_1WIRE_INTERFACE => c_I2C, - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16, - USE_GBE => USE_GBE - ) - - port map( - -- Misc - CLK => clk_sys, - RESET => reset_i, - CLK_125 => CLK_125, - CLEAR_N => GSR_N, - - -- Media direction port - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, - - READOUT_RX => readout_rx, - READOUT_TX => readout_tx, - - --Slow Control Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - BUS_RX => ctrlbus_rx, - BUS_TX => ctrlbus_tx, - BUS_MASTER_IN => bus_master_in, - BUS_MASTER_OUT => bus_master_out, - BUS_MASTER_ACTIVE => bus_master_active, - - ONEWIRE_INOUT => open, - I2C_SCL => I2C_SCL, - I2C_SDA => I2C_SDA, - --Timing registers - TIMERS_OUT => timer, - STATUS_GBE_OUT=> gbe_status - ); - ---------------------------------------------------------------------------- --- Bus Handler ---------------------------------------------------------------------------- - - THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record - generic map( - PORT_NUMBER => 5, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0), - PORT_MASK_ENABLE => 1 - ) - port map( - CLK => clk_sys, - RESET => reset_i, - - REGIO_RX => ctrlbus_rx, - REGIO_TX => ctrlbus_tx, - - BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED - BUS_RX(1) => bussci_rx, --SCI Serdes - BUS_RX(2) => bustc_rx, --Clock switch - BUS_RX(3) => busmimosis_rx, - BUS_RX(4) => busi2c_rx, - --BUS_RX(5) => busgbeip_rx, - --BUS_RX(6) => busgbereg_rx, - --BUS_RX(7) => busfwd_rx, - BUS_TX(0) => bustools_tx, - BUS_TX(1) => bussci_tx, - BUS_TX(2) => bustc_tx, - BUS_TX(3) => busmimosis_tx, - BUS_TX(4) => busi2c_tx, - --BUS_TX(5) => busgbeip_tx, - --BUS_TX(6) => busgbereg_tx, - --BUS_TX(7) => busfwd_tx, - STAT_DEBUG => open - ); - ---------------------------------------------------------------------------- --- Control Tools ---------------------------------------------------------------------------- - THE_TOOLS : entity work.trb3sc_tools - generic map( - ADC_CMD_1 => x"2c3cb", - ADC_CMD_2 => x"1d5cb", - ADC_CMD_3 => x"1e3cb", - ADC_CMD_4 => x"2f5cb", - ADC_CMD_T => x"1F393" - ) - port map( - CLK => clk_sys, - RESET => reset_i, - - --Flash & Reload - FLASH_CS => flash_ncs_i, - FLASH_CLK => FLASH_SCLK, - FLASH_IN => FLASH_MISO, - FLASH_OUT => FLASH_MOSI, - PROGRAMN => PROGRAMN, - REBOOT_IN => common_ctrl_reg(15), - --SPI - SPI_CS_OUT => spi_cs, - SPI_MOSI_OUT => spi_mosi, - SPI_MISO_IN => spi_miso, - SPI_CLK_OUT => spi_clk, - --Header - --HEADER_IO => open, - HEADER_IO(7) => HDR_IO(6), - HEADER_IO(8) => HDR_IO(7), - ADDITIONAL_REG => add_reg, - --ADC - ADC_CS => ADC_NCS, - ADC_MOSI => ADC_MOSI, - ADC_MISO => ADC_MISO, - ADC_CLK => ADC_SCLK, - --Trigger & Monitor - MONITOR_INPUTS => (others => '0'), - TRIG_GEN_INPUTS => (others => '0'), - TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), - TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), - --SED - SED_ERROR_OUT => sed_error_i, - --Slowcontrol - BUS_RX => bustools_rx, - BUS_TX => bustools_tx, - --Control master for default settings - BUS_MASTER_IN => bus_master_in, - BUS_MASTER_OUT => bus_master_out, - BUS_MASTER_ACTIVE => bus_master_active, - DEBUG_OUT => debug_tools - ); - ---counter <= counter + '1' when rising_edge(clk_sys); ---HDR_IO <= std_logic_vector(counter(15 downto 0)); ---LED <= std_logic_vector(counter(23 downto 16)); - - --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; - --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; - - FLASH_HOLD <= '1'; - FLASH_WP <= '1'; - ---------------------------------------------------------------------------- --- I2C ---------------------------------------------------------------------------- -THE_I2C : entity work.i2c_slim2 - port map( - CLOCK => clk_40, - RESET => reset_i, - -- I2C command / setup - I2C_GO_IN => i2c_go, - ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read - WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word - DIRECT_IN => i2c_reg_1(4), -- don't send command - I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) - I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) - I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) - I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command - I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command - STATUS_OUT => i2c_reg_4(23 downto 16), - VALID_OUT => i2c_reg_4(31), - I2C_BUSY_OUT => i2c_reg_4(30), - I2C_DONE_OUT => i2c_reg_4(29), - -- I2C connections - SDA_IN => PIN(4), - SDA_OUT => mimosis_sda_drv, - SCL_IN => PIN(3), - SCL_OUT => mimosis_scl_drv, - -- Debug - BSM_OUT => i2c_reg_4(27 downto 24) -); - --- I2C signal open collector driver --- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; --- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; - -PIN(4) <= MIMOSIS_SDA; -PIN(3) <= MIMOSIS_SCL; -MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z'; -MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z'; - -H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC -PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START -PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET - -PROC_I2C_REGS : process begin - wait until rising_edge(CLK_SYS); - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '0'; - busi2c_tx.nack <= '0'; - busi2c_tx.data <= (others => '0'); - i2c_go_100 <= '0'; - - if busi2c_rx.write = '1' then - busi2c_tx.ack <= '1'; - if busi2c_rx.addr(3 downto 0) = x"0" then - i2c_reg_0 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"1" then - i2c_reg_1 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"2" then - i2c_reg_2 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"3" then - i2c_go_100 <= busi2c_rx.data(0); - elsif busi2c_rx.addr(3 downto 0) = x"5" then - i2c_reg_5 <= busi2c_rx.data; - else - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '1'; - end if; - elsif busi2c_rx.read = '1' then - busi2c_tx.ack <= '1'; - if busi2c_rx.addr(3 downto 0) = x"0" then - busi2c_tx.data <= i2c_reg_0; - elsif busi2c_rx.addr(3 downto 0) = x"1" then - busi2c_tx.data <= i2c_reg_1; - elsif busi2c_rx.addr(3 downto 0) = x"2" then - busi2c_tx.data <= i2c_reg_2; - elsif busi2c_rx.addr(3 downto 0) = x"3" then - busi2c_tx.data <= (others => '0'); - elsif busi2c_rx.addr(3 downto 0) = x"4" then - busi2c_tx.data <= i2c_reg_4; - elsif busi2c_rx.addr(3 downto 0) = x"5" then - busi2c_tx.data <= i2c_reg_5; - else - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '1'; - - end if; - end if; -end process; - - THE_I2C_GO_SYNC : pulse_sync - port map( - CLK_A_IN => clk_sys, - RESET_A_IN => reset_i, - PULSE_A_IN => i2c_go_100, - CLK_B_IN => clk_40, - RESET_B_IN => reset_i, - PULSE_B_OUT => i2c_go - ); - - THE_MIMOSIS_SIGNAL_SYNC : signal_sync - generic map( - WIDTH => 32, - DEPTH => 2 - ) - port map( - RESET => reset_i, - CLK0 => clk_sys, - CLK1 => clk_40, - D_IN => i2c_reg_5, - D_OUT => i2c_reg_5_40 - ); - - - ---------------------------------------------------------------------------- --- LED ---------------------------------------------------------------------------- - - LED_SFP_GREEN <= not med2int(0).stat_op(9); - LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); - LED_SFP_YELLOW <= not med2int(0).stat_op(8); - LED <= x"FF"; - LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used - LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP) - LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used - LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP) - LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used - - TEST(13 downto 1) <= (others => '0'); - TEST(14) <= flash_ncs_i; --for v1 boards - - FLASH_NCS <= flash_ncs_i; - - LED_ADDON_RJ <= "00"; - LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2)); - LED_ADDON_SFP_GREEN(1) <= '0'; - LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4)); - LED_ADDON_SFP_ORANGE(1) <= '0'; - ------------------------------------------------------------------------------ ----- GbE ------------------------------------------------------------------------------ - --GBE : entity work.gbe_wrapper - --generic map( - --DO_SIMULATION => 0, - --INCLUDE_DEBUG => 0, - --USE_INTERNAL_TRBNET_DUMMY => 0, - --USE_EXTERNAL_TRBNET_DUMMY => 0, - --RX_PATH_ENABLE => 1, - --FIXED_SIZE_MODE => 1, - --INCREMENTAL_MODE => 1, - --FIXED_SIZE => 100, - --FIXED_DELAY_MODE => 1, - --UP_DOWN_MODE => 0, - --UP_DOWN_LIMIT => 100, - --FIXED_DELAY => 100, - - --NUMBER_OF_GBE_LINKS => 1, - --LINKS_ACTIVE => "0001", - - --LINK_HAS_READOUT => "0000", - --LINK_HAS_SLOWCTRL => "0000", - --LINK_HAS_DHCP => "0001", - --LINK_HAS_ARP => "0001", - --LINK_HAS_PING => "0001", - --LINK_HAS_FWD => "0001" - --) - --port map( - --CLK_SYS_IN => clk_sys, - --CLK_125_IN => CLK_125, - --RESET => reset_i, - --GSR_N => GSR_N, - ---- Trigger - --TRIGGER_IN => '0', - ---- SFP - --SD_PRSNT_N_IN(0) => SFP_MOD_0, - --SD_LOS_IN(0) => SFP_LOS, - --SD_TXDIS_OUT(0) => SFP_TX_DIS, - ---- trigger channel - ---- only for LINK_HAS_READOUT - --CTS_NUMBER_IN => (others => '0'), - --CTS_CODE_IN => (others => '0'), - --CTS_INFORMATION_IN => (others => '0'), - --CTS_READOUT_TYPE_IN => (others => '0'), - --CTS_START_READOUT_IN => '0', - --CTS_DATA_OUT => open, - --CTS_DATAREADY_OUT => open, - --CTS_READOUT_FINISHED_OUT => open, - --CTS_READ_IN => '1', - --CTS_LENGTH_OUT => open, - --CTS_ERROR_PATTERN_OUT => open, - ---- data channel - ---- only for LINK_HAS_READOUT - --FEE_DATA_IN => (others => '0'), - --FEE_DATAREADY_IN => '0', - --FEE_READ_OUT => open, - --FEE_STATUS_BITS_IN => (others => '0'), - --FEE_BUSY_IN => '0', - ---- unique adresses - --MC_UNIQUE_ID_IN => timer.uid, - --MY_TRBNET_ADDRESS_IN => timer.network_address, - --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected - ---- slow control by GbE - --GSC_CLK_IN => open, - --GSC_INIT_DATAREADY_OUT => open, - --GSC_INIT_DATA_OUT => open, - --GSC_INIT_PACKET_NUM_OUT => open, - --GSC_INIT_READ_IN => '1', - --GSC_REPLY_DATAREADY_IN => '0', - --GSC_REPLY_DATA_IN => (others => '0'), - --GSC_REPLY_PACKET_NUM_IN => (others => '0'), - --GSC_REPLY_READ_OUT => open, - --GSC_BUSY_IN => '0', - ---- readout - --BUS_IP_RX => busgbeip_rx, -- registers inside GbE - --BUS_IP_TX => busgbeip_tx, -- registers inside GbE - --BUS_REG_RX => busgbereg_rx, -- registers inside GbE - --BUS_REG_TX => busgbereg_tx, -- registers inside GbE - ---- Forwarder - --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac, - --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip, - --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port, - --FWD_DATA_IN(7 downto 0) => fwd_data, - --FWD_DATA_VALID_IN(0) => fwd_datavalid, - --FWD_SOP_IN(0) => fwd_sop, - --FWD_EOP_IN(0) => fwd_eop, - --FWD_READY_OUT(0) => fwd_ready, - --FWD_FULL_OUT(0) => fwd_full, - ---- reset - --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected - ---- debug and status - --STATUS_OUT => open, - --DEBUG_OUT => open - --); - - - ------------------------------------------------------------------------------ ----- Test registers ------------------------------------------------------------------------------ ---THE_REGS : process begin - --wait until rising_edge(clk_sys); - --busfwd_tx.ack <= '0'; - --busfwd_tx.nack <= '0'; - --busfwd_tx.unknown <= '0'; - - --if busfwd_rx.write = '1' then - --busfwd_tx.ack <= '1'; - --case busfwd_rx.addr(7 downto 0) is - --when x"00" => fwd_dst_ip <= busfwd_rx.data; - --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0); - --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data; - --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0); - --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0); - --when x"05" => fwd_do_send <= busfwd_rx.data(0); - --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; - --end case; - --elsif busfwd_rx.read = '1' then - --busfwd_tx.ack <= '1'; - --case busfwd_rx.addr(7 downto 0) is - --when x"00" => busfwd_tx.data <= fwd_dst_ip; - --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port; - --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0); - --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32); - --when x"04" => busfwd_tx.data <= x"0000" & fwd_length; - --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send; - --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; - --end case; - --end if; - --if reset_i = '1' then - --fwd_do_send <= '0'; - --end if; ---end process; - - ---------------------------------------------------------------------------- --- Output stage ---------------------------------------------------------------------------- - THE_OUT : entity work.testout - port map( - clkout => open, - refclk => clk_160, - reset => reset_i, - data => out_data, - data_cflag => open, - data_direction => (others => '0'), - data_loadn => (others => '1'), - data_move => (others => '0'), - dout => out_i - ); - - PROC_OUT : process - variable cnt : integer range 0 to 7; - begin - wait until rising_edge(clk_160); - cnt := cnt + 1; - case cnt is - when 0 => out_data <= x"ffff"; - when 1 => out_data <= x"ffff"; - when 2 => out_data <= x"ffff"; - when 3 => out_data <= x"0000"; - when 4 => out_data <= x"5555"; - when 5 => out_data <= x"5555"; - when 6 => out_data <= x"5555"; - when 7 => out_data <= x"5555"; - end case; - end process; - - H3(3 downto 0) <= out_i(3 downto 0); - H4(3 downto 0) <= out_i(7 downto 4); - - ---------------------------------------------------------------------------- --- Input stage ---------------------------------------------------------------------------- - THE_MIMOSIS : entity work.MimosisInput - port map( - CLK => clk_160, - CLK_SYS => clk_sys, - RESET => reset_i, - - INPUT => inp_i, - - BUSRDO_RX => readout_rx, - BUSRDO_TX => readout_tx(0), - - BUS_RX => busmimosis_rx, - BUS_TX => busmimosis_tx - ); - --- inp_i <= H2(3 downto 0) & H1(3 downto 0); - inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); -------------------------------------------------------------------------------- --- No trigger/data endpoint included -------------------------------------------------------------------------------- --- readout_tx(0).data_finished <= '1'; --- readout_tx(0).data_write <= '0'; --- readout_tx(0).busy_release <= '1'; - -SFP_ADDON_TX_DIS <= (others => '0'); -end architecture; - - -