From: HADES DAQ Date: Mon, 20 Nov 2023 12:39:05 +0000 (+0100) Subject: added dirich5d1, mt X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=fc455fda90c704622a66e77413aa75b7bbd72ecb;p=dirich.git added dirich5d1, mt --- diff --git a/dirich5d1/check_located.pl b/dirich5d1/check_located.pl new file mode 100644 index 0000000..e69de29 diff --git a/dirich5d1/code/stretched_OR_trigger.vhd b/dirich5d1/code/stretched_OR_trigger.vhd new file mode 100644 index 0000000..06b8478 --- /dev/null +++ b/dirich5d1/code/stretched_OR_trigger.vhd @@ -0,0 +1,90 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library work; + use work.trb_net_std.all; + +entity stretched_OR_trigger is +generic( + INPUT_WIDTH : integer := 32 +); +port( + CLK : in std_logic; + RESET : in std_logic; + + INPUT : in std_logic_vector(INPUT_WIDTH-1 downto 0); + OUTPUT : out std_logic; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX +); +end entity; + +architecture behaviour of stretched_OR_trigger is + signal input_or_stretched : std_logic; + signal input_inv : std_logic_vector(INPUT_WIDTH-1 downto 0); + signal invert : std_logic_vector(31 downto 0) := x"00000000"; + signal enable : std_logic_vector(31 downto 0) := x"00000000"; + signal stretch : std_logic_vector( 3 downto 0) := x"0"; + signal stretched_input : std_logic_vector(INPUT_WIDTH-1 downto 0) := (others => '0'); + +begin + + GEN_STRETCH : for i in 0 to (INPUT_WIDTH-1) generate + THE_TRIGGER_Stretch : entity work.input_signal_stretcher + port map ( + CLK => CLK, + RESET => RESET, + INPUT => INPUT(i), + INVERT => invert(i), + ENABLE => enable(i), + OUTPUT => stretched_input(i), + STRETCH => stretch + ); + end generate GEN_STRETCH; + + input_or_stretched <= or_all( stretched_input ); + + OUTPUT <= input_or_stretched; + + + proc_reg : process + variable stretch_check : std_logic_vector(3 downto 0) := x"0"; + begin + wait until rising_edge(CLK); + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.unknown <= '0'; + + if BUS_RX.write = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(1 downto 0) is + when "00" => + stretch <= BUS_RX.data(3 downto 0); + + when "01" => + invert <= BUS_RX.data; + when "10" => + enable <= BUS_RX.data; + + when others => + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(1 downto 0) is + when "00" => BUS_TX.data(3 downto 0) <= stretch; + + when "01" => BUS_TX.data <= invert; + + when "10" => BUS_TX.data <= enable; + + when others => BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end case; + end if; + end process; + +end architecture; + diff --git a/dirich5d1/compile.pl b/dirich5d1/compile.pl new file mode 100755 index 0000000..e01be1f --- /dev/null +++ b/dirich5d1/compile.pl @@ -0,0 +1,429 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; +use FileHandle; +use Getopt::Long; +use Term::ANSIColor qw(:constants); +use Cwd; +use lib '.'; + +################################################################################### +#Settings for this project +my $FAMILYNAME = "LatticeECP3"; +my $DEVICENAME = "LFE3-150EA"; +my $PACKAGE = "FPBGA1156"; +my $SPEEDGRADE = "8"; + +my %config = do "config_compile.pl"; + +my $TOPNAME = $config{TOPNAME}; +my $lattice_path = $config{lattice_path}; +my $synplify_path = $config{synplify_path}; +my $lm_license_file_for_synplify = $config{lm_license_file_for_synplify}; +my $lm_license_file_for_par = $config{lm_license_file_for_par}; +my $synplify_command = $config{synplify_command}; + +#my $synplify_locale_workaround = "en_US\@UTF-8"; +my $synplify_locale_workaround = "C"; +my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed + +my $include_TDC = $config{include_TDC} || 0; +my $include_GBE = $config{include_GBE} || 0; +my $include_CTS = $config{include_CTS} || 0; +my $include_HUB = $config{include_HUB} || 0; +my $twr_number_of_errors = $config{twr_number_of_errors} || 10; +my $pinout_file = $config{pinout_file} || $TOPNAME; +my $nodelist_file = $config{nodelist_file} || 'nodelist.txt'; +my $par_options = $config{par_options} || ""; + +$FAMILYNAME = $config{Familyname} if $config{Familyname}; +$DEVICENAME = $config{Devicename} if $config{Devicename}; +$PACKAGE = $config{Package} if $config{Package}; +$SPEEDGRADE = $config{Speedgrade} if $config{Speedgrade}; +################################################################################### + +################################################################################### +#Options for the script +my $help = ""; +my $isMultiPar = 0; # set it to zero for single par run on the local machine +my $nrNodes = 0; # set it to one for single par run on the local machine +my $all = 1; +my $syn = 0; +my $map = 0; +my $par = 0; +my $timing = 0; +my $bitgen = 0; +my $con = 0; +my $guidefile = 0; +my $parallel = ''; +my $compile_all = 0; +my $result = GetOptions ( + "h|help" => \$help, + "m|mpar=i" => \$nrNodes, + "a|all" => \$all, + "c|con" => \$con, + "s|syn" => \$syn, + "mp|map" => \$map, + "p|par" => \$par, + "t|timing" => \$timing, + "b|bitgen" => \$bitgen, + "g|guide" => \$guidefile, + "mc|multicore" => \$parallel + ); + +if ($help) { + print "Usage: compile_priph_gsi.de \n\n"; + print "-h --help\tPrints the usage manual.\n"; + print "-a --all\tRun all compile script. By default the script is going to run the whole process.\n"; + print "-c --con\tCompile constraints only.\n"; + print "-s --syn\tRun synthesis part of the compile script.\n"; + print "-mp --map\tRun map part of the compile script.\n"; + print "-p --par\tRun par part of the compile script.\n"; + print "-t --timing\tRun timing analysis part of the compile script.\n"; + print "-b --bitgen\tRun bit generation part of the compile script.\n"; + print "-m --mpar\tSwitch for multi par. \"-m \" (Default = off).\n"; + print "\t\tThe node list file name has to be edited in the script. (Default = nodes_lxhadeb07.txt).\n"; + print "-g --guide\tDefine guide file for the guided placement & routing.\n"; + print "\n"; + exit; +} + +if ($nrNodes!=0) { + $isMultiPar=1; +} +if ($con!=0 || $syn!=0 || $map!=0 || $par!=0 || $timing!=0 || $bitgen!=0) { + $all=0; +} +$parallel = '&' if $parallel; + +################################################################################### + +# source the standard lattice environment +$ENV{bindir}="$lattice_bin_path"; + +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'LC_ALL'}=$synplify_locale_workaround; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; +$ENV{'SYNPLIFY_BINARY'}=$config{synplify_binary}; + +my $cwd = getcwd(); +my $WORKDIR = "workdir"; +unless(-d $WORKDIR) { + mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!"; + system("cd $WORKDIR; ../../../trb3/base/linkdesignfiles.sh; cd .."); +} + +system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); + +print GREEN, "Compiling $TOPNAME project in $cwd/$WORKDIR...\n\n", RESET; + +if ($con==1 || $all==1) { + #create full lpf file and copy delay line to project folder + my $pinout_file = $config{pinout_file} || $TOPNAME; + print GREEN, "Generating constraints file...\n\n", RESET; + system("cp ../pinout/$pinout_file.lpf $WORKDIR/$TOPNAME.lpf"); + system("cat ../pinout/basic_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("cat $TOPNAME.lpf >> $WORKDIR/$TOPNAME.lpf"); + + + #system("unlink $WORKDIR/Adder_304.ngo"); + + if ($include_TDC && $include_CTS==0) { + if ($TOPNAME =~ /dirich/ || $TOPNAME =~ /trb5sc/) { + system("cat tdc_release/dirich_trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("cat tdc_release/dirich_tdc_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("ln -s $cwd/../../tdc/base/cores/ecp5/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo"); + } elsif ($TOPNAME =~ /mdctdc/) { + system("cat tdc_release/mdctdc_trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("cat tdc_release/mdctdc_tdc_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("ln -s $cwd/../../tdc/base/cores/ecp5/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo"); + } else { +# system("cat tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("cat tdc_release/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("cat tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("ln -s $cwd/../../tdc/base/cores/ecp3/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo"); + } +# system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + + #edit the lpf file according to tdc settings + system("unlink $WORKDIR/compile_tdc.pl"); + system("ln -s $cwd/../../tdc/scripts/compile_tdc.pl $WORKDIR/"); + system ("./$WORKDIR/compile_tdc.pl", $WORKDIR, $TOPNAME, "config"); + } + + if ($include_GBE) { + + } + if ($include_HUB) { + system("cat trb3_periph_hub_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + } +} + +if ($include_CTS) { + my $CbmNetPath = "../../cbmnet"; + my $config_vhd = 'config_mainz_a2.vhd'; + system("ln -f -s $config_vhd config.vhd") unless (-e "config.vhd"); + system("./compile_constraints.pl"); + system("cp ../../trb3/base/mulipar_nodelist_example.txt $WORKDIR/nodelist.txt") unless (-e "$WORKDIR/nodelist.txt"); + symlink($CbmNetPath, '../cbmnet/cbmnet') unless (-e '../cbmnet/cbmnet'); +} + +if ($guidefile && -f "$TOPNAME.ncd") { + system("cp $TOPNAME.ncd guidefile.ncd"); + $guidefile = " -g guidefile.ncd " +} else { + $guidefile = ""; +} + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">$WORKDIR/version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +my $c = ""; +my @a = (); +my $tpmap = $TOPNAME . "_map" ; + +chdir $WORKDIR; +if ($syn==1 || $all==1) { + system("rm $TOPNAME.srr"); + system ("./compile_tdc.pl", $WORKDIR, $TOPNAME, "prj") if ($include_TDC); ## edit prj file for different designs + + print GREEN, "Starting synthesis process...\n\n", RESET; + $synplify_command = "$synplify_path/bin/synplify_premier_dp" unless $synplify_command; + $c="$synplify_command -batch ../$TOPNAME.prj"; + $r=execute($c, "do_not_exit" ); + + $fh = new FileHandle("<$TOPNAME".".srr"); + @a = <$fh>; + $fh -> close; + + foreach (@a) { + if (/\@E:/) { + print "\n"; + $c = "cat $TOPNAME.srr | egrep --color \"\@E:\""; + system($c); + print RED, "ERROR in the log file $TOPNAME.srr Exiting...\n\n", RESET; + exit 129; + } + } +} + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +if ($map==1 || $all==1) { + print GREEN, "Starting mapping process...\n\n", RESET; + + $c=qq|edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; + execute($c); + + $c=qq|edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; + execute($c); + + $c=qq|ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; + execute($c); + + $c=qq|map -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE -oc Commercial "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; + execute($c); + + $c=qq|htmlrpt -mrp $TOPNAME.mrp $TOPNAME|; + execute($c); + + $fh = new FileHandle("<$TOPNAME"."_mrp.html"); + @a = <$fh>; + $fh -> close; + my $i=1; + my $print=0; + foreach (@a) { + if (/WARNING/|$print) { + if ((grep /WARNING - map: There are semantic errors in the preference file/, $_) & ($i == 1)) { + last; + } elsif (grep /WARNING - map: There are semantic errors in the preference file/, $_) { + print RED, "There are errors in the constraints file. Better have a look...\n\n", RESET; + sleep(5); # ERROR -> sleep is effective before the print + last; + } elsif ($i == 1) { + print RED,"\n\n", RESET; + print RED,"#################################################\n", RESET; + print RED,"CONSTRAINTS ERRORS\n", RESET; + print RED,"#################################################\n\n", RESET; + } + $print=1; + if (grep /WARNING.*UGROUP/, $_) { + print RED, $_, RESET; + } elsif (grep /FC|hitBuf|ff_en/, $_) { + print YELLOW, $_, RESET; + } else { + print $_; + } + $i++; + } + } +} + +if ($par==1 || $all==1) { + print GREEN, "Starting placement process...\n\n", RESET; + + system("rm $TOPNAME.ncd"); + if ($isMultiPar) { + $c=qq|LC_ALL=en_US.UTF-8; par -m $nodelist_file -n $nrNodes -f $par_options $guidefile $tpmap.ncd $TOPNAME.dir $TOPNAME.prf;|; + # $c=qq|LC_ALL=en_US.UTF-8; par -m $nodelist_file -n $nrNodes -w -i 15 -l 5 -y -s 8 -t 1 -c 1 -e 2 -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=1:parHoldLimit=10000:paruseNBR=1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf;|; + execute($c); + + # find and copy the .ncd file which has met the timing constraints + $fh = new FileHandle("<$TOPNAME".".par"); + my @a = <$fh>; + $fh -> close; + my $isSuccess = 0; + my $i=1; + foreach (@a) { + my @line = split(/\s+/, $_); + + if (@line && ($line[2] =~ m/^[0-9]+$/) && ($line[4] =~ m/^[0-9]+$/)) { + if (($line[2] == 0) && ($line[4] == 0)) { + print GREEN, "Copying $line[0].ncd file to $WORKDIR\n", RESET; + my $c="cp $TOPNAME.dir/$line[0].ncd $TOPNAME.ncd"; + system($c); + print "\n\n"; + $isSuccess = 1; + last; + } + } + } + + if (!$isSuccess) { + print RED, "\n\n", RESET; + print RED, "#################################################\n", RESET; + print RED, "# !!!PAR not successfull!!! #\n", RESET; + print RED, "#################################################\n\n", RESET; + exit 129; + } + } else { + $c=qq|par -f $par_options $guidefile $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; + # $c=qq|par -w -i 15 -l 5 -y -s 8 -t 1 -c 1 -e 2 -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=1:parHoldLimit=10000:paruseNBR=1 $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; + execute($c); + my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd"; + system($c); + } + my $c="cat $TOPNAME.par"; + system($c); + + # check for automatically assigned Signals + { + my $error=0; + my $result = open(my $fh, "<", "$TOPNAME.pad"); + if (!defined $r) { + print("could not open file '$TOPNAME.pad'\n"); + exit 129; + } + my @file = <$fh>; + chomp(@file); + my $f=join("\n", @file); + my @p=split /^Pinout by Pin Number:$/m, $f; + + my @l=split(/\n/,$p[1]); my @ll=grep(/^\|/,@l); + #print Dumper @ll; + #exit; + + foreach(@ll) { + my (@s)=$_=~/\s+([^\|]+?)\s+\|/g; + #print Dumper \@s; + next if($s[1]=~/unused/ || $s[1]=~/-$/ || $s[1]=~/\s+/); + $r.=$_."\n"; + #print "r: $r\n"; + #print Dumper \@s; + $error=1 if($s[2] ne "LOCATED"); + } + if($error) { + print "\nThere are Signals used, which are not \"LOCATED\"! Error! Dump all relevant signals: \n\n"; + print $r; + #exit 129; + } + else { + print "All signals were assigned to the locations given from the preference (lpf)\n"; + } + + } + +} + + +if ($timing==1 || $all==1) { + print GREEN, "Generating timing report...\n\n", RESET; + + # TWR Timing Report + $c=qq|trce -c -v $twr_number_of_errors -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf" $parallel|; + execute($c); + + $c=qq|trce -hld -c -v $twr_number_of_errors -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf" $parallel|; + execute($c); + + # IOR IO Timing Report + $c=qq|iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + my $c="cat $TOPNAME.par"; + system($c); +} + +if ($bitgen==1 || $all==1) { + print GREEN, "Generating bit file...\n\n", RESET; + + $c=qq|ltxt2ptxt $TOPNAME.ncd|; + execute($c) unless $config{no_ltxt2ptxt} ; + + if ($config{make_jed}) { + $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No -jedec $TOPNAME.ncd $TOPNAME.jed $TOPNAME.prf|; + } else { + $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; + } + execute($c); +} + +$c=qq|htmlrpt -mrp $TOPNAME.mrp -mtwr $TOPNAME.twr.hold -ptwr $TOPNAME.twr.setup $TOPNAME|; +execute($c); + +if ($config{firefox_open}) { + $c=qq|firefox $TOPNAME.html|; + execute($c); +} + +chdir ".."; + + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + $c = ". $lattice_bin_path/diamond_env; " . $c; + print GREEN, "\n\ncommand to execute: $c \n", RESET; + my $r=system($c); + if ($r) { + print "$!"; + if ($op ne "do_not_exit") { + exit; + } + } + return $r; +} diff --git a/dirich5d1/config.vhd b/dirich5d1/config.vhd new file mode 100644 index 0000000..de79397 --- /dev/null +++ b/dirich5d1/config.vhd @@ -0,0 +1,142 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + constant DIRICH_VERSION : integer := 2; --1 or 2. + +--TDC settings + constant BOARD : string := "dirich"; -- Options: dirich, trb3 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 9; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3D8"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"58"; + + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices --needed for Dirich2 + constant INCLUDE_ADC : integer := c_NO; + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + +--input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_YES; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 2; + constant MONITOR_INPUT_NUM : integer := 32; + +--Retransmission + constant USE_RETRANSMISSION : integer := c_NO;--c_YES; + +--Misc + constant FPGA_SIZE : string := "85KUM"; + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"44", x"69", x"52", x"69", x"63", x"68", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"55", x"49", x"44", x"20", x"20", x"89", x"88", x"87", x"86", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + x"54", x"65", x"6d", x"70", x"65", x"72", x"61", x"74", x"75", x"72", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"85", x"0a", + x"8a", x"0a", + x"8b", x"0a", + others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9A800000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/dirich5d1/config_compile_frankfurt.pl b/dirich5d1/config_compile_frankfurt.pl new file mode 100644 index 0000000..8330956 --- /dev/null +++ b/dirich5d1/config_compile_frankfurt.pl @@ -0,0 +1,26 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA381', +Speedgrade => '8', + + +TOPNAME => "dirich5d1", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'dirich5d1', +par_options => '../par.p2t', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/dirich5d1/config_compile_giessen.pl b/dirich5d1/config_compile_giessen.pl new file mode 100644 index 0000000..ab75c3e --- /dev/null +++ b/dirich5d1/config_compile_giessen.pl @@ -0,0 +1,27 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA381', +Speedgrade => '8', + +TOPNAME => "dirich5d1", +lm_license_file_for_synplify => "7788\@fb07pc-u102325", +lm_license_file_for_par => "7788\@fb07pc-u102325", +lattice_path => '/usr/local/diamond/3.11_x64/', +synplify_path => '/usr/local/diamond/3.11_x64/synpbase', +synplify_command => "synpwrap -fg -options", + +nodelist_file => '../nodelist_giessen.txt', +pinout_file => 'dirich5d1', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used +#make_jed => 1, + diff --git a/dirich5d1/config_compile_gsi.pl b/dirich5d1/config_compile_gsi.pl new file mode 100644 index 0000000..7f5ad68 --- /dev/null +++ b/dirich5d1/config_compile_gsi.pl @@ -0,0 +1,26 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA381', +Speedgrade => '8', + +TOPNAME => "dirich5d1", +lm_license_file_for_synplify => "27000\@lxcad04.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.12', +synplify_path => '/opt/synplicity/T-2022.09-SP2', +#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/opt/synplicity/P-2019.09-SP1/bin/synplify_premier_dp", +synplify_command => "/opt/synplicity/T-2022.09-SP2/bin/synplify_premier_dp", + +nodelist_file => "../nodelist_hades69.txt", +pinout_file => 'dirich5d1', +par_options => '../par.p2t', + +#Include only necessary lpf files +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/dirich5d1/dirich5d1.lpf b/dirich5d1/dirich5d1.lpf new file mode 100644 index 0000000..0d6d626 --- /dev/null +++ b/dirich5d1/dirich5d1.lpf @@ -0,0 +1,82 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLOCK_CORE 200 MHz; +FREQUENCY PORT CLOCK_IN 200 MHz; +FREQUENCY PORT CLOCK_CAL 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 30; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + +UGROUP "INPGATE_LEFT" BBOX 35 2 + BLKNAME THE_TDC/GEN_HitSelect.1.Double.HitSelect.hit_in_s_12_u[1] + BLKNAME THE_TDC/GEN_HitSelect.2.Double.HitSelect.hit_in_s_20_u[2] + BLKNAME THE_TDC/GEN_HitSelect.3.Double.HitSelect.hit_in_s_28_u[3] + BLKNAME THE_TDC/GEN_HitSelect.4.Double.HitSelect.hit_in_s_36_u[4] + BLKNAME THE_TDC/GEN_HitSelect.5.Double.HitSelect.hit_in_s_44_u[5] + BLKNAME THE_TDC/GEN_HitSelect.6.Double.HitSelect.hit_in_s_52_u[6] + BLKNAME THE_TDC/GEN_HitSelect.7.Double.HitSelect.hit_in_s_60_u[7] + BLKNAME THE_TDC/GEN_HitSelect.8.Double.HitSelect.hit_in_s_68_u[8] + BLKNAME THE_TDC/GEN_HitSelect.9.Double.HitSelect.hit_in_s_76_u[9] + BLKNAME THE_TDC/GEN_HitSelect.10.Double.HitSelect.hit_in_s_84_u[10] + BLKNAME THE_TDC/GEN_HitSelect.11.Double.HitSelect.hit_in_s_92_u[11] + BLKNAME THE_TDC/GEN_HitSelect.12.Double.HitSelect.hit_in_s_100_u[12] + BLKNAME THE_TDC/GEN_HitSelect.13.Double.HitSelect.hit_in_s_108_u[13] + BLKNAME THE_TDC/GEN_HitSelect.14.Double.HitSelect.hit_in_s_116_u[14] + BLKNAME THE_TDC/GEN_HitSelect.15.Double.HitSelect.hit_in_s_124_u[15] + BLKNAME THE_TDC/GEN_HitSelect.16.Double.HitSelect.hit_in_s_132_u[16] + ; +LOCATE UGROUP "INPGATE_LEFT" SITE "R9C2D" ; + +UGROUP "INPGATE_RIGHT" BBOX 80 2 + BLKNAME THE_TDC/GEN_HitSelect.17.Double.HitSelect.hit_in_s_140_u[17] + BLKNAME THE_TDC/GEN_HitSelect.18.Double.HitSelect.hit_in_s_148_u[18] + BLKNAME THE_TDC/GEN_HitSelect.19.Double.HitSelect.hit_in_s_156_u[19] + BLKNAME THE_TDC/GEN_HitSelect.20.Double.HitSelect.hit_in_s_164_u[20] + BLKNAME THE_TDC/GEN_HitSelect.21.Double.HitSelect.hit_in_s_172_u[21] + BLKNAME THE_TDC/GEN_HitSelect.22.Double.HitSelect.hit_in_s_180_u[22] + BLKNAME THE_TDC/GEN_HitSelect.23.Double.HitSelect.hit_in_s_188_u[23] + BLKNAME THE_TDC/GEN_HitSelect.24.Double.HitSelect.hit_in_s_196_u[24] + BLKNAME THE_TDC/GEN_HitSelect.25.Double.HitSelect.hit_in_s_204_u[25] + BLKNAME THE_TDC/GEN_HitSelect.26.Double.HitSelect.hit_in_s_212_u[26] + BLKNAME THE_TDC/GEN_HitSelect.27.Double.HitSelect.hit_in_s_220_u[27] + BLKNAME THE_TDC/GEN_HitSelect.28.Double.HitSelect.hit_in_s_228_u[28] + BLKNAME THE_TDC/GEN_HitSelect.29.Double.HitSelect.hit_in_s_236_u[29] + BLKNAME THE_TDC/GEN_HitSelect.30.Double.HitSelect.hit_in_s_244_u[30] + BLKNAME THE_TDC/GEN_HitSelect.31.Double.HitSelect.hit_in_s_252_u[31] + BLKNAME THE_TDC/GEN_HitSelect.32.Double.HitSelect.hit_in_s_260_u[32] + ; +LOCATE UGROUP "INPGATE_RIGHT" SITE "R9C123D" ; diff --git a/dirich5d1/dirich5d1.prj b/dirich5d1/dirich5d1.prj new file mode 100644 index 0000000..45065a5 --- /dev/null +++ b/dirich5d1/dirich5d1.prj @@ -0,0 +1,238 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG381C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "dirich5d1" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/dirich5d1.edf" +set_option log_file "workdir/dirich5d1_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -vhdl2008 1 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" +add_file -vhdl -lib work "../code/pwm_generator.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + +add_file -vhdl -lib work "../../trbnet/special/i2c_slim2.vhd" +add_file -vhdl -lib work "../../trbnet/special/i2c_gstart2.vhd" +add_file -vhdl -lib work "../../trbnet/special/i2c_sendb2.vhd" + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + +#add_file -verilog -lib work "diamond/pcs/serdes_sync_0/serdes_sync_0_softlogic.v" +#add_file -vhdl -lib work "diamond/pcs/serdes_sync_0/serdes_sync_0.vhd" +#add_file -vhdl -lib work "diamond/pcs/pcs.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "tdc_release/Channel.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" +add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "tdc_release/Readout_record.vhd" +add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd" +add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "tdc_release/up_counter.vhd" + +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.vhd" + + +### Triggering +add_file -vhdl -lib work "./code/stretched_OR_trigger.vhd" +add_file -vhdl -lib work "../dirich/code/input_signal_stretcher.vhd" + + + +add_file -vhdl -lib work "./dirich5d1.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/dirich5d1/dirich5d1.vhd b/dirich5d1/dirich5d1.vhd new file mode 100644 index 0000000..506b80c --- /dev/null +++ b/dirich5d1/dirich5d1.vhd @@ -0,0 +1,510 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity dirich5d1 is + port( + CLOCK_IN : in std_logic; --Main Oscillator, on_board oscillator + TRIG_IN : in std_logic; --Reference Time + CLOCK_CAL : in std_logic; --on-board calibration oscillator + + CLOCK_OUT : out std_logic; -- CLK to clock cleaner + CLOCK_CLEAN : in std_logic_vector(1 downto 0); -- CLK from clock cleaner + + INPUT : in std_logic_vector(32 downto 1); +-- PWM : out std_logic_vector(32 downto 1); + + --ASYNC_OR : out std_logic; -- asynch OR of all 32 inputs + + --Additional IO + SFP1_TX_DIS : out std_logic; + + --SIG : inout std_logic_vector(5 downto 1); + --1:master ready, 2: slave ready, 3-4 trigger, 5 reset + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + --ADC + ADC_SCLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + TEMP_LINE : inout std_logic; + + SFP_MOD1 : inout std_logic; + SFP_MOD2 : inout std_logic; + + MISO_IN : in std_logic_vector(1 downto 0); + MOSI_OUT : out std_logic_vector(1 downto 0); + SCLK_OUT : out std_logic_vector(1 downto 0); + CS_OUT : out std_logic_vector(1 downto 0); + + SIG_OUT : out std_logic_vector(32 downto 1) + + + --Test Connectors + --TEST_LINE : inout std_logic_vector(14 downto 1) + ); + + + attribute syn_useioff : boolean; +-- attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + attribute syn_useioff of INPUT : signal is false; + +end entity; + +architecture dirich5d1_arch of dirich5d1 is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal link_stat_in, link_stat_out : std_logic; + --READOUT + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in , busOrTrigger_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busOrTrigger_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_clk_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + + signal pwm_i : std_logic_vector(31 downto 0); + signal timer : TIMERS; + signal hdr_io : std_logic_vector(9 downto 0); + signal led_off : std_logic; + --TDC + signal hit_in_i : std_logic_vector(32 downto 1); + signal logic_analyser_i : std_logic_vector(16 downto 1); + +-- signal led_los_lock : std_logic; +-- signal los_count : unsigned(23 downto 0); + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal link_stat_in_reg : std_logic; + signal signals_old_i : std_logic_vector(4 downto 3); + + component usrmclk + port( + USRMCLKI : in std_ulogic; + USRMCLKTS : in std_ulogic + ); + end component; + attribute syn_noprune : boolean; + attribute syn_noprune of USRMCLK : component is true; + + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLOCK_IN, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + +-- process +-- begin +-- wait until rising_edge(CLOCK_CAL); +-- if debug_clock_reset(0) = '0' then +-- led_los_lock <= '0'; +-- los_count <= (others => '0'); +-- elsif los_count(23) = '0' then +-- los_count <= los_count + 1; +-- else +-- led_los_lock <= '1'; +-- end if; +-- end process; + +--THE_CAL_PLL : entity work.pll_in3125_out50 +THE_CAL_PLL : entity work.pll_in200_out50 + port map( + CLKI => CLOCK_CAL, + CLKOP => clk_cal + ); + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + --USE_RETRANSMISSION => USE_RETRANSMISSION, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => link_stat_in, + SD_LOS_IN => link_stat_in, + SD_TXDIS_OUT => link_stat_out, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + SFP1_TX_DIS <= '1' when link_stat_out = '1' else '0'; -- SFP1_TX_DIS + +-- SIG(2) <= '1' when link_stat_out = '1' else '0'; -- SD_TXDIR_OUT +-- -- on pin SIG2, N5 +-- SIG(2) <= '0'; -- when link_stat_out = '1' else '0'; -- SD_TXDIR_OUT on + + link_stat_in <= '0'; --SIG(1); -- not available for SFF + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_IN, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => TEMP_LINE, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 6, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", 5 => x"e000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, 5 => 2, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busthresh_rx, + BUS_RX(4) => bustdc_rx, + BUS_RX(5) => busOrTrigger_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busthresh_tx, + BUS_TX(4) => bustdc_tx, + BUS_TX(5) => busOrTrigger_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, --FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, --FLASH_OUT, + FLASH_OUT => FLASH_IN, --FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => hdr_io, + ADDITIONAL_REG(0) => led_off, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => INPUT, + TRIG_GEN_INPUTS => INPUT, + --TRIG_GEN_OUTPUTS => SIG(4 downto 3), + TRIG_GEN_OUTPUTS => signals_old_i(4 downto 3), + --SED + SED_ERROR_OUT => sed_error_i, + --I2C + SDA_INOUT => SFP_MOD2, + SCL_INOUT => SFP_MOD1, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + +--------------------------------------------------------------------------- +-- PWM / Thresh +--------------------------------------------------------------------------- + + MOSI_OUT <= spi_mosi(1 downto 0); + SCLK_OUT <= spi_clk(1 downto 0); + CS_OUT <= spi_cs(1 downto 0); + spi_miso(1 downto 0) <= MISO_IN; + + +--------------------------------------------------------------------------- +-- ASYNCHRONOUS OR OF ALL INPUTS +--------------------------------------------------------------------------- + +--ASYNC_OR <= or_all(INPUT(32 downto 1)); + +-- THE_OR_TRIGGER: entity work.stretched_OR_trigger +-- port map ( +-- CLK => clk_sys, +-- RESET => reset_i, + +-- INPUT => INPUT(32 downto 1), +-- OUTPUT => ASYNC_OR, + +-- BUS_RX => busOrTrigger_rx, +-- BUS_TX => busOrTrigger_tx +-- ); + + + SIG_OUT(8 downto 1) <= INPUT(8 downto 1); + + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + +--Debug UART + --hdr_io(8) <= TEST_LINE(1); + --TEST_LINE(2) <= hdr_io(9); + +-- TEST_LINE(8 downto 1) <= hdr_io(7 downto 0); +-- TEST_LINE(14 downto 11) <= time_counter(31 downto 28); +-- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 6) & "00" & link_stat_out & link_stat_in_reg & debug_clock_reset(1 downto 0) ; + --& med_stat_debug(18 downto 8); +-- link_stat_in_reg <= link_stat_in when rising_edge(clk_full_osc); + +--TEST_LINE(8 downto 1) <= med_stat_debug(7 downto 0); +--TEST_LINE(8 downto 1) <= clk_sys & med_stat_debug(9) & med_stat_debug(10) & med_stat_debug(11) & clear_i & reset_i & link_stat_out & link_stat_in_reg; +-- TEST_LINE(8 downto 3) <= clear_i & reset_i & link_stat_out & link_stat_in_reg & debug_clock_reset(0) & med_stat_debug(4);-- & med_stat_debug(5) & med_stat_debug(6); + + + +-- TEST_LINE(1) <= med_stat_debug(15); -- RX_CV_ERROR, same as rx_error +-- TEST_LINE(2) <= med_stat_debug(2); -- RX_LOS +-- TEST_LINE(3) <= med_stat_debug(13); -- RX_LSM +-- TEST_LINE(4) <= med_stat_debug(14); -- CDR_LOL +-- TEST_LINE(8 downto 5) <= med_stat_debug(19 downto 16); -- rx_fsm_state + + + + +-- TEST_LINE(1) <= med_stat_debug(10); -- finished_reset_tx +-- TEST_LINE(5) <= med_stat_debug(15); -- RX_CV_ERROR, same as rx_error +-- TEST_LINE(6) <= med_stat_debug(9); -- finished_reset_rx + +-- TEST_LINE(4) <= not med2int(0).stat_op(9) or led_off; --LED_GREEN +-- TEST_LINE(5) <= debug_clock_reset(0) or led_off; --LED_ORANGE +-- TEST_LINE(6) <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; --LED_RED +-- TEST_LINE(7) <= not med2int(0).stat_op(8) or led_off; --LED_YELLOW +-- TEST_LINE(8) <= reset_i; +-- TEST_LINE(9) <= int2med(0).ctrl_op(15); -- SEND_LINK_RESET_IN +-- TEST_LINE(10) <= int2med(0).dataready; -- To SFP +-- TEST_LINE(11) <= med2int(0).dataready; -- from SFP + + --SIG(5) <= '1'; + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_GREEN <= not med2int(0).stat_op(9) or led_off; + LED_ORANGE <= debug_clock_reset(0) or led_off; + LED_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; + LED_YELLOW <= not med2int(0).stat_op(8) or led_off; + + + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process + begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + if reset_i = '1' then + time_counter <= (others => '0'); + end if; + end process; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_NO, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => CLOCK_IN, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => TRIG_IN, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => logic_analyser_i + ); + + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i <= INPUT; + end generate; + + + +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + +end architecture; + + + diff --git a/dirich5d1/nodelist_frankfurt.txt b/dirich5d1/nodelist_frankfurt.txt new file mode 100644 index 0000000..dab616f --- /dev/null +++ b/dirich5d1/nodelist_frankfurt.txt @@ -0,0 +1,21 @@ +// nodes file for parallel place&route + + +[jspc37] +SYSTEM = linux +CORENUM = 4 +ENV = /d/jspc29/lattice/39_settings.sh +WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir + + +[jspc57] +SYSTEM = linux +CORENUM = 4 +ENV = /d/jspc29/lattice/39_settings.sh +WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir + +[jspc29] +SYSTEM = linux +CORENUM = 3 +ENV = /d/jspc29/lattice/39_settings.sh +WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir diff --git a/dirich5d1/nodelist_giessen.txt b/dirich5d1/nodelist_giessen.txt new file mode 100644 index 0000000..cfc134f --- /dev/null +++ b/dirich5d1/nodelist_giessen.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + + +[fb07pc-u102325] +SYSTEM = linux +CORENUM = 12 +WORKDIR = /home/adrian/trbvhdl/dirich/dirich5d1/workdir diff --git a/dirich5d1/nodelist_hades69.txt b/dirich5d1/nodelist_hades69.txt new file mode 100644 index 0000000..1ad1e35 --- /dev/null +++ b/dirich5d1/nodelist_hades69.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + +[localhost] +SYSTEM = linux +CORENUM = 24 +ENV = /home/hadaq/bin/diamond_env +WORKDIR = /home/hadaq/vhdl_dirich5d1/dirich/dirich5d1/workdir diff --git a/dirich5d1/par.p2t b/dirich5d1/par.p2t new file mode 100644 index 0000000..02a5867 --- /dev/null +++ b/dirich5d1/par.p2t @@ -0,0 +1,70 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 2 # Controlled by the compile.pl script. +-s 10 +-t 1 +-c 2 +-e 2 +-i 10 +# -t 20 was good +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=ON:paruseNBR=1 diff --git a/dirich5d1/tdc_release b/dirich5d1/tdc_release new file mode 120000 index 0000000..6a654d0 --- /dev/null +++ b/dirich5d1/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.3 \ No newline at end of file