From: Jan Michel Date: Thu, 6 Aug 2015 09:33:48 +0000 (+0200) Subject: update X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=fdb5f09561437e76ae070b20c3cda84e91c0d833;p=trbnet.git update --- diff --git a/gbe_trb/base/gbe_ipu_dummy.vhd b/gbe_trb/base/gbe_ipu_dummy.vhd new file mode 100644 index 0000000..182adc4 --- /dev/null +++ b/gbe_trb/base/gbe_ipu_dummy.vhd @@ -0,0 +1,626 @@ +LIBRARY ieee; + +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +entity gbe_ipu_dummy is + generic ( + DO_SIMULATION : integer range 0 to 1 := 0; + FIXED_SIZE_MODE : integer range 0 to 1 := 1; + FIXED_SIZE : integer range 0 to 65535 := 10; + INCREMENTAL_MODE : integer range 0 to 1 := 0; + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; + FIXED_DELAY_MODE : integer range 0 to 1 := 1; + FIXED_DELAY : integer range 0 to 16777215 := 16777215 + ); + port ( + clk : in std_logic; + rst : in std_logic; + GBE_READY_IN : in std_logic; + + CFG_EVENT_SIZE_IN : in std_logic_vector(15 downto 0); + CFG_TRIGGERED_MODE_IN : in std_logic; + TRIGGER_IN : in std_logic; + + CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); + CTS_CODE_OUT : out std_logic_vector (7 downto 0); + CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + CTS_START_READOUT_OUT : out std_logic; + CTS_DATA_IN : in std_logic_vector (31 downto 0); + CTS_DATAREADY_IN : in std_logic; + CTS_READOUT_FINISHED_IN : in std_logic; + CTS_READ_OUT : out std_logic; + CTS_LENGTH_IN : in std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_OUT : out std_logic_vector (15 downto 0); + FEE_DATAREADY_OUT : out std_logic; + FEE_READ_IN : in std_logic; + FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + FEE_BUSY_OUT : out std_logic + ); +end entity gbe_ipu_dummy; + +architecture RTL of gbe_ipu_dummy is + + component random_size is + port ( + Clk: in std_logic; + Enb: in std_logic; + Rst: in std_logic; + Dout: out std_logic_vector(31 downto 0)); + end component; + + type states is (IDLE, TIMEOUT, CTS_START, FEE_START, WAIT_FOR_READ_1, WAIT_A_SEC_1, WAIT_FOR_READ_2, WAIT_A_SEC_2, WAIT_FOR_READ_3, WAIT_A_SEC_3, + WAIT_FOR_READ_4, WAIT_A_SEC_4, WAIT_FOR_READ_5, WAIT_A_SEC_5, WAIT_FOR_READ_6, WAIT_A_SEC_6, CLOSE + , LOOP_OVER_DATA, SEND_ONE_WORD, WAIT_A_SEC_7, LOWER_BUSY, WAIT_A_SEC_8, WAIT_A_SEC_9, PULSE_WITH_READ); + signal current_state, next_state : states; + + signal ctr : integer range 0 to 16777215 := 16777215; + signal timeout_stop : integer range 0 to 16777215 := 16777215; + signal pause_cts_fee : integer range 0 to 65535 := 8; + signal pause_dready : integer range 0 to 65535 := 3; + signal pause_wait_1, pause_wait_2, pause_wait_3, pause_wait_4, pause_wait_5, pause_wait_6, send_word_pause, pause_wait_7, pause_wait_8, pause_wait_9 : integer range 0 to 10 := 4; + signal cts_start_readout, fee_busy, fee_dready, cts_read : std_logic; + signal cts_number, fee_data, test_data_len : std_logic_vector(15 downto 0); + signal data_ctr : std_logic_vector(16 downto 0); + signal size_rand_en, delay_rand_en : std_logic; + signal delay_value : std_logic_vector(15 downto 0); + signal d, s : std_logic_vector(31 downto 0); + signal trigger_type, bank_select : std_logic_vector(3 downto 0) := x"0"; + signal constructed_events : std_logic_vector(15 downto 0) := x"0000"; + signal increment_flag : std_logic; + + +begin + + send_word_pause <= 1; + + + fixed_size_gen : if FIXED_SIZE_MODE = 1 generate + test_data_len <= std_logic_vector(to_unsigned(FIXED_SIZE, 16)); --CFG_EVENT_SIZE_IN; --std_logic_vector(to_unsigned(FIXED_SIZE, 16)); + end generate fixed_size_gen; + + random_size_gen : if FIXED_SIZE_MODE = 0 and INCREMENTAL_MODE = 0 generate + + size_rand_inst : random_size + port map(Clk => clk, + Enb => size_rand_en, + Rst => rst, + Dout => s + ); + + test_data_len <= (x"00" & "00" & s(4 downto 0)) + x"0001"; + + process(clk) + begin + if rising_edge(clk) then + if (current_state = TIMEOUT and ctr = timeout_stop) then + size_rand_en <= '1'; + else + size_rand_en <= '0'; + end if; + end if; + end process; + + end generate random_size_gen; + + incremental_size_gen : if FIXED_SIZE_MODE = 0 and INCREMENTAL_MODE = 1 generate + + process(clk) + begin + if rising_edge(clk) then + test_data_len <= std_logic_vector(to_unsigned(FIXED_SIZE, 16)) + constructed_events; + end if; + end process; + + end generate incremental_size_gen; + + fixed_delay_gen : if FIXED_DELAY_MODE = 1 generate + timeout_stop <= FIXED_DELAY when DO_SIMULATION = 0 else 100; + end generate fixed_delay_gen; + + variable_delay_gen : if FIXED_DELAY_MODE = 0 generate + + delay_rand_inst : random_size + port map(Clk => clk, + Enb => delay_rand_en, + Rst => rst, + Dout => d); + + delay_value <= d(31 downto 16); + + process(clk) + begin + if rising_edge(clk) then + if (current_state = IDLE and GBE_READY_IN = '1') then + delay_rand_en <= '1'; + else + delay_rand_en <= '0'; + end if; + end if; + end process; + + timeout_stop <= to_integer(unsigned(delay_value)); + + end generate variable_delay_gen; + + + CTS_INFORMATION_OUT <= x"d" & bank_select; + CTS_READOUT_TYPE_OUT <= trigger_type; --x"1"; + CTS_CODE_OUT <= x"aa"; + CTS_START_READOUT_OUT <= cts_start_readout; + CTS_READ_OUT <= cts_read; + FEE_BUSY_OUT <= fee_busy; + FEE_DATAREADY_OUT <= fee_dready; + FEE_DATA_OUT <= fee_data; + + state_machine_proc : process (clk, rst) is + begin + if rst = '1' then + current_state <= IDLE; + elsif rising_edge(clk) then + current_state <= next_state; + end if; + end process state_machine_proc; + + state_machine : process (current_state, GBE_READY_IN, ctr, timeout_stop, pause_dready, pause_cts_fee, FEE_READ_IN, pause_wait_6, pause_wait_5, + pause_wait_4, pause_wait_3, pause_wait_2, pause_wait_1, send_word_pause, TRIGGER_IN, data_ctr, test_data_len, pause_wait_7, pause_wait_8, pause_wait_9 + ) is + begin + case current_state is + when IDLE => + if (GBE_READY_IN = '1') then + next_state <= TIMEOUT; + else + next_state <= IDLE; + end if; + + when TIMEOUT => + --if (ctr = timeout_stop) then + if (TRIGGER_IN = '1') then + next_state <= CTS_START; + else + next_state <= TIMEOUT; + end if; + + when CTS_START => + if (ctr = pause_cts_fee) then + next_state <= FEE_START; + else + next_state <= CTS_START; + end if; + + when FEE_START => + if (ctr = pause_dready) then + next_state <= WAIT_FOR_READ_1; + else + next_state <= FEE_START; + end if; + + when WAIT_FOR_READ_1 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_1; + else + next_state <= WAIT_FOR_READ_1; + end if; + + when WAIT_A_SEC_1 => + if (ctr = pause_wait_1) then + next_state <= WAIT_FOR_READ_2; + else + next_state <= WAIT_A_SEC_1; + end if; + + when WAIT_FOR_READ_2 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_2; + else + next_state <= WAIT_FOR_READ_2; + end if; + + when WAIT_A_SEC_2 => + if (ctr = pause_wait_2) then + next_state <= WAIT_FOR_READ_3; + else + next_state <= WAIT_A_SEC_2; + end if; + + when WAIT_FOR_READ_3 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_3; + else + next_state <= WAIT_FOR_READ_3; + end if; + + when WAIT_A_SEC_3 => + if (ctr = pause_wait_3) then + next_state <= WAIT_FOR_READ_4; + else + next_state <= WAIT_A_SEC_3; + end if; + + when WAIT_FOR_READ_4 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_4; + else + next_state <= WAIT_FOR_READ_4; + end if; + + when WAIT_A_SEC_4 => + if (ctr = pause_wait_4) then + next_state <= WAIT_FOR_READ_5; + else + next_state <= WAIT_A_SEC_4; + end if; + + when WAIT_FOR_READ_5 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_5; + else + next_state <= WAIT_FOR_READ_5; + end if; + + when WAIT_A_SEC_5 => + if (ctr = pause_wait_5) then + next_state <= WAIT_FOR_READ_6; + else + next_state <= WAIT_A_SEC_5; + end if; + + when WAIT_FOR_READ_6 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_6; + else + next_state <= WAIT_FOR_READ_6; + end if; + + when WAIT_A_SEC_6 => + if (ctr = pause_wait_6) then + next_state <= LOOP_OVER_DATA; + else + next_state <= WAIT_A_SEC_6; + end if; + + when LOOP_OVER_DATA => + if (to_integer(unsigned(data_ctr)) = (2 * (to_integer(unsigned(test_data_len)) - 1))) then + next_state <= WAIT_A_SEC_7; + else + next_state <= LOOP_OVER_DATA; --SEND_ONE_WORD; + end if; + + when SEND_ONE_WORD => +-- if (ctr = send_word_pause) then +-- next_state <= LOOP_OVER_DATA; +-- else +-- next_state <= SEND_ONE_WORD; +-- end if; + next_state <= LOOP_OVER_DATA; + + when WAIT_A_SEC_7 => + if (ctr = pause_wait_7) then + next_state <= LOWER_BUSY; + else + next_state <= WAIT_A_SEC_7; + end if; + + when LOWER_BUSY => + next_state <= WAIT_A_SEC_8; + + when WAIT_A_SEC_8 => + if (ctr = pause_wait_8) then + next_state <= PULSE_WITH_READ; + else + next_state <= WAIT_A_SEC_8; + end if; + + when PULSE_WITH_READ => + next_state <= WAIT_A_SEC_9; + + when WAIT_A_SEC_9 => + if (ctr = pause_wait_9) then + next_state <= CLOSE; + else + next_state <= WAIT_A_SEC_9; + end if; + + when CLOSE => + next_state <= IDLE; + + end case; + end process state_machine; + + process(CLK) + begin + if rising_edge(CLK) then + if (current_state = IDLE) then + data_ctr <= (others => '0'); + elsif (current_state = LOOP_OVER_DATA and fee_dready = '1' and FEE_READ_IN = '1') then + data_ctr <= data_ctr + x"1"; + else + data_ctr <= data_ctr; + end if; + end if; + end process; + + ctr_proc : process(clk) + begin + if rising_edge(clk) then + + ctr <= ctr; + + case current_state is + when IDLE => + ctr <= 0; + when TIMEOUT => +-- if ctr /= timeout_stop then +-- ctr <= ctr + 1; +-- else + ctr <= 0; +-- end if; + when CTS_START => + if (ctr /= pause_cts_fee) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when FEE_START => + if (ctr /= pause_dready) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when WAIT_A_SEC_1 => + if (ctr /= pause_wait_1) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when WAIT_A_SEC_2 => + if (ctr /= pause_wait_2) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when WAIT_A_SEC_3 => + if (ctr /= pause_wait_3) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when WAIT_A_SEC_4 => + if (ctr /= pause_wait_4) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when WAIT_A_SEC_5 => + if (ctr /= pause_wait_5) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when WAIT_A_SEC_6 => + if (ctr /= pause_wait_6) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when SEND_ONE_WORD => + if (ctr /= send_word_pause) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when WAIT_A_SEC_7 => + if (ctr /= pause_wait_7) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when WAIT_A_SEC_8 => + if (ctr /= pause_wait_8) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + when WAIT_A_SEC_9 => + if (ctr /= pause_wait_9) then + ctr <= ctr + 1; + else + ctr <= 0; + end if; + + when others => + ctr <= ctr; + end case; + end if; + end process ctr_proc; + + + process(CLK) + begin + if rising_edge(CLK) then + if (current_state = IDLE) then + cts_start_readout <= '0'; + elsif (current_state = CTS_START and ctr = 0) then + cts_start_readout <= '1'; + elsif (current_state = CLOSE) then + cts_start_readout <= '0'; + else + cts_start_readout <= cts_start_readout; + end if; + end if; + end process; + + process(rst, CLK) + begin + if rst = '1' then + cts_number <= x"0001"; + elsif rising_edge(CLK) then + if (current_state = CLOSE) then + cts_number <= cts_number + x"1"; + else + cts_number <= cts_number; + end if; + end if; + end process; + + process(rst, CLK) + begin + if rst = '1' then + trigger_type <= x"1"; + elsif rising_edge(CLK) then +-- if (cts_number > x"0008" and cts_number < x"000b") then +-- trigger_type <= x"2"; +-- else +-- trigger_type <= x"1"; +-- end if; + --trigger_type <= cts_number(3 downto 0); + trigger_type <= x"1"; + end if; + end process; + + bank_select <= trigger_type; + + process(CLK) + begin + if rising_edge(CLK) then + if (current_state = IDLE) then + fee_busy <= '0'; + elsif (current_state = FEE_START and ctr = 0) then + fee_busy <= '1'; + elsif (current_state = LOWER_BUSY) then + fee_busy <= '0'; + else + fee_busy <= fee_busy; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if (current_state = WAIT_FOR_READ_1) then + fee_dready <= '1'; + elsif (current_state = WAIT_FOR_READ_2) then + fee_dready <= '1'; + elsif (current_state = WAIT_FOR_READ_3) then + fee_dready <= '1'; + elsif (current_state = WAIT_FOR_READ_4) then + fee_dready <= '1'; + elsif (current_state = WAIT_FOR_READ_5) then + fee_dready <= '1'; + elsif (current_state = WAIT_FOR_READ_6) then + fee_dready <= '1'; + elsif (current_state = LOOP_OVER_DATA and FEE_READ_IN = '1') then + fee_dready <= '1'; + elsif (current_state = SEND_ONE_WORD) then -- and ctr = send_word_pause) then + fee_dready <= '1'; + else + fee_dready <= '0'; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + case current_state is + when WAIT_FOR_READ_1 => + fee_data <= x"00bb"; + when WAIT_FOR_READ_2 => + fee_data <= cts_number; + when WAIT_FOR_READ_3 => + fee_data <= test_data_len + x"1"; + when WAIT_FOR_READ_4 => + fee_data <= x"ff21"; + when WAIT_FOR_READ_5 => + fee_data <= test_data_len; + when WAIT_FOR_READ_6 => + fee_data <= x"ff22"; + when LOOP_OVER_DATA => + fee_data <= data_ctr(15 downto 0); + when SEND_ONE_WORD => + fee_data <= data_ctr(15 downto 0); + when others => + fee_data <= x"12bc"; + end case; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if (current_state = IDLE) then + cts_read <= '0'; + elsif (current_state = PULSE_WITH_READ) then + cts_read <= '1'; + else + cts_read <= '0'; + end if; + end if; + end process; + + + static_incr_gen : if UP_DOWN_MODE = 0 generate + + process(CLK) + begin + if rising_edge(CLK) then + if (current_state = CLOSE) then + constructed_events <= constructed_events + x"1"; + else + constructed_events <= constructed_events; + end if; + end if; + end process; + + end generate static_incr_gen; + + up_down_gen : if UP_DOWN_MODE = 1 generate + + process(CLK) + begin + if rising_edge(CLK) then + if (current_state = CLOSE) then + if (increment_flag = '1') then + constructed_events <= constructed_events + x"1"; + else + constructed_events <= constructed_events - x"1"; + end if; + else + constructed_events <= constructed_events; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if (current_state = CLOSE and test_data_len = UP_DOWN_LIMIT) then + increment_flag <= '0'; + elsif (current_state = CLOSE and test_data_len = FIXED_SIZE) then + increment_flag <= '1'; + else + increment_flag <= increment_flag; + end if; + end if; + end process; + + end generate up_down_gen; + + + +end architecture RTL; diff --git a/gbe_trb/base/gbe_ipu_multiplexer.vhd b/gbe_trb/base/gbe_ipu_multiplexer.vhd new file mode 100644 index 0000000..3c73e48 --- /dev/null +++ b/gbe_trb/base/gbe_ipu_multiplexer.vhd @@ -0,0 +1,176 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_ARITH.all; +use IEEE.std_logic_UNSIGNED.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--package vector_func is +--function find_next_active_link(v : std_logic_vector; s : integer) return integer is +-- variable next_one : integer range 0 to v'length - 1; +--begin +-- if (s) +-- for i in s + 1 to v'length - 1 loop +-- if (v(i) = '1') then next_one := i; end if; +-- end loop; +-- return next_one; +-- end function find_next_active_link; +--end package; + +entity gbe_ipu_multiplexer is + generic( + DO_SIMULATION : integer range 0 to 1 := 0; + INCLUDE_DEBUG : integer range 0 to 1 := 0; + + LINK_HAS_READOUT : std_logic_vector(3 downto 0) := "1111"; + NUMBER_OF_GBE_LINKS : integer range 0 to 4 := 0 + ); + port( + CLK_SYS_IN : in std_logic; + RESET : in std_logic; + + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); + CTS_CODE_IN : in std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + FEE_BUSY_IN : in std_logic; + + -- CTS interface + MLT_CTS_NUMBER_OUT : out std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_CODE_OUT : out std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_INFORMATION_OUT : out std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_READOUT_TYPE_OUT : out std_logic_vector(4 * NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_START_READOUT_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_DATA_IN : in std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_DATAREADY_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_READOUT_FINISHED_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_READ_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_LENGTH_IN : in std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_CTS_ERROR_PATTERN_IN : in std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0); + -- Data payload interface + MLT_FEE_DATA_OUT : out std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_FEE_DATAREADY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_FEE_READ_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_FEE_STATUS_BITS_OUT : out std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0); + MLT_FEE_BUSY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + DEBUG_OUT : out std_logic_vector(127 downto 0) + ); +end entity gbe_ipu_multiplexer; + +architecture RTL of gbe_ipu_multiplexer is + signal client_ptr : integer range 0 to NUMBER_OF_GBE_LINKS - 1 := 0; + signal cts_readout, cts_readout_q : std_logic; + +begin + process(RESET, CLK_SYS_IN) + begin + if (RESET = '1') then + if (LINK_HAS_READOUT(0) = '1') then client_ptr <= 0; + elsif (LINK_HAS_READOUT(1) = '1') then client_ptr <= 1; + elsif (LINK_HAS_READOUT(2) = '1') then client_ptr <= 2; + else client_ptr <= 3; + end if; + elsif rising_edge(CLK_SYS_IN) then + cts_readout <= CTS_START_READOUT_IN; + cts_readout_q <= cts_readout; + + if (cts_readout = '0' and cts_readout_q = '1') then + client_ptr <= client_ptr; + case client_ptr is + when 0 => + if (LINK_HAS_READOUT(1) = '1') then client_ptr <= 1; + elsif (LINK_HAS_READOUT(2) = '1') then client_ptr <= 2; + elsif (LINK_HAS_READOUT(3) = '1') then client_ptr <= 3; + else client_ptr <= 0; + end if; + + when 1 => + if (LINK_HAS_READOUT(2) = '1') then client_ptr <= 2; + elsif (LINK_HAS_READOUT(3) = '1') then client_ptr <= 3; + elsif (LINK_HAS_READOUT(0) = '1') then client_ptr <= 0; + else client_ptr <= 1; + end if; + + when 2 => + if (LINK_HAS_READOUT(3) = '1') then client_ptr <= 3; + elsif (LINK_HAS_READOUT(0) = '1') then client_ptr <= 0; + elsif (LINK_HAS_READOUT(1) = '1') then client_ptr <= 1; + else client_ptr <= 2; + end if; + + when 3 => + if (LINK_HAS_READOUT(0) = '1') then client_ptr <= 0; + elsif (LINK_HAS_READOUT(1) = '1') then client_ptr <= 1; + elsif (LINK_HAS_READOUT(2) = '1') then client_ptr <= 2; + else client_ptr <= 3; + end if; + when others => client_ptr <= client_ptr; + end case; + else + client_ptr <= client_ptr; + end if; + + end if; + end process; + + process(CLK_SYS_IN, RESET, client_ptr) + begin + if (RESET = '1') then + MLT_CTS_NUMBER_OUT(16 * (client_ptr + 1) - 1 downto 16 * client_ptr) <= (others => '0'); + MLT_CTS_CODE_OUT(8 * (client_ptr + 1) - 1 downto 8 * client_ptr) <= (others => '0'); + MLT_CTS_INFORMATION_OUT(8 * (client_ptr + 1) - 1 downto 8 * client_ptr) <= (others => '0'); + MLT_CTS_READOUT_TYPE_OUT(4 * (client_ptr + 1) - 1 downto 4 * client_ptr) <= (others => '0'); + MLT_CTS_START_READOUT_OUT(client_ptr) <= '0'; + CTS_DATA_OUT <= (others => '0'); + CTS_DATAREADY_OUT <= '0'; + CTS_READOUT_FINISHED_OUT <= '0'; + MLT_CTS_READ_OUT(client_ptr) <= '0'; + CTS_LENGTH_OUT <= (others => '0'); + CTS_ERROR_PATTERN_OUT <= (others => '0'); + + MLT_FEE_DATA_OUT(16 * (client_ptr + 1) - 1 downto 16 * client_ptr) <= (others => '0'); + MLT_FEE_DATAREADY_OUT(client_ptr) <= '0'; + FEE_READ_OUT <= '0'; + MLT_FEE_STATUS_BITS_OUT(32 * (client_ptr + 1) - 1 downto 32 * client_ptr) <= (others => '0'); + MLT_FEE_BUSY_OUT(client_ptr) <= '0'; + elsif rising_edge(CLK_SYS_IN) then + MLT_CTS_NUMBER_OUT(16 * (client_ptr + 1) - 1 downto 16 * client_ptr) <= CTS_NUMBER_IN; + MLT_CTS_CODE_OUT(8 * (client_ptr + 1) - 1 downto 8 * client_ptr) <= CTS_CODE_IN; + MLT_CTS_INFORMATION_OUT(8 * (client_ptr + 1) - 1 downto 8 * client_ptr) <= CTS_INFORMATION_IN; + MLT_CTS_READOUT_TYPE_OUT(4 * (client_ptr + 1) - 1 downto 4 * client_ptr) <= CTS_READOUT_TYPE_IN; + MLT_CTS_START_READOUT_OUT(client_ptr) <= CTS_START_READOUT_IN; + CTS_DATA_OUT <= MLT_CTS_DATA_IN(32 * (client_ptr + 1) - 1 downto 32 * client_ptr); + CTS_DATAREADY_OUT <= MLT_CTS_DATAREADY_IN(client_ptr); + CTS_READOUT_FINISHED_OUT <= MLT_CTS_READOUT_FINISHED_IN(client_ptr); + MLT_CTS_READ_OUT(client_ptr) <= CTS_READ_IN; + CTS_LENGTH_OUT <= MLT_CTS_LENGTH_IN(16 * (client_ptr + 1) - 1 downto 16 * client_ptr); + CTS_ERROR_PATTERN_OUT <= MLT_CTS_ERROR_PATTERN_IN(32 * (client_ptr + 1) - 1 downto 32 * client_ptr); + + MLT_FEE_DATA_OUT(16 * (client_ptr + 1) - 1 downto 16 * client_ptr) <= FEE_DATA_IN; + MLT_FEE_DATAREADY_OUT(client_ptr) <= FEE_DATAREADY_IN; + FEE_READ_OUT <= MLT_FEE_READ_IN(client_ptr); + MLT_FEE_STATUS_BITS_OUT(32 * (client_ptr + 1) - 1 downto 32 * client_ptr) <= FEE_STATUS_BITS_IN; + MLT_FEE_BUSY_OUT(client_ptr) <= FEE_BUSY_IN; + end if; + end process; + +end architecture RTL; \ No newline at end of file diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd new file mode 100644 index 0000000..4d81fa8 --- /dev/null +++ b/gbe_trb/base/gbe_logic_wrapper.vhd @@ -0,0 +1,921 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +entity gbe_logic_wrapper is + generic ( + DO_SIMULATION : integer range 0 to 1; + INCLUDE_DEBUG : integer range 0 to 1; + USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1; + RX_PATH_ENABLE : integer range 0 to 1; + + INCLUDE_READOUT : std_logic := '0'; + INCLUDE_SLOWCTRL : std_logic := '0'; + INCLUDE_DHCP : std_logic := '0'; + INCLUDE_ARP : std_logic := '0'; + INCLUDE_PING : std_logic := '0'; + + FRAME_BUFFER_SIZE : integer range 1 to 4 := 1; + READOUT_BUFFER_SIZE : integer range 1 to 4 := 1; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1; + + FIXED_SIZE_MODE : integer range 0 to 1 := 1; + INCREMENTAL_MODE : integer range 0 to 1 := 0; + FIXED_SIZE : integer range 0 to 65535 := 10; + FIXED_DELAY_MODE : integer range 0 to 1 := 1; + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; + FIXED_DELAY : integer range 0 to 16777215 := 16777215 + ); + port ( + CLK_SYS_IN : in std_logic; + CLK_125_IN : in std_logic; + CLK_RX_125_IN : in std_logic; + RESET : in std_logic; + GSR_N : in std_logic; + + MY_MAC_OUT : out std_logic_vector(47 downto 0); + MY_MAC_IN : in std_logic_vector(47 downto 0); + DHCP_DONE_OUT : out std_logic; + + -- connection to MAC + MAC_READY_CONF_IN : in std_logic; + MAC_RECONF_OUT : out std_logic; + MAC_AN_READY_IN : in std_logic; + + MAC_FIFOAVAIL_OUT : out std_logic; + MAC_FIFOEOF_OUT : out std_logic; + MAC_FIFOEMPTY_OUT : out std_logic; + MAC_RX_FIFOFULL_OUT : out std_logic; + + MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0); + MAC_TX_READ_IN : in std_logic; + MAC_TX_DISCRFRM_IN : in std_logic; + MAC_TX_STAT_EN_IN : in std_logic; + MAC_TX_STATS_IN : in std_logic_vector(30 downto 0); + MAC_TX_DONE_IN : in std_logic; + + MAC_RX_FIFO_ERR_IN : in std_logic; + MAC_RX_STATS_IN : in std_logic_vector(31 downto 0); + MAC_RX_DATA_IN : in std_logic_vector(7 downto 0); + MAC_RX_WRITE_IN : in std_logic; + MAC_RX_STAT_EN_IN : in std_logic; + MAC_RX_EOF_IN : in std_logic; + MAC_RX_ERROR_IN : in std_logic; + + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + -- SlowControl + MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + -- IP configuration + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- configuration of gbe core + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_MAX_FRAME_IN : in std_logic_vector(15 downto 0); + CFG_ALLOW_RX_IN : in std_logic; + CFG_SOFT_RESET_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + + MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0); + MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0); + MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0); + MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0); + + MAKE_RESET_OUT : out std_logic + ); +end entity gbe_logic_wrapper; + +architecture RTL of gbe_logic_wrapper is + + signal fr_q : std_logic_vector(8 downto 0); + signal fr_rd_en : std_logic; + signal fr_frame_valid : std_logic; + signal rc_rd_en : std_logic; + signal rc_q : std_logic_vector(8 downto 0); + signal rc_frames_rec_ctr : std_logic_vector(31 downto 0); + signal mc_data : std_logic_vector(8 downto 0); + signal mc_wr_en : std_logic; + signal fc_wr_en : std_logic; + signal fc_data : std_logic_vector(7 downto 0); + signal fc_ip_size : std_logic_vector(15 downto 0); + signal fc_udp_size : std_logic_vector(15 downto 0); + signal fc_ident : std_logic_vector(15 downto 0); + signal fc_flags_offset : std_logic_vector(15 downto 0); + signal fc_sod : std_logic; + signal fc_eod : std_logic; + signal fc_h_ready : std_logic; + signal fc_ready : std_logic; + signal rc_frame_ready : std_logic; + signal fr_frame_size : std_logic_vector(15 downto 0); + signal rc_frame_size : std_logic_vector(15 downto 0); + signal mc_frame_size : std_logic_vector(15 downto 0); + signal rc_bytes_rec : std_logic_vector(31 downto 0); + signal rc_debug : std_logic_vector(63 downto 0); + signal mc_transmit_ctrl : std_logic; + signal rc_loading_done : std_logic; + signal fr_get_frame : std_logic; + signal mc_transmit_done : std_logic; + + signal fr_frame_proto : std_logic_vector(15 downto 0); + signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + signal mc_type : std_logic_vector(15 downto 0); + signal fr_src_mac : std_logic_vector(47 downto 0); + signal fr_dest_mac : std_logic_vector(47 downto 0); + signal fr_src_ip : std_logic_vector(31 downto 0); + signal fr_dest_ip : std_logic_vector(31 downto 0); + signal fr_src_udp : std_logic_vector(15 downto 0); + signal fr_dest_udp : std_logic_vector(15 downto 0); + signal rc_src_mac : std_logic_vector(47 downto 0); + signal rc_dest_mac : std_logic_vector(47 downto 0); + signal rc_src_ip : std_logic_vector(31 downto 0); + signal rc_dest_ip : std_logic_vector(31 downto 0); + signal rc_src_udp : std_logic_vector(15 downto 0); + signal rc_dest_udp : std_logic_vector(15 downto 0); + + signal mc_dest_mac : std_logic_vector(47 downto 0); + signal mc_dest_ip : std_logic_vector(31 downto 0); + signal mc_dest_udp : std_logic_vector(15 downto 0); + signal mc_src_mac : std_logic_vector(47 downto 0); + signal mc_src_ip : std_logic_vector(31 downto 0); + signal mc_src_udp : std_logic_vector(15 downto 0); + + signal fc_dest_mac : std_logic_vector(47 downto 0); + signal fc_dest_ip : std_logic_vector(31 downto 0); + signal fc_dest_udp : std_logic_vector(15 downto 0); + signal fc_src_mac : std_logic_vector(47 downto 0); + signal fc_src_ip : std_logic_vector(31 downto 0); + signal fc_src_udp : std_logic_vector(15 downto 0); + signal fc_type : std_logic_vector(15 downto 0); + signal fc_ihl_version : std_logic_vector(7 downto 0); + signal fc_tos : std_logic_vector(7 downto 0); + signal fc_ttl : std_logic_vector(7 downto 0); + signal fc_protocol : std_logic_vector(7 downto 0); + + signal ft_data : std_logic_vector(8 downto 0); + signal ft_tx_empty : std_logic; + signal ft_start_of_packet : std_logic; + signal ft_bsm_init : std_logic_vector(3 downto 0); + signal ft_bsm_mac : std_logic_vector(3 downto 0); + signal ft_bsm_trans : std_logic_vector(3 downto 0); + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal fr_ip_proto : std_logic_vector(7 downto 0); + signal mc_ip_proto : std_logic_vector(7 downto 0); + signal mc_ident : std_logic_vector(15 downto 0); + + signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_rec_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_sent_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_drop_in : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_drop_out : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_gen : std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); + + signal global_reset, rst_n, ff : std_logic; + signal link_ok, dhcp_done : std_logic; + + signal dum_busy, dum_read, dum_dataready : std_logic; + signal dum_data : std_logic_vector(15 downto 0); + + signal monitor_tx_packets : std_logic_vector(31 downto 0); + signal monitor_rx_bytes, monitor_rx_frames, monitor_tx_bytes, monitor_tx_frames : std_logic_vector(31 downto 0); + + signal dbg_hist, dbg_hist2 : hist_array; + signal monitor_dropped : std_logic_vector(31 downto 0); + signal dbg_ft : std_logic_vector(63 downto 0); + signal dbg_q : std_logic_vector(15 downto 0); + signal make_reset : std_logic; + signal my_mac : std_logic_vector(47 downto 0); + +begin + + reset_sync : process(GSR_N, CLK_SYS_IN) + begin + if (GSR_N = '0') then + ff <= '0'; + rst_n <= '0'; + elsif rising_edge(CLK_SYS_IN) then + ff <= '1'; + rst_n <= ff; + end if; + end process reset_sync; + + global_reset <= not rst_n; + + fc_ihl_version <= x"45"; + fc_tos <= x"10"; + fc_ttl <= x"ff"; + + MY_MAC_OUT <= my_mac; + DHCP_DONE_OUT <= dhcp_done; + + + main_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate + MAIN_CONTROL : trb_net16_gbe_main_control + generic map( + RX_PATH_ENABLE => RX_PATH_ENABLE, + DO_SIMULATION => DO_SIMULATION, + + INCLUDE_READOUT => INCLUDE_READOUT, + INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, + INCLUDE_DHCP => INCLUDE_DHCP, + INCLUDE_ARP => INCLUDE_ARP, + INCLUDE_PING => INCLUDE_PING, + + READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, + SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE + ) + port map( + CLK => CLK_SYS_IN, + CLK_125 => CLK_125_IN, + RESET => RESET, + + MC_LINK_OK_OUT => link_ok, + MC_RESET_LINK_IN => global_reset, + MC_IDLE_TOO_LONG_OUT => open, + MC_DHCP_DONE_OUT => dhcp_done, + MC_MY_MAC_OUT => my_mac, + MC_MY_MAC_IN => MY_MAC_IN, + + -- signals to/from receive controller + RC_FRAME_WAITING_IN => rc_frame_ready, + RC_LOADING_DONE_OUT => rc_loading_done, + RC_DATA_IN => rc_q, + RC_RD_EN_OUT => rc_rd_en, + RC_FRAME_SIZE_IN => rc_frame_size, + RC_FRAME_PROTO_IN => rc_frame_proto, + + RC_SRC_MAC_ADDRESS_IN => rc_src_mac, + RC_DEST_MAC_ADDRESS_IN => rc_dest_mac, + RC_SRC_IP_ADDRESS_IN => rc_src_ip, + RC_DEST_IP_ADDRESS_IN => rc_dest_ip, + RC_SRC_UDP_PORT_IN => rc_src_udp, + RC_DEST_UDP_PORT_IN => rc_dest_udp, + + -- signals to/from transmit controller + TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl, + TC_DATA_OUT => mc_data, + TC_RD_EN_IN => mc_wr_en, + TC_FRAME_SIZE_OUT => mc_frame_size, + TC_FRAME_TYPE_OUT => mc_type, + TC_IP_PROTOCOL_OUT => mc_ip_proto, + TC_IDENT_OUT => mc_ident, + + TC_DEST_MAC_OUT => mc_dest_mac, + TC_DEST_IP_OUT => mc_dest_ip, + TC_DEST_UDP_OUT => mc_dest_udp, + TC_SRC_MAC_OUT => mc_src_mac, + TC_SRC_IP_OUT => mc_src_ip, + TC_SRC_UDP_OUT => mc_src_udp, + TC_TRANSMIT_DONE_IN => mc_transmit_done, + + -- signals to/from sgmii/gbe pcs_an_complete + PCS_AN_COMPLETE_IN => MAC_AN_READY_IN, + + -- signals to/from hub + MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, + GSC_CLK_IN => GSC_CLK_IN, + GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => GSC_INIT_READ_IN, + GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, + GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, + GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, + GSC_BUSY_IN => GSC_BUSY_IN, + + MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT, + + -- CTS interface + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + -- Data payload interface + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + -- ip configurator + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + + CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, + CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, + CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, + CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, + CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, + CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, + CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, + CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, + CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, + CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, + CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, + CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, + CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, + CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, + CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN, + + TSM_HADDR_OUT => open, --mac_haddr, + TSM_HDATA_OUT => open, --mac_hdataout, + TSM_HCS_N_OUT => open, --mac_hcs, + TSM_HWRITE_N_OUT => open, --mac_hwrite, + TSM_HREAD_N_OUT => open, --mac_hread, + TSM_HREADY_N_IN => '0', --mac_hready, + TSM_HDATA_EN_N_IN => '1', --mac_hdata_en, + TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec, + TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en, + + MAC_READY_CONF_IN => MAC_READY_CONF_IN, + MAC_RECONF_OUT => MAC_RECONF_OUT, + + MONITOR_SELECT_REC_OUT => dbg_select_rec, + MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes, + MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes, + MONITOR_SELECT_SENT_OUT => dbg_select_sent, + MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in, + MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out, + MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen, + + DATA_HIST_OUT => dbg_hist, + SCTRL_HIST_OUT => dbg_hist2 + ); + end generate main_gen; + + main_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate + MAIN_CONTROL : trb_net16_gbe_main_control + generic map( + RX_PATH_ENABLE => RX_PATH_ENABLE, + DO_SIMULATION => DO_SIMULATION, + + INCLUDE_READOUT => INCLUDE_READOUT, + INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, + INCLUDE_DHCP => INCLUDE_DHCP, + INCLUDE_ARP => INCLUDE_ARP, + INCLUDE_PING => INCLUDE_PING, + + READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, + SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE + ) + port map( + CLK => CLK_SYS_IN, + CLK_125 => CLK_125_IN, + RESET => RESET, + + MC_LINK_OK_OUT => link_ok, + MC_RESET_LINK_IN => global_reset, + MC_IDLE_TOO_LONG_OUT => open, + MC_DHCP_DONE_OUT => dhcp_done, + MC_MY_MAC_OUT => my_mac, + MC_MY_MAC_IN => MY_MAC_IN, + + -- signals to/from receive controller + RC_FRAME_WAITING_IN => rc_frame_ready, + RC_LOADING_DONE_OUT => rc_loading_done, + RC_DATA_IN => rc_q, + RC_RD_EN_OUT => rc_rd_en, + RC_FRAME_SIZE_IN => rc_frame_size, + RC_FRAME_PROTO_IN => rc_frame_proto, + + RC_SRC_MAC_ADDRESS_IN => rc_src_mac, + RC_DEST_MAC_ADDRESS_IN => rc_dest_mac, + RC_SRC_IP_ADDRESS_IN => rc_src_ip, + RC_DEST_IP_ADDRESS_IN => rc_dest_ip, + RC_SRC_UDP_PORT_IN => rc_src_udp, + RC_DEST_UDP_PORT_IN => rc_dest_udp, + + -- signals to/from transmit controller + TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl, + TC_DATA_OUT => mc_data, + TC_RD_EN_IN => mc_wr_en, + --TC_DATA_NOT_VALID_OUT => tc_data_not_valid, + TC_FRAME_SIZE_OUT => mc_frame_size, + TC_FRAME_TYPE_OUT => mc_type, + TC_IP_PROTOCOL_OUT => mc_ip_proto, + TC_IDENT_OUT => mc_ident, + + TC_DEST_MAC_OUT => mc_dest_mac, + TC_DEST_IP_OUT => mc_dest_ip, + TC_DEST_UDP_OUT => mc_dest_udp, + TC_SRC_MAC_OUT => mc_src_mac, + TC_SRC_IP_OUT => mc_src_ip, + TC_SRC_UDP_OUT => mc_src_udp, + TC_TRANSMIT_DONE_IN => mc_transmit_done, + + -- signals to/from sgmii/gbe pcs_an_complete + PCS_AN_COMPLETE_IN => MAC_AN_READY_IN, + + -- signals to/from hub + MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, + GSC_CLK_IN => GSC_CLK_IN, + GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => '1', + GSC_REPLY_DATAREADY_IN => dum_dataready, + GSC_REPLY_DATA_IN => dum_data, + GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => dum_read, + GSC_BUSY_IN => dum_busy, + + MAKE_RESET_OUT => make_reset, + + -- CTS interface + CTS_NUMBER_IN => gbe_cts_number, + CTS_CODE_IN => gbe_cts_code, + CTS_INFORMATION_IN => gbe_cts_information, + CTS_READOUT_TYPE_IN => gbe_cts_readout_type, + CTS_START_READOUT_IN => gbe_cts_start_readout, + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, + --Data payload interface + FEE_DATA_IN => gbe_fee_data, + FEE_DATAREADY_IN => gbe_fee_dataready, + FEE_READ_OUT => gbe_fee_read, + FEE_STATUS_BITS_IN => gbe_fee_status_bits, + FEE_BUSY_IN => gbe_fee_busy, + -- ip configurator + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + + CFG_GBE_ENABLE_IN => '1', + CFG_IPU_ENABLE_IN => '0', + CFG_MULT_ENABLE_IN => '0', + CFG_SUBEVENT_ID_IN => x"0000_00cf", + CFG_SUBEVENT_DEC_IN => x"0002_0001", + CFG_QUEUE_DEC_IN => x"0003_0062", + CFG_READOUT_CTR_IN => x"00_0000", + CFG_READOUT_CTR_VALID_IN => '0', + CFG_INSERT_TTYPE_IN => '0', + CFG_MAX_SUB_IN => x"e998", -- 59800 + CFG_MAX_QUEUE_IN => x"ea60", -- 60000 + CFG_MAX_SUBS_IN_QUEUE_IN => x"00c8", -- 200 + CFG_MAX_SINGLE_SUB_IN => x"e998", --x"7d00", -- 32000 + + CFG_ADDITIONAL_HDR_IN => '0', + CFG_MAX_REPLY_SIZE_IN => x"0000_fa00", + + -- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT => open, --mac_haddr, + TSM_HDATA_OUT => open, --mac_hdataout, + TSM_HCS_N_OUT => open, --mac_hcs, + TSM_HWRITE_N_OUT => open, --mac_hwrite, + TSM_HREAD_N_OUT => open, --mac_hread, + TSM_HREADY_N_IN => '0', --mac_hready, + TSM_HDATA_EN_N_IN => '1', --mac_hdata_en, + TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec, + TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en, + + MAC_READY_CONF_IN => MAC_READY_CONF_IN, + MAC_RECONF_OUT => MAC_RECONF_OUT, + + MONITOR_SELECT_REC_OUT => dbg_select_rec, + MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes, + MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes, + MONITOR_SELECT_SENT_OUT => dbg_select_sent, + MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in, + MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out, + MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen, + + DATA_HIST_OUT => dbg_hist, + SCTRL_HIST_OUT => dbg_hist2 + ); + + dummy : gbe_ipu_dummy + generic map( + DO_SIMULATION => DO_SIMULATION, + FIXED_SIZE_MODE => FIXED_SIZE_MODE, + INCREMENTAL_MODE => INCREMENTAL_MODE, + FIXED_SIZE => FIXED_SIZE, + UP_DOWN_MODE => UP_DOWN_MODE, + UP_DOWN_LIMIT => UP_DOWN_LIMIT, + FIXED_DELAY_MODE => FIXED_DELAY_MODE, + FIXED_DELAY => FIXED_DELAY + ) + port map( + clk => CLK_SYS_IN, + rst => RESET, + GBE_READY_IN => dhcp_done, + + CFG_EVENT_SIZE_IN => (others => '0'), + CFG_TRIGGERED_MODE_IN => '0', + TRIGGER_IN => '0', + + CTS_NUMBER_OUT => gbe_cts_number, + CTS_CODE_OUT => gbe_cts_code, + CTS_INFORMATION_OUT => gbe_cts_information, + CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, + CTS_START_READOUT_OUT => gbe_cts_start_readout, + CTS_DATA_IN => (others => '0'), + CTS_DATAREADY_IN => '0', + CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, + CTS_READ_OUT => open, + CTS_LENGTH_IN => (others => '0'), + CTS_ERROR_PATTERN_IN => gbe_cts_status_bits, + -- Data payload interfac => + FEE_DATA_OUT => gbe_fee_data, + FEE_DATAREADY_OUT => gbe_fee_dataready, + FEE_READ_IN => gbe_fee_read, + FEE_STATUS_BITS_OUT => gbe_fee_status_bits, + FEE_BUSY_OUT => gbe_fee_busy + ); + end generate main_with_dummy_gen; + + MAKE_RESET_OUT <= make_reset; -- or idle_too_long; + + transmit_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate + + TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2 + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, --RESET, + + -- signal to/from main controller + TC_DATAREADY_IN => mc_transmit_ctrl, + TC_RD_EN_OUT => mc_wr_en, + TC_DATA_IN => mc_data(7 downto 0), + TC_FRAME_SIZE_IN => mc_frame_size, + TC_FRAME_TYPE_IN => mc_type, + TC_IP_PROTOCOL_IN => mc_ip_proto, + TC_DEST_MAC_IN => mc_dest_mac, + TC_DEST_IP_IN => mc_dest_ip, + TC_DEST_UDP_IN => mc_dest_udp, + TC_SRC_MAC_IN => mc_src_mac, + TC_SRC_IP_IN => mc_src_ip, + TC_SRC_UDP_IN => mc_src_udp, + TC_TRANSMISSION_DONE_OUT => mc_transmit_done, + TC_IDENT_IN => mc_ident, + TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN, + + -- signal to/from frame constructor + FC_DATA_OUT => fc_data, + FC_WR_EN_OUT => fc_wr_en, + FC_READY_IN => fc_ready, + FC_H_READY_IN => fc_h_ready, + FC_FRAME_TYPE_OUT => fc_type, + FC_IP_SIZE_OUT => fc_ip_size, + FC_UDP_SIZE_OUT => fc_udp_size, + FC_IDENT_OUT => fc_ident, + FC_FLAGS_OFFSET_OUT => fc_flags_offset, + FC_SOD_OUT => fc_sod, + FC_EOD_OUT => fc_eod, + FC_IP_PROTOCOL_OUT => fc_protocol, + + DEST_MAC_ADDRESS_OUT => fc_dest_mac, + DEST_IP_ADDRESS_OUT => fc_dest_ip, + DEST_UDP_PORT_OUT => fc_dest_udp, + SRC_MAC_ADDRESS_OUT => fc_src_mac, + SRC_IP_ADDRESS_OUT => fc_src_ip, + SRC_UDP_PORT_OUT => fc_src_udp, + + MONITOR_TX_PACKETS_OUT => monitor_tx_packets + ); + end generate transmit_gen; + + transmit_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate + TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2 + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, --RESET, + + -- signal to/from main controller + TC_DATAREADY_IN => mc_transmit_ctrl, + TC_RD_EN_OUT => mc_wr_en, + TC_DATA_IN => mc_data(7 downto 0), + TC_FRAME_SIZE_IN => mc_frame_size, + TC_FRAME_TYPE_IN => mc_type, + TC_IP_PROTOCOL_IN => mc_ip_proto, + TC_DEST_MAC_IN => mc_dest_mac, + TC_DEST_IP_IN => mc_dest_ip, + TC_DEST_UDP_IN => mc_dest_udp, + TC_SRC_MAC_IN => mc_src_mac, + TC_SRC_IP_IN => mc_src_ip, + TC_SRC_UDP_IN => mc_src_udp, + TC_TRANSMISSION_DONE_OUT => mc_transmit_done, + TC_IDENT_IN => mc_ident, + TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN, + + -- signal to/from frame constructor + FC_DATA_OUT => fc_data, + FC_WR_EN_OUT => fc_wr_en, + FC_READY_IN => fc_ready, + FC_H_READY_IN => fc_h_ready, + FC_FRAME_TYPE_OUT => fc_type, + FC_IP_SIZE_OUT => fc_ip_size, + FC_UDP_SIZE_OUT => fc_udp_size, + FC_IDENT_OUT => fc_ident, + FC_FLAGS_OFFSET_OUT => fc_flags_offset, + FC_SOD_OUT => fc_sod, + FC_EOD_OUT => fc_eod, + FC_IP_PROTOCOL_OUT => fc_protocol, + + DEST_MAC_ADDRESS_OUT => fc_dest_mac, + DEST_IP_ADDRESS_OUT => fc_dest_ip, + DEST_UDP_PORT_OUT => fc_dest_udp, + SRC_MAC_ADDRESS_OUT => fc_src_mac, + SRC_IP_ADDRESS_OUT => fc_src_ip, + SRC_UDP_PORT_OUT => fc_src_udp, + + MONITOR_TX_PACKETS_OUT => monitor_tx_packets + ); + end generate transmit_with_dummy_gen; + + FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr + generic map ( + FRAME_BUFFER_SIZE => FRAME_BUFFER_SIZE + ) + port map( + -- ports for user logic + RESET => global_reset, + CLK => CLK_SYS_IN, + LINK_OK_IN => '1', + -- + WR_EN_IN => fc_wr_en, + DATA_IN => fc_data, + START_OF_DATA_IN => fc_sod, + END_OF_DATA_IN => fc_eod, + IP_F_SIZE_IN => fc_ip_size, + UDP_P_SIZE_IN => fc_udp_size, + HEADERS_READY_OUT => fc_h_ready, + READY_OUT => fc_ready, + DEST_MAC_ADDRESS_IN => fc_dest_mac, + DEST_IP_ADDRESS_IN => fc_dest_ip, + DEST_UDP_PORT_IN => fc_dest_udp, + SRC_MAC_ADDRESS_IN => fc_src_mac, + SRC_IP_ADDRESS_IN => fc_src_ip, + SRC_UDP_PORT_IN => fc_src_udp, + FRAME_TYPE_IN => fc_type, + IHL_VERSION_IN => fc_ihl_version, + TOS_IN => fc_tos, + IDENTIFICATION_IN => fc_ident, + FLAGS_OFFSET_IN => fc_flags_offset, + TTL_IN => fc_ttl, + PROTOCOL_IN => fc_protocol, + FRAME_DELAY_IN => (others => '0'), + + RD_CLK => CLK_125_IN, + FT_DATA_OUT => ft_data, + FT_TX_EMPTY_OUT => ft_tx_empty, + FT_TX_RD_EN_IN => MAC_TX_READ_IN, + FT_START_OF_PACKET_OUT => ft_start_of_packet, + FT_TX_DONE_IN => MAC_TX_DONE_IN, + FT_TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN, + + MONITOR_TX_BYTES_OUT => monitor_tx_bytes, + MONITOR_TX_FRAMES_OUT => monitor_tx_frames + ); + + MAC_TX_DATA_OUT <= ft_data(7 downto 0); + + dbg_q(15 downto 9) <= (others => '0'); + + FRAME_TRANSMITTER: trb_net16_gbe_frame_trans + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, + LINK_OK_IN => link_ok, + TX_MAC_CLK => CLK_125_IN, + TX_EMPTY_IN => ft_tx_empty, + START_OF_PACKET_IN => ft_start_of_packet, + DATA_ENDFLAG_IN => ft_data(8), + + TX_FIFOAVAIL_OUT => MAC_FIFOAVAIL_OUT, + TX_FIFOEOF_OUT => MAC_FIFOEOF_OUT, + TX_FIFOEMPTY_OUT => MAC_FIFOEMPTY_OUT, + TX_DONE_IN => MAC_TX_DONE_IN, + TX_STAT_EN_IN => MAC_TX_STAT_EN_IN, + TX_STATVEC_IN => MAC_TX_STATS_IN, + TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN, + -- Debug + BSM_INIT_OUT => ft_bsm_init, + BSM_MAC_OUT => ft_bsm_mac, + BSM_TRANS_OUT => ft_bsm_trans, + DBG_RD_DONE_OUT => open, + DBG_INIT_DONE_OUT => open, + DBG_ENABLED_OUT => open, + DEBUG_OUT => dbg_ft + ); + + rx_enable_gen : if (RX_PATH_ENABLE = 1) generate + + RECEIVE_CONTROLLER : trb_net16_gbe_receive_control + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, + + -- signals to/from frame_receiver + RC_DATA_IN => fr_q, + FR_RD_EN_OUT => fr_rd_en, + FR_FRAME_VALID_IN => fr_frame_valid, + FR_GET_FRAME_OUT => fr_get_frame, + FR_FRAME_SIZE_IN => fr_frame_size, + FR_FRAME_PROTO_IN => fr_frame_proto, + FR_IP_PROTOCOL_IN => fr_ip_proto, + + FR_SRC_MAC_ADDRESS_IN => fr_src_mac, + FR_DEST_MAC_ADDRESS_IN => fr_dest_mac, + FR_SRC_IP_ADDRESS_IN => fr_src_ip, + FR_DEST_IP_ADDRESS_IN => fr_dest_ip, + FR_SRC_UDP_PORT_IN => fr_src_udp, + FR_DEST_UDP_PORT_IN => fr_dest_udp, + + -- signals to/from main controller + RC_RD_EN_IN => rc_rd_en, + RC_Q_OUT => rc_q, + RC_FRAME_WAITING_OUT => rc_frame_ready, + RC_LOADING_DONE_IN => rc_loading_done, + RC_FRAME_SIZE_OUT => rc_frame_size, + RC_FRAME_PROTO_OUT => rc_frame_proto, + + RC_SRC_MAC_ADDRESS_OUT => rc_src_mac, + RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac, + RC_SRC_IP_ADDRESS_OUT => rc_src_ip, + RC_DEST_IP_ADDRESS_OUT => rc_dest_ip, + RC_SRC_UDP_PORT_OUT => rc_src_udp, + RC_DEST_UDP_PORT_OUT => rc_dest_udp, + + -- statistics + FRAMES_RECEIVED_OUT => rc_frames_rec_ctr, + BYTES_RECEIVED_OUT => rc_bytes_rec, + + DEBUG_OUT => rc_debug + ); + + FRAME_RECEIVER : trb_net16_gbe_frame_receiver + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, + LINK_OK_IN => link_ok, + ALLOW_RX_IN => CFG_ALLOW_RX_IN, + RX_MAC_CLK => CLK_RX_125_IN, + MY_MAC_IN => MY_MAC_IN, + + -- input signals from TS_MAC + MAC_RX_EOF_IN => MAC_RX_EOF_IN, + MAC_RX_ER_IN => MAC_RX_ERROR_IN, + MAC_RXD_IN => MAC_RX_DATA_IN, + MAC_RX_EN_IN => MAC_RX_WRITE_IN, + MAC_RX_FIFO_ERR_IN => MAC_RX_FIFO_ERR_IN, + MAC_RX_FIFO_FULL_OUT => MAC_RX_FIFOFULL_OUT, + MAC_RX_STAT_EN_IN => MAC_RX_STAT_EN_IN, + MAC_RX_STAT_VEC_IN => MAC_RX_STATS_IN, + -- output signal to control logic + FR_Q_OUT => fr_q, + FR_RD_EN_IN => fr_rd_en, + FR_FRAME_VALID_OUT => fr_frame_valid, + FR_GET_FRAME_IN => fr_get_frame, + FR_FRAME_SIZE_OUT => fr_frame_size, + FR_FRAME_PROTO_OUT => fr_frame_proto, + FR_IP_PROTOCOL_OUT => fr_ip_proto, + FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types, + FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip, + FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp, + FR_VLAN_ID_IN => (others => '0'), --vlan_id, + + FR_SRC_MAC_ADDRESS_OUT => fr_src_mac, + FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac, + FR_SRC_IP_ADDRESS_OUT => fr_src_ip, + FR_DEST_IP_ADDRESS_OUT => fr_dest_ip, + FR_SRC_UDP_PORT_OUT => fr_src_udp, + FR_DEST_UDP_PORT_OUT => fr_dest_udp, + + MONITOR_RX_BYTES_OUT => monitor_rx_bytes, + MONITOR_RX_FRAMES_OUT => monitor_rx_frames, + MONITOR_DROPPED_OUT => monitor_dropped + ); + + end generate rx_enable_gen; + + rx_disable_gen : if (RX_PATH_ENABLE = 0) generate + + rc_q <= (others => '0'); + rc_frame_ready <= '0'; + rc_frame_size <= (others => '0'); + rc_frame_proto <= (others => '0'); + + rc_src_mac <= (others => '0'); + rc_dest_mac <= (others => '0'); + rc_src_ip <= (others => '0'); + rc_dest_ip <= (others => '0'); + rc_src_udp <= (others => '0'); + rc_dest_udp <= (others => '0'); + + rc_frames_rec_ctr <= (others => '0'); + rc_bytes_rec <= (others => '0'); + rc_debug <= (others => '0'); + + monitor_rx_bytes <= (others => '0'); + monitor_rx_frames <= (others => '0'); + monitor_dropped <= (others => '0'); + + end generate rx_disable_gen; + + + MONITOR_RX_FRAMES_OUT <= monitor_rx_frames; + MONITOR_RX_BYTES_OUT <= monitor_rx_bytes; + MONITOR_TX_FRAMES_OUT <= monitor_tx_frames; + MONITOR_TX_BYTES_OUT <= monitor_tx_bytes; + MONITOR_TX_PACKETS_OUT <= monitor_tx_packets; + MONITOR_DROPPED_OUT <= monitor_dropped; + + +-- MONITOR_RX_BYTES_OUT <= monitor_rx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_rx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_rx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_rx_bytes(1 * 32 - 1 downto 0 * 32); +-- MONITOR_RX_FRAMES_OUT <= monitor_rx_frames(4 * 32 - 1 downto 3 * 32) + monitor_rx_frames(3 * 32 - 1 downto 2 * 32) + monitor_rx_frames(2 * 32 - 1 downto 1 * 32) + monitor_rx_frames(1 * 32 - 1 downto 0 * 32); +-- MONITOR_TX_BYTES_OUT <= monitor_tx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_tx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_tx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_tx_bytes(1 * 32 - 1 downto 0 * 32); +-- MONITOR_TX_FRAMES_OUT <= monitor_tx_frames(4 * 32 - 1 downto 3 * 32) + monitor_tx_frames(3 * 32 - 1 downto 2 * 32) + monitor_tx_frames(2 * 32 - 1 downto 1 * 32) + monitor_tx_frames(1 * 32 - 1 downto 0 * 32); +-- MONITOR_TX_PACKETS_OUT <= monitor_tx_packets(4 * 32 - 1 downto 3 * 32) + monitor_tx_packets(3 * 32 - 1 downto 2 * 32) + monitor_tx_packets(2 * 32 - 1 downto 1 * 32) + monitor_tx_packets(1 * 32 - 1 downto 0 * 32); +-- MONITOR_DROPPED_OUT <= (others => '0'); + + +end architecture RTL; diff --git a/gbe_trb/base/gbe_med_interface.vhd b/gbe_trb/base/gbe_med_interface.vhd new file mode 100644 index 0000000..82f5fe2 --- /dev/null +++ b/gbe_trb/base/gbe_med_interface.vhd @@ -0,0 +1,705 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +use work.trb_net_gbe_components.all; + +entity gbe_med_interface is + generic ( + DO_SIMULATION : integer range 0 to 1; + NUMBER_OF_GBE_LINKS : integer range 1 to 4; + LINKS_ACTIVE : std_logic_vector(3 downto 0) + ); + port ( + RESET : in std_logic; + GSR_N : in std_logic; + CLK_SYS_IN : in std_logic; + CLK_125_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + CLK_125_IN : in std_logic; + CLK_125_RX_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC status and config + MAC_READY_CONF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RECONF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_AN_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC data interface + MAC_FIFOAVAIL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEOF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEMPTY_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_FIFOFULL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_TX_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_TX_READ_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_DISCRFRM_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0); + MAC_TX_DONE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_RX_FIFO_ERR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0); + MAC_RX_DATA_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_RX_WRITE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_EOF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_ERROR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_RXD_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_P_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_N_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable + + DEBUG_OUT : out std_logic_vector(255 downto 0) + ); +end entity gbe_med_interface; + +architecture RTL of gbe_med_interface is + + component sgmii_gbe_pcs35 +port( rst_n : in std_logic; + signal_detect : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + + rx_compensation_err : out std_logic; + + ctc_drop_flag : out std_logic; + ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + + tx_clk_125 : in std_logic; + tx_clock_enable_source : out std_logic; + tx_clock_enable_sink : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_clk_125 : in std_logic; + rx_clock_enable_source : out std_logic; + rx_clock_enable_sink : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + tx_data : out std_logic_vector(7 downto 0); + tx_kcntl : out std_logic; + tx_disparity_cntl : out std_logic; + + xmit_autoneg : out std_logic; + + serdes_recovered_clk : in std_logic; + rx_data : in std_logic_vector(7 downto 0); + rx_even : in std_logic; + rx_kcntl : in std_logic; + rx_disp_err : in std_logic; + rx_cv_err : in std_logic; + rx_err_decode_mode : in std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0) + ); +end component; + +component reset_controller_pcs port ( + rst_n : in std_logic; + clk : in std_logic; + tx_plol : in std_logic; + rx_cdr_lol : in std_logic; + quad_rst_out : out std_logic; + tx_pcs_rst_out : out std_logic; + rx_pcs_rst_out : out std_logic + ); +end component; +component reset_controller_cdr port ( + rst_n : in std_logic; + clk : in std_logic; + cdr_lol : in std_logic; + cdr_rst_out : out std_logic + ); +end component; + +component rate_resolution port ( + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + an_enable : in std_logic; + advertised_rate : in std_logic_vector(1 downto 0); + link_partner_rate : in std_logic_vector(1 downto 0); + non_an_rate : in std_logic_vector(1 downto 0); + operational_rate : out std_logic_vector(1 downto 0) + ); +end component; + +component register_interface_hb port ( + rst_n : in std_logic; + hclk : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + hcs_n : in std_logic; + hwrite_n : in std_logic; + haddr : in std_logic_vector(3 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hdataout : out std_logic_vector(7 downto 0); + hready_n : out std_logic; + mr_an_complete : in std_logic; + mr_page_rx : in std_logic; + mr_lp_adv_ability : in std_logic_vector(15 downto 0); + mr_main_reset : out std_logic; + mr_an_enable : out std_logic; + mr_restart_an : out std_logic; + mr_adv_ability : out std_logic_vector(15 downto 0) + ); +end component; + +component tsmac35 --tsmac36 --tsmac35 +port( + --------------- clock and reset port declarations ------------------ + hclk : in std_logic; + txmac_clk : in std_logic; + rxmac_clk : in std_logic; + reset_n : in std_logic; + txmac_clk_en : in std_logic; + rxmac_clk_en : in std_logic; + ------------------- Input signals to the GMII ---------------- + rxd : in std_logic_vector(7 downto 0); + rx_dv : in std_logic; + rx_er : in std_logic; + col : in std_logic; + crs : in std_logic; + -------------------- Input signals to the CPU I/F ------------------- + haddr : in std_logic_vector(7 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hcs_n : in std_logic; + hwrite_n : in std_logic; + hread_n : in std_logic; + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata : in std_logic_vector(7 downto 0); + tx_fifoavail : in std_logic; + tx_fifoeof : in std_logic; + tx_fifoempty : in std_logic; + tx_sndpaustim : in std_logic_vector(15 downto 0); + tx_sndpausreq : in std_logic; + tx_fifoctrl : in std_logic; + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full : in std_logic; + ignore_pkt : in std_logic; + -------------------- Output signals from the GMII ----------------------- + txd : out std_logic_vector(7 downto 0); + tx_en : out std_logic; + tx_er : out std_logic; + -------------------- Output signals from the CPU I/F ------------------- + hdataout : out std_logic_vector(7 downto 0); + hdataout_en_n : out std_logic; + hready_n : out std_logic; + cpu_if_gbit_en : out std_logic; + ---------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread : out std_logic; + tx_discfrm : out std_logic; + tx_staten : out std_logic; + tx_done : out std_logic; + tx_statvec : out std_logic_vector(30 downto 0); + ---------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error : out std_logic; + rx_stat_vector : out std_logic_vector(31 downto 0); + rx_dbout : out std_logic_vector(7 downto 0); + rx_write : out std_logic; + rx_stat_en : out std_logic; + rx_eof : out std_logic; + rx_error : out std_logic +); +end component; + + signal sd_rx_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_kcntl_q, sd_tx_kcntl : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_data_q, sd_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal xmit : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_correct_disp_q, sd_tx_correct_disp : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_data, sd_rx_data_q : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal sd_rx_kcntl, sd_rx_kcntl_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_disp_error, sd_rx_disp_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_cv_error, sd_rx_cv_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_power, rx_power : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal los, signal_detected : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal rx_cdr_lol: std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_pll_lol, quad_rst : std_logic; + signal tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + --signal rst_n : std_logic; + signal rx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal operational_rate : std_logic_vector(NUMBER_OF_GBE_LINKS * 2 - 1 downto 0); + signal an_complete : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_page_rx : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_lp_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0); + signal mr_main_reset : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_restart_an : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0); + signal mr_an_enable : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_rxd, pcs_rxd_q, pcs_rxd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal pcs_rx_en, pcs_rx_en_q, pcs_rx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_rx_er, pcs_rx_er_q, pcs_rx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_col, pcs_crs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_txd, pcs_txd_q, pcs_txd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal pcs_tx_en, pcs_tx_en_q, pcs_tx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_tx_er, pcs_tx_er_q, pcs_tx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hdataout_en_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hready_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hread_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hwrite_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hcs_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hdata : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal tsm_haddr : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + + signal synced_rst, ff : std_logic; + +begin + + rx_power <= "1111"; + tx_power <= "1111"; + + --rst_n <= not RESET; + + reset_sync : process(GSR_N, CLK_SYS_IN) + begin + if (GSR_N = '0') then + ff <= '0'; + synced_rst <= '0'; + elsif rising_edge(CLK_SYS_IN) then + ff <= '1'; + synced_rst <= ff; + end if; + end process reset_sync; + + SD_TXDIS_OUT <= "0000"; + + CLK_125_OUT <= CLK_125_IN & CLK_125_IN & CLK_125_IN & CLK_125_IN; + CLK_125_RX_OUT <= sd_rx_clk; + + impl_gen : if DO_SIMULATION = 0 generate + + gbe_serdes : entity work.serdes_gbe_4ch + port map( + ------------------ + -- CH0 -- + hdinp_ch0 => SD_RXD_P_IN(0), + hdinn_ch0 => SD_RXD_N_IN(0), + hdoutp_ch0 => SD_TXD_P_OUT(0), + hdoutn_ch0 => SD_TXD_N_OUT(0), + rxiclk_ch0 => sd_rx_clk(0), + txiclk_ch0 => CLK_125_IN, + rx_full_clk_ch0 => sd_rx_clk(0), + rx_half_clk_ch0 => open, + tx_full_clk_ch0 => open, + tx_half_clk_ch0 => open, + fpga_rxrefclk_ch0 => CLK_125_IN, + txdata_ch0 => sd_tx_data_q(7 downto 0), + tx_k_ch0 => sd_tx_kcntl_q(0), + xmit_ch0 => xmit(0), + tx_disp_correct_ch0 => sd_tx_correct_disp_q(0), + rxdata_ch0 => sd_rx_data(7 downto 0), + rx_k_ch0 => sd_rx_kcntl(0), + rx_disp_err_ch0 => sd_rx_disp_error(0), + rx_cv_err_ch0 => sd_rx_cv_error(0), + rx_serdes_rst_ch0_c => rx_serdes_rst(0), + sb_felb_ch0_c => '0', + sb_felb_rst_ch0_c => '0', + tx_pwrup_ch0_c => tx_power(0), + rx_pwrup_ch0_c => rx_power(0), + rx_los_low_ch0_s => los(0), + lsm_status_ch0_s => signal_detected(0), + rx_cdr_lol_ch0_s => rx_cdr_lol(0), + tx_pcs_rst_ch0_c => tx_pcs_rst(0), + rx_pcs_rst_ch0_c => rx_pcs_rst(0), + -- CH1 -- + hdinp_ch1 => SD_RXD_P_IN(1), + hdinn_ch1 => SD_RXD_N_IN(1), + hdoutp_ch1 => SD_TXD_P_OUT(1), + hdoutn_ch1 => SD_TXD_N_OUT(1), + rxiclk_ch1 => sd_rx_clk(1), + txiclk_ch1 => CLK_125_IN, + rx_full_clk_ch1 => sd_rx_clk(1), + rx_half_clk_ch1 => open, + tx_full_clk_ch1 => open, + tx_half_clk_ch1 => open, + fpga_rxrefclk_ch1 => CLK_125_IN, + txdata_ch1 => sd_tx_data_q(15 downto 8), + tx_k_ch1 => sd_tx_kcntl_q(1), + xmit_ch1 => xmit(1), + tx_disp_correct_ch1 => sd_tx_correct_disp_q(1), + rxdata_ch1 => sd_rx_data(15 downto 8), + rx_k_ch1 => sd_rx_kcntl(1), + rx_disp_err_ch1 => sd_rx_disp_error(1), + rx_cv_err_ch1 => sd_rx_cv_error(1), + rx_serdes_rst_ch1_c => rx_serdes_rst(1), + sb_felb_ch1_c => '0', + sb_felb_rst_ch1_c => '0', + tx_pwrup_ch1_c => tx_power(1), + rx_pwrup_ch1_c => rx_power(1), + rx_los_low_ch1_s => los(1), + lsm_status_ch1_s => signal_detected(1), + rx_cdr_lol_ch1_s => rx_cdr_lol(1), + tx_pcs_rst_ch1_c => tx_pcs_rst(1), + rx_pcs_rst_ch1_c => rx_pcs_rst(1), + -- CH2 -- + hdinp_ch2 => SD_RXD_P_IN(2), + hdinn_ch2 => SD_RXD_N_IN(2), + hdoutp_ch2 => SD_TXD_P_OUT(2), + hdoutn_ch2 => SD_TXD_N_OUT(2), + rxiclk_ch2 => sd_rx_clk(2), + txiclk_ch2 => CLK_125_IN, + rx_full_clk_ch2 => sd_rx_clk(2), + rx_half_clk_ch2 => open, + tx_full_clk_ch2 => open, + tx_half_clk_ch2 => open, + fpga_rxrefclk_ch2 => CLK_125_IN, + txdata_ch2 => sd_tx_data_q(23 downto 16), + tx_k_ch2 => sd_tx_kcntl_q(2), + xmit_ch2 => xmit(2), + tx_disp_correct_ch2 => sd_tx_correct_disp_q(2), + rxdata_ch2 => sd_rx_data(23 downto 16), + rx_k_ch2 => sd_rx_kcntl(2), + rx_disp_err_ch2 => sd_rx_disp_error(2), + rx_cv_err_ch2 => sd_rx_cv_error(2), + rx_serdes_rst_ch2_c => rx_serdes_rst(2), + sb_felb_ch2_c => '0', + sb_felb_rst_ch2_c => '0', + tx_pwrup_ch2_c => tx_power(2), + rx_pwrup_ch2_c => rx_power(2), + rx_los_low_ch2_s => los(2), + lsm_status_ch2_s => signal_detected(2), + rx_cdr_lol_ch2_s => rx_cdr_lol(2), + tx_pcs_rst_ch2_c => tx_pcs_rst(2), + rx_pcs_rst_ch2_c => rx_pcs_rst(2), + -- CH3 -- + hdinp_ch3 => SD_RXD_P_IN(3), + hdinn_ch3 => SD_RXD_N_IN(3), + hdoutp_ch3 => SD_TXD_P_OUT(3), + hdoutn_ch3 => SD_TXD_N_OUT(3), + rxiclk_ch3 => sd_rx_clk(3), + txiclk_ch3 => CLK_125_IN, + rx_full_clk_ch3 => sd_rx_clk(3), + rx_half_clk_ch3 => open, + tx_full_clk_ch3 => open, + tx_half_clk_ch3 => open, + fpga_rxrefclk_ch3 => CLK_125_IN, + txdata_ch3 => sd_tx_data_q(31 downto 24), + tx_k_ch3 => sd_tx_kcntl_q(3), + xmit_ch3 => xmit(3), + tx_disp_correct_ch3 => sd_tx_correct_disp_q(3), + rxdata_ch3 => sd_rx_data(31 downto 24), + rx_k_ch3 => sd_rx_kcntl(3), + rx_disp_err_ch3 => sd_rx_disp_error(3), + rx_cv_err_ch3 => sd_rx_cv_error(3), + rx_serdes_rst_ch3_c => rx_serdes_rst(3), + sb_felb_ch3_c => '0', + sb_felb_rst_ch3_c => '0', + tx_pwrup_ch3_c => tx_power(3), + rx_pwrup_ch3_c => rx_power(3), + rx_los_low_ch3_s => los(3), + lsm_status_ch3_s => signal_detected(3), + rx_cdr_lol_ch3_s => rx_cdr_lol(3), + tx_pcs_rst_ch3_c => tx_pcs_rst(3), + rx_pcs_rst_ch3_c => rx_pcs_rst(3), + ---- Miscillaneous ports + fpga_txrefclk => CLK_125_IN, + tx_serdes_rst_c => '0', + tx_pll_lol_qd_s => tx_pll_lol, + tx_sync_qd_c => '0', + rst_qd_c => quad_rst, + serdes_rst_qd_c => '0' + ); + + SYNC_TX_PROC : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + sd_tx_data_q <= sd_tx_data; + sd_tx_kcntl_q <= sd_tx_kcntl; + sd_tx_correct_disp_q <= sd_tx_correct_disp; + end if; + end process SYNC_TX_PROC; + + + pcs_gen : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate + + SYNC_RX_PROC : process(sd_rx_clk) + begin + if rising_edge(sd_rx_clk(i)) then + sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8) <= sd_rx_data( (i + 1) * 8 - 1 downto i * 8); + sd_rx_kcntl_q(i) <= sd_rx_kcntl(i); + sd_rx_disp_error_q(i) <= sd_rx_disp_error(i); + sd_rx_cv_error_q(i) <= sd_rx_cv_error(i); + end if; + end process SYNC_RX_PROC; + + SGMII_GBE_PCS : sgmii_gbe_pcs35 + port map( + rst_n => synced_rst, --rst_n, + signal_detect => signal_detected(i), + gbe_mode => '1', + sgmii_mode => '0', + operational_rate => operational_rate( (i + 1) * 2 - 1 downto (i * 2)), + debug_link_timer_short => '0', + + force_isolate => '0', + force_loopback => '0', + force_unidir => '0', + + rx_compensation_err => open, + + ctc_drop_flag => open, + ctc_add_flag => open, + an_link_ok => open, + + -- MAC interface + tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes + tx_clock_enable_source => tx_clk_en(i), + tx_clock_enable_sink => tx_clk_en(i), + tx_d => pcs_txd( (i + 1) * 8 - 1 downto i * 8), -- TX data from MAC + tx_en => pcs_tx_en(i), -- TX data enable from MAC + tx_er => pcs_tx_er(i), -- TX error from MAC + rx_clk_125 => sd_rx_clk(i), + rx_clock_enable_source => rx_clk_en(i), + rx_clock_enable_sink => rx_clk_en(i), + rx_d => pcs_rxd( (i + 1) * 8 - 1 downto i * 8), -- RX data to MAC + rx_dv => pcs_rx_en(i), -- RX data enable to MAC + rx_er => pcs_rx_er(i), -- RX error to MAC + col => pcs_col(i), + crs => pcs_crs(i), + + -- SerDes interface + tx_data => sd_tx_data( (i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes + tx_kcntl => sd_tx_kcntl(i), -- TX komma control to SerDes + tx_disparity_cntl => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes) + + xmit_autoneg => xmit(i), + + serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream + rx_data => sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes + rx_kcntl => sd_rx_kcntl_q(i), -- RX komma control from SerDes + rx_err_decode_mode => '0', -- receive error control mode fixed to normal + rx_even => '0', -- unused (receive error control mode = normal, tie to GND) + rx_disp_err => sd_rx_disp_error_q(i), -- RX disparity error from SerDes + rx_cv_err => sd_rx_cv_error_q(i), -- RX code violation error from SerDes + -- Autonegotiation stuff + mr_an_complete => an_complete(i), + mr_page_rx => mr_page_rx(i), + mr_lp_adv_ability => mr_lp_adv_ability( (i + 1) * 16 - 1 downto i * 16), + mr_main_reset => mr_main_reset(i), + mr_an_enable => '1', + mr_restart_an => mr_restart_an(i), + mr_adv_ability => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16) + ); + + MAC_AN_READY_OUT(i) <= an_complete(i); + + u0_reset_controller_pcs : reset_controller_pcs port map( + rst_n => synced_rst, --rst_n, + clk => CLK_125_IN, + tx_plol => tx_pll_lol, + rx_cdr_lol => rx_cdr_lol(i), + quad_rst_out => open, --quad_rst, + tx_pcs_rst_out => tx_pcs_rst(i), + rx_pcs_rst_out => rx_pcs_rst(i) + ); + + u0_reset_controller_cdr : reset_controller_cdr port map( + rst_n => synced_rst, --rst_n, + clk => CLK_125_IN, + cdr_lol => rx_cdr_lol(i), + cdr_rst_out => rx_serdes_rst(i) + ); + + u0_rate_resolution : rate_resolution port map( + gbe_mode => '1', + sgmii_mode => '0', + an_enable => '1', + advertised_rate => mr_adv_ability(i * 16 + 11 downto i * 16 + 10), + link_partner_rate => mr_lp_adv_ability(i * 16 + 11 downto i * 16 + 10), + non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled + + operational_rate => operational_rate( (i + 1) * 2 - 1 downto i * 2) + ); + + u0_ri : register_interface_hb port map( + -- Control Signals + rst_n => synced_rst, --rst_n, + hclk => CLK_125_IN, + gbe_mode => '1', + sgmii_mode => '0', + + -- Host Bus + hcs_n => '1', + hwrite_n => '1', + haddr => (others => '0'), + hdatain => (others => '0'), + + hdataout => open, + hready_n => open, + + -- Register Outputs + mr_an_enable => mr_an_enable(i), + mr_restart_an => mr_restart_an(i), + mr_main_reset => mr_main_reset(i), + mr_adv_ability => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16), + + -- Register Inputs + mr_an_complete => an_complete(i), + mr_page_rx => mr_page_rx(i), + mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16) + ); + + MAC: tsmac35 + port map( + ----------------- clock and reset port declarations ------------------ + hclk => CLK_SYS_IN, + txmac_clk => CLK_125_IN, + rxmac_clk => sd_rx_clk(i), + reset_n => GSR_N, + txmac_clk_en => '1', + rxmac_clk_en => '1', + ------------------- Input signals to the GMII ---------------- + rxd => pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8), + rx_dv => pcs_rx_en_qq(i), + rx_er => pcs_rx_er_qq(i), + col => pcs_col(i), + crs => pcs_crs(i), + -------------------- Input signals to the CPU I/F ------------------- + haddr => tsm_haddr( (i + 1) * 8 - 1 downto i * 8), + hdatain => tsm_hdata( (i + 1) * 8 - 1 downto i * 8), + hcs_n => tsm_hcs_n(i), + hwrite_n => tsm_hwrite_n(i), + hread_n => tsm_hread_n(i), + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata => MAC_TX_DATA_IN( (i + 1) * 8 - 1 downto i * 8), + tx_fifoavail => MAC_FIFOAVAIL_IN(i), + tx_fifoeof => MAC_FIFOEOF_IN(i), + tx_fifoempty => MAC_FIFOEMPTY_IN(i), + tx_sndpaustim => x"0000", + tx_sndpausreq => '0', + tx_fifoctrl => '0', -- always data frame + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full => MAC_RX_FIFOFULL_IN(i), --'0', + ignore_pkt => '0', + ---------------- Output signals from the GMII ----------------------- + txd => pcs_txd( (i + 1) * 8 - 1 downto i * 8), + tx_en => pcs_tx_en(i), + tx_er => pcs_tx_er(i), + ----------------- Output signals from the CPU I/F ------------------- + hdataout => open, + hdataout_en_n => tsm_hdataout_en_n(i), + hready_n => tsm_hready_n(i), + cpu_if_gbit_en => open, + ------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread => MAC_TX_READ_OUT(i), + tx_discfrm => MAC_TX_DISCRFRM_OUT(i), + tx_staten => MAC_TX_STAT_EN_OUT(i), + tx_statvec => MAC_TX_STATS_OUT( (i + 1) * 31 - 1 downto i * 31), + tx_done => MAC_TX_DONE_OUT(i), + ------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error => MAC_RX_FIFO_ERR_OUT(i), + rx_stat_vector => MAC_RX_STATS_OUT( (i + 1) * 32 - 1 downto i * 32), + rx_dbout => MAC_RX_DATA_OUT( (i + 1) * 8 - 1 downto i * 8), + rx_write => MAC_RX_WRITE_OUT(i), + rx_stat_en => MAC_RX_STAT_EN_OUT(i), + rx_eof => MAC_RX_EOF_OUT(i), + rx_error => MAC_RX_ERROR_OUT(i) + ); + + TSMAC_CONTROLLER : trb_net16_gbe_mac_control + port map( + CLK => CLK_SYS_IN, + RESET => RESET, + + -- signals to/from main controller + MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(i), + MC_RECONF_IN => MAC_RECONF_IN(i), + MC_GBE_EN_IN => '1', + MC_RX_DISCARD_FCS => '0', + MC_PROMISC_IN => '1', + MC_MAC_ADDR_IN => (others => '0'), + + -- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT => tsm_haddr( (i + 1) * 8 - 1 downto i * 8), + TSM_HDATA_OUT => tsm_hdata( (i + 1) * 8 - 1 downto i * 8), + TSM_HCS_N_OUT => tsm_hcs_n(i), + TSM_HWRITE_N_OUT => tsm_hwrite_n(i), + TSM_HREAD_N_OUT => tsm_hread_n(i), + TSM_HREADY_N_IN => tsm_hready_n(i), + TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i), + + DEBUG_OUT => open + ); + + SYNC_GMII_RX_PROC : process(sd_rx_clk) + begin + if rising_edge(sd_rx_clk(i)) then + pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd( (i + 1) * 8 - 1 downto i * 8); + pcs_rx_en_q(i) <= pcs_rx_en(i); + pcs_rx_er_q(i) <= pcs_rx_er(i); + + pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8); + pcs_rx_en_qq(i) <= pcs_rx_en_q(i); + pcs_rx_er_qq(i) <= pcs_rx_er_q(i); + end if; + end process SYNC_GMII_RX_PROC; + + SYNC_GMII_TX_PROC : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + pcs_txd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd( (i + 1) * 8 - 1 downto i * 8); + pcs_tx_en_q <= pcs_tx_en; + pcs_tx_er_q <= pcs_tx_er; + + pcs_txd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd_q( (i + 1) * 8 - 1 downto i * 8); + pcs_tx_en_qq <= pcs_tx_en_q; + pcs_tx_er_qq <= pcs_tx_er_q; + end if; + end process SYNC_GMII_TX_PROC; + + end generate pcs_gen; + + end generate impl_gen; + + sim_gen : if DO_SIMULATION = 1 generate + + process + begin + + MAC_AN_READY_OUT <= (others => '0'); + wait for 2 us; + MAC_AN_READY_OUT <= (others => '1'); + + wait; + end process; + + process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN; + + MAC_TX_DONE_OUT <= MAC_FIFOEOF_IN; + end if; + end process; + + + end generate sim_gen; + + +end architecture RTL; diff --git a/gbe_trb/base/gbe_wrapper.vhd b/gbe_trb/base/gbe_wrapper.vhd new file mode 100644 index 0000000..8785d70 --- /dev/null +++ b/gbe_trb/base/gbe_wrapper.vhd @@ -0,0 +1,1428 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_ARITH.all; +use IEEE.std_logic_UNSIGNED.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +use work.trb_net_gbe_components.all; + +entity gbe_wrapper is + generic( + DO_SIMULATION : integer range 0 to 1 := 0; + INCLUDE_DEBUG : integer range 0 to 1 := 0; + + USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; + USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; + RX_PATH_ENABLE : integer range 0 to 1 := 1; + + FIXED_SIZE_MODE : integer range 0 to 1 := 1; + INCREMENTAL_MODE : integer range 0 to 1 := 0; + FIXED_SIZE : integer range 0 to 65535 := 10; + FIXED_DELAY_MODE : integer range 0 to 1 := 1; + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; + FIXED_DELAY : integer range 0 to 16777215 := 16777215; + + NUMBER_OF_GBE_LINKS : integer range 1 to 4 := 4; + LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111"; + LINK_HAS_PING : std_logic_vector(3 downto 0) := "1111"; + LINK_HAS_ARP : std_logic_vector(3 downto 0) := "1111"; + LINK_HAS_DHCP : std_logic_vector(3 downto 0) := "1111"; + LINK_HAS_READOUT : std_logic_vector(3 downto 0) := "1111"; -- only one can be active + LINK_HAS_SLOWCTRL : std_logic_vector(3 downto 0) := "1111"; + + NUMBER_OF_OUTPUT_LINKS : integer range 0 to 4 := 0 + ); + port( + CLK_SYS_IN : in std_logic; + CLK_125_IN : in std_logic; + RESET : in std_logic; + GSR_N : in std_logic; + + SD_RXD_P_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_RXD_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_P_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_N_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable + + TRIGGER_IN : in std_logic; -- for debug purpose only + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); + CTS_CODE_IN : in std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + FEE_BUSY_IN : in std_logic; + -- SlowControl + MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + -- IP configuration + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- Registers config + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + BUS_WRITE_EN_IN : in std_logic; + BUS_READ_EN_IN : in std_logic; + BUS_ACK_OUT : out std_logic; + + MAKE_RESET_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(127 downto 0) + ); +end entity gbe_wrapper; + +architecture RTL of gbe_wrapper is + signal mac_ready_conf : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_reconf : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_an_ready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_fifoavail : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_fifoeof : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_fifoempty : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_rx_fifofull : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal mac_tx_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_tx_discrfrm : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_tx_stat_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_tx_stats : std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0); + signal mac_tx_done : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_rx_fifo_err : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_rx_stats : std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0); + signal mac_rx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal mac_rx_write : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_rx_stat_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_rx_eof : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mac_rx_err : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + signal clk_125_from_pcs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal clk_125_rx_from_pcs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + signal cfg_gbe_enable : std_logic; + signal cfg_ipu_enable : std_logic; + signal cfg_mult_enable : std_logic; + signal cfg_subevent_id : std_logic_vector(31 downto 0); + signal cfg_subevent_dec : std_logic_vector(31 downto 0); + signal cfg_queue_dec : std_logic_vector(31 downto 0); + signal cfg_readout_ctr : std_logic_vector(23 downto 0); + signal cfg_readout_ctr_valid : std_logic; + signal cfg_insert_ttype : std_logic; + signal cfg_max_sub : std_logic_vector(15 downto 0); + signal cfg_max_queue : std_logic_vector(15 downto 0); + signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0); + signal cfg_max_single_sub : std_logic_vector(15 downto 0); + signal cfg_additional_hdr : std_logic; + signal cfg_soft_rst : std_logic; + signal cfg_allow_rx : std_logic; + signal cfg_max_frame : std_logic_vector(15 downto 0); + + signal dbg_hist, dbg_hist2 : hist_array; + + signal master_mac, mac_0, mac_1, mac_2, mac_3 : std_logic_vector(47 downto 0); + signal cfg_max_reply : std_logic_vector(31 downto 0); + + signal mlt_cts_number : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_code : std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_information : std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_readout_type : std_logic_vector(4 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_start_readout : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_data : std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_readout_finished : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_length : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_cts_error_pattern : std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_fee_data : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_fee_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_fee_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_fee_status : std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_fee_busy : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + signal mlt_gsc_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_gsc_init_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_gsc_init_data : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_gsc_init_packet : std_logic_vector(3 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_gsc_init_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_gsc_reply_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_gsc_reply_data : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_gsc_reply_packet : std_logic_vector(3 * NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_gsc_reply_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mlt_gsc_busy : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + signal local_cts_number : std_logic_vector(15 downto 0); + signal local_cts_code : std_logic_vector(7 downto 0); + signal local_cts_information : std_logic_vector(7 downto 0); + signal local_cts_readout_type : std_logic_vector(3 downto 0); + signal local_cts_start_readout : std_logic; + signal local_cts_readout_finished : std_logic; + signal local_cts_status_bits : std_logic_vector(31 downto 0); + signal local_fee_data : std_logic_vector(15 downto 0); + signal local_fee_dataready : std_logic; + signal local_fee_read : std_logic; + signal local_fee_status_bits : std_logic_vector(31 downto 0); + signal local_fee_busy : std_logic; + signal dhcp_done : std_logic_vector(3 downto 0); + signal all_links_ready : std_logic; + signal monitor_rx_frames, monitor_rx_bytes, monitor_tx_frames, monitor_tx_bytes, monitor_tx_packets, monitor_dropped : std_logic_vector(4 * 32 - 1 downto 0); + signal sum_rx_frames, sum_rx_bytes, sum_tx_frames, sum_tx_bytes, sum_tx_packets, sum_dropped : std_logic_vector(31 downto 0); + + signal dummy_event : std_logic_vector(15 downto 0); + signal dummy_mode : std_logic; + +begin + + mac_impl_gen : if DO_SIMULATION = 0 generate + mac_0 <= master_mac(31 downto 8) & x"f50002"; + mac_1 <= master_mac(31 downto 8) & x"f60002"; + mac_2 <= master_mac(31 downto 8) & x"f70002"; + mac_3 <= master_mac(31 downto 8) & x"f80002"; + end generate mac_impl_gen; + + mac_sim_gen : if DO_SIMULATION = 1 generate + mac_0 <= x"ffffffffffff"; + mac_1 <= x"ffffffffffff"; + mac_2 <= x"ffffffffffff"; + mac_3 <= x"ffffffffffff"; + end generate mac_sim_gen; + + all_links_ready <= '1' when dhcp_done = x"f" else '0'; + + physical_impl_gen : if DO_SIMULATION = 0 generate + physical : entity work.gbe_med_interface + generic map(DO_SIMULATION => DO_SIMULATION, + NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS, + LINKS_ACTIVE => LINKS_ACTIVE) + port map( + RESET => RESET, + GSR_N => GSR_N, + CLK_SYS_IN => CLK_SYS_IN, + CLK_125_OUT => clk_125_from_pcs, + CLK_125_IN => CLK_125_IN, + CLK_125_RX_OUT => clk_125_rx_from_pcs, + MAC_READY_CONF_OUT => mac_ready_conf, + MAC_RECONF_IN => mac_reconf, + MAC_AN_READY_OUT => mac_an_ready, + MAC_FIFOAVAIL_IN => mac_fifoavail, + MAC_FIFOEOF_IN => mac_fifoeof, + MAC_FIFOEMPTY_IN => mac_fifoempty, + MAC_RX_FIFOFULL_IN => mac_rx_fifofull, + MAC_TX_DATA_IN => mac_tx_data, + MAC_TX_READ_OUT => mac_tx_read, + MAC_TX_DISCRFRM_OUT => mac_tx_discrfrm, + MAC_TX_STAT_EN_OUT => mac_tx_stat_en, + MAC_TX_STATS_OUT => mac_tx_stats, + MAC_TX_DONE_OUT => mac_tx_done, + MAC_RX_FIFO_ERR_OUT => mac_rx_fifo_err, + MAC_RX_STATS_OUT => mac_rx_stats, + MAC_RX_DATA_OUT => mac_rx_data, + MAC_RX_WRITE_OUT => mac_rx_write, + MAC_RX_STAT_EN_OUT => mac_rx_stat_en, + MAC_RX_EOF_OUT => mac_rx_eof, + MAC_RX_ERROR_OUT => mac_rx_err, + SD_RXD_P_IN => SD_RXD_P_IN, + SD_RXD_N_IN => SD_RXD_N_IN, + SD_TXD_P_OUT => SD_TXD_P_OUT, + SD_TXD_N_OUT => SD_TXD_N_OUT, + SD_PRSNT_N_IN => SD_PRSNT_N_IN, + SD_LOS_IN => SD_LOS_IN, + SD_TXDIS_OUT => SD_TXDIS_OUT, + DEBUG_OUT => open + ); + end generate physical_impl_gen; + + -- sfp8 + GEN_LINK_3 : if (LINKS_ACTIVE(3) = '1') generate + gbe_inst3 : entity work.gbe_logic_wrapper + generic map(DO_SIMULATION => DO_SIMULATION, + INCLUDE_DEBUG => INCLUDE_DEBUG, + USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY, + RX_PATH_ENABLE => RX_PATH_ENABLE, + INCLUDE_READOUT => LINK_HAS_READOUT(3), + INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(3), + INCLUDE_DHCP => LINK_HAS_DHCP(3), + INCLUDE_ARP => LINK_HAS_ARP(3), + INCLUDE_PING => LINK_HAS_PING(3), + FRAME_BUFFER_SIZE => 1, + READOUT_BUFFER_SIZE => 4, + SLOWCTRL_BUFFER_SIZE => 2, + FIXED_SIZE_MODE => FIXED_SIZE_MODE, + INCREMENTAL_MODE => INCREMENTAL_MODE, + FIXED_SIZE => FIXED_SIZE, + FIXED_DELAY_MODE => FIXED_DELAY_MODE, + UP_DOWN_MODE => UP_DOWN_MODE, + UP_DOWN_LIMIT => UP_DOWN_LIMIT, + FIXED_DELAY => FIXED_DELAY) + port map( + CLK_SYS_IN => CLK_SYS_IN, + CLK_125_IN => CLK_125_IN, + CLK_RX_125_IN => clk_125_rx_from_pcs(3), + RESET => RESET, + GSR_N => GSR_N, + MY_MAC_OUT => master_mac, + MY_MAC_IN => mac_3, + DHCP_DONE_OUT => dhcp_done(3), + MAC_READY_CONF_IN => mac_ready_conf(3), + MAC_RECONF_OUT => mac_reconf(3), + MAC_AN_READY_IN => mac_an_ready(3), + MAC_FIFOAVAIL_OUT => mac_fifoavail(3), + MAC_FIFOEOF_OUT => mac_fifoeof(3), + MAC_FIFOEMPTY_OUT => mac_fifoempty(3), + MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(3), + MAC_TX_DATA_OUT => mac_tx_data(4 * 8 - 1 downto 3 * 8), + MAC_TX_READ_IN => mac_tx_read(3), + MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(3), + MAC_TX_STAT_EN_IN => mac_tx_stat_en(3), + MAC_TX_STATS_IN => mac_tx_stats(4 * 31 - 1 downto 3 * 31), + MAC_TX_DONE_IN => mac_tx_done(3), + MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(3), + MAC_RX_STATS_IN => mac_rx_stats(4 * 32 - 1 downto 3 * 32), + MAC_RX_DATA_IN => mac_rx_data(4 * 8 - 1 downto 3 * 8), + MAC_RX_WRITE_IN => mac_rx_write(3), + MAC_RX_STAT_EN_IN => mac_rx_stat_en(3), + MAC_RX_EOF_IN => mac_rx_eof(3), + MAC_RX_ERROR_IN => mac_rx_err(3), + CTS_NUMBER_IN => mlt_cts_number(4 * 16 - 1 downto 3 * 16), + CTS_CODE_IN => mlt_cts_code(4 * 8 - 1 downto 3 * 8), + CTS_INFORMATION_IN => mlt_cts_information(4 * 8 - 1 downto 3 * 8), + CTS_READOUT_TYPE_IN => mlt_cts_readout_type(4 * 4 - 1 downto 3 * 4), + CTS_START_READOUT_IN => mlt_cts_start_readout(3), + CTS_DATA_OUT => mlt_cts_data(4 * 32 - 1 downto 3 * 32), + CTS_DATAREADY_OUT => mlt_cts_dataready(3), + CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(3), + CTS_READ_IN => mlt_cts_read(3), + CTS_LENGTH_OUT => mlt_cts_length(4 * 16 - 1 downto 3 * 16), + CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(4 * 32 - 1 downto 3 * 32), + FEE_DATA_IN => mlt_fee_data(4 * 16 - 1 downto 3 * 16), + FEE_DATAREADY_IN => mlt_fee_dataready(3), + FEE_READ_OUT => mlt_fee_read(3), + FEE_STATUS_BITS_IN => mlt_fee_status(4 * 32 - 1 downto 3 * 32), + FEE_BUSY_IN => mlt_fee_busy(3), + MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, + GSC_CLK_IN => mlt_gsc_clk(3), + GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(3), + GSC_INIT_DATA_OUT => mlt_gsc_init_data(4 * 16 - 1 downto 3 * 16), + GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(4 * 3 - 1 downto 3 * 3), + GSC_INIT_READ_IN => mlt_gsc_init_read(3), + GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(3), + GSC_REPLY_DATA_IN => mlt_gsc_reply_data(4 * 16 - 1 downto 3 * 16), + GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(4 * 3 - 1 downto 3 * 3), + GSC_REPLY_READ_OUT => mlt_gsc_reply_read(3), + GSC_BUSY_IN => mlt_gsc_busy(3), + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + CFG_GBE_ENABLE_IN => cfg_gbe_enable, + CFG_IPU_ENABLE_IN => cfg_ipu_enable, + CFG_MULT_ENABLE_IN => cfg_mult_enable, + CFG_MAX_FRAME_IN => cfg_max_frame, + CFG_ALLOW_RX_IN => cfg_allow_rx, + CFG_SOFT_RESET_IN => cfg_soft_rst, + CFG_SUBEVENT_ID_IN => cfg_subevent_id, + CFG_SUBEVENT_DEC_IN => cfg_subevent_dec, + CFG_QUEUE_DEC_IN => cfg_queue_dec, + CFG_READOUT_CTR_IN => cfg_readout_ctr, + CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid, + CFG_INSERT_TTYPE_IN => cfg_insert_ttype, + CFG_MAX_SUB_IN => cfg_max_sub, + CFG_MAX_QUEUE_IN => cfg_max_queue, + CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue, + CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub, + CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr, + CFG_MAX_REPLY_SIZE_IN => cfg_max_reply, + MONITOR_RX_FRAMES_OUT => monitor_rx_frames(4 * 32 - 1 downto 3 * 32), + MONITOR_RX_BYTES_OUT => monitor_rx_bytes(4 * 32 - 1 downto 3 * 32), + MONITOR_TX_FRAMES_OUT => monitor_tx_frames(4 * 32 - 1 downto 3 * 32), + MONITOR_TX_BYTES_OUT => monitor_tx_bytes(4 * 32 - 1 downto 3 * 32), + MONITOR_TX_PACKETS_OUT => monitor_tx_packets(4 * 32 - 1 downto 3 * 32), + MONITOR_DROPPED_OUT => monitor_dropped(4 * 32 - 1 downto 3 * 32), + MAKE_RESET_OUT => MAKE_RESET_OUT + ); + end generate GEN_LINK_3; + + -- sfp7 + GEN_LINK_2 : if (LINKS_ACTIVE(2) = '1') generate + gbe_inst2 : entity work.gbe_logic_wrapper + generic map(DO_SIMULATION => DO_SIMULATION, + INCLUDE_DEBUG => INCLUDE_DEBUG, + USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY, + RX_PATH_ENABLE => 1, + INCLUDE_READOUT => LINK_HAS_READOUT(2), + INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(2), + INCLUDE_DHCP => LINK_HAS_DHCP(2), + INCLUDE_ARP => LINK_HAS_ARP(2), + INCLUDE_PING => LINK_HAS_PING(2), + FRAME_BUFFER_SIZE => 1, + READOUT_BUFFER_SIZE => 4, + SLOWCTRL_BUFFER_SIZE => 2, + FIXED_SIZE_MODE => FIXED_SIZE_MODE, + INCREMENTAL_MODE => INCREMENTAL_MODE, + FIXED_SIZE => FIXED_SIZE, + FIXED_DELAY_MODE => FIXED_DELAY_MODE, + UP_DOWN_MODE => UP_DOWN_MODE, + UP_DOWN_LIMIT => UP_DOWN_LIMIT, + FIXED_DELAY => FIXED_DELAY) + port map( + CLK_SYS_IN => CLK_SYS_IN, + CLK_125_IN => CLK_125_IN, + CLK_RX_125_IN => clk_125_rx_from_pcs(2), + RESET => RESET, + GSR_N => GSR_N, + MY_MAC_OUT => open, + MY_MAC_IN => mac_2, + DHCP_DONE_OUT => dhcp_done(2), + MAC_READY_CONF_IN => mac_ready_conf(2), + MAC_RECONF_OUT => mac_reconf(2), + MAC_AN_READY_IN => mac_an_ready(2), + MAC_FIFOAVAIL_OUT => mac_fifoavail(2), + MAC_FIFOEOF_OUT => mac_fifoeof(2), + MAC_FIFOEMPTY_OUT => mac_fifoempty(2), + MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(2), + MAC_TX_DATA_OUT => mac_tx_data(3 * 8 - 1 downto 2 * 8), + MAC_TX_READ_IN => mac_tx_read(2), + MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(2), + MAC_TX_STAT_EN_IN => mac_tx_stat_en(2), + MAC_TX_STATS_IN => mac_tx_stats(3 * 31 - 1 downto 2 * 31), + MAC_TX_DONE_IN => mac_tx_done(2), + MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(2), + MAC_RX_STATS_IN => mac_rx_stats(3 * 32 - 1 downto 2 * 32), + MAC_RX_DATA_IN => mac_rx_data(3 * 8 - 1 downto 2 * 8), + MAC_RX_WRITE_IN => mac_rx_write(2), + MAC_RX_STAT_EN_IN => mac_rx_stat_en(2), + MAC_RX_EOF_IN => mac_rx_eof(2), + MAC_RX_ERROR_IN => mac_rx_err(2), + CTS_NUMBER_IN => mlt_cts_number(3 * 16 - 1 downto 2 * 16), + CTS_CODE_IN => mlt_cts_code(3 * 8 - 1 downto 2 * 8), + CTS_INFORMATION_IN => mlt_cts_information(3 * 8 - 1 downto 2 * 8), + CTS_READOUT_TYPE_IN => mlt_cts_readout_type(3 * 4 - 1 downto 2 * 4), + CTS_START_READOUT_IN => mlt_cts_start_readout(2), + CTS_DATA_OUT => mlt_cts_data(3 * 32 - 1 downto 2 * 32), + CTS_DATAREADY_OUT => mlt_cts_dataready(2), + CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(2), + CTS_READ_IN => mlt_cts_read(2), + CTS_LENGTH_OUT => mlt_cts_length(3 * 16 - 1 downto 2 * 16), + CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(3 * 32 - 1 downto 2 * 32), + FEE_DATA_IN => mlt_fee_data(3 * 16 - 1 downto 2 * 16), + FEE_DATAREADY_IN => mlt_fee_dataready(2), + FEE_READ_OUT => mlt_fee_read(2), + FEE_STATUS_BITS_IN => mlt_fee_status(3 * 32 - 1 downto 2 * 32), + FEE_BUSY_IN => mlt_fee_busy(2), + MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, + GSC_CLK_IN => mlt_gsc_clk(2), + GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(2), + GSC_INIT_DATA_OUT => mlt_gsc_init_data(3 * 16 - 1 downto 2 * 16), + GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(3 * 3 - 1 downto 2 * 3), + GSC_INIT_READ_IN => mlt_gsc_init_read(2), + GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(2), + GSC_REPLY_DATA_IN => mlt_gsc_reply_data(3 * 16 - 1 downto 2 * 16), + GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(3 * 3 - 1 downto 2 * 3), + GSC_REPLY_READ_OUT => mlt_gsc_reply_read(2), + GSC_BUSY_IN => mlt_gsc_busy(2), + + -- SLV_ADDR_IN => (others => '0'), --SLV_ADDR_IN, + -- SLV_READ_IN => '0', --SLV_READ_IN, + -- SLV_WRITE_IN => '0', --SLV_WRITE_IN, + -- SLV_BUSY_OUT => open, --SLV_BUSY_OUT, + -- SLV_ACK_OUT => open, --SLV_ACK_OUT, + -- SLV_DATA_IN => (others => '0'), --SLV_DATA_IN, + -- SLV_DATA_OUT => open, --SLV_DATA_OUT, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => open, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => open, + CFG_GBE_ENABLE_IN => cfg_gbe_enable, + CFG_IPU_ENABLE_IN => cfg_ipu_enable, + CFG_MULT_ENABLE_IN => cfg_mult_enable, + CFG_MAX_FRAME_IN => cfg_max_frame, + CFG_ALLOW_RX_IN => cfg_allow_rx, + CFG_SOFT_RESET_IN => cfg_soft_rst, + CFG_SUBEVENT_ID_IN => cfg_subevent_id, + CFG_SUBEVENT_DEC_IN => cfg_subevent_dec, + CFG_QUEUE_DEC_IN => cfg_queue_dec, + CFG_READOUT_CTR_IN => cfg_readout_ctr, + CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid, + CFG_INSERT_TTYPE_IN => cfg_insert_ttype, + CFG_MAX_SUB_IN => cfg_max_sub, + CFG_MAX_QUEUE_IN => cfg_max_queue, + CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue, + CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub, + CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr, + CFG_MAX_REPLY_SIZE_IN => cfg_max_reply, + MONITOR_RX_FRAMES_OUT => monitor_rx_frames(3 * 32 - 1 downto 2 * 32), + MONITOR_RX_BYTES_OUT => monitor_rx_bytes(3 * 32 - 1 downto 2 * 32), + MONITOR_TX_FRAMES_OUT => monitor_tx_frames(3 * 32 - 1 downto 2 * 32), + MONITOR_TX_BYTES_OUT => monitor_tx_bytes(3 * 32 - 1 downto 2 * 32), + MONITOR_TX_PACKETS_OUT => monitor_tx_packets(3 * 32 - 1 downto 2 * 32), + MONITOR_DROPPED_OUT => monitor_dropped(3 * 32 - 1 downto 2 * 32), + MAKE_RESET_OUT => open --MAKE_RESET_OUT + ); + end generate GEN_LINK_2; + + -- sfp6 + GEN_LINK_1 : if (LINKS_ACTIVE(1) = '1') generate + gbe_inst1 : entity work.gbe_logic_wrapper + generic map(DO_SIMULATION => DO_SIMULATION, + INCLUDE_DEBUG => INCLUDE_DEBUG, + USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY, + RX_PATH_ENABLE => 1, + INCLUDE_READOUT => LINK_HAS_READOUT(1), + INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(1), + INCLUDE_DHCP => LINK_HAS_DHCP(1), + INCLUDE_ARP => LINK_HAS_ARP(1), + INCLUDE_PING => LINK_HAS_PING(1), + FRAME_BUFFER_SIZE => 1, + READOUT_BUFFER_SIZE => 4, + SLOWCTRL_BUFFER_SIZE => 2, + FIXED_SIZE_MODE => FIXED_SIZE_MODE, + INCREMENTAL_MODE => INCREMENTAL_MODE, + FIXED_SIZE => FIXED_SIZE, + FIXED_DELAY_MODE => FIXED_DELAY_MODE, + UP_DOWN_MODE => UP_DOWN_MODE, + UP_DOWN_LIMIT => UP_DOWN_LIMIT, + FIXED_DELAY => FIXED_DELAY) + port map( + CLK_SYS_IN => CLK_SYS_IN, + CLK_125_IN => CLK_125_IN, + CLK_RX_125_IN => clk_125_rx_from_pcs(1), + RESET => RESET, + GSR_N => GSR_N, + MY_MAC_OUT => open, + MY_MAC_IN => mac_1, + DHCP_DONE_OUT => dhcp_done(1), + MAC_READY_CONF_IN => mac_ready_conf(1), + MAC_RECONF_OUT => mac_reconf(1), + MAC_AN_READY_IN => mac_an_ready(1), + MAC_FIFOAVAIL_OUT => mac_fifoavail(1), + MAC_FIFOEOF_OUT => mac_fifoeof(1), + MAC_FIFOEMPTY_OUT => mac_fifoempty(1), + MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(1), + MAC_TX_DATA_OUT => mac_tx_data(2 * 8 - 1 downto 1 * 8), + MAC_TX_READ_IN => mac_tx_read(1), + MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(1), + MAC_TX_STAT_EN_IN => mac_tx_stat_en(1), + MAC_TX_STATS_IN => mac_tx_stats(2 * 31 - 1 downto 1 * 31), + MAC_TX_DONE_IN => mac_tx_done(1), + MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(1), + MAC_RX_STATS_IN => mac_rx_stats(2 * 32 - 1 downto 1 * 32), + MAC_RX_DATA_IN => mac_rx_data(2 * 8 - 1 downto 1 * 8), + MAC_RX_WRITE_IN => mac_rx_write(1), + MAC_RX_STAT_EN_IN => mac_rx_stat_en(1), + MAC_RX_EOF_IN => mac_rx_eof(1), + MAC_RX_ERROR_IN => mac_rx_err(1), + CTS_NUMBER_IN => mlt_cts_number(2 * 16 - 1 downto 1 * 16), + CTS_CODE_IN => mlt_cts_code(2 * 8 - 1 downto 1 * 8), + CTS_INFORMATION_IN => mlt_cts_information(2 * 8 - 1 downto 1 * 8), + CTS_READOUT_TYPE_IN => mlt_cts_readout_type(2 * 4 - 1 downto 1 * 4), + CTS_START_READOUT_IN => mlt_cts_start_readout(1), + CTS_DATA_OUT => mlt_cts_data(2 * 32 - 1 downto 1 * 32), + CTS_DATAREADY_OUT => mlt_cts_dataready(1), + CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(1), + CTS_READ_IN => mlt_cts_read(1), + CTS_LENGTH_OUT => mlt_cts_length(2 * 16 - 1 downto 1 * 16), + CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(2 * 32 - 1 downto 1 * 32), + FEE_DATA_IN => mlt_fee_data(2 * 16 - 1 downto 1 * 16), + FEE_DATAREADY_IN => mlt_fee_dataready(1), + FEE_READ_OUT => mlt_fee_read(1), + FEE_STATUS_BITS_IN => mlt_fee_status(2 * 32 - 1 downto 1 * 32), + FEE_BUSY_IN => mlt_fee_busy(1), + MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, + GSC_CLK_IN => mlt_gsc_clk(1), + GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(1), + GSC_INIT_DATA_OUT => mlt_gsc_init_data(2 * 16 - 1 downto 1 * 16), + GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(2 * 3 - 1 downto 1 * 3), + GSC_INIT_READ_IN => mlt_gsc_init_read(1), + GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(1), + GSC_REPLY_DATA_IN => mlt_gsc_reply_data(2 * 16 - 1 downto 1 * 16), + GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(2 * 3 - 1 downto 1 * 3), + GSC_REPLY_READ_OUT => mlt_gsc_reply_read(1), + GSC_BUSY_IN => mlt_gsc_busy(1), + + -- SLV_ADDR_IN => (others => '0'), --SLV_ADDR_IN, + -- SLV_READ_IN => '0', --SLV_READ_IN, + -- SLV_WRITE_IN => '0', --SLV_WRITE_IN, + -- SLV_BUSY_OUT => open, --SLV_BUSY_OUT, + -- SLV_ACK_OUT => open, --SLV_ACK_OUT, + -- SLV_DATA_IN => (others => '0'), --SLV_DATA_IN, + -- SLV_DATA_OUT => open, --SLV_DATA_OUT, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => open, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => open, + CFG_GBE_ENABLE_IN => cfg_gbe_enable, + CFG_IPU_ENABLE_IN => cfg_ipu_enable, + CFG_MULT_ENABLE_IN => cfg_mult_enable, + CFG_MAX_FRAME_IN => cfg_max_frame, + CFG_ALLOW_RX_IN => cfg_allow_rx, + CFG_SOFT_RESET_IN => cfg_soft_rst, + CFG_SUBEVENT_ID_IN => cfg_subevent_id, + CFG_SUBEVENT_DEC_IN => cfg_subevent_dec, + CFG_QUEUE_DEC_IN => cfg_queue_dec, + CFG_READOUT_CTR_IN => cfg_readout_ctr, + CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid, + CFG_INSERT_TTYPE_IN => cfg_insert_ttype, + CFG_MAX_SUB_IN => cfg_max_sub, + CFG_MAX_QUEUE_IN => cfg_max_queue, + CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue, + CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub, + CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr, + CFG_MAX_REPLY_SIZE_IN => cfg_max_reply, + MONITOR_RX_FRAMES_OUT => monitor_rx_frames(2 * 32 - 1 downto 1 * 32), + MONITOR_RX_BYTES_OUT => monitor_rx_bytes(2 * 32 - 1 downto 1 * 32), + MONITOR_TX_FRAMES_OUT => monitor_tx_frames(2 * 32 - 1 downto 1 * 32), + MONITOR_TX_BYTES_OUT => monitor_tx_bytes(2 * 32 - 1 downto 1 * 32), + MONITOR_TX_PACKETS_OUT => monitor_tx_packets(2 * 32 - 1 downto 1 * 32), + MONITOR_DROPPED_OUT => monitor_dropped(2 * 32 - 1 downto 1 * 32), + MAKE_RESET_OUT => open --MAKE_RESET_OUT + ); + end generate GEN_LINK_1; + + -- sfp5 + GEN_LINK_0 : if (LINKS_ACTIVE(0) = '1') generate + gbe_inst0 : entity work.gbe_logic_wrapper + generic map(DO_SIMULATION => DO_SIMULATION, + INCLUDE_DEBUG => INCLUDE_DEBUG, + USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY, + RX_PATH_ENABLE => 1, + INCLUDE_READOUT => LINK_HAS_READOUT(0), + INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(0), + INCLUDE_DHCP => LINK_HAS_DHCP(0), + INCLUDE_ARP => LINK_HAS_ARP(0), + INCLUDE_PING => LINK_HAS_PING(0), + FRAME_BUFFER_SIZE => 1, + READOUT_BUFFER_SIZE => 4, + SLOWCTRL_BUFFER_SIZE => 2, + FIXED_SIZE_MODE => FIXED_SIZE_MODE, + INCREMENTAL_MODE => INCREMENTAL_MODE, + FIXED_SIZE => FIXED_SIZE, + FIXED_DELAY_MODE => FIXED_DELAY_MODE, + UP_DOWN_MODE => UP_DOWN_MODE, + UP_DOWN_LIMIT => UP_DOWN_LIMIT, + FIXED_DELAY => FIXED_DELAY) + port map( + CLK_SYS_IN => CLK_SYS_IN, + CLK_125_IN => CLK_125_IN, + CLK_RX_125_IN => clk_125_rx_from_pcs(0), + RESET => RESET, + GSR_N => GSR_N, + MY_MAC_OUT => open, + MY_MAC_IN => mac_0, + DHCP_DONE_OUT => dhcp_done(0), + MAC_READY_CONF_IN => mac_ready_conf(0), + MAC_RECONF_OUT => mac_reconf(0), + MAC_AN_READY_IN => mac_an_ready(0), + MAC_FIFOAVAIL_OUT => mac_fifoavail(0), + MAC_FIFOEOF_OUT => mac_fifoeof(0), + MAC_FIFOEMPTY_OUT => mac_fifoempty(0), + MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(0), + MAC_TX_DATA_OUT => mac_tx_data(1 * 8 - 1 downto 0 * 8), + MAC_TX_READ_IN => mac_tx_read(0), + MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(0), + MAC_TX_STAT_EN_IN => mac_tx_stat_en(0), + MAC_TX_STATS_IN => mac_tx_stats(1 * 31 - 1 downto 0 * 31), + MAC_TX_DONE_IN => mac_tx_done(0), + MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(0), + MAC_RX_STATS_IN => mac_rx_stats(1 * 32 - 1 downto 0 * 32), + MAC_RX_DATA_IN => mac_rx_data(1 * 8 - 1 downto 0 * 8), + MAC_RX_WRITE_IN => mac_rx_write(0), + MAC_RX_STAT_EN_IN => mac_rx_stat_en(0), + MAC_RX_EOF_IN => mac_rx_eof(0), + MAC_RX_ERROR_IN => mac_rx_err(0), + CTS_NUMBER_IN => mlt_cts_number(1 * 16 - 1 downto 0 * 16), + CTS_CODE_IN => mlt_cts_code(1 * 8 - 1 downto 0 * 8), + CTS_INFORMATION_IN => mlt_cts_information(1 * 8 - 1 downto 0 * 8), + CTS_READOUT_TYPE_IN => mlt_cts_readout_type(1 * 4 - 1 downto 0 * 4), + CTS_START_READOUT_IN => mlt_cts_start_readout(0), + CTS_DATA_OUT => mlt_cts_data(1 * 32 - 1 downto 0 * 32), + CTS_DATAREADY_OUT => mlt_cts_dataready(0), + CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0), + CTS_READ_IN => mlt_cts_read(0), + CTS_LENGTH_OUT => mlt_cts_length(1 * 16 - 1 downto 0 * 16), + CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(1 * 32 - 1 downto 0 * 32), + FEE_DATA_IN => mlt_fee_data(1 * 16 - 1 downto 0 * 16), + FEE_DATAREADY_IN => mlt_fee_dataready(0), + FEE_READ_OUT => mlt_fee_read(0), + FEE_STATUS_BITS_IN => mlt_fee_status(1 * 32 - 1 downto 0 * 32), + FEE_BUSY_IN => mlt_fee_busy(0), + MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, + GSC_CLK_IN => mlt_gsc_clk(0), + GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(0), + GSC_INIT_DATA_OUT => mlt_gsc_init_data(1 * 16 - 1 downto 0 * 16), + GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(1 * 3 - 1 downto 0 * 3), + GSC_INIT_READ_IN => mlt_gsc_init_read(0), + GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(0), + GSC_REPLY_DATA_IN => mlt_gsc_reply_data(1 * 16 - 1 downto 0 * 16), + GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(1 * 3 - 1 downto 0* 3), + GSC_REPLY_READ_OUT => mlt_gsc_reply_read(0), + GSC_BUSY_IN => mlt_gsc_busy(0), + + -- SLV_ADDR_IN => (others => '0'), --SLV_ADDR_IN, + -- SLV_READ_IN => '0', --SLV_READ_IN, + -- SLV_WRITE_IN => '0', --SLV_WRITE_IN, + -- SLV_BUSY_OUT => open, --SLV_BUSY_OUT, + -- SLV_ACK_OUT => open, --SLV_ACK_OUT, + -- SLV_DATA_IN => (others => '0'), --SLV_DATA_IN, + -- SLV_DATA_OUT => open, --SLV_DATA_OUT, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => open, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => open, + CFG_GBE_ENABLE_IN => cfg_gbe_enable, + CFG_IPU_ENABLE_IN => cfg_ipu_enable, + CFG_MULT_ENABLE_IN => cfg_mult_enable, + CFG_MAX_FRAME_IN => cfg_max_frame, + CFG_ALLOW_RX_IN => cfg_allow_rx, + CFG_SOFT_RESET_IN => cfg_soft_rst, + CFG_SUBEVENT_ID_IN => cfg_subevent_id, + CFG_SUBEVENT_DEC_IN => cfg_subevent_dec, + CFG_QUEUE_DEC_IN => cfg_queue_dec, + CFG_READOUT_CTR_IN => cfg_readout_ctr, + CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid, + CFG_INSERT_TTYPE_IN => cfg_insert_ttype, + CFG_MAX_SUB_IN => cfg_max_sub, + CFG_MAX_QUEUE_IN => cfg_max_queue, + CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue, + CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub, + CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr, + CFG_MAX_REPLY_SIZE_IN => cfg_max_reply, + MONITOR_RX_FRAMES_OUT => monitor_rx_frames(1 * 32 - 1 downto 0 * 32), + MONITOR_RX_BYTES_OUT => monitor_rx_bytes(1 * 32 - 1 downto 0 * 32), + MONITOR_TX_FRAMES_OUT => monitor_tx_frames(1 * 32 - 1 downto 0 * 32), + MONITOR_TX_BYTES_OUT => monitor_tx_bytes(1 * 32 - 1 downto 0 * 32), + MONITOR_TX_PACKETS_OUT => monitor_tx_packets(1 * 32 - 1 downto 0 * 32), + MONITOR_DROPPED_OUT => monitor_dropped(1 * 32 - 1 downto 0 * 32), + MAKE_RESET_OUT => open --MAKE_RESET_OUT + ); + end generate GEN_LINK_0; + + real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate + ipu_mult : entity work.gbe_ipu_multiplexer + generic map( + DO_SIMULATION => DO_SIMULATION, + INCLUDE_DEBUG => INCLUDE_DEBUG, + LINK_HAS_READOUT => LINK_HAS_READOUT, + NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS + ) + port map( + CLK_SYS_IN => CLK_SYS_IN, + RESET => RESET, + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + MLT_CTS_NUMBER_OUT => mlt_cts_number, + MLT_CTS_CODE_OUT => mlt_cts_code, + MLT_CTS_INFORMATION_OUT => mlt_cts_information, + MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type, + MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout, + MLT_CTS_DATA_IN => mlt_cts_data, + MLT_CTS_DATAREADY_IN => mlt_cts_dataready, + MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished, + MLT_CTS_READ_OUT => mlt_cts_read, + MLT_CTS_LENGTH_IN => mlt_cts_length, + MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern, + MLT_FEE_DATA_OUT => mlt_fee_data, + MLT_FEE_DATAREADY_OUT => mlt_fee_dataready, + MLT_FEE_READ_IN => mlt_fee_read, + MLT_FEE_STATUS_BITS_OUT => mlt_fee_status, + MLT_FEE_BUSY_OUT => mlt_fee_busy, + DEBUG_OUT => open + ); + end generate real_ipu_gen; + + dummy_ipu_gen : if (USE_EXTERNAL_TRBNET_DUMMY = 1) generate + ipu_mult : entity work.gbe_ipu_multiplexer + generic map( + DO_SIMULATION => DO_SIMULATION, + INCLUDE_DEBUG => INCLUDE_DEBUG, + LINK_HAS_READOUT => LINK_HAS_READOUT, + NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS + ) + port map( + CLK_SYS_IN => CLK_SYS_IN, + RESET => RESET, + CTS_NUMBER_IN => local_cts_number, + CTS_CODE_IN => local_cts_code, + CTS_INFORMATION_IN => local_cts_information, + CTS_READOUT_TYPE_IN => local_cts_readout_type, + CTS_START_READOUT_IN => local_cts_start_readout, + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => local_cts_readout_finished, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => local_cts_status_bits, + FEE_DATA_IN => local_fee_data, + FEE_DATAREADY_IN => local_fee_dataready, + FEE_READ_OUT => local_fee_read, + FEE_STATUS_BITS_IN => local_fee_status_bits, + FEE_BUSY_IN => local_fee_busy, + MLT_CTS_NUMBER_OUT => mlt_cts_number, + MLT_CTS_CODE_OUT => mlt_cts_code, + MLT_CTS_INFORMATION_OUT => mlt_cts_information, + MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type, + MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout, + MLT_CTS_DATA_IN => mlt_cts_data, + MLT_CTS_DATAREADY_IN => mlt_cts_dataready, + MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished, + MLT_CTS_READ_OUT => mlt_cts_read, + MLT_CTS_LENGTH_IN => mlt_cts_length, + MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern, + MLT_FEE_DATA_OUT => mlt_fee_data, + MLT_FEE_DATAREADY_OUT => mlt_fee_dataready, + MLT_FEE_READ_IN => mlt_fee_read, + MLT_FEE_STATUS_BITS_OUT => mlt_fee_status, + MLT_FEE_BUSY_OUT => mlt_fee_busy, + DEBUG_OUT => open + ); + + dummy : entity work.gbe_ipu_dummy + generic map( + DO_SIMULATION => DO_SIMULATION, + FIXED_SIZE_MODE => FIXED_SIZE_MODE, + INCREMENTAL_MODE => INCREMENTAL_MODE, + FIXED_SIZE => FIXED_SIZE, + UP_DOWN_MODE => UP_DOWN_MODE, + UP_DOWN_LIMIT => UP_DOWN_LIMIT, + FIXED_DELAY_MODE => FIXED_DELAY_MODE, + FIXED_DELAY => FIXED_DELAY + ) + port map( + clk => CLK_SYS_IN, + rst => RESET, + GBE_READY_IN => '1', --all_links_ready, + + CFG_EVENT_SIZE_IN => dummy_event, + CFG_TRIGGERED_MODE_IN => dummy_mode, + TRIGGER_IN => TRIGGER_IN, + CTS_NUMBER_OUT => local_cts_number, + CTS_CODE_OUT => local_cts_code, + CTS_INFORMATION_OUT => local_cts_information, + CTS_READOUT_TYPE_OUT => local_cts_readout_type, + CTS_START_READOUT_OUT => local_cts_start_readout, + CTS_DATA_IN => (others => '0'), + CTS_DATAREADY_IN => '0', + CTS_READOUT_FINISHED_IN => local_cts_readout_finished, + CTS_READ_OUT => open, + CTS_LENGTH_IN => (others => '0'), + CTS_ERROR_PATTERN_IN => local_cts_status_bits, + -- Data payload interface + FEE_DATA_OUT => local_fee_data, + FEE_DATAREADY_OUT => local_fee_dataready, + FEE_READ_IN => local_fee_read, + FEE_STATUS_BITS_OUT => local_fee_status_bits, + FEE_BUSY_OUT => local_fee_busy + ); + + -- handler for triggers + DUMMY_HANDLER : entity work.trb_net16_gbe_ipu_interface + port map( + CLK_IPU => CLK_SYS_IN, + CLK_GBE => CLK_125_IN, + RESET => RESET, + --Event information coming from CTS + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + -- Data from Frontends + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + -- slow control interface + START_CONFIG_OUT => open, + BANK_SELECT_OUT => open, + CONFIG_DONE_IN => '1', + DATA_GBE_ENABLE_IN => '1', + DATA_IPU_ENABLE_IN => '1', + MULT_EVT_ENABLE_IN => '1', + MAX_SUBEVENT_SIZE_IN => (others => '0'), + MAX_QUEUE_SIZE_IN => (others => '0'), + MAX_SUBS_IN_QUEUE_IN => (others => '0'), + MAX_SINGLE_SUB_SIZE_IN => (others => '0'), + READOUT_CTR_IN => (others => '0'), + READOUT_CTR_VALID_IN => '0', + -- PacketConstructor interface + PC_WR_EN_OUT => open, + PC_DATA_OUT => open, + PC_READY_IN => '1', + PC_SOS_OUT => open, + PC_EOS_OUT => open, + PC_EOQ_OUT => open, + PC_SUB_SIZE_OUT => open, + PC_TRIG_NR_OUT => open, + PC_TRIGGER_TYPE_OUT => open, + MONITOR_OUT => open, + DEBUG_OUT => open + ); + end generate dummy_ipu_gen; + + setup_imp_gen : if (DO_SIMULATION = 0) generate + SETUP : gbe_setup + port map( + CLK => CLK_SYS_IN, + RESET => RESET, + + -- interface to regio bus + BUS_ADDR_IN => BUS_ADDR_IN, + BUS_DATA_IN => BUS_DATA_IN, + BUS_DATA_OUT => BUS_DATA_OUT, + BUS_WRITE_EN_IN => BUS_WRITE_EN_IN, + BUS_READ_EN_IN => BUS_READ_EN_IN, + BUS_ACK_OUT => BUS_ACK_OUT, + + -- output to gbe_buf + GBE_SUBEVENT_ID_OUT => cfg_subevent_id, + GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec, + GBE_QUEUE_DEC_OUT => cfg_queue_dec, + GBE_MAX_FRAME_OUT => cfg_max_frame, + GBE_USE_GBE_OUT => cfg_gbe_enable, + GBE_USE_TRBNET_OUT => cfg_ipu_enable, + GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable, + GBE_READOUT_CTR_OUT => cfg_readout_ctr, + GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid, + GBE_ALLOW_RX_OUT => cfg_allow_rx, + GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr, + GBE_INSERT_TTYPE_OUT => cfg_insert_ttype, + GBE_SOFT_RESET_OUT => cfg_soft_rst, + GBE_MAX_REPLY_OUT => cfg_max_reply, + GBE_MAX_SUB_OUT => cfg_max_sub, + GBE_MAX_QUEUE_OUT => cfg_max_queue, + GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue, + GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub, + MONITOR_RX_BYTES_IN => sum_rx_bytes, + MONITOR_RX_FRAMES_IN => sum_rx_frames, + MONITOR_TX_BYTES_IN => sum_tx_bytes, + MONITOR_TX_FRAMES_IN => sum_tx_frames, + MONITOR_TX_PACKETS_IN => sum_tx_packets, + MONITOR_DROPPED_IN => sum_dropped, + MONITOR_SELECT_REC_IN => (others => '0'), --dbg_select_rec, + MONITOR_SELECT_REC_BYTES_IN => (others => '0'), --dbg_select_rec_bytes, + MONITOR_SELECT_SENT_BYTES_IN => (others => '0'), --dbg_select_sent_bytes, + MONITOR_SELECT_SENT_IN => (others => '0'), --dbg_select_sent, + MONITOR_SELECT_DROP_IN_IN => (others => '0'), --dbg_select_drop_in, + MONITOR_SELECT_DROP_OUT_IN => (others => '0'), --dbg_select_drop_out, + MONITOR_SELECT_GEN_DBG_IN => (others => '0'), --dbg_select_gen, + + DUMMY_EVENT_SIZE_OUT => dummy_event, + DUMMY_TRIGGERED_MODE_OUT => dummy_mode, + DATA_HIST_IN => dbg_hist, + SCTRL_HIST_IN => dbg_hist2 + ); + end generate; + + setup_sim_gen : if (DO_SIMULATION = 1) generate + cfg_subevent_id <= x"12345678"; + cfg_subevent_dec <= x"00010002"; + cfg_queue_dec <= x"00030004"; + cfg_max_frame <= x"0578"; + cfg_gbe_enable <= '1'; + cfg_ipu_enable <= '1'; + cfg_mult_enable <= '0'; + cfg_readout_ctr <= x"000000"; + cfg_readout_ctr_valid <= '0'; + cfg_allow_rx <= '1'; + cfg_additional_hdr <= '0'; + cfg_insert_ttype <= '0'; + cfg_soft_rst <= '0'; + cfg_max_reply <= x"0000fff0"; + cfg_max_sub <= x"fff0"; + cfg_max_queue <= x"fff0"; + cfg_max_subs_in_queue <= x"0001"; + cfg_max_single_sub <= x"fff0"; + end generate; + + SCTRL_MAP_GEN : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate + ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(i) = '1') generate + mlt_gsc_clk(i) <= GSC_CLK_IN; + GSC_INIT_DATAREADY_OUT <= mlt_gsc_init_dataready(i); + GSC_INIT_DATA_OUT <= mlt_gsc_init_data((i + 1) * 16 - 1 downto i* 16); + GSC_INIT_PACKET_NUM_OUT <= mlt_gsc_init_packet((i + 1) * 3 - 1 downto i * 3); + mlt_gsc_init_read(i) <= GSC_INIT_READ_IN; + mlt_gsc_reply_dataready(i) <= GSC_REPLY_DATAREADY_IN; + mlt_gsc_reply_data((i + 1) * 16 - 1 downto i * 16) <= GSC_REPLY_DATA_IN; + mlt_gsc_reply_packet((i + 1) * 3 - 1 downto i * 3) <= GSC_REPLY_PACKET_NUM_IN; + GSC_REPLY_READ_OUT <= mlt_gsc_reply_read(i); + mlt_gsc_busy(i) <= GSC_BUSY_IN; + end generate ACTIVE_MAP_GEN; + + INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(i) = '0') generate + mlt_gsc_clk(i) <= '0'; + --GSC_INIT_DATAREADY_OUT <= '0'; + --GSC_INIT_DATA_OUT <= (others => '0'); + --GSC_INIT_PACKET_NUM_OUT <= (others => '0'); + mlt_gsc_init_read(i) <= '0'; + mlt_gsc_reply_dataready(i) <= '0'; + mlt_gsc_reply_data((i + 1) * 16 - 1 downto i * 16) <= (others => '0'); + mlt_gsc_reply_packet((i + 1) * 3 - 1 downto i * 3) <= (others => '0'); + --GSC_REPLY_READ_OUT <= '0'; + mlt_gsc_busy(i) <= '0'; + end generate INACTIVE_MAP_GEN; + end generate SCTRL_MAP_GEN; + + sum_rx_bytes <= monitor_rx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_rx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_rx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_rx_bytes(1 * 32 - 1 downto 0 * 32); + sum_rx_frames <= monitor_rx_frames(4 * 32 - 1 downto 3 * 32) + monitor_rx_frames(3 * 32 - 1 downto 2 * 32) + monitor_rx_frames(2 * 32 - 1 downto 1 * 32) + monitor_rx_frames(1 * 32 - 1 downto 0 * 32); + sum_tx_bytes <= monitor_tx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_tx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_tx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_tx_bytes(1 * 32 - 1 downto 0 * 32); + sum_tx_frames <= monitor_tx_frames(4 * 32 - 1 downto 3 * 32) + monitor_tx_frames(3 * 32 - 1 downto 2 * 32) + monitor_tx_frames(2 * 32 - 1 downto 1 * 32) + monitor_tx_frames(1 * 32 - 1 downto 0 * 32); + sum_tx_packets <= monitor_tx_packets(4 * 32 - 1 downto 3 * 32) + monitor_tx_packets(3 * 32 - 1 downto 2 * 32) + monitor_tx_packets(2 * 32 - 1 downto 1 * 32) + monitor_tx_packets(1 * 32 - 1 downto 0 * 32); + sum_dropped <= monitor_dropped(4 * 32 - 1 downto 3 * 32) + monitor_dropped(3 * 32 - 1 downto 2 * 32) + monitor_dropped(2 * 32 - 1 downto 1 * 32) + monitor_dropped(1 * 32 - 1 downto 0 * 32); + + include_debug_gen : if (INCLUDE_DEBUG = 1) generate + DEBUG_OUT(0) <= mac_an_ready(3); + DEBUG_OUT(1) <= clk_125_rx_from_pcs(3); + DEBUG_OUT(2) <= RESET; + DEBUG_OUT(3) <= CLK_125_IN; + + DEBUG_OUT(127 downto 4) <= (others => '0'); + end generate; + + + testbench_sim : if DO_SIMULATION = 1 generate + + clk_125_rx_from_pcs(0) <= CLK_125_IN; + clk_125_rx_from_pcs(1) <= CLK_125_IN; + clk_125_rx_from_pcs(2) <= CLK_125_IN; + clk_125_rx_from_pcs(3) <= CLK_125_IN; + + process + begin + mac_tx_done(0) <= '0'; + wait until rising_edge(mac_fifoeof(0)); + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_tx_done(0) <= '1'; + wait until rising_edge(clk_125_rx_from_pcs(0)); + end process; + + process + begin + mac_tx_done(1) <= '0'; + wait until rising_edge(mac_fifoeof(1)); + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_tx_done(1) <= '1'; + wait until rising_edge(clk_125_rx_from_pcs(0)); + end process; + + process(clk_125_rx_from_pcs(0)) + begin + if rising_edge(clk_125_rx_from_pcs(0)) then + mac_tx_read(0) <= mac_fifoavail(0); + mac_tx_read(1) <= mac_fifoavail(1); + mac_tx_read(2) <= mac_fifoavail(2); + mac_tx_read(3) <= mac_fifoavail(3); + end if; + end process; + + mac_rx_eof(1) <= mac_rx_eof(0); + mac_rx_eof(2) <= mac_rx_eof(0); + mac_rx_eof(3) <= mac_rx_eof(0); + mac_rx_write(1) <= mac_rx_write(0); + mac_rx_write(2) <= mac_rx_write(0); + mac_rx_write(3) <= mac_rx_write(0); + mac_rx_data(2 * 8 - 1 downto 1 * 8) <= mac_rx_data(1 * 8 - 1 downto 0 * 8); + mac_rx_data(3 * 8 - 1 downto 2 * 8) <= mac_rx_data(1 * 8 - 1 downto 0 * 8); + mac_rx_data(4 * 8 - 1 downto 3 * 8) <= mac_rx_data(1 * 8 - 1 downto 0 * 8); + + + testbench_proc : process + begin + + --trigger <= '0'; + --gbe_ready <= '0'; + mac_rx_write(0) <= '0'; + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + mac_rx_eof(0) <= '0'; + + wait for 5 us; + + -- FIRST FRAME UDP - DHCP Offer + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_write(0) <= '1'; + -- dest mac + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + -- src mac + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + -- frame type + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + -- ip headers + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"45"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"5a"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"49"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"11"; -- udp + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02"; + -- udp headers + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"43"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"44"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"2c"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb"; + -- dhcp data + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"06"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; --transcation id + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";--transcation id + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"fa";--transcation id + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ce";--transcation id + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10"; + + for i in 0 to 219 loop + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + end loop; + + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"35"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_eof(0) <= '1'; + + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_write(0) <='0'; + mac_rx_eof(0) <= '0'; + + wait for 6 us; + + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_write(0) <= '1'; + -- dest mac + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + -- src mac + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + -- frame type + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + -- ip headers + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"45"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"5a"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"49"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"11"; -- udp + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02"; + -- udp headers + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"43"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"44"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"2c"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb"; + -- dhcp data + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"06"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"fa"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ce"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10"; + + for i in 0 to 219 loop + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + end loop; + + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"35"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"05"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00"; + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_eof(0) <= '1'; + + wait until rising_edge(clk_125_rx_from_pcs(0)); + mac_rx_write(0) <='0'; + mac_rx_eof(0) <= '0'; + + + wait for 5 us; + + wait for 2 us; + + --gbe_ready <= '1'; + + wait for 1 us; + + --trigger <= '1'; + + wait; + + end process testbench_proc; + + end generate testbench_sim; + +end architecture RTL; diff --git a/gbe_trb/base/ip_configurator.vhd b/gbe_trb/base/ip_configurator.vhd new file mode 100755 index 0000000..d6b0778 --- /dev/null +++ b/gbe_trb/base/ip_configurator.vhd @@ -0,0 +1,342 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use IEEE.std_logic_arith.all; + +library work; + +entity ip_configurator is +port( + CLK : in std_logic; + RESET : in std_logic; + -- configuration interface + START_CONFIG_IN : in std_logic; -- start configuration run + BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank + CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used + MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for + MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory + MEM_CLK_OUT : out std_logic; -- clock for BlockRAM + -- information for IP cores + DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address + DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address + DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port + SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address + SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address + SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port + MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size) + -- Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end entity; + +architecture ip_configurator of ip_configurator is + +-- -- Placer Directives +-- attribute HGROUP : string; +-- -- for whole architecture +-- attribute HGROUP of ip_configurator : architecture is "GBE_conf_group"; + +type STATES is (IDLE, LOAD_REG, DELAY0, DELAY1, DELAY2, LOAD_DONE); +signal CURRENT_STATE, NEXT_STATE : STATES; +signal bsm : std_logic_vector(3 downto 0); +signal ce_ctr_comb : std_logic; +signal ce_ctr : std_logic; +signal rst_ctr_comb : std_logic; +signal rst_ctr : std_logic; +signal cfg_done_comb : std_logic; +signal cfg_done : std_logic; + +signal ctr_done_comb : std_logic; +signal ctr_done : std_logic; + +signal wr_select_comb : std_logic_vector(15 downto 0); +signal wr_select : std_logic_vector(15 downto 0); +signal wr_select_q : std_logic_vector(15 downto 0); + +signal addr_ctr : std_logic_vector(3 downto 0); +signal dest_mac : std_logic_vector(47 downto 0); +signal dest_ip : std_logic_vector(31 downto 0); +signal dest_udp : std_logic_vector(15 downto 0); +signal src_mac : std_logic_vector(47 downto 0); +signal src_ip : std_logic_vector(31 downto 0); +signal src_udp : std_logic_vector(15 downto 0); +signal mtu : std_logic_vector(15 downto 0); + +signal debug : std_logic_vector(31 downto 0); + +begin + + +-- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO +STATE_MACHINE_PROC: process( CLK ) +begin + if rising_edge(CLK) then + if RESET = '1' then + CURRENT_STATE <= IDLE; + ce_ctr <= '0'; + rst_ctr <= '0'; + cfg_done <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + ce_ctr <= ce_ctr_comb; + rst_ctr <= rst_ctr_comb; + cfg_done <= cfg_done_comb; + end if; + end if; +end process STATE_MACHINE_PROC; + +STATE_MACHINE_TRANS: process( CURRENT_STATE, START_CONFIG_IN, ctr_done ) +begin + NEXT_STATE <= IDLE; + ce_ctr_comb <= '0'; + rst_ctr_comb <= '0'; + cfg_done_comb <= '0'; + case CURRENT_STATE is + when IDLE => + bsm <= x"0"; + if( START_CONFIG_IN = '1' ) then + NEXT_STATE <= LOAD_REG; + ce_ctr_comb <= '1'; + else + NEXT_STATE <= IDLE; + end if; + when LOAD_REG => + bsm <= x"1"; + if( ctr_done = '1' ) then + NEXT_STATE <= DELAY0; + rst_ctr_comb <= '1'; + else + NEXT_STATE <= LOAD_REG; + ce_ctr_comb <= '1'; + end if; + when DELAY0 => + bsm <= x"2"; + NEXT_STATE <= DELAY1; + when DELAY1 => + bsm <= x"3"; + NEXT_STATE <= DELAY2; + when DELAY2 => + bsm <= x"4"; + NEXT_STATE <= LOAD_DONE; + cfg_done_comb <= '1'; + when LOAD_DONE => + bsm <= x"2"; + if( START_CONFIG_IN = '0' ) then + NEXT_STATE <= IDLE; + else + NEXT_STATE <= LOAD_DONE; + cfg_done_comb <= '1'; + end if; + when others => + bsm <= x"f"; + NEXT_STATE <= IDLE; + end case; +end process STATE_MACHINE_TRANS; + +-- address counter +THE_ADDR_CTR_PROC: process( CLK ) +begin + if ( rising_edge(CLK) ) then + if ( (RESET = '1') or (rst_ctr = '1') ) then + addr_ctr <= (others => '0'); + elsif( ce_ctr = '1' ) then + addr_ctr <= addr_ctr + 1; + end if; + end if; +end process THE_ADDR_CTR_PROC; + +ctr_done_comb <= '1' when (addr_ctr = x"e") else '0'; + +THE_SYNC_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + ctr_done <= ctr_done_comb; + wr_select_q <= wr_select; + wr_select <= wr_select_comb; + end if; +end process THE_SYNC_PROC; + +-- generate combinatorial write select signals, register and delay the (output registers in EBR!) +wr_select_comb(0) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"0") ) else '0'; -- dest MAC low +wr_select_comb(1) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"1") ) else '0'; -- dest MAC high +wr_select_comb(2) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"2") ) else '0'; -- dest IP +wr_select_comb(3) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"3") ) else '0'; -- dest port +wr_select_comb(4) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"4") ) else '0'; -- src MAC low +wr_select_comb(5) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"5") ) else '0'; -- src MAC high +wr_select_comb(6) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"6") ) else '0'; -- src IP +wr_select_comb(7) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"7") ) else '0'; -- src port +wr_select_comb(8) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"8") ) else '0'; -- MTU +wr_select_comb(9) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"9") ) else '0'; +wr_select_comb(10) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"a") ) else '0'; +wr_select_comb(11) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"b") ) else '0'; +wr_select_comb(12) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"c") ) else '0'; +wr_select_comb(13) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"d") ) else '0'; +wr_select_comb(14) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"e") ) else '0'; +wr_select_comb(15) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"f") ) else '0'; + +-- destination MAC low register +THE_D_MAC_LOW_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + dest_mac(31 downto 0) <= (others => '0'); + elsif( wr_select_q(0) = '1') then + dest_mac(31 downto 0) <= mem_data_in; + end if; + end if; +end process THE_D_MAC_LOW_PROC; + +-- destination MAC high register +THE_D_MAC_HIGH_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + dest_mac(47 downto 32) <= (others => '0'); + elsif( wr_select_q(1) = '1') then + dest_mac(47 downto 32) <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_D_MAC_HIGH_PROC; + +-- destination IP register +THE_D_IP_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + dest_ip <= (others => '0'); + elsif( wr_select_q(2) = '1') then + dest_ip <= mem_data_in; + end if; + end if; +end process THE_D_IP_PROC; + +-- destination PORT register +THE_D_PORT_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + dest_udp <= (others => '0'); + elsif( wr_select_q(3) = '1') then + dest_udp <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_D_PORT_PROC; + +-- source MAC low register +THE_S_MAC_LOW_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + src_mac(31 downto 0) <= (others => '0'); + elsif( wr_select_q(4) = '1') then + src_mac(31 downto 0) <= mem_data_in; + end if; + end if; +end process THE_S_MAC_LOW_PROC; + +-- source MAC high register +THE_S_MAC_HIGH_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + src_mac(47 downto 32) <= (others => '0'); + elsif( wr_select_q(5) = '1') then + src_mac(47 downto 32) <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_S_MAC_HIGH_PROC; + +-- source IP register +THE_S_IP_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + src_ip <= (others => '0'); + elsif( wr_select_q(6) = '1') then + src_ip <= mem_data_in; + end if; + end if; +end process THE_S_IP_PROC; + +-- source PORT register +THE_S_PORT_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + src_udp <= (others => '0'); + elsif( wr_select_q(7) = '1') then + src_udp <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_S_PORT_PROC; + +-- MTU size register +THE_MTU_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then + if ( RESET = '1' ) then + mtu <= (others => '0'); + elsif( wr_select_q(8) = '1') then + mtu <= mem_data_in(15 downto 0); + end if; + end if; +end process THE_MTU_PROC; + + +-- Debug signals +debug(31 downto 12) <= (others => '0'); +debug(11 downto 8) <= addr_ctr; +debug(7) <= '0'; +debug(6) <= ctr_done; +debug(5) <= ce_ctr; +debug(4) <= rst_ctr; +debug(3 downto 0) <= bsm; +-- Outputs +MEM_ADDR_OUT(7 downto 4) <= BANK_SELECT_IN; +MEM_ADDR_OUT(3 downto 0) <= addr_ctr; +MEM_CLK_OUT <= CLK; +CONFIG_DONE_OUT <= cfg_done; + +-- destination MAC address - swap for user convinience +DEST_MAC_OUT(47 downto 40) <= dest_mac(7 downto 0); +DEST_MAC_OUT(39 downto 32) <= dest_mac(15 downto 8); +DEST_MAC_OUT(31 downto 24) <= dest_mac(23 downto 16); +DEST_MAC_OUT(23 downto 16) <= dest_mac(31 downto 24); +DEST_MAC_OUT(15 downto 8) <= dest_mac(39 downto 32); +DEST_MAC_OUT(7 downto 0) <= dest_mac(47 downto 40); + +-- destination IP address - swap for user convinience +DEST_IP_OUT(31 downto 24) <= dest_ip(7 downto 0); +DEST_IP_OUT(23 downto 16) <= dest_ip(15 downto 8); +DEST_IP_OUT(15 downto 8) <= dest_ip(23 downto 16); +DEST_IP_OUT(7 downto 0) <= dest_ip(31 downto 24); + +-- destination port address - swap for user convinience +DEST_UDP_OUT(15 downto 8) <= dest_udp(7 downto 0); +DEST_UDP_OUT(7 downto 0) <= dest_udp(15 downto 8); + +-- source MAC address - swap for user convinience +SRC_MAC_OUT(47 downto 40) <= src_mac(7 downto 0); +SRC_MAC_OUT(39 downto 32) <= src_mac(15 downto 8); +SRC_MAC_OUT(31 downto 24) <= src_mac(23 downto 16); +SRC_MAC_OUT(23 downto 16) <= src_mac(31 downto 24); +SRC_MAC_OUT(15 downto 8) <= src_mac(39 downto 32); +SRC_MAC_OUT(7 downto 0) <= src_mac(47 downto 40); + +-- source IP address - swap for user convinience +SRC_IP_OUT(31 downto 24) <= src_ip(7 downto 0); +SRC_IP_OUT(23 downto 16) <= src_ip(15 downto 8); +SRC_IP_OUT(15 downto 8) <= src_ip(23 downto 16); +SRC_IP_OUT(7 downto 0) <= src_ip(31 downto 24); + +-- source port address - swap for user convinience +SRC_UDP_OUT(15 downto 8) <= src_udp(7 downto 0); +SRC_UDP_OUT(7 downto 0) <= src_udp(15 downto 8); + +-- DO NOT SWAP! +MTU_OUT <= mtu; + +DEBUG_OUT <= debug; + +end architecture; \ No newline at end of file diff --git a/gbe_trb/base/trb_net16_gbe_event_constr.vhd b/gbe_trb/base/trb_net16_gbe_event_constr.vhd new file mode 100644 index 0000000..df3cc90 --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_event_constr.vhd @@ -0,0 +1,780 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.std_logic_UNSIGNED.all; +use IEEE.std_logic_arith.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +entity trb_net16_gbe_event_constr is + generic( + READOUT_BUFFER_SIZE : integer range 1 to 4 := 1; + DO_SIMULATION : integer range 0 to 1 := 0 + ); + port( + RESET : in std_logic; + CLK : in std_logic; + -- ports for user logic + PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic + PC_DATA_IN : in std_logic_vector(7 downto 0); + PC_READY_OUT : out std_logic; + PC_START_OF_SUB_IN : in std_logic; + PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 + PC_END_OF_QUEUE_IN : in std_logic; + -- queue and subevent layer headers + PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap + PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap + PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap + PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! + PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); + PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap + PC_INSERT_TTYPE_IN : in std_logic; + -- FrameConstructor ports + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_SOD_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); +end entity trb_net16_gbe_event_constr; + +architecture RTL of trb_net16_gbe_event_constr is + attribute syn_encoding : string; + + type loadStates is (IDLE, GET_Q_SIZE, START_TRANSFER, LOAD_Q_HEADERS, LOAD_DATA, LOAD_SUB, LOAD_PADDING, LOAD_TERM, CLEANUP); + signal load_current_state, load_next_state : loadStates; + attribute syn_encoding of load_current_state : signal is "onehot"; + + type saveSubHdrStates is (IDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRG_NR); + signal save_sub_hdr_current_state, save_sub_hdr_next_state : saveSubHdrStates; + attribute syn_encoding of save_sub_hdr_current_state : signal is "onehot"; + + signal df_eos, df_wr_en, df_rd_en, df_empty, df_full, load_eod : std_logic; + signal df_q, df_qq : std_logic_vector(7 downto 0); + + signal header_ctr : integer range 0 to 31; + + signal shf_data, shf_q, shf_qq : std_logic_vector(7 downto 0); + signal shf_wr_en, shf_rd_en, shf_empty, shf_full : std_logic; + signal sub_int_ctr : integer range 0 to 3; + signal sub_size_to_save : std_logic_vector(31 downto 0); + + signal qsf_data : std_logic_vector(31 downto 0); + signal qsf_q : std_logic_vector(7 downto 0); + signal qsf_wr, qsf_wr_en, qsf_wr_en_q, qsf_wr_en_qq, qsf_wr_en_qqq, qsf_rd_en, qsf_rd_en_q, qsf_empty : std_logic; + + signal queue_size : std_logic_vector(31 downto 0); + + signal termination : std_logic_vector(255 downto 0); + signal term_ctr : integer range 0 to 33; + + signal actual_q_size : std_logic_vector(15 downto 0); + signal tc_data : std_logic_vector(7 downto 0); + signal df_data : std_logic_vector(7 downto 0); + signal df_eos_q, df_eos_qq : std_logic; + signal df_wr_en_q, df_wr_en_qq : std_logic; + signal qsf_full : std_logic; + + signal padding_needed, insert_padding : std_logic; + signal load_eod_q : std_logic; + signal loaded_queue_bytes : std_logic_vector(15 downto 0); + signal shf_padding : std_logic; + signal block_shf_after_divide, previous_tc_rd : std_logic; + signal block_term_after_divide : std_logic; + signal df_full_real, df_afull : std_logic; + +begin + + --******* + -- SAVING PART + --******* + + DF_EOD_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (PC_END_OF_SUB_IN = '1') then + df_eos <= '1'; + else + df_eos <= '0'; + end if; + + df_eos_q <= df_eos; + df_eos_qq <= df_eos_q; + end if; + end process DF_EOD_PROC; + + DF_WR_EN_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (PC_WR_EN_IN = '1') then + df_wr_en <= '1'; + else + df_wr_en <= '0'; + end if; + + df_wr_en_q <= df_wr_en; + df_wr_en_qq <= df_wr_en_q; + + df_data <= PC_DATA_IN; + end if; + end process DF_WR_EN_PROC; + + df_64k_gen : if READOUT_BUFFER_SIZE = 4 generate + DATA_FIFO : entity work.fifo_64kx9_af + port map( + Data(7 downto 0) => df_data, + Data(8) => df_eos_q, + WrClock => CLK, + RdClock => CLK, + WrEn => df_wr_en_qq, + RdEn => df_rd_en, + Reset => RESET, + RPReset => RESET, + Q(7 downto 0) => df_q, + Q(8) => load_eod, + Empty => df_empty, + Full => df_full_real, + AlmostFull => df_afull + ); + end generate df_64k_gen; + + df_8k_gen : if READOUT_BUFFER_SIZE = 2 generate + DATA_FIFO : entity work.fifo_8kx9 + port map( + Data(7 downto 0) => df_data, + Data(8) => df_eos_q, + WrClock => CLK, + RdClock => CLK, + WrEn => df_wr_en_qq, + RdEn => df_rd_en, + Reset => RESET, + RPReset => RESET, + Q(7 downto 0) => df_q, + Q(8) => load_eod, + Empty => df_empty, + Full => df_full_real + ); + end generate df_8k_gen; + + df_4k_gen : if READOUT_BUFFER_SIZE = 1 generate + DATA_FIFO : fifo_4096x9 + port map( + Data(7 downto 0) => df_data, + Data(8) => df_eos_q, + WrClock => CLK, + RdClock => CLK, + WrEn => df_wr_en_qq, + RdEn => df_rd_en, + Reset => RESET, + RPReset => RESET, + Q(7 downto 0) => df_q, + Q(8) => load_eod, + Empty => df_empty, + Full => df_full_real + ); + end generate df_4k_gen; + + DF_QQ_PROC : process(CLK) + begin + if rising_edge(CLK) then + df_qq <= df_q; + end if; + end process DF_QQ_PROC; + + ready_impl_gen : if DO_SIMULATION = 0 generate + READY_PROC : process(CLK) + begin + if rising_edge(CLK) then + PC_READY_OUT <= not df_full; + end if; + end process READY_PROC; + + df_full <= df_afull; --df_full_real; + end generate ready_impl_gen; + + ready_sim_gen : if DO_SIMULATION = 1 generate + + +-- FULL_PROC : process +-- begin +-- df_full <= '0'; +-- +-- wait for 22000 ns; +-- wait until rising_edge(CLK); +-- df_full <= '1'; +-- wait until rising_edge(CLK); +-- wait until rising_edge(CLK); +-- wait until rising_edge(CLK); +-- df_full <= '0'; +-- +-- wait; +-- end process FULL_PROC; + + df_full <= df_afull; + + READY_PROC : process(CLK) + begin + if rising_edge(CLK) then + PC_READY_OUT <= not df_full; + end if; + end process READY_PROC; + + end generate ready_sim_gen; + + --***** + -- subevent headers + SUBEVENT_HEADERS_FIFO : fifo_4096x9 --fifo_4kx8_ecp3 + port map( + Data(7 downto 0) => shf_data, + Data(8) => PC_SUB_SIZE_IN(2), + WrClock => CLK, + RdClock => CLK, + WrEn => shf_wr_en, + RdEn => shf_rd_en, + Reset => RESET, + RPReset => RESET, + Q(7 downto 0) => shf_q, + Q(8) => shf_padding, + Empty => shf_empty, + Full => shf_full + ); + + SHF_WR_EN_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (save_sub_hdr_current_state = IDLE) then + shf_wr_en <= '0'; + else + shf_wr_en <= '1'; + end if; + end if; + end process SHF_WR_EN_PROC; + + VARIOUS_SYNC : process(CLK) + begin + if rising_edge(CLK) then + shf_qq <= shf_q; + end if; + end process VARIOUS_SYNC; + + SAVE_SUB_HDR_MACHINE_PROC : process(RESET, CLK) + begin + if RESET = '1' then + save_sub_hdr_current_state <= IDLE; + elsif rising_edge(CLK) then + save_sub_hdr_current_state <= save_sub_hdr_next_state; + end if; + end process SAVE_SUB_HDR_MACHINE_PROC; + + SAVE_SUB_HDR_MACHINE : process(save_sub_hdr_current_state, PC_START_OF_SUB_IN, sub_int_ctr) + begin + case (save_sub_hdr_current_state) is + when IDLE => + if (PC_START_OF_SUB_IN = '1') then + save_sub_hdr_next_state <= SAVE_SIZE; + else + save_sub_hdr_next_state <= IDLE; + end if; + + when SAVE_SIZE => + if (sub_int_ctr = 0) then + save_sub_hdr_next_state <= SAVE_DECODING; + else + save_sub_hdr_next_state <= SAVE_SIZE; + end if; + + when SAVE_DECODING => + if (sub_int_ctr = 0) then + save_sub_hdr_next_state <= SAVE_ID; + else + save_sub_hdr_next_state <= SAVE_DECODING; + end if; + + when SAVE_ID => + if (sub_int_ctr = 0) then + save_sub_hdr_next_state <= SAVE_TRG_NR; + else + save_sub_hdr_next_state <= SAVE_ID; + end if; + + when SAVE_TRG_NR => + if (sub_int_ctr = 0) then + save_sub_hdr_next_state <= IDLE; + else + save_sub_hdr_next_state <= SAVE_TRG_NR; + end if; + + when others => save_sub_hdr_next_state <= IDLE; + + end case; + end process SAVE_SUB_HDR_MACHINE; + + SUB_INT_CTR_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (save_sub_hdr_current_state = IDLE) then + sub_int_ctr <= 3; + else + if (sub_int_ctr = 0) then + sub_int_ctr <= 3; + else + sub_int_ctr <= sub_int_ctr - 1; + end if; + end if; + end if; + end process SUB_INT_CTR_PROC; + + SUB_SIZE_TO_SAVE_PROC : process(CLK) + begin + if rising_edge(CLK) then + sub_size_to_save <= PC_SUB_SIZE_IN + x"10" + x"8"; -- addition for subevent headers and subsubevent + end if; + end process SUB_SIZE_TO_SAVE_PROC; + + SHF_DATA_PROC : process(CLK) + begin + if rising_edge(CLK) then + case (save_sub_hdr_current_state) is + when IDLE => + shf_data <= x"ac"; + + when SAVE_SIZE => + shf_data <= sub_size_to_save(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); + + when SAVE_DECODING => + if (PC_INSERT_TTYPE_IN = '0') then + shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); + else + if (sub_int_ctr = 0) then + shf_data(3 downto 0) <= PC_DECODING_IN(3 downto 0); + shf_data(7 downto 4) <= PC_TRIGGER_TYPE_IN; + else + shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); + end if; + end if; + + when SAVE_ID => + shf_data <= PC_EVENT_ID_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); + + when SAVE_TRG_NR => + shf_data <= PC_TRIG_NR_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); + + when others => shf_data <= x"00"; + + end case; + end if; + end process SHF_DATA_PROC; + + --******* + -- queue sizes + + QUEUE_SIZE_FIFO : fifo_512x32x8 + port map( + Data => qsf_data, + WrClock => CLK, + RdClock => CLK, + WrEn => qsf_wr, + RdEn => qsf_rd_en, + Reset => RESET, + RPReset => RESET, + Q => qsf_q, + Empty => qsf_empty, + Full => qsf_full + ); + + qsf_wr <= qsf_wr_en_qqq or qsf_wr_en_qq or qsf_wr_en_q; + + QSF_DATA_PROC : process(CLK) + begin + if rising_edge(CLK) then + -- queue size is saved twice in a row to facilitate readout and packet construction + if (qsf_wr_en = '1' or qsf_wr_en_q = '1') then + if (qsf_wr_en = '1' and qsf_wr_en_q = '0') then + qsf_data(7) <= padding_needed; + qsf_data(6 downto 0) <= (others => '0'); + else + qsf_data(7 downto 0) <= queue_size(31 downto 24); + end if; + qsf_data(15 downto 8) <= queue_size(23 downto 16); + qsf_data(23 downto 16) <= queue_size(15 downto 8); + qsf_data(31 downto 24) <= queue_size(7 downto 0); + elsif (qsf_wr_en_qq = '1') then + qsf_data(7 downto 0) <= PC_QUEUE_DEC_IN(31 downto 24); + qsf_data(15 downto 8) <= PC_QUEUE_DEC_IN(23 downto 16); + qsf_data(23 downto 16) <= PC_QUEUE_DEC_IN(15 downto 8); + qsf_data(31 downto 24) <= PC_QUEUE_DEC_IN(7 downto 0); + else + qsf_data <= (others => '1'); + end if; + end if; + end process QSF_DATA_PROC; + + QSF_WR_PROC : process(CLK) + begin + if rising_edge(CLK) then + qsf_wr_en_q <= qsf_wr_en; + qsf_wr_en_qq <= qsf_wr_en_q; + qsf_wr_en_qqq <= qsf_wr_en_qq; + + qsf_wr_en <= PC_END_OF_QUEUE_IN; + end if; + end process QSF_WR_PROC; + + QUEUE_SIZE_PROC : process(RESET, CLK) + begin + if RESET = '1' then + queue_size <= x"0000_0008"; -- queue headers + elsif rising_edge(CLK) then + if (qsf_wr_en_qqq = '1') then + queue_size <= x"0000_0008"; + elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then + if (PC_SUB_SIZE_IN(2) = '1') then + queue_size <= queue_size + PC_SUB_SIZE_IN + x"4" + x"10" + x"8"; -- subevent data size + padding + subevent headers + subsubevent + else + queue_size <= queue_size + PC_SUB_SIZE_IN + x"10" + x"8"; -- subevent data size + subevent headers + subsubevent + end if; + else + queue_size <= queue_size; + end if; + end if; + end process QUEUE_SIZE_PROC; + + process(CLK) + begin + if rising_edge(CLK) then + if (PC_START_OF_SUB_IN = '1') then + padding_needed <= '0'; + elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then + if (PC_SUB_SIZE_IN(2) = '1') then + padding_needed <= '1'; + else + padding_needed <= '0'; + end if; + else + padding_needed <= padding_needed; + end if; + end if; + end process; + + --******* + -- LOADING PART + --******* + + size_check_debug : if DO_SIMULATION = 1 generate + process(df_q, loaded_queue_bytes, load_current_state) + begin + if (loaded_queue_bytes > x"0021" and load_current_state = LOAD_DATA and loaded_queue_bytes(0) = '0') then + assert (df_q - x"0020" = loaded_queue_bytes(15 downto 1)) report "EVT_CONSTR: Mismatch between data and internal counters" severity warning; + end if; + end process; + + end generate size_check_debug; + + LOAD_MACHINE_PROC : process(RESET, CLK) is + begin + if RESET = '1' then + load_current_state <= IDLE; + elsif rising_edge(CLK) then + load_current_state <= load_next_state; + end if; + end process LOAD_MACHINE_PROC; + + LOAD_MACHINE : process(load_current_state, qsf_empty, header_ctr, load_eod_q, term_ctr, insert_padding, loaded_queue_bytes, actual_q_size) + begin + case (load_current_state) is + when IDLE => + if (qsf_empty = '0') then -- something in queue sizes fifo means entire queue is waiting + load_next_state <= GET_Q_SIZE; + else + load_next_state <= IDLE; + end if; + + when GET_Q_SIZE => + if (header_ctr = 0) then + load_next_state <= START_TRANSFER; + else + load_next_state <= GET_Q_SIZE; + end if; + + when START_TRANSFER => + load_next_state <= LOAD_Q_HEADERS; + + when LOAD_Q_HEADERS => + if (header_ctr = 0) then + load_next_state <= LOAD_SUB; + else + load_next_state <= LOAD_Q_HEADERS; + end if; + + when LOAD_SUB => + if (header_ctr = 0) then + load_next_state <= LOAD_DATA; + else + load_next_state <= LOAD_SUB; + end if; + + when LOAD_DATA => + if (load_eod_q = '1' and term_ctr = 33) then + if (insert_padding = '1') then + load_next_state <= LOAD_PADDING; + else + if (loaded_queue_bytes = actual_q_size) then + load_next_state <= LOAD_TERM; + else + load_next_state <= LOAD_SUB; + end if; + end if; + else + load_next_state <= LOAD_DATA; + end if; + + when LOAD_PADDING => + if (header_ctr = 0) then + if (loaded_queue_bytes = actual_q_size) then + load_next_state <= LOAD_TERM; + else + load_next_state <= LOAD_SUB; + end if; + else + load_next_state <= LOAD_PADDING; + end if; + + when LOAD_TERM => + if (header_ctr = 0) then + load_next_state <= CLEANUP; + else + load_next_state <= LOAD_TERM; + end if; + + when CLEANUP => + load_next_state <= IDLE; + + end case; + end process LOAD_MACHINE; + + process(CLK) + begin + if rising_edge(CLK) then + load_eod_q <= load_eod; + end if; + end process; + + HEADER_CTR_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (load_current_state = IDLE) then + header_ctr <= 3; + elsif (load_current_state = GET_Q_SIZE and header_ctr = 0) then + header_ctr <= 8; + elsif (load_current_state = LOAD_Q_HEADERS and header_ctr = 0) then + header_ctr <= 15; + elsif (load_current_state = LOAD_SUB and header_ctr = 0) then + if (insert_padding = '1') then + header_ctr <= 3; + else + header_ctr <= 31; + end if; + elsif (load_current_state = LOAD_PADDING and header_ctr = 0) then + if (loaded_queue_bytes = actual_q_size) then + header_ctr <= 31; + else + header_ctr <= 15; + end if; + elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes = actual_q_size and insert_padding = '0') then + header_ctr <= 31; + elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes /= actual_q_size and insert_padding = '0') then + header_ctr <= 15; + elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes /= actual_q_size and insert_padding = '1') then + header_ctr <= 3; + elsif (load_current_state = LOAD_TERM and header_ctr = 0) then + header_ctr <= 3; + elsif (TC_RD_EN_IN = '1') then + if (load_current_state = LOAD_Q_HEADERS or load_current_state = LOAD_TERM or load_current_state = LOAD_PADDING) then + if (load_current_state = LOAD_TERM) then + if (block_term_after_divide = '1') then + header_ctr <= 31; + else + header_ctr <= header_ctr - 1; + end if; + else + header_ctr <= header_ctr - 1; + end if; + elsif (load_current_state = LOAD_SUB and block_shf_after_divide = '0') then + header_ctr <= header_ctr - 1; + else + header_ctr <= header_ctr; + end if; + elsif (load_current_state = GET_Q_SIZE) then + header_ctr <= header_ctr - 1; + else + header_ctr <= header_ctr; + end if; + end if; + end process HEADER_CTR_PROC; + + SIZE_FOR_PADDING_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (load_current_state = IDLE) then + insert_padding <= '0'; + elsif (load_current_state = LOAD_SUB and header_ctr = 12) then + insert_padding <= shf_padding; + else + insert_padding <= insert_padding; + end if; + end if; + end process SIZE_FOR_PADDING_PROC; + + TC_SOD_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (load_current_state = START_TRANSFER) then + TC_SOD_OUT <= '1'; + else + TC_SOD_OUT <= '0'; + end if; + end if; + end process TC_SOD_PROC; + + process(CLK) + begin + if rising_edge(CLK) then + if (load_current_state = IDLE) then + loaded_queue_bytes <= (others => '0'); + elsif (TC_RD_EN_IN = '1') then + loaded_queue_bytes <= loaded_queue_bytes + x"1"; + else + loaded_queue_bytes <= loaded_queue_bytes; + end if; + end if; + end process; + + --***** + -- read from fifos + + df_rd_en <= '1' when (load_current_state = LOAD_DATA and TC_RD_EN_IN = '1' and load_eod_q = '0') or (load_current_state = LOAD_SUB and header_ctr = 0 and TC_RD_EN_IN = '1') + else '0'; + + shf_rd_en <= '1' when (load_current_state = LOAD_SUB and TC_RD_EN_IN = '1' and header_ctr /= 0 and block_shf_after_divide = '0') or (load_current_state = LOAD_Q_HEADERS and header_ctr = 0 and TC_RD_EN_IN = '1') or (load_current_state = LOAD_DATA and load_eod_q = '1' and (loaded_queue_bytes + /= actual_q_size) and (loaded_queue_bytes + x"4" /= actual_q_size)) + else '0'; + + -- nasty workaround for the case when the packet is divided on LOAD_SUB state + process(CLK) + begin + if rising_edge(CLK) then + previous_tc_rd <= TC_RD_EN_IN; + end if; + end process; + block_shf_after_divide <= '1' when previous_tc_rd = '0' and TC_RD_EN_IN = '1' and header_ctr = 15 else '0'; + block_term_after_divide <= '1' when previous_tc_rd = '0' and TC_RD_EN_IN = '1' and header_ctr = 31 else '0'; + + QUEUE_FIFO_RD_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (load_current_state = GET_Q_SIZE and header_ctr /= 0) then + qsf_rd_en_q <= '1'; + elsif (load_current_state = IDLE and qsf_empty = '0') then + qsf_rd_en_q <= '1'; + else + qsf_rd_en_q <= '0'; + end if; + end if; + end process QUEUE_FIFO_RD_PROC; + + qsf_rd_en <= '1' when load_current_state = LOAD_Q_HEADERS and TC_RD_EN_IN = '1' and header_ctr /= 0 else qsf_rd_en_q; + + ACTUAL_Q_SIZE_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (load_current_state = START_TRANSFER) then + actual_q_size(7 downto 0) <= qsf_q; + elsif (load_current_state = GET_Q_SIZE and header_ctr = 0) then + actual_q_size(15 downto 8) <= qsf_q; + end if; + end if; + end process ACTUAL_Q_SIZE_PROC; + + TC_EVENT_SIZE_OUT <= actual_q_size; -- queue size without termination + + TERMINATION_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (load_current_state = IDLE) then + termination(255 downto 8) <= (others => '0'); + elsif (TC_RD_EN_IN = '1' and term_ctr /= 33 and term_ctr /= 0) then + termination(255 downto 8) <= termination(247 downto 0); + else + termination(255 downto 8) <= termination(255 downto 8); + end if; + end if; + end process TERMINATION_PROC; + + term_bits_gen : for I in 0 to 7 generate + process(CLK) + begin + if rising_edge(CLK) then + if (TC_RD_EN_IN = '1' and term_ctr /= 33 and term_ctr /= 0) then + case (load_current_state) is + when LOAD_Q_HEADERS => termination(I) <= qsf_q(I); + when LOAD_SUB => termination(I) <= shf_q(I); + when LOAD_DATA => termination(I) <= df_q(I); + when others => termination(I) <= '0'; + end case; + else + termination(I) <= termination(I); + end if; + end if; + end process; + end generate term_bits_gen; + + TERM_CTR_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (load_current_state = IDLE) then + term_ctr <= 0; + elsif (TC_RD_EN_IN = '1' and term_ctr /= 33) then + term_ctr <= term_ctr + 1; + end if; + end if; + end process TERM_CTR_PROC; + + TC_DATA_PROC : process(CLK) + begin + if rising_edge(CLK) then + case (load_current_state) is + when LOAD_Q_HEADERS => tc_data <= qsf_q; + when LOAD_SUB => tc_data <= shf_q; + when LOAD_DATA => tc_data <= df_q; + when LOAD_PADDING => tc_data <= x"aa"; + when LOAD_TERM => tc_data <= termination((header_ctr + 1) * 8 - 1 downto header_ctr * 8); + when others => tc_data <= x"cc"; + end case; + end if; + end process TC_DATA_PROC; + + TC_DATA_OUT(7 downto 0) <= tc_data; + TC_DATA_8_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (load_current_state = LOAD_TERM and header_ctr = 0) then + TC_DATA_OUT(8) <= '1'; + else + TC_DATA_OUT(8) <= '0'; + end if; + end if; + end process TC_DATA_8_PROC; + + --***** + -- outputs + + + DEBUG_OUT <= (others => '0'); + +end architecture RTL; diff --git a/gbe_trb/base/trb_net16_gbe_frame_constr.vhd b/gbe_trb/base/trb_net16_gbe_frame_constr.vhd new file mode 100755 index 0000000..9db9170 --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_frame_constr.vhd @@ -0,0 +1,668 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +entity trb_net16_gbe_frame_constr is + generic ( + FRAME_BUFFER_SIZE : integer range 1 to 4 := 1 + ); +port( + -- ports for user logic + RESET : in std_logic; + CLK : in std_logic; + LINK_OK_IN : in std_logic; -- gk 03.08.10 + -- + WR_EN_IN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + START_OF_DATA_IN : in std_logic; + END_OF_DATA_IN : in std_logic; + IP_F_SIZE_IN : in std_logic_vector(15 downto 0); + UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation + HEADERS_READY_OUT : out std_logic; + READY_OUT : out std_logic; + DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + FRAME_TYPE_IN : in std_logic_vector(15 downto 0); + IHL_VERSION_IN : in std_logic_vector(7 downto 0); + TOS_IN : in std_logic_vector(7 downto 0); + IDENTIFICATION_IN : in std_logic_vector(15 downto 0); + FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); + TTL_IN : in std_logic_vector(7 downto 0); + PROTOCOL_IN : in std_logic_vector(7 downto 0); + FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10 + -- ports for packetTransmitter + RD_CLK : in std_logic; -- 125MHz clock!!! + FT_DATA_OUT : out std_logic_vector(8 downto 0); + FT_TX_EMPTY_OUT : out std_logic; + FT_TX_RD_EN_IN : in std_logic; + FT_START_OF_PACKET_OUT : out std_logic; + FT_TX_DONE_IN : in std_logic; + FT_TX_DISCFRM_IN : in std_logic; + + MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_frame_constr; + +architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_frame_constr : architecture is "GBE_LINK_group"; + +component fifo_4096x9 is --fifo_8kx9 is +port( + Data : in std_logic_vector(8 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_8kx9 is +port( + Data : in std_logic_vector(8 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +attribute syn_encoding : string; + +type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION, + TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS, + SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH, + UDP_CS, SAVE_DATA, CLEANUP, DELAY); +signal constructCurrentState, constructNextState : constructStates; +signal bsm_constr : std_logic_vector(7 downto 0); +attribute syn_encoding of constructCurrentState: signal is "onehot"; + +type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP); +signal transmitCurrentState, transmitNextState : transmitStates; +attribute syn_encoding of transmitCurrentState : signal is "onehot"; + +signal bsm_trans : std_logic_vector(3 downto 0); + +signal headers_int_counter : integer range 0 to 6; +signal fpf_data : std_logic_vector(7 downto 0); +signal fpf_empty : std_logic; +signal fpf_full : std_logic; +signal fpf_wr_en : std_logic; +signal fpf_rd_en : std_logic; +signal fpf_q : std_logic_vector(8 downto 0); +signal ip_size : std_logic_vector(15 downto 0); +signal ip_checksum : std_logic_vector(31 downto 0); +signal udp_size : std_logic_vector(15 downto 0); +signal udp_checksum : std_logic_vector(15 downto 0); +signal ft_sop : std_logic; +signal put_udp_headers : std_logic; +signal ready_frames_ctr : std_logic_vector(15 downto 0) := x"0000"; +signal sent_frames_ctr : std_logic_vector(15 downto 0) := x"0000"; +signal debug : std_logic_vector(63 downto 0); +signal ready : std_logic; +signal headers_ready : std_logic; + +signal cur_max : integer range 0 to 10; + +signal ready_frames_ctr_q : std_logic_vector(15 downto 0) := x"0000"; +signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10 + +signal fpf_reset : std_logic; -- gk 01.01.01 +signal link_ok_125, link_ok_q : std_logic; + +-- gk 09.12.10 +signal delay_ctr : std_logic_vector(31 downto 0); +signal frame_delay_reg : std_logic_vector(31 downto 0); +signal fpf_data_q : std_logic_vector(7 downto 0); +signal fpf_wr_en_q, fpf_eod : std_logic; + +signal mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0); + +begin + +-- Fakes +udp_checksum <= x"0000"; -- no checksum test needed +--debug <= (others => '0'); + +process(CLK) +begin + if rising_edge(CLK) then + if constructCurrentState = IDLE then + ready <= '1'; + else + ready <= '0'; + end if; + + if (constructCurrentState = SAVE_DATA) then + headers_ready <= '1'; + else + headers_ready <= '0'; + end if; + end if; +end process; +--ready <= '1' when (constructCurrentState = IDLE) +-- else '0'; +--headers_ready <= '1' when (constructCurrentState = SAVE_DATA) +-- else '0'; + +sizeProc: process(CLK) -- put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN, DEST_UDP_PORT_IN) +begin + if rising_edge(CLK) then + if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then + ip_size <= IP_F_SIZE_IN + x"14" + x"8"; + udp_size <= UDP_P_SIZE_IN + x"8"; + else + ip_size <= IP_F_SIZE_IN + x"14"; + udp_size <= UDP_P_SIZE_IN; + end if; + end if; +end process sizeProc; + +ipCsProc : process(CLK) +begin + if rising_edge(CLK) then + if (constructCurrentState = IDLE) then + ip_checksum <= x"00000000"; + else + case constructCurrentState is + when DEST_MAC_ADDR => + case headers_int_counter is + when 0 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(7 downto 0); + when 1 => + ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(15 downto 8); + when 2 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(23 downto 16); + when 3 => + ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(31 downto 24); + when 4 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(7 downto 0); + when 5 => + ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(15 downto 8); + when others => null; + end case; + when SRC_MAC_ADDR => + case headers_int_counter is + when 0 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(23 downto 16); + when 1 => + ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(31 downto 24); + when 2 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IHL_VERSION_IN; + when 3 => + ip_checksum <= ip_checksum + TOS_IN; + when 4 => + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + ip_size(15 downto 8); + when 5 => + ip_checksum <= ip_checksum + ip_size(7 downto 0); + when others => null; + end case; + when VERSION => + if headers_int_counter = 0 then + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IDENTIFICATION_IN(7 downto 0); + end if; + when TOS_S => + if headers_int_counter = 0 then + ip_checksum <= ip_checksum + IDENTIFICATION_IN(15 downto 8); + end if; + when IP_LENGTH => + if headers_int_counter = 0 then + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + FLAGS_OFFSET_IN(15 downto 8); + elsif headers_int_counter = 1 then + ip_checksum <= ip_checksum + FLAGS_OFFSET_IN(7 downto 0); + end if; + when IDENT => + if headers_int_counter = 0 then + ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + TTL_IN; + elsif headers_int_counter = 1 then + ip_checksum <= ip_checksum + PROTOCOL_IN; + end if; + -- gk 29.03.10 corrected the bug with bad checksums when sum larger than 16b + when FLAGS => + if headers_int_counter = 0 then + ip_cs_temp_right <= ip_checksum(31 downto 16); + elsif headers_int_counter = 1 then + ip_checksum(31 downto 16) <= (others => '0'); + end if; + when TTL_S => + if headers_int_counter = 0 then + ip_checksum <= ip_checksum + ip_cs_temp_right; + end if; + when PROTO => + if headers_int_counter = 0 then + ip_checksum(15 downto 0) <= ip_checksum(15 downto 0) + ip_checksum(31 downto 16); + end if; + when others => null; + end case; + end if; + end if; +end process ipCsProc; + + +constructMachineProc: process(RESET, CLK ) +begin + if RESET = '1' then + constructCurrentState <= IDLE; + elsif( rising_edge(CLK) ) then + constructCurrentState <= constructNextState; + end if; +end process constructMachineProc; + +--find next state of construct machine +constructMachine: process( constructCurrentState, delay_ctr, FRAME_DELAY_IN, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, FRAME_TYPE_IN, DEST_UDP_PORT_IN) +begin + constructNextState <= constructCurrentState; + if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0 + case constructCurrentState is + when IDLE => + if( START_OF_DATA_IN = '1' ) then + constructNextState <= DEST_MAC_ADDR; + end if; + when DEST_MAC_ADDR => + constructNextState <= SRC_MAC_ADDR; + when SRC_MAC_ADDR => + constructNextState <= FRAME_TYPE_S; + when FRAME_TYPE_S => + --if (DEST_IP_ADDRESS_IN /= x"0000_0000") then -- in case of ip frame continue with ip/udp headers + if (FRAME_TYPE_IN = x"0008") then + constructNextState <= VERSION; + else -- otherwise transmit data as pure ethernet frame + constructNextState <= SAVE_DATA; + end if; + when VERSION => + constructNextState <= TOS_S; + when TOS_S => + constructNextState <= IP_LENGTH; + when IP_LENGTH => + constructNextState <= IDENT; + when IDENT => + constructNextState <= FLAGS; + when FLAGS => + constructNextState <= TTL_S; + when TTL_S => + constructNextState <= PROTO; + when PROTO => + constructNextState <= HEADER_CS; + when HEADER_CS => + constructNextState <= SRC_IP_ADDR; + when SRC_IP_ADDR => + constructNextState <= DEST_IP_ADDR; + when DEST_IP_ADDR => + if (put_udp_headers = '1') and (DEST_UDP_PORT_IN /= x"0000") then + constructNextState <= SRC_PORT; + else + constructNextState <= SAVE_DATA; + end if; + when SRC_PORT => + constructNextState <= DEST_PORT; + when DEST_PORT => + constructNextState <= UDP_LENGTH; + when UDP_LENGTH => + constructNextState <= UDP_CS; + when UDP_CS => + constructNextState <= SAVE_DATA; + when SAVE_DATA => + if (END_OF_DATA_IN = '1') then + constructNextState <= CLEANUP; + end if; + when CLEANUP => + --constructNextState <= IDLE; + constructNextState <= DELAY; -- gk 10.12.10 IDLE; + -- gk 09.12.10 + when DELAY => + if (delay_ctr = FRAME_DELAY_IN) then + constructNextState <= IDLE; + else + constructNextState <= DELAY; + end if; + + when others => + constructNextState <= IDLE; + end case; + end if; +end process constructMachine; + +-- gk 09.12.10 +delayCtrProc : process(CLK) +begin + if rising_edge(CLK) then + if (constructCurrentState = IDLE) or (constructCurrentState = CLEANUP) then + delay_ctr <= (others => '0'); + elsif (constructCurrentState = DELAY) then + delay_ctr <= delay_ctr + x"1"; + end if; + + frame_delay_reg <= FRAME_DELAY_IN; + end if; +end process delayCtrProc; + + +bsmConstrProc : process(constructCurrentState) +begin +--find maximum time in each state & set state bits + case constructCurrentState is + when IDLE => cur_max <= 0; bsm_constr <= x"01"; + when DEST_MAC_ADDR => cur_max <= 5; bsm_constr <= x"02"; + when SRC_MAC_ADDR => cur_max <= 5; bsm_constr <= x"03"; + when FRAME_TYPE_S => cur_max <= 1; bsm_constr <= x"04"; + when VERSION => cur_max <= 0; bsm_constr <= x"05"; + when TOS_S => cur_max <= 0; bsm_constr <= x"06"; + when IP_LENGTH => cur_max <= 1; bsm_constr <= x"07"; + when IDENT => cur_max <= 1; bsm_constr <= x"08"; + when FLAGS => cur_max <= 1; bsm_constr <= x"09"; + when TTL_S => cur_max <= 0; bsm_constr <= x"0a"; + when PROTO => cur_max <= 0; bsm_constr <= x"0b"; + when HEADER_CS => cur_max <= 1; bsm_constr <= x"0c"; + when SRC_IP_ADDR => cur_max <= 3; bsm_constr <= x"0d"; + when DEST_IP_ADDR => cur_max <= 3; bsm_constr <= x"0e"; + when SRC_PORT => cur_max <= 1; bsm_constr <= x"0f"; + when DEST_PORT => cur_max <= 1; bsm_constr <= x"10"; + when UDP_LENGTH => cur_max <= 1; bsm_constr <= x"11"; + when UDP_CS => cur_max <= 1; bsm_constr <= x"12"; + when SAVE_DATA => cur_max <= 0; bsm_constr <= x"13"; + when CLEANUP => cur_max <= 0; bsm_constr <= x"14"; + when DELAY => cur_max <= 0; bsm_constr <= x"15"; + when others => cur_max <= 0; bsm_constr <= x"1f"; + end case; +end process; + + +headersIntProc : process(CLK) +begin + if rising_edge(CLK) then + if (constructCurrentState = IDLE) then + headers_int_counter <= 0; + else + if (headers_int_counter = cur_max) then + headers_int_counter <= 0; + else + headers_int_counter <= headers_int_counter + 1; + end if; + end if; + end if; +end process headersIntProc; + + + +putUdpHeadersProc : process(CLK) +begin + if rising_edge(CLK) then + if (FLAGS_OFFSET_IN(12 downto 0) = "0000000000000") then + put_udp_headers <= '1'; + else + put_udp_headers <= '0'; + end if; + end if; +end process putUdpHeadersProc; + +fpfWrEnProc : process(constructCurrentState, WR_EN_IN, LINK_OK_IN) +begin + if (LINK_OK_IN = '0') then -- gk 01.10.10 + fpf_wr_en <= '0'; + elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) and (constructCurrentState /= DELAY) then + fpf_wr_en <= '1'; + elsif (constructCurrentState = SAVE_DATA) and (WR_EN_IN = '1') then + fpf_wr_en <= '1'; + else + fpf_wr_en <= '0'; + end if; +end process fpfWrEnProc; + +fpfDataProc : process(constructCurrentState, DEST_MAC_ADDRESS_IN, SRC_MAC_ADDRESS_IN, FRAME_TYPE_IN, IHL_VERSION_IN, + TOS_IN, ip_size, IDENTIFICATION_IN, FLAGS_OFFSET_IN, TTL_IN, PROTOCOL_IN, + ip_checksum, SRC_IP_ADDRESS_IN, DEST_IP_ADDRESS_IN, + SRC_UDP_PORT_IN, DEST_UDP_PORT_IN, udp_size, udp_checksum, headers_int_counter, DATA_IN) +begin + case constructCurrentState is + when IDLE => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when DEST_MAC_ADDR => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when SRC_MAC_ADDR => fpf_data <= SRC_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when FRAME_TYPE_S => fpf_data <= FRAME_TYPE_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when VERSION => fpf_data <= IHL_VERSION_IN; + when TOS_S => fpf_data <= TOS_IN; + when IP_LENGTH => fpf_data <= ip_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when IDENT => fpf_data <= IDENTIFICATION_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when FLAGS => fpf_data <= FLAGS_OFFSET_IN(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when TTL_S => fpf_data <= TTL_IN; + when PROTO => fpf_data <= PROTOCOL_IN; + when HEADER_CS => fpf_data <= x"ff" - ip_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when SRC_IP_ADDR => fpf_data <= SRC_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when DEST_IP_ADDR => fpf_data <= DEST_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when SRC_PORT => fpf_data <= SRC_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when DEST_PORT => fpf_data <= DEST_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); + when UDP_LENGTH => fpf_data <= udp_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when UDP_CS => fpf_data <= udp_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); + when SAVE_DATA => fpf_data <= DATA_IN; + when CLEANUP => fpf_data <= x"ab"; + when DELAY => fpf_data <= x"ac"; + when others => fpf_data <= x"00"; + end case; +end process fpfDataProc; + +syncProc : process(CLK) +begin + if rising_edge(CLK) then + fpf_data_q <= fpf_data; + fpf_wr_en_q <= fpf_wr_en; + fpf_eod <= END_OF_DATA_IN; + end if; +end process syncProc; + + + +readyFramesCtrProc: process( CLK ) +begin + if rising_edge(CLK) then + if (LINK_OK_IN = '0') then -- gk 01.10.10 + ready_frames_ctr <= (others => '0'); + elsif (constructCurrentState = CLEANUP) then + ready_frames_ctr <= ready_frames_ctr + 1; + else + ready_frames_ctr <= ready_frames_ctr; + end if; + end if; +end process readyFramesCtrProc; + +fpfResetProc : process(CLK) +begin + if rising_edge(CLK) then + if (LINK_OK_IN = '0') then + fpf_reset <= '1'; + else + fpf_reset <= '0'; + end if; + end if; +end process fpfResetProc; +--fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10 + + +fpf_4k_gen : if FRAME_BUFFER_SIZE = 1 generate + FINAL_PACKET_FIFO: fifo_4096x9 + port map( + Data(7 downto 0) => fpf_data_q, + Data(8) => fpf_eod, --END_OF_DATA_IN, + WrClock => CLK, + RdClock => RD_CLK, + WrEn => fpf_wr_en_q, + RdEn => fpf_rd_en, --FT_TX_RD_EN_IN, + Reset => fpf_reset, + RPReset => fpf_reset, + Q => fpf_q, + Empty => fpf_empty, + Full => fpf_full + ); +end generate fpf_4k_gen; + +fpf_8k_gen : if FRAME_BUFFER_SIZE = 2 generate + FINAL_PACKET_FIFO: fifo_8kx9 + port map( + Data(7 downto 0) => fpf_data_q, + Data(8) => fpf_eod, --END_OF_DATA_IN, + WrClock => CLK, + RdClock => RD_CLK, + WrEn => fpf_wr_en_q, + RdEn => fpf_rd_en, --FT_TX_RD_EN_IN, + Reset => fpf_reset, + RPReset => fpf_reset, + Q => fpf_q, + Empty => fpf_empty, + Full => fpf_full + ); +end generate fpf_8k_gen; + +--fpf_rd_en <= FT_TX_RD_EN_IN; +fpf_rd_en <= '1' when ((link_ok_125 = '1') and (FT_TX_RD_EN_IN = '1')) + or (link_ok_125 = '0') -- clear the fifo if link is down + else '0'; + +transferToRdClock : signal_sync + generic map( + DEPTH => 2, + WIDTH => 16 + ) + port map( + RESET => RESET, + D_IN => ready_frames_ctr, + CLK0 => RD_CLK, --CLK, + CLK1 => RD_CLK, + D_OUT => ready_frames_ctr_q + ); + +process(RD_CLK) +begin + if rising_edge(RD_CLK) then + link_ok_q <= LINK_OK_IN; + link_ok_125 <= link_ok_q; + end if; +end process; + +transmitMachineProc: process( RD_CLK, RESET ) +begin + if RESET = '1' then + transmitCurrentState <= T_IDLE; + elsif( rising_edge(RD_CLK) ) then + if (link_ok_125 = '0') then -- gk 01.10.10 + transmitCurrentState <= T_IDLE; + else + transmitCurrentState <= transmitNextState; + end if; + end if; +end process transmitMachineProc; + +transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, link_ok_125, ready_frames_ctr_q, FT_TX_DISCFRM_IN ) +begin + case transmitCurrentState is + when T_IDLE => + bsm_trans <= x"0"; + if( (sent_frames_ctr /= ready_frames_ctr_q) ) then + transmitNextState <= T_LOAD; + else + transmitNextState <= T_IDLE; + end if; + when T_LOAD => + bsm_trans <= x"1"; + if( fpf_q(8) = '1' ) then + transmitNextState <= T_TRANSMIT; + else + transmitNextState <= T_LOAD; + end if; + when T_TRANSMIT => + bsm_trans <= x"2"; + -- gk 03.08.10 + if ((link_ok_125 = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then + transmitNextState <= T_CLEANUP; + elsif (link_ok_125 = '0') then + transmitNextState <= T_PAUSE; + else + transmitNextState <= T_TRANSMIT; + end if; + when T_PAUSE => + transmitNextState <= T_CLEANUP; + when T_CLEANUP => + bsm_trans <= x"3"; + transmitNextState <= T_IDLE; + when others => + bsm_trans <= x"f"; + transmitNextState <= T_IDLE; + end case; +end process transmitMachine; + + + +sopProc: process( RD_CLK ) +begin + if rising_edge(RD_CLK) then + if (link_ok_125 = '0') then -- gk 01.10.10 + ft_sop <= '0'; + elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then + ft_sop <= '1'; + else + ft_sop <= '0'; + end if; + end if; +end process sopProc; + +sentFramesCtrProc: process( RD_CLK ) +begin + if rising_edge(RD_CLK) then + if (LINK_OK_IN = '0') then -- gk 01.10.10 + sent_frames_ctr <= (others => '0'); + mon_sent_frames <= (others => '0'); + elsif( FT_TX_DONE_IN = '1' ) or (FT_TX_DISCFRM_IN = '1') then + sent_frames_ctr <= sent_frames_ctr + 1; + mon_sent_frames <= mon_sent_frames + x"1"; + else + sent_frames_ctr <= sent_frames_ctr; + mon_sent_frames <= mon_sent_frames; + end if; + end if; +end process sentFramesCtrProc; + + + +FT_DATA_OUT <= fpf_q; +FT_TX_EMPTY_OUT <= fpf_empty; +FT_START_OF_PACKET_OUT <= ft_sop; +READY_OUT <= ready; +HEADERS_READY_OUT <= headers_ready; + + +MONITOR_TX_BYTES_OUT <= mon_sent_bytes; +MONITOR_TX_FRAMES_OUT <= mon_sent_frames; + +process(RD_CLK) +begin + if rising_edge(RD_CLK) then + if (LINK_OK_IN = '0') then + mon_sent_bytes <= (others => '0'); + elsif (fpf_rd_en = '1') then + mon_sent_bytes <= mon_sent_bytes + x"1"; + else + mon_sent_bytes <= mon_sent_bytes; + end if; + end if; +end process; + +end trb_net16_gbe_frame_constr; \ No newline at end of file diff --git a/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd b/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd new file mode 100644 index 0000000..bc7ee97 --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd @@ -0,0 +1,753 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- here all frame checking has to be done, if the frame fits into protocol standards +-- if so FR_FRAME_VALID_OUT is asserted after having received all bytes of a frame +-- otherwise, after receiving all bytes, FR_FRAME_VALID_OUT keeps low and the fifo is cleared +-- also a part of addresses assignemt has to be done here + +entity trb_net16_gbe_frame_receiver is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + LINK_OK_IN : in std_logic; + ALLOW_RX_IN : in std_logic; + RX_MAC_CLK : in std_logic; -- receiver serdes clock + MY_MAC_IN : in std_logic_vector(47 downto 0); + +-- input signals from TS_MAC + MAC_RX_EOF_IN : in std_logic; + MAC_RX_ER_IN : in std_logic; + MAC_RXD_IN : in std_logic_vector(7 downto 0); + MAC_RX_EN_IN : in std_logic; + MAC_RX_FIFO_ERR_IN : in std_logic; + MAC_RX_FIFO_FULL_OUT : out std_logic; + MAC_RX_STAT_EN_IN : in std_logic; + MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); + +-- output signal to control logic + FR_Q_OUT : out std_logic_vector(8 downto 0); + FR_RD_EN_IN : in std_logic; + FR_FRAME_VALID_OUT : out std_logic; + FR_GET_FRAME_IN : in std_logic; + FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0); + FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); + FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0); + FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0); + FR_VLAN_ID_IN : in std_logic_vector(31 downto 0); + + FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + + MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0); + MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_frame_receiver; + + +architecture trb_net16_gbe_frame_receiver of trb_net16_gbe_frame_receiver is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_frame_receiver : architecture is "GBE_LINK_group"; + +attribute syn_encoding : string; +type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME, REMOVE_VID, REMOVE_VTYPE, REMOVE_IP, REMOVE_UDP, DECIDE, CLEANUP); +signal filter_current_state, filter_next_state : filter_states; +attribute syn_encoding of filter_current_state : signal is "onehot"; + +signal fifo_wr_en : std_logic; +signal rx_bytes_ctr : std_logic_vector(15 downto 0); +signal frame_valid_q : std_logic; +signal delayed_frame_valid : std_logic; +signal delayed_frame_valid_q : std_logic; + +signal rec_fifo_empty : std_logic; +signal rec_fifo_full : std_logic; +signal sizes_fifo_full : std_logic; +signal sizes_fifo_empty : std_logic; + +signal remove_ctr : std_logic_vector(7 downto 0); +signal new_frame : std_logic; +signal new_frame_lock : std_logic := '0'; +signal saved_frame_type : std_logic_vector(15 downto 0); +signal saved_vid : std_logic_vector(15 downto 0) := (others => '0'); +signal saved_src_mac : std_logic_vector(47 downto 0); +signal saved_dest_mac : std_logic_vector(47 downto 0); +signal frame_type_valid : std_logic; +signal saved_proto : std_logic_vector(7 downto 0); +signal saved_src_ip : std_logic_vector(31 downto 0); +signal saved_dest_ip : std_logic_vector(31 downto 0); +signal saved_src_udp : std_logic_vector(15 downto 0); +signal saved_dest_udp : std_logic_vector(15 downto 0); + +signal dump : std_logic_vector(7 downto 0); +signal dump2 : std_logic_vector(7 downto 0); + +signal error_frames_ctr : std_logic_vector(15 downto 0); + +-- debug signals +signal dbg_rec_frames : std_logic_vector(31 downto 0); +signal dbg_drp_frames : std_logic_vector(31 downto 0); +signal state : std_logic_vector(3 downto 0); + +signal rx_data, fr_q : std_logic_vector(8 downto 0); + +signal fr_src_ip, fr_dest_ip : std_logic_vector(31 downto 0); +signal fr_dest_udp, fr_src_udp, fr_frame_size, fr_frame_proto : std_logic_vector(15 downto 0); +signal fr_dest_mac, fr_src_mac : std_logic_vector(47 downto 0); +signal fr_ip_proto : std_logic_vector(7 downto 0); +signal mon_rec_bytes : std_logic_vector(31 downto 0); + +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_keep of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true; +attribute syn_preserve of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true; + +begin + +-- new_frame is asserted when first byte of the frame arrives +NEW_FRAME_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (LINK_OK_IN = '0' or MAC_RX_EOF_IN = '1') then + new_frame <= '0'; + new_frame_lock <= '0'; + elsif (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') then + new_frame <= '1'; + new_frame_lock <= '1'; + else + new_frame <= '0'; + new_frame_lock <= new_frame_lock; + end if; + end if; +end process NEW_FRAME_PROC; + + +FILTER_MACHINE_PROC : process(RX_MAC_CLK, RESET) +begin + if RESET = '1' then + filter_current_state <= IDLE; + elsif rising_edge(RX_MAC_CLK) then + filter_current_state <= filter_next_state; + end if; +end process FILTER_MACHINE_PROC; + +FILTER_MACHINE : process(filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, MY_MAC_IN, saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN) +begin + + case filter_current_state is + + when IDLE => + state <= x"1"; + if (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') then + filter_next_state <= REMOVE_DEST; + else + filter_next_state <= IDLE; + end if; + + -- frames arrive without preamble! + when REMOVE_DEST => + state <= x"3"; + if (remove_ctr = x"03") then -- counter starts with a delay that's why only 3 + -- destination MAC address filtering here + if (saved_dest_mac = MY_MAC_IN) or (saved_dest_mac = x"ffffffffffff") then -- must accept broadcasts for ARP + filter_next_state <= REMOVE_SRC; + else + filter_next_state <= DECIDE; + end if; + else + filter_next_state <= REMOVE_DEST; + end if; + + when REMOVE_SRC => + state <= x"4"; + if (remove_ctr = x"09") then + filter_next_state <= REMOVE_TYPE; + else + filter_next_state <= REMOVE_SRC; + end if; + + when REMOVE_TYPE => + state <= x"5"; + if (remove_ctr = x"0b") then + if (saved_frame_type = x"8100") then -- VLAN tagged frame + filter_next_state <= REMOVE_VID; + else -- no VLAN tag + if (saved_frame_type = x"0800") then -- in case of IP continue removing headers + filter_next_state <= REMOVE_IP; + else + filter_next_state <= DECIDE; + end if; + end if; + else + filter_next_state <= REMOVE_TYPE; + end if; + + when REMOVE_VID => + state <= x"a"; + if (remove_ctr = x"0d") then + filter_next_state <= REMOVE_VTYPE; + else + filter_next_state <= REMOVE_VID; + end if; + + when REMOVE_VTYPE => + state <= x"b"; + if (remove_ctr = x"0f") then + if (saved_frame_type = x"0800") then -- in case of IP continue removing headers + filter_next_state <= REMOVE_IP; + else + filter_next_state <= DECIDE; + end if; + else + filter_next_state <= REMOVE_VTYPE; + end if; + + when REMOVE_IP => + state <= x"c"; + if (remove_ctr = x"11") then + if (saved_proto = x"11") then -- forced to recognize udp only, TODO check all protocols + filter_next_state <= REMOVE_UDP; + else + filter_next_state <= DECIDE; -- changed from drop + end if; + else + filter_next_state <= REMOVE_IP; + end if; + + when REMOVE_UDP => + state <= x"d"; + if (remove_ctr = x"19") then + filter_next_state <= DECIDE; + else + filter_next_state <= REMOVE_UDP; + end if; + + when DECIDE => + state <= x"6"; + if (frame_type_valid = '1') then + filter_next_state <= SAVE_FRAME; + elsif (saved_frame_type = x"0806") then + filter_next_state <= SAVE_FRAME; + else + filter_next_state <= DROP_FRAME; + end if; + + when SAVE_FRAME => + state <= x"7"; + if (MAC_RX_EOF_IN = '1') then + filter_next_state <= CLEANUP; + else + filter_next_state <= SAVE_FRAME; + end if; + + when DROP_FRAME => + state <= x"8"; + if (MAC_RX_EOF_IN = '1') then + filter_next_state <= CLEANUP; + else + filter_next_state <= DROP_FRAME; + end if; + + when CLEANUP => + state <= x"9"; + filter_next_state <= IDLE; + + when others => null; + + end case; +end process; + +-- counts the bytes to be removed from the ethernet headers fields +REMOVE_CTR_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = IDLE) or + (filter_current_state = REMOVE_VTYPE and remove_ctr = x"0f") or + (filter_current_state = REMOVE_TYPE and remove_ctr = x"0b") then + + remove_ctr <= (others => '1'); + elsif (MAC_RX_EN_IN = '1') and (filter_current_state /= IDLE) then --and (filter_current_state /= CLEANUP) then + remove_ctr <= remove_ctr + x"1"; + else + remove_ctr <= remove_ctr; + end if; + end if; +end process REMOVE_CTR_PROC; + +SAVED_PROTO_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = CLEANUP) then + saved_proto <= (others => '0'); + elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"07") then + saved_proto <= MAC_RXD_IN; + else + saved_proto <= saved_proto; + end if; + end if; +end process SAVED_PROTO_PROC; + +SAVED_SRC_IP_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = CLEANUP) then + saved_src_ip <= (others => '0'); + elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0a") then + saved_src_ip(7 downto 0) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0b") then + saved_src_ip(15 downto 8) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0c") then + saved_src_ip(23 downto 16) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0d") then + saved_src_ip(31 downto 24) <= MAC_RXD_IN; + else + saved_src_ip <= saved_src_ip; + end if; + end if; +end process SAVED_SRC_IP_PROC; + +SAVED_DEST_IP_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = CLEANUP) then + saved_dest_ip <= (others => '0'); + elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0e") then + saved_dest_ip(7 downto 0) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0f") then + saved_dest_ip(15 downto 8) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"10") then + saved_dest_ip(23 downto 16) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"11") then + saved_dest_ip(31 downto 24) <= MAC_RXD_IN; + else + saved_dest_ip <= saved_dest_ip; + end if; + end if; +end process SAVED_DEST_IP_PROC; + +SAVED_SRC_UDP_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = CLEANUP) then + saved_src_udp <= (others => '0'); + elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"12") then + saved_src_udp(15 downto 8) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"13") then + saved_src_udp(7 downto 0) <= MAC_RXD_IN; + else + saved_src_udp <= saved_src_udp; + end if; + end if; +end process SAVED_SRC_UDP_PROC; + +SAVED_DEST_UDP_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = CLEANUP) then + saved_dest_udp <= (others => '0'); + elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"14") then + saved_dest_udp(15 downto 8) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"15") then + saved_dest_udp(7 downto 0) <= MAC_RXD_IN; + else + saved_dest_udp <= saved_dest_udp; + end if; + end if; +end process SAVED_DEST_UDP_PROC; + +-- saves the destination mac address of the incoming frame +SAVED_DEST_MAC_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = CLEANUP) then + saved_dest_mac <= (others => '0'); + elsif (filter_current_state = IDLE) and (MAC_RX_EN_IN = '1') and (new_frame = '0') then + saved_dest_mac(7 downto 0) <= MAC_RXD_IN; + elsif (filter_current_state = IDLE) and (new_frame = '1') and (ALLOW_RX_IN = '1') then + saved_dest_mac(15 downto 8) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"FF") then + saved_dest_mac(23 downto 16) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"00") then + saved_dest_mac(31 downto 24) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"01") then + saved_dest_mac(39 downto 32) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"02") then + saved_dest_mac(47 downto 40) <= MAC_RXD_IN; + else + saved_dest_mac <= saved_dest_mac; + end if; + end if; +end process SAVED_DEST_MAC_PROC; + +-- saves the source mac address of the incoming frame +SAVED_SRC_MAC_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = CLEANUP) then + saved_src_mac <= (others => '0'); + elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"03") then + saved_src_mac(7 downto 0) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"04") then + saved_src_mac(15 downto 8) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"05") then + saved_src_mac(23 downto 16) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"06") then + saved_src_mac(31 downto 24) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"07") then + saved_src_mac(39 downto 32) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"08") then + saved_src_mac(47 downto 40) <= MAC_RXD_IN; + else + saved_src_mac <= saved_src_mac; + end if; + end if; +end process SAVED_SRC_MAC_PROC; + +-- saves the frame type of the incoming frame for futher check +SAVED_FRAME_TYPE_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = CLEANUP) then + saved_frame_type <= (others => '0'); + elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"09") then + saved_frame_type(15 downto 8) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0a") then + saved_frame_type(7 downto 0) <= MAC_RXD_IN; + -- two more cases for VLAN tagged frame + elsif (filter_current_state = REMOVE_VID) and (remove_ctr = x"0d") then + saved_frame_type(15 downto 8) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0e") then + saved_frame_type(7 downto 0) <= MAC_RXD_IN; + else + saved_frame_type <= saved_frame_type; + end if; + end if; +end process SAVED_FRAME_TYPE_PROC; + +-- saves VLAN id when tagged frame spotted +SAVED_VID_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (filter_current_state = CLEANUP) then + saved_vid <= (others => '0'); + elsif (filter_current_state = REMOVE_TYPE and remove_ctr = x"0b" and saved_frame_type = x"8100") then + saved_vid(15 downto 8) <= MAC_RXD_IN; + elsif (filter_current_state = REMOVE_VID and remove_ctr = x"0c") then + saved_vid(7 downto 0) <= MAC_RXD_IN; + else + saved_vid <= saved_vid; + end if; + end if; +end process SAVED_VID_PROC; + +type_validator : trb_net16_gbe_type_validator +port map( + CLK => RX_MAC_CLK, + RESET => RESET, + FRAME_TYPE_IN => saved_frame_type, + SAVED_VLAN_ID_IN => saved_vid, + ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN, + VLAN_ID_IN => FR_VLAN_ID_IN, + + -- IP level + IP_PROTOCOLS_IN => saved_proto, + ALLOWED_IP_PROTOCOLS_IN => FR_ALLOWED_IP_IN, + + -- UDP level + UDP_PROTOCOL_IN => saved_dest_udp, + ALLOWED_UDP_PROTOCOLS_IN => FR_ALLOWED_UDP_IN, + + VALID_OUT => frame_type_valid +); + +receive_fifo : fifo_4096x9 +port map( +-- Data(7 downto 0) => MAC_RXD_IN, +-- Data(8) => MAC_RX_EOF_IN, + Data => rx_data, + WrClock => RX_MAC_CLK, + RdClock => CLK, + WrEn => fifo_wr_en, + RdEn => FR_RD_EN_IN, + Reset => RESET, + RPReset => RESET, + Q => fr_q, --FR_Q_OUT, + Empty => rec_fifo_empty, + Full => rec_fifo_full +); + +-- BUG HERE, probably more lost bytes in the fifo in other conditions +--fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FRAME) or +-- --( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or +-- ((filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or +-- (filter_current_state = DECIDE and frame_type_valid = '1'))) +-- else '0'; + +RX_FIFO_SYNC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + + rx_data(8) <= MAC_RX_EOF_IN; + rx_data(7 downto 0) <= MAC_RXD_IN; + + if (MAC_RX_EN_IN = '1') then + if (filter_current_state = SAVE_FRAME) then + fifo_wr_en <= '1'; + elsif (filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") then + fifo_wr_en <= '1'; + elsif (filter_current_state = DECIDE and frame_type_valid = '1') then + fifo_wr_en <= '1'; + else + fifo_wr_en <= '0'; + end if; + else + fifo_wr_en <= '0'; + end if; + + MAC_RX_FIFO_FULL_OUT <= rec_fifo_full; + end if; +end process RX_FIFO_SYNC; + + + +sizes_fifo : fifo_512x32 +port map( + Data(15 downto 0) => rx_bytes_ctr, + Data(31 downto 16) => saved_frame_type, + WrClock => RX_MAC_CLK, + RdClock => CLK, + WrEn => frame_valid_q, + RdEn => FR_GET_FRAME_IN, + Reset => RESET, + RPReset => RESET, + Q(15 downto 0) => fr_frame_size, --FR_FRAME_SIZE_OUT, + Q(31 downto 16) => fr_frame_proto, --FR_FRAME_PROTO_OUT, + Empty => sizes_fifo_empty, + Full => sizes_fifo_full +); + +macs_fifo : fifo_512x72 +port map( + Data(47 downto 0) => saved_src_mac, + Data(63 downto 48) => saved_src_udp, + Data(71 downto 64) => (others => '0'), + WrClock => RX_MAC_CLK, + RdClock => CLK, + WrEn => frame_valid_q, + RdEn => FR_GET_FRAME_IN, + Reset => RESET, + RPReset => RESET, + Q(47 downto 0) => fr_src_mac, --FR_SRC_MAC_ADDRESS_OUT, + Q(63 downto 48) => fr_src_udp, --FR_SRC_UDP_PORT_OUT, + Q(71 downto 64) => dump2, + Empty => open, + Full => open +); + +macd_fifo : fifo_512x72 +port map( + Data(47 downto 0) => saved_dest_mac, + Data(63 downto 48) => saved_dest_udp, + Data(71 downto 64) => (others => '0'), + WrClock => RX_MAC_CLK, + RdClock => CLK, + WrEn => frame_valid_q, + RdEn => FR_GET_FRAME_IN, + Reset => RESET, + RPReset => RESET, + Q(47 downto 0) => fr_dest_mac, --FR_DEST_MAC_ADDRESS_OUT, + Q(63 downto 48) => fr_dest_udp, --FR_DEST_UDP_PORT_OUT, + Q(71 downto 64) => dump, + Empty => open, + Full => open +); + +ip_fifo : fifo_512x72 +port map( + Data(31 downto 0) => saved_src_ip, + Data(63 downto 32) => saved_dest_ip, + Data(71 downto 64) => saved_proto, + WrClock => RX_MAC_CLK, + RdClock => CLK, + WrEn => frame_valid_q, + RdEn => FR_GET_FRAME_IN, + Reset => RESET, + RPReset => RESET, + Q(31 downto 0) => fr_src_ip, --FR_SRC_IP_ADDRESS_OUT, + Q(63 downto 32) => fr_dest_ip, --FR_DEST_IP_ADDRESS_OUT, + Q(71 downto 64) => fr_ip_proto, --FR_IP_PROTOCOL_OUT, + Empty => open, + Full => open +); + +process(CLK) +begin + if rising_edge(CLK) then + FR_SRC_IP_ADDRESS_OUT <= fr_src_ip; + FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip; + FR_IP_PROTOCOL_OUT <= fr_ip_proto; + FR_DEST_UDP_PORT_OUT <= fr_dest_udp; + FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac; + FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac; + FR_SRC_UDP_PORT_OUT <= fr_src_udp; + FR_FRAME_PROTO_OUT <= fr_frame_proto; + FR_FRAME_SIZE_OUT <= fr_frame_size; + FR_Q_OUT <= fr_q; + end if; +end process; + +FRAME_VALID_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (MAC_RX_EOF_IN = '1' and ALLOW_RX_IN = '1' and frame_type_valid = '1') then + frame_valid_q <= '1'; + else + frame_valid_q <= '0'; + end if; + end if; +end process FRAME_VALID_PROC; + +RX_BYTES_CTR_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (RESET = '1') or (delayed_frame_valid_q = '1') then + rx_bytes_ctr <= x"0001"; + elsif (fifo_wr_en = '1') then + rx_bytes_ctr <= rx_bytes_ctr + x"1"; + end if; + end if; +end process; + +ERROR_FRAMES_CTR_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (RESET = '1') then + error_frames_ctr <= (others => '0'); + elsif (MAC_RX_ER_IN = '1') then + error_frames_ctr <= error_frames_ctr + x"1"; + end if; + end if; +end process ERROR_FRAMES_CTR_PROC; + + +SYNC_PROC : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + delayed_frame_valid <= MAC_RX_EOF_IN; + delayed_frame_valid_q <= delayed_frame_valid; + end if; +end process SYNC_PROC; + +--***************** +-- synchronization between 125MHz receive clock and 100MHz system clock +FRAME_VALID_SYNC : pulse_sync +port map( + CLK_A_IN => RX_MAC_CLK, + RESET_A_IN => RESET, + PULSE_A_IN => frame_valid_q, + CLK_B_IN => CLK, + RESET_B_IN => RESET, + PULSE_B_OUT => FR_FRAME_VALID_OUT +); + + +-- **** +-- debug counters, to be removed later +RECEIVED_FRAMES_CTR : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (RESET = '1') then + dbg_rec_frames <= (others => '0'); + elsif (MAC_RX_EOF_IN = '1') then + dbg_rec_frames <= dbg_rec_frames + x"1"; + end if; + end if; +end process RECEIVED_FRAMES_CTR; + +DROPPED_FRAMES_CTR : process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (RESET = '1') then + dbg_drp_frames <= (others => '0'); + elsif (filter_current_state = DECIDE and frame_type_valid = '0') then + dbg_drp_frames <= dbg_drp_frames + x"1"; + end if; + end if; +end process DROPPED_FRAMES_CTR; + +sync1 : signal_sync +generic map ( + WIDTH => 32, + DEPTH => 2 +) +port map ( + RESET => RESET, + CLK0 => CLK, + CLK1 => CLK, + D_IN => dbg_drp_frames, + D_OUT => MONITOR_DROPPED_OUT +); + +sync3 : signal_sync +generic map ( + WIDTH => 32, + DEPTH => 2 +) +port map ( + RESET => RESET, + CLK0 => CLK, + CLK1 => CLK, + D_IN => dbg_rec_frames, + D_OUT => MONITOR_RX_FRAMES_OUT +); + +sync4 : signal_sync +generic map ( + WIDTH => 32, + DEPTH => 2 +) +port map ( + RESET => RESET, + CLK0 => CLK, + CLK1 => CLK, + D_IN => mon_rec_bytes, + D_OUT => MONITOR_RX_BYTES_OUT +); + +process(RX_MAC_CLK) +begin + if rising_edge(RX_MAC_CLK) then + if (RESET = '1') then + mon_rec_bytes <= (others => '0'); + elsif (fifo_wr_en = '1') then + mon_rec_bytes <= mon_rec_bytes + x"1"; + else + mon_rec_bytes <= mon_rec_bytes; + end if; + end if; +end process; + +-- end of debug counters +-- **** + +end trb_net16_gbe_frame_receiver; + + diff --git a/gbe_trb/base/trb_net16_gbe_frame_trans.vhd b/gbe_trb/base/trb_net16_gbe_frame_trans.vhd new file mode 100755 index 0000000..e0f1954 --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_frame_trans.vhd @@ -0,0 +1,226 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +entity trb_net16_gbe_frame_trans is +port ( + CLK : in std_logic; + RESET : in std_logic; + LINK_OK_IN : in std_logic; -- gk 03.08.10 + TX_MAC_CLK : in std_logic; + TX_EMPTY_IN : in std_logic; + START_OF_PACKET_IN : in std_logic; + DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC + + TX_FIFOAVAIL_OUT : out std_logic; + TX_FIFOEOF_OUT : out std_logic; + TX_FIFOEMPTY_OUT : out std_logic; + TX_DONE_IN : in std_logic; + TX_STAT_EN_IN : in std_logic; + TX_STATVEC_IN : in std_logic_vector(30 downto 0); + TX_DISCFRM_IN : in std_logic; + -- Debug + BSM_INIT_OUT : out std_logic_vector(3 downto 0); + BSM_MAC_OUT : out std_logic_vector(3 downto 0); + BSM_TRANS_OUT : out std_logic_vector(3 downto 0); + DBG_RD_DONE_OUT : out std_logic; + DBG_INIT_DONE_OUT : out std_logic; + DBG_ENABLED_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end trb_net16_gbe_frame_trans; + +-- FifoRd ?!? + +architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_frame_trans : architecture is "GBE_BUF_group"; + +component mac_init_mem is +port ( + Address : in std_logic_vector(5 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0) +); +end component; + +attribute syn_encoding : string; + +type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED); +signal macInitState, macInitNextState : macInitStates; +attribute syn_encoding of macInitState: signal is "onehot"; +signal bsm_init : std_logic_vector(3 downto 0); + +type macStates is (M_RESETING, M_IDLE, M_INIT); +signal macCurrentState, macNextState : macStates; +attribute syn_encoding of macCurrentState : signal is "onehot"; +signal bsm_mac : std_logic_vector(3 downto 0); + +type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO); +signal transmitCurrentState, transmitNextState : transmitStates; +attribute syn_encoding of transmitCurrentState: signal is "onehot"; +signal bsm_trans : std_logic_vector(3 downto 0); + +signal tx_fifoavail_i : std_logic; +signal tx_fifoeof_i : std_logic; + +-- host interface signals +signal hcs_n_i : std_logic; +signal hwrite_n_i : std_logic; +signal hread_n_i : std_logic; + +-- MAC INITIALIZATION signals +signal macInitMemAddr : std_logic_vector(5 downto 0); +signal macInitMemQ : std_logic_vector(7 downto 0); +signal macInitMemEn : std_logic; +signal reading_done : std_logic; +signal init_done : std_logic; +signal enabled : std_logic; +signal addrSig : std_logic_vector(5 downto 0); +signal addr2 : std_logic_vector(5 downto 0); +signal resetAddr : std_logic; + +signal FifoEmpty : std_logic; +signal debug : std_logic_vector(63 downto 0); +signal sent_ctr : std_logic_vector(31 downto 0); +signal link_ok_125 : std_logic; + +begin + +linkOkSync : pulse_sync +port map( + CLK_A_IN => CLK, + RESET_A_IN => RESET, + PULSE_A_IN => LINK_OK_IN, + CLK_B_IN => TX_MAC_CLK, + RESET_B_IN => RESET, + PULSE_B_OUT => link_ok_125 +); + +-- Fakes +debug(63 downto 32) <= (others => '0'); +--debug(31 downto 0) <= sent_ctr; + + +TransmitStateMachineProc : process (TX_MAC_CLK, reset) +begin + if RESET = '1' then + transmitCurrentState <= T_IDLE; + elsif rising_edge(TX_MAC_CLK) then + if (LINK_OK_IN = '0') then -- gk 01.10.10 + transmitCurrentState <= T_IDLE; + else + transmitCurrentState <= transmitNextState; + end if; + end if; +end process TransmitStatemachineProc; + +TransmitStateMachine : process (transmitCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN) +begin + case transmitCurrentState is + when T_IDLE => + bsm_trans <= x"0"; + if (START_OF_PACKET_IN = '1') then + transmitNextState <= T_TRANSMIT; + else + transmitNextState <= T_IDLE; + end if; + when T_TRANSMIT => + bsm_trans <= x"1"; + if (DATA_ENDFLAG_IN = '1') then + transmitNextState <= T_WAITFORFIFO; + else + transmitNextState <= T_TRANSMIT; + end if; + when T_WAITFORFIFO => + bsm_trans <= x"2"; + if (TX_DONE_IN = '1') then + transmitNextState <= T_IDLE; + else + transmitNextState <= T_WAITFORFIFO; + end if; + when others => + bsm_trans <= x"f"; + transmitNextState <= T_IDLE; + end case; +end process TransmitStateMachine; + +FifoAvailProc : process (TX_MAC_CLK) +begin + if rising_edge(TX_MAC_CLK) then + if (LINK_OK_IN = '0') then -- gk 01.10.10 + tx_fifoavail_i <= '0'; + elsif (transmitCurrentState = T_TRANSMIT) then + tx_fifoavail_i <= '1'; + else + tx_fifoavail_i <= '0'; + end if; + end if; +end process FifoAvailProc; + +FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, LINK_OK_IN) +begin + if (LINK_OK_IN = '0') then -- gk 01.10.10 + FifoEmpty <= '1'; + elsif (transmitCurrentState = T_WAITFORFIFO) then + FifoEmpty <= '1'; + elsif (transmitCurrentState = T_TRANSMIT) then + FifoEmpty <= TX_EMPTY_IN; + elsif (((transmitCurrentState = T_IDLE) or (transmitCurrentState = T_WAITFORFIFO)) and (START_OF_PACKET_IN = '1')) then + FifoEmpty <= '0'; + else + FifoEmpty <= '1'; + end if; +end process FifoEmptyProc; + +tx_fifoeof_i <= '1' when ((DATA_ENDFLAG_IN = '1') and (transmitCurrentState = T_TRANSMIT)) + else '0'; + +SENT_CTR_PROC : process(TX_MAC_CLK, RESET) +begin + if (RESET = '1') then + sent_ctr <= (others => '0'); + elsif rising_edge(TX_MAC_CLK) then + if (TX_DONE_IN = '1') and (TX_STAT_EN_IN = '1') and (TX_STATVEC_IN(0) = '1') then + sent_ctr <= sent_ctr + x"1"; + else + sent_ctr <= sent_ctr; + end if; + end if; +end process SENT_CTR_PROC; + +sync1 : signal_sync +generic map( + WIDTH => 32, + DEPTH => 2 +) +port map ( + RESET => RESET, + CLK0 => CLK, + CLK1 => CLK, + D_IN => sent_ctr, + D_OUT => debug(31 downto 0) +); + +TX_FIFOAVAIL_OUT <= tx_fifoavail_i; +TX_FIFOEOF_OUT <= tx_fifoeof_i; +TX_FIFOEMPTY_OUT <= FifoEmpty; + +BSM_INIT_OUT <= bsm_init; +BSM_MAC_OUT <= bsm_mac; +BSM_TRANS_OUT <= bsm_trans; +DBG_RD_DONE_OUT <= reading_done; +DBG_INIT_DONE_OUT <= init_done; +DBG_ENABLED_OUT <= enabled; +DEBUG_OUT <= debug; + +end trb_net16_gbe_frame_trans; diff --git a/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd b/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd new file mode 100644 index 0000000..56527d3 --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd @@ -0,0 +1,912 @@ +library ieee; + +use ieee.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.std_logic_UNSIGNED.all; +use IEEE.std_logic_arith.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +entity trb_net16_gbe_ipu_interface is + generic( + DO_SIMULATION : integer range 0 to 1 := 0 + ); + port( + CLK_IPU : in std_logic; + CLK_GBE : in std_logic; + RESET : in std_logic; + -- IPU interface directed toward the CTS + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); + CTS_CODE_IN : in std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_READ_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + -- Data from Frontends + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_BUSY_IN : in std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + -- slow control interface + START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size + BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address + CONFIG_DONE_IN : in std_logic; -- configuration finished + DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE + DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet + MULT_EVT_ENABLE_IN : in std_logic; + MAX_SUBEVENT_SIZE_IN : in std_logic_vector(15 downto 0); + MAX_QUEUE_SIZE_IN : in std_logic_vector(15 downto 0); + MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + MAX_SINGLE_SUB_SIZE_IN : in std_logic_vector(15 downto 0); + READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 + READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 + -- PacketConstructor interface + PC_WR_EN_OUT : out std_logic; + PC_DATA_OUT : out std_logic_vector(7 downto 0); + PC_READY_IN : in std_logic; + PC_SOS_OUT : out std_logic; + PC_EOS_OUT : out std_logic; + PC_EOQ_OUT : out std_logic; + PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); + PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); + PC_TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0); + MONITOR_OUT : out std_logic_vector(223 downto 0); + DEBUG_OUT : out std_logic_vector(383 downto 0) + ); +end entity trb_net16_gbe_ipu_interface; + +architecture RTL of trb_net16_gbe_ipu_interface is + attribute syn_encoding : string; + + type saveStates is (IDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, CLOSE, FINISH_4_WORDS, CLEANUP); + signal save_current_state, save_next_state : saveStates; + attribute syn_encoding of save_current_state : signal is "onehot"; + + type loadStates is (IDLE, WAIT_FOR_SUBS, REMOVE, WAIT_ONE, WAIT_TWO, DECIDE, PREPARE_TO_LOAD_SUB, WAIT_FOR_LOAD, LOAD, CLOSE_PACKET, CLOSE_SUB, CLOSE_QUEUE, CLOSE_QUEUE_IMMEDIATELY); + signal load_current_state, load_next_state : loadStates; + attribute syn_encoding of load_current_state : signal is "onehot"; + + signal sf_data : std_Logic_vector(15 downto 0); + signal save_eod, sf_wr_en, sf_rd_en, sf_reset, sf_empty, sf_full, sf_afull, sf_eos : std_logic; + signal sf_q, pc_data : std_logic_vector(7 downto 0); + + signal cts_rnd, cts_trg : std_logic_vector(15 downto 0); + signal save_ctr : std_logic_vector(15 downto 0); + + signal saved_events_ctr, loaded_events_ctr, saved_events_ctr_gbe : std_logic_vector(7 downto 0); + signal loaded_bytes_ctr : std_Logic_vector(15 downto 0); + + signal trigger_random : std_logic_vector(7 downto 0); + signal trigger_number : std_logic_vector(15 downto 0); + signal subevent_size : std_logic_vector(17 downto 0); + signal trigger_type : std_logic_vector(3 downto 0); + + signal bank_select : std_logic_vector(3 downto 0); + signal readout_ctr : std_logic_vector(23 downto 0) := x"000000"; + signal pc_ready_q : std_logic; + signal sf_afull_q,sf_afull_qq, sf_afull_qqq, sf_afull_qqqq, sf_afull_qqqqq : std_logic; + signal sf_aempty : std_logic; + signal rec_state, load_state : std_logic_vector(3 downto 0); + signal queue_size : std_logic_vector(17 downto 0); + signal number_of_subs : std_logic_vector(15 downto 0); + signal size_check_ctr : integer range 0 to 7; + signal sf_data_q, sf_data_qq, sf_data_qqq, sf_data_qqqq, sf_data_qqqqq : std_logic_vector(15 downto 0); + signal sf_wr_q, sf_wr_lock : std_logic; + signal save_eod_q, save_eod_qq, save_eod_qqq, save_eod_qqqq, save_eod_qqqqq : std_logic; + signal sf_wr_qq, sf_wr_qqq, sf_wr_qqqq, sf_wr_qqqqq : std_logic; + signal too_large_dropped : std_logic_vector(31 downto 0); + signal previous_ttype, previous_bank : std_logic_vector(3 downto 0); + signal sf_afull_real : std_logic; + +begin + + --********* + -- RECEIVING PART + --********* + + SAVE_MACHINE_PROC : process(RESET, CLK_IPU) + begin + if RESET = '1' then + save_current_state <= IDLE; + elsif rising_edge(CLK_IPU) then + save_current_state <= save_next_state; + end if; + end process SAVE_MACHINE_PROC; + + SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, size_check_ctr) + begin + case (save_current_state) is + when IDLE => + rec_state <= x"1"; + if (CTS_START_READOUT_IN = '1') then + save_next_state <= SAVE_EVT_ADDR; + else + save_next_state <= IDLE; + end if; + + when SAVE_EVT_ADDR => + rec_state <= x"2"; + save_next_state <= WAIT_FOR_DATA; + + when WAIT_FOR_DATA => + rec_state <= x"3"; + if (FEE_BUSY_IN = '1') then + save_next_state <= SAVE_DATA; + else + save_next_state <= WAIT_FOR_DATA; + end if; + + when SAVE_DATA => + rec_state <= x"4"; + if (FEE_BUSY_IN = '0') then + save_next_state <= TERMINATE; + else + save_next_state <= SAVE_DATA; + end if; + + when TERMINATE => + rec_state <= x"5"; + if (CTS_READ_IN = '1') then + save_next_state <= CLOSE; + else + save_next_state <= TERMINATE; + end if; + + when CLOSE => + rec_state <= x"6"; + if (CTS_START_READOUT_IN = '0') then + save_next_state <= ADD_SUBSUB1; + else + save_next_state <= CLOSE; + end if; + + when ADD_SUBSUB1 => + rec_state <= x"7"; + save_next_state <= ADD_SUBSUB2; + + when ADD_SUBSUB2 => + rec_state <= x"8"; + save_next_state <= ADD_SUBSUB3; + + when ADD_SUBSUB3 => + rec_state <= x"9"; + save_next_state <= ADD_SUBSUB4; + + when ADD_SUBSUB4 => + rec_state <= x"a"; + save_next_state <= FINISH_4_WORDS; + + when FINISH_4_WORDS => + rec_state <= x"b"; + if (size_check_ctr = 1) then + save_next_state <= CLEANUP; + else + save_next_state <= FINISH_4_WORDS; + end if; + + when CLEANUP => + rec_state <= x"c"; + save_next_state <= IDLE; + + end case; + end process SAVE_MACHINE; + + SF_WR_EN_PROC : process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + sf_afull_q <= sf_afull; + sf_afull_qq <= sf_afull_q; + sf_afull_qqq <= sf_afull_qq; + sf_afull_qqqq <= sf_afull_qqq; + sf_afull_qqqqq <= sf_afull_qqqq; + + --if (sf_afull_q = '0' and save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and FEE_BUSY_IN = '1') then + if (sf_afull_qqqqq = '0' and save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and FEE_BUSY_IN = '1') then + sf_wr_en <= '1'; + elsif (save_current_state = SAVE_EVT_ADDR) then + sf_wr_en <= '1'; + elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then + sf_wr_en <= '1'; + elsif (save_current_state = FINISH_4_WORDS) then + sf_wr_en <= '1'; + else + sf_wr_en <= '0'; + end if; + end if; + end process SF_WR_EN_PROC; + + SF_DATA_EOD_PROC : process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + case (save_current_state) is + when SAVE_EVT_ADDR => + sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); + sf_data(7 downto 4) <= CTS_READOUT_TYPE_IN; + sf_data(15 downto 8) <= x"ab"; + save_eod <= '0'; + + when SAVE_DATA => + sf_data <= FEE_DATA_IN; + save_eod <= '0'; + + when ADD_SUBSUB1 => + sf_data <= x"0001"; + save_eod <= '0'; + + when ADD_SUBSUB2 => + sf_data <= x"5555"; + save_eod <= '0'; + + when ADD_SUBSUB3 => + sf_data <= FEE_STATUS_BITS_IN(31 downto 16); + save_eod <= '1'; + + when ADD_SUBSUB4 => + sf_data <= FEE_STATUS_BITS_IN(15 downto 0); + save_eod <= '0'; + + when others => sf_data <= (others => '0'); + save_eod <= '0'; + + end case; + end if; + end process SF_DATA_EOD_PROC; + + process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (sf_wr_en = '1') then + sf_data_q <= sf_data; + sf_data_qq <= sf_data_q; + sf_data_qqq <= sf_data_qq; + sf_data_qqqq <= sf_data_qqq; + sf_data_qqqqq <= sf_data_qqqq; + + save_eod_q <= save_eod; + save_eod_qq <= save_eod_q; + save_eod_qqq <= save_eod_qq; + save_eod_qqqq <= save_eod_qqq; + save_eod_qqqqq <= save_eod_qqqq; + else + sf_data_q <= sf_data_q; + sf_data_qq <= sf_data_qq; + sf_data_qqq <= sf_data_qqq; + sf_data_qqqq <= sf_data_qqqq; + sf_data_qqqqq <= sf_data_qqqqq; + + save_eod_q <= save_eod_q; + save_eod_qq <= save_eod_qq; + save_eod_qqq <= save_eod_qqq; + save_eod_qqqq <= save_eod_qqqq; + save_eod_qqqqq <= save_eod_qqqq; + end if; + + sf_wr_q <= sf_wr_en and (not sf_wr_lock) and DATA_GBE_ENABLE_IN; + sf_wr_qq <= sf_wr_q; + sf_wr_qqq <= sf_wr_qq; + sf_wr_qqqq <= sf_wr_qqq; + sf_wr_qqqqq <= sf_wr_qqqq; + + end if; + end process; + + process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (save_current_state = IDLE) then + size_check_ctr <= 0; + elsif (save_current_state = SAVE_DATA and sf_wr_en = '1' and size_check_ctr /= 4) then + size_check_ctr <= size_check_ctr + 1; + elsif (save_current_state = FINISH_4_WORDS and size_check_ctr /= 0) then + size_check_ctr <= size_check_ctr - 1; + else + size_check_ctr <= size_check_ctr; + end if; + + if (save_current_state = IDLE) then + sf_wr_lock <= '1'; + elsif (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") < ("00" & MAX_SUBEVENT_SIZE_IN)) then -- condition to ALLOW an event to be passed forward + sf_wr_lock <= '0'; + else + sf_wr_lock <= sf_wr_lock; + end if; + + end if; + end process; + + process(RESET, CLK_IPU) + begin + if (RESET = '1') then + too_large_dropped <= (others => '0'); + elsif rising_edge(CLK_IPU) then + if (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") >= ("00" & MAX_SUBEVENT_SIZE_IN)) then + too_large_dropped <= too_large_dropped + x"1"; + else + too_large_dropped <= too_large_dropped; + end if; + end if; + end process; + + SAVED_EVENTS_CTR_PROC : process(RESET, CLK_IPU) + begin + if (RESET = '1') then + saved_events_ctr <= (others => '0'); + elsif rising_edge(CLK_IPU) then + if (save_current_state = ADD_SUBSUB4 and sf_wr_lock = '0' and DATA_GBE_ENABLE_IN = '1') then + saved_events_ctr <= saved_events_ctr + x"1"; + else + saved_events_ctr <= saved_events_ctr; + end if; + end if; + end process SAVED_EVENTS_CTR_PROC; + + CTS_DATAREADY_PROC : process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then + CTS_DATAREADY_OUT <= '1'; + elsif (save_current_state = TERMINATE) then + CTS_DATAREADY_OUT <= '1'; + else + CTS_DATAREADY_OUT <= '0'; + end if; + end if; + end process CTS_DATAREADY_PROC; + + CTS_READOUT_FINISHED_PROC : process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (save_current_state = CLOSE) then + CTS_READOUT_FINISHED_OUT <= '1'; + else + CTS_READOUT_FINISHED_OUT <= '0'; + end if; + end if; + end process CTS_READOUT_FINISHED_PROC; + + CTS_LENGTH_OUT <= (others => '0'); + CTS_ERROR_PATTERN_OUT <= (others => '0'); + + CTS_DATA_PROC : process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + CTS_DATA_OUT <= "0001" & cts_rnd(11 downto 0) & cts_trg; + end if; + end process CTS_DATA_PROC; + + CTS_RND_TRG_PROC : process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (save_current_state = SAVE_DATA and save_ctr = x"0000") then + cts_rnd <= sf_data; + cts_trg <= cts_trg; + elsif (save_current_state = SAVE_DATA and save_ctr = x"0001") then + cts_rnd <= cts_rnd; + cts_trg <= sf_data; + else + cts_rnd <= cts_rnd; + cts_trg <= cts_trg; + end if; + end if; + end process CTS_RND_TRG_PROC; + + SAVE_CTR_PROC : process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (save_current_state = IDLE) then + save_ctr <= (others => '0'); + elsif (save_current_state = SAVE_DATA and sf_wr_en = '1') then + save_ctr <= save_ctr + x"1"; + else + save_ctr <= save_ctr; + end if; + end if; + end process SAVE_CTR_PROC; + + sf_afull_sim_gen : if DO_SIMULATION = 1 generate + +-- process +-- begin +-- sf_afull <= '0'; +-- wait for 20850 ns; +-- sf_afull <= '1'; +-- wait for 20 ns; +-- sf_afull <= '0'; +-- wait; +-- end process; + + sf_afull <= sf_afull_real; + + end generate sf_afull_sim_gen; + + sf_afull_impl_gen : if DO_SIMULATION = 0 generate + + sf_afull <= sf_afull_real; + + end generate sf_afull_impl_gen; + + size_check_debug : if DO_SIMULATION = 1 generate + + process(save_ctr, sf_data_qqqqq, save_current_state) + begin + if (save_ctr > x"000c" and save_current_state = SAVE_DATA) then + assert (save_ctr - x"000c" = sf_data_qqqqq) report "IPU_INTERFACE: Mismatch between data and internal counters" severity warning; + end if; + end process; + + end generate size_check_debug; + + FEE_READ_PROC : process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (sf_afull = '0') then + if (save_current_state = IDLE or save_current_state = SAVE_EVT_ADDR or save_current_state = WAIT_FOR_DATA or save_current_state = SAVE_DATA) then + FEE_READ_OUT <= '1'; + else + FEE_READ_OUT <= '0'; + end if; + else + FEE_READ_OUT <= '0'; + end if; + end if; + end process FEE_READ_PROC; + + THE_SPLIT_FIFO : fifo_32kx16x8_mb2 --fifo_16kx18x9 + port map( + -- Byte swapping for correct byte order on readout side of FIFO + Data(7 downto 0) => sf_data_qqqqq(15 downto 8), + Data(8) => '0', + Data(16 downto 9) => sf_data_qqqqq(7 downto 0), + Data(17) => save_eod_qqqqq, + WrClock => CLK_IPU, + RdClock => CLK_GBE, + WrEn => sf_wr_q, -- sf_wr_en + RdEn => sf_rd_en, + Reset => sf_reset, + RPReset => sf_reset, + AmEmptyThresh => b"0000_0000_0000_0010", --b"0000_0000_0000_0010", -- one byte ahead + AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 -- b"001_0011_1000_1000" + Q(7 downto 0) => sf_q, + Q(8) => sf_eos, + --WCNT => open, + --RCNT => open, + Empty => sf_empty, + AlmostEmpty => sf_aempty, + Full => sf_full, -- WARNING, JUST FOR DEBUG + AlmostFull => sf_afull_real + ); + + sf_reset <= RESET; + + --********* + -- LOADING PART + --********* + + PC_DATA_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + pc_data <= sf_q; + end if; + end process PC_DATA_PROC; + + LOAD_MACHINE_PROC : process(RESET, CLK_GBE) + begin + if RESET = '1' then + load_current_state <= IDLE; + elsif rising_edge(CLK_GBE) then + load_current_state <= load_next_state; + end if; + end process LOAD_MACHINE_PROC; + + LOAD_MACHINE : process(load_current_state, saved_events_ctr_gbe, loaded_events_ctr, loaded_bytes_ctr, PC_READY_IN, sf_eos, queue_size, number_of_subs, subevent_size, MAX_QUEUE_SIZE_IN, MAX_SUBS_IN_QUEUE_IN, MAX_SINGLE_SUB_SIZE_IN, previous_bank, previous_ttype, trigger_type, bank_select, MULT_EVT_ENABLE_IN) + begin + case (load_current_state) is + when IDLE => + load_state <= x"1"; + load_next_state <= WAIT_FOR_SUBS; + + when WAIT_FOR_SUBS => + load_state <= x"2"; + if (saved_events_ctr_gbe /= loaded_events_ctr) then + load_next_state <= REMOVE; + else + load_next_state <= WAIT_FOR_SUBS; + end if; + + when REMOVE => + load_state <= x"3"; + if (loaded_bytes_ctr = x"0008") then + load_next_state <= WAIT_ONE; + else + load_next_state <= REMOVE; + end if; + + when WAIT_ONE => + load_state <= x"4"; + load_next_state <= WAIT_TWO; + + when WAIT_TWO => + load_state <= x"4"; + load_next_state <= DECIDE; + + --TODO: all queue split conditions here and also in the size process + when DECIDE => + load_state <= x"5"; + if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then -- max udp packet exceeded + load_next_state <= CLOSE_QUEUE; + elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then + load_next_state <= CLOSE_QUEUE; + elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then + load_next_state <= CLOSE_QUEUE; + elsif (trigger_type /= previous_ttype and number_of_subs /= x"0000") then + load_next_state <= CLOSE_QUEUE; + elsif (bank_select /= previous_bank and number_of_subs /= x"0000") then + load_next_state <= CLOSE_QUEUE; + else + load_next_state <= PREPARE_TO_LOAD_SUB; + end if; + + when PREPARE_TO_LOAD_SUB => + load_state <= x"6"; + load_next_state <= WAIT_FOR_LOAD; + + when WAIT_FOR_LOAD => + load_state <= x"7"; + if (PC_READY_IN = '1') then + load_next_state <= LOAD; + else + load_next_state <= WAIT_FOR_LOAD; + end if; + + when LOAD => + load_state <= x"8"; + if (sf_eos = '1') then + load_next_state <= CLOSE_SUB; + else + load_next_state <= LOAD; + end if; + + when CLOSE_SUB => + load_state <= x"9"; + if (subevent_size > ("00" & MAX_SINGLE_SUB_SIZE_IN) and queue_size = (subevent_size + x"10" + x"8" + x"4")) then + load_next_state <= CLOSE_QUEUE_IMMEDIATELY; + else + load_next_state <= WAIT_FOR_SUBS; + end if; + + when CLOSE_QUEUE => + load_state <= x"a"; + load_next_state <= PREPARE_TO_LOAD_SUB; + + when CLOSE_QUEUE_IMMEDIATELY => + load_state <= x"b"; + load_next_state <= WAIT_FOR_SUBS; + + when others => load_next_state <= IDLE; + + end case; + end process LOAD_MACHINE; + + saved_ctr_sync : signal_sync + generic map( + WIDTH => 8, + DEPTH => 2 + ) + port map( + RESET => RESET, + CLK0 => CLK_GBE, + CLK1 => CLK_GBE, + D_IN => saved_events_ctr, + D_OUT => saved_events_ctr_gbe + ); + + --TODO: all queue split conditions here + -- the queue size counter used only for closing current queue + -- sums up all subevent sizes with their headers and stuff + process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = IDLE) then + queue_size <= (others => '0'); + elsif (load_current_state = CLOSE_QUEUE_IMMEDIATELY) then + queue_size <= (others => '0'); + elsif (load_current_state = WAIT_TWO) then + queue_size <= queue_size + subevent_size + x"10" + x"8" + x"4"; + elsif (load_current_state = DECIDE) then + if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then + queue_size <= subevent_size + x"10" + x"8" + x"4"; + elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then + queue_size <= subevent_size + x"10" + x"8" + x"4"; + elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then + queue_size <= subevent_size + x"10" + x"8" + x"4"; + elsif (trigger_type /= previous_ttype and number_of_subs /= x"0000") then + queue_size <= subevent_size + x"10" + x"8" + x"4"; + elsif (bank_select /= previous_bank and number_of_subs /= x"0000") then + queue_size <= subevent_size + x"10" + x"8" + x"4"; + else + queue_size <= queue_size; + end if; + else + queue_size <= queue_size; + end if; + end if; + end process; + + process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = IDLE or load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY) then + number_of_subs <= (others => '0'); + elsif (load_current_state = PREPARE_TO_LOAD_SUB) then + number_of_subs <= number_of_subs + x"1"; + else + number_of_subs <= number_of_subs; + end if; + end if; + end process; + + SF_RD_EN_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (PC_READY_IN = '1') then + if (load_current_state = REMOVE) then + sf_rd_en <= '1'; + elsif (load_current_state = LOAD and PC_READY_IN = '1') then --pc_ready_q = '1') then + sf_rd_en <= '1'; + else + sf_rd_en <= '0'; + end if; + else + sf_rd_en <= '0'; + end if; + end if; + end process SF_RD_EN_PROC; + + --***** + -- information extraction + + process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = IDLE) then + previous_bank <= x"0"; + previous_ttype <= x"0"; + elsif (load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY or load_current_state = CLOSE_SUB) then + previous_bank <= bank_select; + previous_ttype <= trigger_type; + else + previous_bank <= previous_bank; + previous_ttype <= previous_ttype; + end if; + end if; + end process; + + TRIGGER_RANDOM_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = IDLE) then + trigger_random <= (others => '0'); + elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0005") then + trigger_random <= pc_data; + else + trigger_random <= trigger_random; + end if; + end if; + end process TRIGGER_RANDOM_PROC; + + TRIGGER_NUMBER_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = IDLE) then + trigger_number <= (others => '0'); + elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0007") then + trigger_number(7 downto 0) <= pc_data; + elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0006") then + trigger_number(15 downto 8) <= pc_data; + else + trigger_number <= trigger_number; + end if; + end if; + end process TRIGGER_NUMBER_PROC; + + SUBEVENT_SIZE_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = IDLE) then + subevent_size <= (others => '0'); + elsif (load_current_state = WAIT_ONE and sf_rd_en = '1' and loaded_bytes_ctr = x"0009") then + subevent_size(9 downto 2) <= pc_data; + elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0008") then + subevent_size(17 downto 10) <= pc_data; + else + subevent_size <= subevent_size; + end if; + end if; + end process SUBEVENT_SIZE_PROC; + + TRIGGER_TYPE_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = IDLE) then + trigger_type <= x"0"; + elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then + trigger_type <= pc_data(7 downto 4); + else + trigger_type <= trigger_type; + end if; + end if; + end process TRIGGER_TYPE_PROC; + + -- end of extraction + --***** + + --***** + -- counters + + LOADED_EVENTS_CTR_PROC : process(RESET, CLK_GBE) + begin + if (RESET = '1') then + loaded_events_ctr <= (others => '0'); + elsif rising_edge(CLK_GBE) then + if (load_current_state = CLOSE_SUB) then + loaded_events_ctr <= loaded_events_ctr + x"1"; + else + loaded_events_ctr <= loaded_events_ctr; + end if; + end if; + end process LOADED_EVENTS_CTR_PROC; + + LOADED_BYTES_CTR_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = WAIT_FOR_SUBS) then + loaded_bytes_ctr <= (others => '0'); + elsif (sf_rd_en = '1') then + if (load_current_state = REMOVE) then + loaded_bytes_ctr <= loaded_bytes_ctr + x"1"; + else + loaded_bytes_ctr <= loaded_bytes_ctr; + end if; + else + loaded_bytes_ctr <= loaded_bytes_ctr; + end if; + end if; + end process LOADED_BYTES_CTR_PROC; + + READOUT_CTR_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (READOUT_CTR_VALID_IN = '1') then + readout_ctr <= READOUT_CTR_IN; + elsif (load_current_state = DECIDE) then + readout_ctr <= readout_ctr + x"1"; + else + readout_ctr <= readout_ctr; + end if; + end if; + end process READOUT_CTR_PROC; + + -- end of counters + --***** + + --***** + -- event builder selection + + + BANK_SELECT_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = IDLE) then + bank_select <= x"0"; + elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then + bank_select <= pc_data(3 downto 0); + else + bank_select <= bank_select; + end if; + end if; + end process BANK_SELECT_PROC; + + BANK_SELECT_OUT <= bank_select; + + START_CONFIG_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then + START_CONFIG_OUT <= '1'; + elsif (CONFIG_DONE_IN = '1') then + START_CONFIG_OUT <= '0'; + else + START_CONFIG_OUT <= '0'; + end if; + end if; + end process START_CONFIG_PROC; + + -- end of event builder selection + --***** + + + PC_WR_EN_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + --pc_ready_q <= PC_READY_IN; + if (PC_READY_IN = '1') then + if (load_current_state = LOAD) then + PC_WR_EN_OUT <= '1'; + else + PC_WR_EN_OUT <= '0'; + end if; + else + PC_WR_EN_OUT <= '0'; + end if; + end if; + end process PC_WR_EN_PROC; + + PC_SOS_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = PREPARE_TO_LOAD_SUB) then + PC_SOS_OUT <= '1'; + else + PC_SOS_OUT <= '0'; + end if; + end if; + end process PC_SOS_PROC; + + PC_EOD_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + PC_EOS_OUT <= sf_eos; + end if; + end process PC_EOD_PROC; + + PC_EOQ_PROC : process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY) then + PC_EOQ_OUT <= '1'; + else + PC_EOQ_OUT <= '0'; + end if; + end if; + end process PC_EOQ_PROC; + + --******* + -- outputs + + PC_DATA_OUT <= pc_data; + + PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & subevent_size; + + PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & trigger_number & trigger_random; + + PC_TRIGGER_TYPE_OUT <= trigger_type; + + process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + DEBUG_OUT(3 downto 0) <= rec_state; + DEBUG_OUT(7 downto 4) <= load_state; + DEBUG_OUT(8) <= sf_empty; + DEBUG_OUT(9) <= sf_aempty; + DEBUG_OUT(10) <= sf_full; + DEBUG_OUT(11) <= sf_afull; + end if; + end process; + + DEBUG_OUT(383 downto 12) <= (others => '0'); + MONITOR_OUT(31 downto 0) <= too_large_dropped; + MONITOR_OUT(223 downto 32) <= (others => '0'); + +end architecture RTL; diff --git a/gbe_trb/base/trb_net16_gbe_mac_control.vhd b/gbe_trb/base/trb_net16_gbe_mac_control.vhd new file mode 100644 index 0000000..5a9a607 --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_mac_control.vhd @@ -0,0 +1,223 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +--******** +-- configures TriSpeed MAC and signalizes when it's ready +-- used also to filter out frames with different addresses +-- after main configuration (by setting TsMAC filtering accordingly) + + + +entity trb_net16_gbe_mac_control is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- signals to/from main controller + MC_TSMAC_READY_OUT : out std_logic; + MC_RECONF_IN : in std_logic; + MC_GBE_EN_IN : in std_logic; + MC_RX_DISCARD_FCS : in std_logic; + MC_PROMISC_IN : in std_logic; + MC_MAC_ADDR_IN : in std_logic_vector(47 downto 0); + +-- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT : out std_logic_vector(7 downto 0); + TSM_HDATA_OUT : out std_logic_vector(7 downto 0); + TSM_HCS_N_OUT : out std_logic; + TSM_HWRITE_N_OUT : out std_logic; + TSM_HREAD_N_OUT : out std_logic; + TSM_HREADY_N_IN : in std_logic; + TSM_HDATA_EN_N_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end trb_net16_gbe_mac_control; + + +architecture trb_net16_gbe_mac_control of trb_net16_gbe_mac_control is + +attribute syn_encoding : string; + +type mac_conf_states is (IDLE, DISABLE, WRITE_TX_RX_CTRL1, WRITE_TX_RX_CTRL2, ENABLE, READY); +signal mac_conf_current_state, mac_conf_next_state : mac_conf_states; +attribute syn_encoding of mac_conf_current_state : signal is "onehot"; + +signal tsmac_ready : std_logic; +signal reg_mode : std_logic_vector(7 downto 0); +signal reg_tx_rx_ctrl1, reg_tx_rx_ctrl2 : std_logic_vector(7 downto 0); +signal reg_max_pkt_size : std_logic_vector(15 downto 0); +signal reg_ipg : std_logic_vector(15 downto 0); +signal reg_mac0 : std_logic_vector(15 downto 0); +signal reg_mac1 : std_logic_vector(15 downto 0); +signal reg_mac2 : std_logic_vector(15 downto 0); + +signal haddr : std_logic_vector(7 downto 0); +signal hcs_n : std_logic; +signal hwrite_n : std_logic; +signal hdata_pointer : integer range 0 to 1; +signal state : std_logic_vector(3 downto 0); +signal hready_n_q : std_logic; + +begin + +reg_mode(7 downto 4) <= x"0"; +reg_mode(3) <= '1'; -- tx_en +reg_mode(2) <= '1'; -- rx_en +reg_mode(1) <= '1'; -- flow_control en +reg_mode(0) <= MC_GBE_EN_IN; -- gbe en + +reg_tx_rx_ctrl2(7 downto 1) <= (others => '0'); -- reserved +reg_tx_rx_ctrl2(0) <= '1'; -- receive short +reg_tx_rx_ctrl1(7) <= '1'; -- receive broadcast +reg_tx_rx_ctrl1(6) <= '1'; -- drop control +reg_tx_rx_ctrl1(5) <= '0'; -- half_duplex en +reg_tx_rx_ctrl1(4) <= '1'; -- receive multicast +reg_tx_rx_ctrl1(3) <= '1'; -- receive pause +reg_tx_rx_ctrl1(2) <= '0'; -- transmit disable FCS +reg_tx_rx_ctrl1(1) <= '1'; -- receive discard FCS and padding +reg_tx_rx_ctrl1(0) <= MC_PROMISC_IN; -- promiscuous mode + + +MAC_CONF_MACHINE_PROC : process(CLK) +begin + if RESET = '1' then + mac_conf_current_state <= IDLE; + elsif rising_edge(CLK) then +-- if (RESET = '1') then +-- mac_conf_current_state <= IDLE; +-- else + mac_conf_current_state <= mac_conf_next_state; +-- end if; + end if; +end process MAC_CONF_MACHINE_PROC; + +MAC_CONF_MACHINE : process(mac_conf_current_state, MC_RECONF_IN, TSM_HREADY_N_IN) +begin + + case mac_conf_current_state is + + when IDLE => + if (MC_RECONF_IN = '1') then + mac_conf_next_state <= DISABLE; + else + mac_conf_next_state <= IDLE; + end if; + + when DISABLE => + if (TSM_HREADY_N_IN = '0') then + mac_conf_next_state <= WRITE_TX_RX_CTRL1; + else + mac_conf_next_state <= DISABLE; + end if; + + when WRITE_TX_RX_CTRL1 => + if (TSM_HREADY_N_IN = '0') then + mac_conf_next_state <= WRITE_TX_RX_CTRL2; + else + mac_conf_next_state <= WRITE_TX_RX_CTRL1; + end if; + + when WRITE_TX_RX_CTRL2 => + if (TSM_HREADY_N_IN = '0') then + mac_conf_next_state <= ENABLE; + else + mac_conf_next_state <= WRITE_TX_RX_CTRL2; + end if; + + when ENABLE => + if (TSM_HREADY_N_IN = '0') then + mac_conf_next_state <= READY; + else + mac_conf_next_state <= ENABLE; + end if; + + when READY => + if (MC_RECONF_IN = '1') then + mac_conf_next_state <= DISABLE; + else + mac_conf_next_state <= READY; + end if; + + end case; + +end process MAC_CONF_MACHINE; + +HADDR_PROC : process(CLK) +begin + if rising_edge(CLK) then + case mac_conf_current_state is + when IDLE => + TSM_HADDR_OUT <= x"00"; + when DISABLE => + TSM_HADDR_OUT <= x"00"; + when WRITE_TX_RX_CTRL1 => + TSM_HADDR_OUT <= x"02"; + when WRITE_TX_RX_CTRL2 => + TSM_HADDR_OUT <= x"03"; + when ENABLE => + TSM_HADDR_OUT <= x"00"; + when READY => + TSM_HADDR_OUT <= x"00"; + end case; + end if; +end process HADDR_PROC; + +HDATA_PROC : process(CLK) +begin + if rising_edge(CLK) then + case mac_conf_current_state is + when IDLE => + TSM_HDATA_OUT <= x"00"; + when DISABLE => + TSM_HDATA_OUT <= x"00"; + when WRITE_TX_RX_CTRL1 => + TSM_HDATA_OUT <= reg_tx_rx_ctrl1; + when WRITE_TX_RX_CTRL2 => + TSM_HDATA_OUT <= reg_tx_rx_ctrl2; + when ENABLE => + TSM_HDATA_OUT <= reg_mode; + when READY => + TSM_HDATA_OUT <= x"00"; + end case; + end if; +end process HDATA_PROC; + +process(CLK) +begin + if rising_edge(CLK) then + if (mac_conf_current_state = IDLE or mac_conf_current_state = READY) then + hcs_n <= '1'; + hwrite_n <= '1'; + elsif (TSM_HREADY_N_IN = '1') then + hcs_n <= '0'; + hwrite_n <= '0'; + else + hcs_n <= '1'; + hwrite_n <= '1'; + end if; + + if (mac_conf_current_state = READY) then + tsmac_ready <= '1'; + else + tsmac_ready <= '0'; + end if; + end if; +end process; + +TSM_HCS_N_OUT <= hcs_n; +TSM_HWRITE_N_OUT <= hwrite_n; +TSM_HREAD_N_OUT <= '1'; +MC_TSMAC_READY_OUT <= tsmac_ready; + + +end trb_net16_gbe_mac_control; + + diff --git a/gbe_trb/base/trb_net16_gbe_main_control.vhd b/gbe_trb/base/trb_net16_gbe_main_control.vhd new file mode 100644 index 0000000..1123e1f --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_main_control.vhd @@ -0,0 +1,1000 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- controls the work of the whole gbe in both directions +-- multiplexes the output between data stream and output slow control packets based on priority +-- reacts to incoming gbe slow control commands +-- + + +entity trb_net16_gbe_main_control is + generic( + RX_PATH_ENABLE : integer range 0 to 1 := 1; + DO_SIMULATION : integer range 0 to 1 := 0; + + INCLUDE_READOUT : std_logic := '0'; + INCLUDE_SLOWCTRL : std_logic := '0'; + INCLUDE_DHCP : std_logic := '0'; + INCLUDE_ARP : std_logic := '0'; + INCLUDE_PING : std_logic := '0'; + + READOUT_BUFFER_SIZE : integer range 1 to 4; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 + ); +port ( + CLK : in std_logic; -- system clock + CLK_125 : in std_logic; + RESET : in std_logic; + + MC_LINK_OK_OUT : out std_logic; + MC_RESET_LINK_IN : in std_logic; + MC_IDLE_TOO_LONG_OUT : out std_logic; + MC_DHCP_DONE_OUT : out std_logic; + MC_MY_MAC_OUT : out std_logic_vector(47 downto 0); + MC_MY_MAC_IN : in std_logic_vector(47 downto 0); + +-- signals to/from receive controller + RC_FRAME_WAITING_IN : in std_logic; + RC_LOADING_DONE_OUT : out std_logic; + RC_DATA_IN : in std_logic_vector(8 downto 0); + RC_RD_EN_OUT : out std_logic; + RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + +-- signals to/from transmit controller + TC_TRANSMIT_CTRL_OUT : out std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_RD_EN_IN : in std_logic; + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_TRANSMIT_DONE_IN : in std_logic; + +-- signals to/from sgmii/gbe pcs_an_complete + PCS_AN_COMPLETE_IN : in std_logic; + +-- signals to/from hub + MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); + + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + + -- signal for data readout + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + -- ip configurator + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + + MAKE_RESET_OUT : out std_logic; + +-- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT : out std_logic_vector(7 downto 0); + TSM_HDATA_OUT : out std_logic_vector(7 downto 0); + TSM_HCS_N_OUT : out std_logic; + TSM_HWRITE_N_OUT : out std_logic; + TSM_HREAD_N_OUT : out std_logic; + TSM_HREADY_N_IN : in std_logic; + TSM_HDATA_EN_N_IN : in std_logic; + TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); + TSM_RX_STAT_EN_IN : in std_logic; + + MAC_READY_CONF_IN : in std_logic; + MAC_RECONF_OUT : out std_logic; + + + MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); + + DATA_HIST_OUT : out hist_array; + SCTRL_HIST_OUT : out hist_array +); +end trb_net16_gbe_main_control; + + +architecture trb_net16_gbe_main_control of trb_net16_gbe_main_control is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group"; + +attribute syn_encoding : string; + +signal tsm_ready : std_logic; +signal tsm_reconf : std_logic; +signal tsm_haddr : std_logic_vector(7 downto 0); +signal tsm_hdata : std_logic_vector(7 downto 0); +signal tsm_hcs_n : std_logic; +signal tsm_hwrite_n : std_logic; +signal tsm_hread_n : std_logic; + +type link_states is (INACTIVE, ACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS); +signal link_current_state, link_next_state : link_states; +attribute syn_encoding of link_current_state : signal is "onehot"; + +signal link_down_ctr : std_logic_vector(15 downto 0); +signal link_down_ctr_lock : std_logic; +signal link_ok : std_logic; +signal link_ok_timeout_ctr : std_logic_vector(15 downto 0); + +signal mac_control_debug : std_logic_vector(63 downto 0); + +type flow_states is (IDLE, TRANSMIT_CTRL, WAIT_FOR_FC, CLEANUP); +signal flow_current_state, flow_next_state : flow_states; +attribute syn_encoding of flow_current_state : signal is "onehot"; + +signal state : std_logic_vector(3 downto 0); +signal link_state : std_logic_vector(3 downto 0); +signal redirect_state : std_logic_vector(3 downto 0); + +signal ps_wr_en : std_logic; +signal ps_response_ready : std_logic; +signal ps_busy : std_logic_vector(c_MAX_PROTOCOLS -1 downto 0); +signal rc_rd_en : std_logic; +signal first_byte : std_logic; +signal first_byte_q : std_logic; +signal first_byte_qq : std_logic; +signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal loaded_bytes_ctr : std_Logic_vector(15 downto 0); + +signal dhcp_start : std_logic; +signal dhcp_done : std_logic; +signal wait_ctr : std_logic_vector(31 downto 0); + +signal rc_data_local : std_logic_vector(8 downto 0); + +-- debug +signal frame_waiting_ctr : std_logic_vector(15 downto 0); +signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + +type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, WAIT_ONE, FINISH, CLEANUP); +signal redirect_current_state, redirect_next_state : redirect_states; +attribute syn_encoding of redirect_current_state : signal is "onehot"; + +signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic; + +type stats_states is (IDLE, LOAD_VECTOR, CLEANUP); +signal stats_current_state, stats_next_state : stats_states; + +signal stat_rdy, stat_ack : std_logic; +signal rx_stat_en_q : std_logic; +signal rx_stat_vec_q : std_logic_vector(31 downto 0); + +type array_of_ctrs is array(15 downto 0) of std_logic_vector(31 downto 0); +signal arr : array_of_ctrs; +signal stats_ctr : integer range 0 to 15; +signal stat_data : std_logic_vector(31 downto 0); +signal stat_addr : std_logic_vector(7 downto 0); + +signal unique_id : std_logic_vector(63 downto 0); + + +signal nothing_sent : std_logic; +signal nothing_sent_ctr : std_logic_vector(31 downto 0); + +signal dbg_ps : std_Logic_vector(63 downto 0); + +signal tc_data : std_logic_vector(8 downto 0); + +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_keep of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true; +attribute syn_preserve of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true; + +signal mc_busy : std_logic; +signal incl_dhcp : std_logic; + +begin + +unique_id <= MC_UNIQUE_ID_IN; + +protocol_selector : trb_net16_gbe_protocol_selector +generic map( + RX_PATH_ENABLE => RX_PATH_ENABLE, + DO_SIMULATION => DO_SIMULATION, + + INCLUDE_READOUT => INCLUDE_READOUT, + INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, + INCLUDE_DHCP => INCLUDE_DHCP, + INCLUDE_ARP => INCLUDE_ARP, + INCLUDE_PING => INCLUDE_PING, + + READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, + SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE + ) +port map( + CLK => CLK, + RESET => RESET, + RESET_FOR_DHCP => MC_RESET_LINK_IN, + + PS_DATA_IN => rc_data_local, -- RC_DATA_IN, + PS_WR_EN_IN => ps_wr_en_qq, --ps_wr_en, + PS_PROTO_SELECT_IN => proto_select, + PS_BUSY_OUT => ps_busy, + PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN, + PS_RESPONSE_READY_OUT => ps_response_ready, + + PS_SRC_MAC_ADDRESS_IN => RC_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => RC_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => RC_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => RC_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => RC_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => RC_DEST_UDP_PORT_IN, + + TC_DATA_OUT => tc_data, + TC_RD_EN_IN => TC_RD_EN_IN, + TC_FRAME_SIZE_OUT => TC_FRAME_SIZE_OUT, + TC_FRAME_TYPE_OUT => TC_FRAME_TYPE_OUT, + TC_IP_PROTOCOL_OUT => TC_IP_PROTOCOL_OUT, + TC_IDENT_OUT => TC_IDENT_OUT, + TC_DEST_MAC_OUT => TC_DEST_MAC_OUT, + TC_DEST_IP_OUT => TC_DEST_IP_OUT, + TC_DEST_UDP_OUT => TC_DEST_UDP_OUT, + TC_SRC_MAC_OUT => TC_SRC_MAC_OUT, + TC_SRC_IP_OUT => TC_SRC_IP_OUT, + TC_SRC_UDP_OUT => TC_SRC_UDP_OUT, + + MC_BUSY_IN => mc_busy, + + MY_MAC_IN => MC_MY_MAC_IN, + MY_IP_OUT => open, + DHCP_START_IN => dhcp_start, + DHCP_DONE_OUT => dhcp_done, + + GSC_CLK_IN => GSC_CLK_IN, + GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => GSC_INIT_READ_IN, + GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, + GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, + GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, + GSC_BUSY_IN => GSC_BUSY_IN, + + MAKE_RESET_OUT => MAKE_RESET_OUT, + + -- CTS interface + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + -- Data payload interface + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + -- ip configurator + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + + CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, + CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, + CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, + CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, + CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, + CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, + CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, + CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, + CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, + CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, + CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, + CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, + CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, + + CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, + CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN, + + -- input for statistics from outside + STAT_DATA_IN => stat_data, + STAT_ADDR_IN => stat_addr, + STAT_DATA_RDY_IN => stat_rdy, + STAT_DATA_ACK_OUT => stat_ack, + + MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT, + MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT, + MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT, + MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT, + MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT, + MONITOR_SELECT_DROP_IN_OUT => MONITOR_SELECT_DROP_IN_OUT, + MONITOR_SELECT_GEN_DBG_OUT => MONITOR_SELECT_GEN_DBG_OUT, + + DATA_HIST_OUT => DATA_HIST_OUT, + SCTRL_HIST_OUT => SCTRL_HIST_OUT +); + +TC_DATA_OUT <= tc_data; + +-- gk 07.11.11 +-- do not select any response constructors when dropping a frame +proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0'); + +-- gk 07.11.11 +DISABLE_REDIRECT_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + disable_redirect <= '0'; + elsif (redirect_current_state = CHECK_TYPE) then + if (link_current_state /= ACTIVE and link_current_state /= GET_ADDRESS) then + disable_redirect <= '1'; + elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN /= "10") then + disable_redirect <= '1'; + else + disable_redirect <= '0'; + end if; + else + disable_redirect <= disable_redirect; + end if; + end if; +end process DISABLE_REDIRECT_PROC; + +-- warning +SYNC_PROC : process(CLK) +begin + if rising_edge(CLK) then + rc_data_local <= RC_DATA_IN; + end if; +end process SYNC_PROC; + +REDIRECT_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + redirect_current_state <= IDLE; + elsif rising_edge(CLK) then + if RX_PATH_ENABLE = 1 then + redirect_current_state <= redirect_next_state; + else + redirect_current_state <= IDLE; + end if; + end if; +end process REDIRECT_MACHINE_PROC; + +REDIRECT_MACHINE : process(redirect_current_state, link_current_state, RC_FRAME_WAITING_IN, ps_busy, RC_FRAME_PROTO_IN, loaded_bytes_ctr, RC_FRAME_SIZE_IN) +begin + case redirect_current_state is + + when IDLE => + redirect_state <= x"1"; + if (RC_FRAME_WAITING_IN = '1') then + redirect_next_state <= CHECK_TYPE; + else + redirect_next_state <= IDLE; + end if; + + when CHECK_TYPE => + if (link_current_state = ACTIVE) then + redirect_next_state <= CHECK_BUSY; + elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then + redirect_next_state <= CHECK_BUSY; + else + redirect_next_state <= DROP; + end if; + + when DROP => + redirect_state <= x"7"; + if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then + redirect_next_state <= WAIT_ONE; + else + redirect_next_state <= DROP; + end if; + + when CHECK_BUSY => + redirect_state <= x"6"; + if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then + redirect_next_state <= LOAD; + else + redirect_next_state <= BUSY; + end if; + + when LOAD => + redirect_state <= x"2"; + if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then + redirect_next_state <= WAIT_ONE; + else + redirect_next_state <= LOAD; + end if; + + when BUSY => + redirect_state <= x"3"; + if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then + redirect_next_state <= LOAD; + else + redirect_next_state <= BUSY; + end if; + + when WAIT_ONE => + redirect_state <= x"f"; + redirect_next_state <= FINISH; + + when FINISH => + redirect_state <= x"4"; + redirect_next_state <= CLEANUP; + + when CLEANUP => + redirect_state <= x"5"; + redirect_next_state <= IDLE; + + end case; +end process REDIRECT_MACHINE; + +rc_rd_en <= '1' when redirect_current_state = LOAD or redirect_current_state = DROP else '0'; +RC_RD_EN_OUT <= rc_rd_en; + +LOADING_DONE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RC_DATA_IN(8) = '1' and ps_wr_en_q = '1') then + RC_LOADING_DONE_OUT <= '1'; + else + RC_LOADING_DONE_OUT <= '0'; + end if; + end if; +end process LOADING_DONE_PROC; + +PS_WR_EN_PROC : process(CLK) +begin + if rising_edge(CLK) then + ps_wr_en <= rc_rd_en; + ps_wr_en_q <= ps_wr_en; + ps_wr_en_qq <= ps_wr_en_q; + end if; +end process PS_WR_EN_PROC; + +LOADED_BYTES_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (redirect_current_state = IDLE) then + loaded_bytes_ctr <= (others => '0'); + elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then + loaded_bytes_ctr <= loaded_bytes_ctr + x"1"; + else + loaded_bytes_ctr <= loaded_bytes_ctr; + end if; + end if; +end process LOADED_BYTES_CTR_PROC; + +FIRST_BYTE_PROC : process(CLK) +begin + if rising_edge(CLK) then + first_byte_q <= first_byte; + first_byte_qq <= first_byte_q; + + if (redirect_current_state = IDLE) then + first_byte <= '1'; + else + first_byte <= '0'; + end if; + end if; +end process FIRST_BYTE_PROC; + +--********************* +-- DATA FLOW CONTROL + +FLOW_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + flow_current_state <= IDLE; + elsif rising_edge(CLK) then + flow_current_state <= flow_next_state; + end if; +end process FLOW_MACHINE_PROC; + +FLOW_MACHINE : process(flow_current_state, TC_TRANSMIT_DONE_IN, ps_response_ready, tc_data) +begin + case flow_current_state is + + when IDLE => + if (ps_response_ready = '1') then + flow_next_state <= TRANSMIT_CTRL; + else + flow_next_state <= IDLE; + end if; + + when TRANSMIT_CTRL => + if (tc_data(8) = '1') then + flow_next_state <= WAIT_FOR_FC; + else + flow_next_state <= TRANSMIT_CTRL; + end if; + + when WAIT_FOR_FC => + if (TC_TRANSMIT_DONE_IN = '1') then + flow_next_state <= CLEANUP; + else + flow_next_state <= WAIT_FOR_FC; + end if; + + when CLEANUP => + flow_next_state <= IDLE; + + end case; +end process FLOW_MACHINE; + +process(CLK) +begin + if rising_edge(CLK) then + if (flow_current_state = IDLE and ps_response_ready = '1') then + TC_TRANSMIT_CTRL_OUT <= '1'; + else + TC_TRANSMIT_CTRL_OUT <= '0'; + end if; + + if (flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC) then + mc_busy <= '1'; + else + mc_busy <= '0'; + end if; + end if; +end process; + +--*********************** +-- LINK STATE CONTROL + +lsm_impl_gen : if DO_SIMULATION = 0 generate + LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) + begin + if MC_RESET_LINK_IN = '1' then + link_current_state <= INACTIVE; + elsif rising_edge(CLK) then + if RX_PATH_ENABLE = 1 then + link_current_state <= link_next_state; + else + link_current_state <= INACTIVE; + end if; + end if; + end process; +end generate lsm_impl_gen; + +lsm_sim_gen : if DO_SIMULATION = 1 generate + LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) + begin + if MC_RESET_LINK_IN = '1' then + link_current_state <= GET_ADDRESS; + elsif rising_edge(CLK) then + if RX_PATH_ENABLE = 1 then + link_current_state <= link_next_state; + else + link_current_state <= ACTIVE; + end if; + end if; + end process; +end generate lsm_sim_gen; + +incl_dhcp_gen : if (INCLUDE_DHCP = '1') generate + incl_dhcp <= '1'; +end generate incl_dhcp_gen; +noincl_dhcp_gen : if (INCLUDE_DHCP = '0') generate + incl_dhcp <= '0'; +end generate noincl_dhcp_gen; + +LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, incl_dhcp, MAC_READY_CONF_IN, link_ok_timeout_ctr) +begin + case link_current_state is + + when INACTIVE => + link_state <= x"2"; + if (PCS_AN_COMPLETE_IN = '1') then + link_next_state <= TIMEOUT; + else + link_next_state <= INACTIVE; + end if; + + when TIMEOUT => + link_state <= x"3"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + else + if (link_ok_timeout_ctr = x"ffff") then + link_next_state <= ENABLE_MAC; --FINALIZE; + else + link_next_state <= TIMEOUT; + end if; + end if; + + when ENABLE_MAC => + link_state <= x"4"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + --elsif (tsm_ready = '1') then + elsif (MAC_READY_CONF_IN = '1') then + link_next_state <= FINALIZE; --INACTIVE; + else + link_next_state <= ENABLE_MAC; + end if; + + when FINALIZE => + link_state <= x"5"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + else + link_next_state <= WAIT_FOR_BOOT; --ACTIVE; + end if; + + when WAIT_FOR_BOOT => + link_state <= x"6"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + else + if (wait_ctr = x"0000_1000") then + if (incl_dhcp = '1') then + link_next_state <= GET_ADDRESS; + else + link_next_state <= ACTIVE; + end if; + else + link_next_state <= WAIT_FOR_BOOT; + end if; + end if; + + when GET_ADDRESS => + link_state <= x"7"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + else + if (dhcp_done = '1') then + link_next_state <= ACTIVE; + else + link_next_state <= GET_ADDRESS; + end if; + end if; + + when ACTIVE => + link_state <= x"1"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + else + link_next_state <= ACTIVE; + end if; + + end case; +end process LINK_STATE_MACHINE; + +MC_DHCP_DONE_OUT <= '1' when link_current_state = ACTIVE else '0'; + +LINK_OK_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + --if (RESET = '1') or (link_current_state /= TIMEOUT) then + if (link_current_state /= TIMEOUT) then + link_ok_timeout_ctr <= (others => '0'); + elsif (link_current_state = TIMEOUT) then + link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1"; + end if; + +-- if (link_current_state = ACTIVE or link_current_state = GET_ADDRESS) then +-- link_ok <= '1'; +-- else +-- link_ok <= '0'; +-- end if; + + if (link_current_state = GET_ADDRESS) then + dhcp_start <= '1'; + else + dhcp_start <= '0'; + end if; + end if; +end process LINK_OK_CTR_PROC; + +--link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) else '0'; +link_ok <= '1'; + +WAIT_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (link_current_state = WAIT_FOR_BOOT) then + wait_ctr <= wait_ctr + x"1"; + else + wait_ctr <= (others => '0'); + end if; + end if; +end process WAIT_CTR_PROC; + +--dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0'; + +--LINK_DOWN_CTR_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- link_down_ctr <= (others => '0'); +-- link_down_ctr_lock <= '0'; +-- elsif (PCS_AN_COMPLETE_IN = '1') then +-- link_down_ctr_lock <= '0'; +-- elsif ((PCS_AN_COMPLETE_IN = '0') and (link_down_ctr_lock = '0')) then +-- link_down_ctr <= link_down_ctr + x"1"; +-- link_down_ctr_lock <= '1'; +-- end if; +-- end if; +--end process LINK_DOWN_CTR_PROC; + +MC_LINK_OK_OUT <= link_ok; -- or nothing_sent; + +-- END OF LINK STATE CONTROL +--************* + +--************* +-- GENERATE MAC_ADDRESS +--g_MY_MAC <= unique_id(31 downto 8) & x"be0002"; +MC_MY_MAC_OUT <= unique_id(31 downto 8) & x"be0002"; + +--************* + +--**************** +-- TRI SPEED MAC CONTROLLER + +--TSMAC_CONTROLLER : trb_net16_gbe_mac_control +--port map( +-- CLK => CLK, +-- RESET => MC_RESET_LINK_IN, +-- +---- signals to/from main controller +-- MC_TSMAC_READY_OUT => tsm_ready, +-- MC_RECONF_IN => tsm_reconf, +-- MC_GBE_EN_IN => '1', +-- MC_RX_DISCARD_FCS => '0', +-- MC_PROMISC_IN => '1', +-- MC_MAC_ADDR_IN => g_MY_MAC, --x"001122334455", +-- +---- signal to/from Host interface of TriSpeed MAC +-- TSM_HADDR_OUT => tsm_haddr, +-- TSM_HDATA_OUT => tsm_hdata, +-- TSM_HCS_N_OUT => tsm_hcs_n, +-- TSM_HWRITE_N_OUT => tsm_hwrite_n, +-- TSM_HREAD_N_OUT => tsm_hread_n, +-- TSM_HREADY_N_IN => TSM_HREADY_N_IN, +-- TSM_HDATA_EN_N_IN => TSM_HDATA_EN_N_IN, +-- +-- DEBUG_OUT => open +--); + +--DEBUG_OUT <= mac_control_debug; +process(CLK) +begin + if rising_edge(CLK) then + if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then + tsm_reconf <= '1'; + else + tsm_reconf <= '0'; + end if; + end if; +end process; +MAC_RECONF_OUT <= tsm_reconf; +--tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '0') else '0'; + +TSM_HADDR_OUT <= tsm_haddr; +TSM_HCS_N_OUT <= tsm_hcs_n; +TSM_HDATA_OUT <= tsm_hdata; +TSM_HREAD_N_OUT <= tsm_hread_n; +TSM_HWRITE_N_OUT <= tsm_hwrite_n; + +-- END OF TRI SPEED MAC CONTROLLER +--*************** + + +-- ***** +-- STATISTICS +-- ***** + +-- +--CTRS_GEN : for n in 0 to 15 generate +-- +-- CTR_PROC : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- arr(n) <= (others => '0'); +-- elsif (rx_stat_en_q = '1' and rx_stat_vec_q(16 + n) = '1') then +-- arr(n) <= arr(n) + x"1"; +-- end if; +-- end if; +-- end process CTR_PROC; +-- +--end generate CTRS_GEN; +-- +--STAT_VEC_SYNC : signal_sync +--generic map ( +-- WIDTH => 32, +-- DEPTH => 2 +--) +--port map ( +-- RESET => RESET, +-- CLK0 => CLK, +-- CLK1 => CLK, +-- D_IN => TSM_RX_STAT_VEC_IN, +-- D_OUT => rx_stat_vec_q +--); +-- +-- +--STAT_VEC_EN_SYNC : pulse_sync +--port map( +-- CLK_A_IN => CLK_125, +-- RESET_A_IN => RESET, +-- PULSE_A_IN => TSM_RX_STAT_EN_IN, +-- CLK_B_IN => CLK, +-- RESET_B_IN => RESET, +-- PULSE_B_OUT => rx_stat_en_q +--); +-- +-- +--STATS_MACHINE_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- stats_current_state <= IDLE; +-- else +-- stats_current_state <= stats_next_state; +-- end if; +-- end if; +--end process STATS_MACHINE_PROC; +-- +--STATS_MACHINE : process(stats_current_state, rx_stat_en_q, stats_ctr) +--begin +-- +-- case (stats_current_state) is +-- +-- when IDLE => +-- if (rx_stat_en_q = '1') then +-- stats_next_state <= LOAD_VECTOR; +-- else +-- stats_next_state <= IDLE; +-- end if; +-- +-- when LOAD_VECTOR => +-- --if (stat_ack = '1') then +-- if (stats_ctr = 15) then +-- stats_next_state <= CLEANUP; +-- else +-- stats_next_state <= LOAD_VECTOR; +-- end if; +-- +-- when CLEANUP => +-- stats_next_state <= IDLE; +-- +-- end case; +-- +--end process STATS_MACHINE; +-- +--STATS_CTR_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') or (stats_current_state = IDLE) then +-- stats_ctr <= 0; +-- elsif (stats_current_state = LOAD_VECTOR and stat_ack ='1') then +-- stats_ctr <= stats_ctr + 1; +-- end if; +-- end if; +--end process STATS_CTR_PROC; +-- +----stat_data <= arr(stats_ctr); +-- +--stat_addr <= x"0c" + std_logic_vector(to_unsigned(stats_ctr, 8)); +-- +--stat_rdy <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; +-- +--stat_data(7 downto 0) <= arr(stats_ctr)(31 downto 24); +--stat_data(15 downto 8) <= arr(stats_ctr)(23 downto 16); +--stat_data(23 downto 16) <= arr(stats_ctr)(15 downto 8); +--stat_data(31 downto 24) <= arr(stats_ctr)(7 downto 0); + + +-- **** debug +--FRAME_WAITING_CTR_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- frame_waiting_ctr <= (others => '0'); +-- elsif (RC_FRAME_WAITING_IN = '1') then +-- frame_waiting_ctr <= frame_waiting_ctr + x"1"; +-- end if; +-- end if; +--end process FRAME_WAITING_CTR_PROC; +-- +--SAVE_VALUES_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- ps_busy_q <= (others => '0'); +-- rc_frame_proto_q <= (others => '0'); +-- elsif (redirect_current_state = IDLE and RC_FRAME_WAITING_IN = '1') then +-- ps_busy_q <= ps_busy; +-- rc_frame_proto_q <= RC_FRAME_PROTO_IN; +-- end if; +-- end if; +--end process SAVE_VALUES_PROC; + + +-- **** + + + +end trb_net16_gbe_main_control; \ No newline at end of file diff --git a/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd b/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd new file mode 100644 index 0000000..d7dd176 --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd @@ -0,0 +1,87 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- maps the frame type and protocol code into internal value which sets the priority + +entity trb_net16_gbe_protocol_prioritizer is +port ( + CLK : in std_logic; + RESET : in std_logic; + + FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type + PROTOCOL_CODE_IN : in std_logic_vector(7 downto 0); -- ip protocol + UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0); + + CODE_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0) +); +end trb_net16_gbe_protocol_prioritizer; + + +architecture trb_net16_gbe_protocol_prioritizer of trb_net16_gbe_protocol_prioritizer is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_protocol_prioritizer : architecture is "GBE_MAIN_group"; + +begin + +PRIORITIZE : process(RESET, CLK) +begin + if RESET = '1' then + CODE_OUT <= (others => '0'); + elsif rising_edge(CLK) then + + CODE_OUT <= (others => '0'); + + --**** HERE ADD YOU PROTOCOL RECOGNITION AT WANTED PRIORITY LEVEL + -- priority level is the bit position in the CODE_OUT vector + -- less significant bit has the higher priority + case FRAME_TYPE_IN is + + -- IPv4 + when x"0800" => + if (PROTOCOL_CODE_IN = x"11") then -- UDP + -- No. 2 = DHCP + if (UDP_PROTOCOL_IN = x"0044") then -- DHCP Client + CODE_OUT(1) <= '1'; + -- No. 4 = SCTRL + elsif (UDP_PROTOCOL_IN = x"6590") then -- SCTRL module + CODE_OUT(2) <= '1'; + else + -- branch for pure IPv4 + CODE_OUT <= (others => '0'); + end if; + -- No. 3 = ICMP + elsif (PROTOCOL_CODE_IN = x"01") then -- ICMP + CODE_OUT(4) <= '1'; + else + CODE_OUT <= (others => '0'); + end if; + + -- No. 1 = ARP + when x"0806" => + CODE_OUT(0) <= '1'; + + -- last slot is reserved for Trash + when others => + CODE_OUT <= (others => '0'); + + end case; + + end if; + +end process PRIORITIZE; + +end trb_net16_gbe_protocol_prioritizer; + + diff --git a/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd b/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd new file mode 100644 index 0000000..3489079 --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd @@ -0,0 +1,764 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- multiplexes between different protocols and manages the responses +-- +-- + + +entity trb_net16_gbe_protocol_selector is + generic( + RX_PATH_ENABLE : integer range 0 to 1 := 1; + DO_SIMULATION : integer range 0 to 1 := 0; + + INCLUDE_READOUT : std_logic := '0'; + INCLUDE_SLOWCTRL : std_logic := '0'; + INCLUDE_DHCP : std_logic := '0'; + INCLUDE_ARP : std_logic := '0'; + INCLUDE_PING : std_logic := '0'; + + READOUT_BUFFER_SIZE : integer range 1 to 4; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 + ); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + RESET_FOR_DHCP : in std_logic; + +-- signals to/from main controller + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + PS_RESPONSE_READY_OUT : out std_logic; + + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + +-- singals to/from transmit controller with constructed response + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_RD_EN_IN : in std_logic; + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + MC_BUSY_IN : in std_logic; + + -- misc signals for response constructors + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_OUT : out std_logic_vector(31 downto 0); + DHCP_START_IN : in std_logic; + DHCP_DONE_OUT : out std_logic; + + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + + MAKE_RESET_OUT : out std_logic; + + -- signal for data readout + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + -- ip configurator + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + + -- input for statistics from outside + STAT_DATA_IN : in std_logic_vector(31 downto 0); + STAT_ADDR_IN : in std_logic_vector(7 downto 0); + STAT_DATA_RDY_IN : in std_logic; + STAT_DATA_ACK_OUT : out std_logic; + + MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); + + DATA_HIST_OUT : out hist_array; + SCTRL_HIST_OUT : out hist_array +); +end trb_net16_gbe_protocol_selector; + + +architecture trb_net16_gbe_protocol_selector of trb_net16_gbe_protocol_selector is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_protocol_selector : architecture is "GBE_MAIN_group"; + +attribute syn_encoding : string; + +signal rd_en : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal resp_ready : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal tc_wr : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal tc_data : std_logic_vector(c_MAX_PROTOCOLS * 9 - 1 downto 0); +signal tc_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); +signal tc_type : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); +signal busy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal selected : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal tc_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0); +signal tc_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); +signal tc_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); +signal tc_src_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0); +signal tc_src_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); +signal tc_src_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); +signal tc_ip_proto : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0); + +-- plus 1 is for the outside +signal stat_data : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); +signal stat_addr : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0); +signal stat_rdy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal stat_ack : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal tc_ip_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); +signal tc_udp_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); +signal tc_size_left : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); +signal tc_flags_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + +signal tc_data_not_valid : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + +type select_states is (IDLE, LOOP_OVER, SELECT_ONE, PROCESS_REQUEST, CLEANUP); +signal select_current_state, select_next_state : select_states; +attribute syn_encoding of select_current_state : signal is "onehot"; + +signal state : std_logic_vector(3 downto 0); +signal index : integer range 0 to c_MAX_PROTOCOLS - 1; + +signal mult : std_logic; + +signal tc_ident : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); +signal zeros : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_keep of state, mult : signal is true; +attribute syn_preserve of state, mult : signal is true; + +signal my_ip : std_logic_vector(31 downto 0); + + +begin + +zeros <= (others => '0'); + + + +arp_gen : if INCLUDE_ARP = '1' generate + -- protocol Nr. 1 ARP + ARP : trb_net16_gbe_response_constructor_ARP + generic map( STAT_ADDRESS_BASE => 6 + ) + port map ( + CLK => CLK, + RESET => RESET, + + -- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(0), + PS_RESPONSE_READY_OUT => resp_ready(0), + PS_BUSY_OUT => busy(0), + PS_SELECTED_IN => selected(0), + + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(1 * 9 - 1 downto 0 * 9), + TC_FRAME_SIZE_OUT => tc_size(1 * 16 - 1 downto 0 * 16), + TC_FRAME_TYPE_OUT => tc_type(1 * 16 - 1 downto 0 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(1 * 8 - 1 downto 0 * 8), + TC_IDENT_OUT => tc_ident(1 * 16 - 1 downto 0 * 16), + + TC_DEST_MAC_OUT => tc_mac(1 * 48 - 1 downto 0 * 48), + TC_DEST_IP_OUT => tc_ip(1 * 32 - 1 downto 0 * 32), + TC_DEST_UDP_OUT => tc_udp(1 * 16 - 1 downto 0 * 16), + TC_SRC_MAC_OUT => tc_src_mac(1 * 48 - 1 downto 0 * 48), + TC_SRC_IP_OUT => tc_src_ip(1 * 32 - 1 downto 0 * 32), + TC_SRC_UDP_OUT => tc_src_udp(1 * 16 - 1 downto 0 * 16), + + STAT_DATA_OUT => stat_data(1 * 32 - 1 downto 0 * 32), + STAT_ADDR_OUT => stat_addr(1 * 8 - 1 downto 0 * 8), + STAT_DATA_RDY_OUT => stat_rdy(0), + STAT_DATA_ACK_IN => stat_ack(0), + RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16), + SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16), + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(1 * 64 - 1 downto 0 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32) + -- END OF INTERFACE + ); +end generate arp_gen; + +no_arp_gen : if INCLUDE_ARP = '0' generate + resp_ready(0) <= '0'; + busy(0) <= '0'; +end generate no_arp_gen; + + +dhcp_gen : if INCLUDE_DHCP = '1' generate + -- protocol No. 2 DHCP + DHCP : trb_net16_gbe_response_constructor_DHCP + generic map( + STAT_ADDRESS_BASE => 0, + DO_SIMULATION => DO_SIMULATION + ) + port map ( + CLK => CLK, + RESET => RESET_FOR_DHCP, --RESET, + + -- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(1), + PS_RESPONSE_READY_OUT => resp_ready(1), + PS_BUSY_OUT => busy(1), + PS_SELECTED_IN => selected(1), + + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(2 * 9 - 1 downto 1 * 9), + TC_FRAME_SIZE_OUT => tc_size(2 * 16 - 1 downto 1 * 16), + TC_FRAME_TYPE_OUT => tc_type(2 * 16 - 1 downto 1 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(2 * 8 - 1 downto 1 * 8), + TC_IDENT_OUT => tc_ident(2 * 16 - 1 downto 1 * 16), + + TC_DEST_MAC_OUT => tc_mac(2 * 48 - 1 downto 1 * 48), + TC_DEST_IP_OUT => tc_ip(2 * 32 - 1 downto 1 * 32), + TC_DEST_UDP_OUT => tc_udp(2 * 16 - 1 downto 1 * 16), + TC_SRC_MAC_OUT => tc_src_mac(2 * 48 - 1 downto 1 * 48), + TC_SRC_IP_OUT => tc_src_ip(2 * 32 - 1 downto 1 * 32), + TC_SRC_UDP_OUT => tc_src_udp(2 * 16 - 1 downto 1 * 16), + + STAT_DATA_OUT => stat_data(2 * 32 - 1 downto 1 * 32), + STAT_ADDR_OUT => stat_addr(2 * 8 - 1 downto 1 * 8), + STAT_DATA_RDY_OUT => stat_rdy(1), + STAT_DATA_ACK_IN => stat_ack(1), + RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16), + SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16), + -- END OF INTERFACE + + MY_IP_OUT => my_ip, + DHCP_START_IN => DHCP_START_IN, + DHCP_DONE_OUT => DHCP_DONE_OUT, + + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32) + ); +end generate dhcp_gen; + +no_dhcp_gen : if INCLUDE_DHCP = '0' generate + resp_ready(1) <= '0'; + busy(1) <= '0'; +end generate no_dhcp_gen; + +ping_gen : if INCLUDE_PING = '1' generate + --protocol No. 3 Ping + Ping : trb_net16_gbe_response_constructor_Ping + generic map( STAT_ADDRESS_BASE => 3 + ) + port map ( + CLK => CLK, + RESET => RESET, + + ---- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4), + PS_RESPONSE_READY_OUT => resp_ready(4), + PS_BUSY_OUT => busy(4), + PS_SELECTED_IN => selected(4), + + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9), + TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16), + TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8), + TC_IDENT_OUT => tc_ident(5 * 16 - 1 downto 4 * 16), + + TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48), + TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32), + TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16), + TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48), + TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32), + TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16), + + STAT_DATA_OUT => open, + STAT_ADDR_OUT => open, + STAT_DATA_RDY_OUT => open, + STAT_DATA_ACK_IN => '0', + RECEIVED_FRAMES_OUT => open, + SENT_FRAMES_OUT => open, + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(5 * 64 - 1 downto 4 * 64) + -- END OF INTERFACE + ); +end generate ping_gen; + +no_ping_gen : if INCLUDE_PING = '0' generate + resp_ready(4) <= '0'; + busy(4) <= '0'; +end generate no_ping_gen; + +sctrl_gen : if INCLUDE_SLOWCTRL = '1' generate + SCTRL : trb_net16_gbe_response_constructor_SCTRL + generic map( STAT_ADDRESS_BASE => 8, + SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE + ) + port map ( + CLK => CLK, + RESET => RESET, + + -- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2), + PS_RESPONSE_READY_OUT => resp_ready(2), + PS_BUSY_OUT => busy(2), + PS_SELECTED_IN => selected(2), + + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9), + TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16), + TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8), + TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16), + + TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48), + TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32), + TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16), + TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48), + TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32), + TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16), + + STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32), + STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8), + STAT_DATA_RDY_OUT => stat_rdy(2), + STAT_DATA_ACK_IN => stat_ack(2), + + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(3 * 64 - 1 downto 2 * 64), + -- END OF INTERFACE + + GSC_CLK_IN => GSC_CLK_IN, + GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => GSC_INIT_READ_IN, + GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, + GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, + GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, + GSC_BUSY_IN => GSC_BUSY_IN, + CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, + CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN, + MAKE_RESET_OUT => MAKE_RESET_OUT, + + MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(3 * 32 - 1 downto 2 * 32), + MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(3 * 32 - 1 downto 2 * 32), + MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(3 * 32 - 1 downto 2 * 32), + MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(3 * 32 - 1 downto 2 * 32), + + DATA_HIST_OUT => SCTRL_HIST_OUT + ); +end generate sctrl_gen; + +no_sctrl_gen : if INCLUDE_SLOWCTRL = '0' generate + resp_ready(2) <= '0'; + busy(2) <= '0'; +end generate no_sctrl_gen; + +trbnet_gen : if INCLUDE_READOUT = '1' generate + TrbNetData : trb_net16_gbe_response_constructor_TrbNetData + generic map( + RX_PATH_ENABLE => RX_PATH_ENABLE, + DO_SIMULATION => DO_SIMULATION, + + READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE + ) + port map ( + CLK => CLK, + RESET => RESET, + + -- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3), + PS_RESPONSE_READY_OUT => resp_ready(3), + PS_BUSY_OUT => busy(3), + PS_SELECTED_IN => selected(3), + + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9), + TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16), + TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8), + TC_IDENT_OUT => tc_ident(4 * 16 - 1 downto 3 * 16), + + TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48), + TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32), + TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16), + TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48), + TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32), + TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16), + + STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32), + STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8), + STAT_DATA_RDY_OUT => stat_rdy(3), + STAT_DATA_ACK_IN => stat_ack(3), + + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64), + -- END OF INTERFACE + + -- CTS interface + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + -- Data payload interface + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + -- ip configurator + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + + CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, + CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, + CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, + CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, + CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, + CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, + CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, + CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, + CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, + CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, + CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, + CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, + CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, + + MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_DROP_IN_OUT => open, + + DATA_HIST_OUT => DATA_HIST_OUT + ); +end generate trbnet_gen; + +no_readout_gen : if INCLUDE_READOUT = '0' generate + resp_ready(3) <= '0'; + busy(3) <= '0'; +end generate no_readout_gen; + +--stat_gen : if g_SIMULATE = 0 generate +--Stat : trb_net16_gbe_response_constructor_Stat +--generic map( STAT_ADDRESS_BASE => 10 +--) +--port map ( +-- CLK => CLK, +-- RESET => RESET, +-- +---- INTERFACE +-- PS_DATA_IN => PS_DATA_IN, +-- PS_WR_EN_IN => PS_WR_EN_IN, +-- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4), +-- PS_RESPONSE_READY_OUT => resp_ready(4), +-- PS_BUSY_OUT => busy(4), +-- PS_SELECTED_IN => selected(4), +-- +-- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, +-- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, +-- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, +-- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, +-- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, +-- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, +-- +-- TC_WR_EN_OUT => TC_WR_EN_OUT, +-- TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9), +-- TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16), +-- TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16), +-- TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8), +-- +-- TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48), +-- TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32), +-- TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16), +-- TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48), +-- TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32), +-- TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16), +-- +-- TC_IP_SIZE_OUT => tc_ip_size(5 * 16 - 1 downto 4 * 16), +-- TC_UDP_SIZE_OUT => tc_udp_size(5 * 16 - 1 downto 4 * 16), +-- TC_FLAGS_OFFSET_OUT => tc_flags_size(5 * 16 - 1 downto 4 * 16), +-- +-- TC_BUSY_IN => TC_BUSY_IN, +-- +-- STAT_DATA_OUT => stat_data(5 * 32 - 1 downto 4 * 32), +-- STAT_ADDR_OUT => stat_addr(5 * 8 - 1 downto 4 * 8), +-- STAT_DATA_RDY_OUT => stat_rdy(4), +-- STAT_DATA_ACK_IN => stat_ack(4), +-- +-- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(5 * 16 - 1 downto 4 * 16), +-- SENT_FRAMES_OUT => SENT_FRAMES_OUT(5 * 16 - 1 downto 4 * 16), +-- DEBUG_OUT => PROTOS_DEBUG_OUT(5 * 32 - 1 downto 4 * 32), +-- +-- STAT_DATA_IN => stat_data, +-- STAT_ADDR_IN => stat_addr, +-- STAT_DATA_RDY_IN => stat_rdy, +-- STAT_DATA_ACK_OUT => stat_ack +--); +--end generate; + +--*************** +-- DO NOT TOUCH, response selection logic + +--stat_data((c_MAX_PROTOCOLS + 1) * 32 - 1 downto c_MAX_PROTOCOLS * 32) <= STAT_DATA_IN; +--stat_addr((c_MAX_PROTOCOLS + 1) * 8 - 1 downto c_MAX_PROTOCOLS * 8) <= STAT_ADDR_IN; +--stat_rdy(c_MAX_PROTOCOLS) <= STAT_DATA_RDY_IN; +--STAT_DATA_ACK_OUT <= stat_ack(c_MAX_PROTOCOLS); + +--mult <= or_all(resp_ready(2 downto 0)); --or_all(resp_ready(2 downto 0)) and or_all(resp_ready(4 downto 3)); + +PS_BUSY_OUT <= busy; + +SELECT_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + select_current_state <= IDLE; + elsif rising_edge(CLK) then +-- if (RESET = '1') then +-- select_current_state <= IDLE; +-- else + select_current_state <= select_next_state; +-- end if; + end if; +end process SELECT_MACHINE_PROC; + +SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index, zeros, busy) +begin + + case (select_current_state) is + + when IDLE => + if (MC_BUSY_IN = '0') then + select_next_state <= LOOP_OVER; + else + select_next_state <= IDLE; + end if; + + when LOOP_OVER => + if (resp_ready /= zeros) then + if (resp_ready(index) = '1') then + select_next_state <= SELECT_ONE; + elsif (index = c_MAX_PROTOCOLS) then + select_next_state <= CLEANUP; + else + select_next_state <= LOOP_OVER; + end if; + else + select_next_state <= CLEANUP; + end if; + + when SELECT_ONE => + if (MC_BUSY_IN = '1') then + select_next_state <= PROCESS_REQUEST; + else + select_next_state <= SELECT_ONE; + end if; + + when PROCESS_REQUEST => + if (busy(index) = '0') then --if (MC_BUSY_IN = '0') then + select_next_state <= CLEANUP; + else + select_next_state <= PROCESS_REQUEST; + end if; + + when CLEANUP => + select_next_state <= IDLE; + + end case; + +end process SELECT_MACHINE; + +INDEX_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (select_current_state = IDLE) then + index <= 0; + elsif (select_current_state = LOOP_OVER and resp_ready(index) = '0') then + index <= index + 1; + else + index <= index; + end if; + end if; +end process INDEX_PROC; + +SELECTOR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (select_current_state = SELECT_ONE or select_current_state = PROCESS_REQUEST) then + TC_DATA_OUT <= tc_data((index + 1) * 9 - 1 downto index * 9); + TC_FRAME_SIZE_OUT <= tc_size((index + 1) * 16 - 1 downto index * 16); + TC_FRAME_TYPE_OUT <= tc_type((index + 1) * 16 - 1 downto index * 16); + TC_DEST_MAC_OUT <= tc_mac((index + 1) * 48 - 1 downto index * 48); + TC_DEST_IP_OUT <= tc_ip((index + 1) * 32 - 1 downto index * 32); + TC_DEST_UDP_OUT <= tc_udp((index + 1) * 16 - 1 downto index * 16); + TC_SRC_MAC_OUT <= tc_src_mac((index + 1) * 48 - 1 downto index * 48); + TC_SRC_IP_OUT <= tc_src_ip((index + 1) * 32 - 1 downto index * 32); + TC_SRC_UDP_OUT <= tc_src_udp((index + 1) * 16 - 1 downto index * 16); + TC_IP_PROTOCOL_OUT <= tc_ip_proto((index + 1) * 8 - 1 downto index * 8); + TC_IDENT_OUT <= tc_ident((index + 1) * 16 - 1 downto index * 16); + if (select_current_state = SELECT_ONE) then + PS_RESPONSE_READY_OUT <= '1'; + selected(index) <= '0'; + else + PS_RESPONSE_READY_OUT <= '0'; + selected(index) <= '1'; + end if; + else + TC_DATA_OUT <= (others => '0'); + TC_FRAME_SIZE_OUT <= (others => '0'); + TC_FRAME_TYPE_OUT <= (others => '0'); + TC_DEST_MAC_OUT <= (others => '0'); + TC_DEST_IP_OUT <= (others => '0'); + TC_DEST_UDP_OUT <= (others => '0'); + TC_SRC_MAC_OUT <= (others => '0'); + TC_SRC_IP_OUT <= (others => '0'); + TC_SRC_UDP_OUT <= (others => '0'); + TC_IP_PROTOCOL_OUT <= (others => '0'); + TC_IDENT_OUT <= (others => '0'); + PS_RESPONSE_READY_OUT <= '0'; + selected <= (others => '0'); + end if; + end if; +end process SELECTOR_PROC; + +end trb_net16_gbe_protocol_selector; + + diff --git a/gbe_trb/base/trb_net16_gbe_receive_control.vhd b/gbe_trb/base/trb_net16_gbe_receive_control.vhd new file mode 100644 index 0000000..4a7bc6f --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_receive_control.vhd @@ -0,0 +1,256 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- controller has to control the rest of the logic (TX part, TS_MAC, HUB) accordingly to +-- the message received from receiver, frame checking is already done +-- + + +entity trb_net16_gbe_receive_control is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- signals to/from frame_receiver + RC_DATA_IN : in std_logic_vector(8 downto 0); + FR_RD_EN_OUT : out std_logic; + FR_FRAME_VALID_IN : in std_logic; + FR_GET_FRAME_OUT : out std_logic; + FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0); + FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); + + FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + +-- signals to/from main controller + RC_RD_EN_IN : in std_logic; + RC_Q_OUT : out std_logic_vector(8 downto 0); + RC_FRAME_WAITING_OUT : out std_logic; + RC_LOADING_DONE_IN : in std_logic; + RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + +-- statistics + FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0); + BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0); + + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end trb_net16_gbe_receive_control; + + +architecture trb_net16_gbe_receive_control of trb_net16_gbe_receive_control is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_receive_control : architecture is "GBE_MAIN_group"; +attribute syn_encoding : string; + +type load_states is (IDLE, PREPARE, WAIT_ONE, READY); +signal load_current_state, load_next_state : load_states; +attribute syn_encoding of load_current_state : signal is "onehot"; + +signal frames_received_ctr : std_logic_vector(31 downto 0); +signal frames_readout_ctr : std_logic_vector(31 downto 0); +signal bytes_rec_ctr : std_logic_vector(31 downto 0); + +signal state : std_logic_vector(3 downto 0); +signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +signal reset_prioritizer : std_logic; +signal frame_waiting : std_logic; + +-- debug only +signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + +begin + +FR_RD_EN_OUT <= RC_RD_EN_IN; +RC_Q_OUT <= RC_DATA_IN; +RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN; +RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN; +RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN; +RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN; +RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN; +RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN; +RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN; + +protocol_prioritizer : trb_net16_gbe_protocol_prioritizer +port map( + CLK => CLK, + RESET => reset_prioritizer, + + FRAME_TYPE_IN => FR_FRAME_PROTO_IN, + PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN, + UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN, + + CODE_OUT => proto_code +); + +reset_prioritizer <= '1' when load_current_state = IDLE else '0'; + +--RC_FRAME_PROTO_OUT <= proto_code when (and_all(proto_code) = '0') else (others => '0'); +RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash + +--DEBUG_OUT(3 downto 0) <= state; +--DEBUG_OUT(11 downto 4) <= frames_received_ctr(7 downto 0); +--DEBUG_OUT(19 downto 12) <= frames_readout_ctr(7 downto 0); +--DEBUG_OUT(31 downto 20) <= bytes_rec_ctr(11 downto 0); + +LOAD_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + load_current_state <= IDLE; + elsif rising_edge(CLK) then + load_current_state <= load_next_state; + end if; +end process LOAD_MACHINE_PROC; + +LOAD_MACHINE : process(load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN) +begin + case load_current_state is + + when IDLE => + state <= x"1"; + if (frames_readout_ctr /= frames_received_ctr) then -- frame is still waiting in frame_receiver + load_next_state <= PREPARE; + else + load_next_state <= IDLE; + end if; + + when PREPARE => -- prepare frame size + state <= x"2"; + load_next_state <= WAIT_ONE; --READY; + + when WAIT_ONE => + load_next_state <= READY; + + when READY => -- wait for reading out the whole frame + state <= x"3"; + if (RC_LOADING_DONE_IN = '1') then + load_next_state <= IDLE; + else + load_next_state <= READY; + end if; + + end case; +end process LOAD_MACHINE; + +process(CLK) +begin + if rising_edge(CLK) then + if (load_current_state = PREPARE) then + FR_GET_FRAME_OUT <= '1'; + else + FR_GET_FRAME_OUT <= '0'; + end if; + + if (load_current_state = READY and RC_LOADING_DONE_IN = '0') then + RC_FRAME_WAITING_OUT <= '1'; + else + RC_FRAME_WAITING_OUT <= '0'; + end if; + + --RC_FRAME_WAITING_OUT <= frame_waiting; + end if; +end process; + +--FR_GET_FRAME_OUT <= '1' when (load_current_state = PREPARE) +-- else '0'; +-- +--RC_FRAME_WAITING_OUT <= '1' when (load_current_state = READY) +-- else '0'; + +--SYNC_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- FRAMES_RECEIVED_OUT <= frames_received_ctr; +-- --BYTES_RECEIVED_OUT <= bytes_rec_ctr; +-- BYTES_RECEIVED_OUT(15 downto 0) <= bytes_rec_ctr(15 downto 0); +-- BYTES_RECEIVED_OUT(16 + c_MAX_PROTOCOLS - 1 downto 16) <= saved_proto; +-- BYTES_RECEIVED_OUT(31 downto 16 + c_MAX_PROTOCOLS) <= (others => '0'); +-- end if; +--end process SYNC_PROC; + +FRAMES_REC_CTR_PROC : process(RESET, CLK) +begin + if (RESET = '1') then + frames_received_ctr <= (others => '0'); + elsif rising_edge(CLK) then + if (FR_FRAME_VALID_IN = '1') then + frames_received_ctr <= frames_received_ctr + x"1"; + else + frames_received_ctr <= frames_received_ctr; + end if; + end if; +end process FRAMES_REC_CTR_PROC; + +FRAMES_READOUT_CTR_PROC : process(RESET, CLK) +begin + if (RESET = '1') then + frames_readout_ctr <= (others => '0'); + elsif rising_edge(CLK) then + if (RC_LOADING_DONE_IN = '1') then + frames_readout_ctr <= frames_readout_ctr + x"1"; + else + frames_readout_ctr <= frames_readout_ctr; + end if; + end if; +end process FRAMES_READOUT_CTR_PROC; + +-- debug only +BYTES_REC_CTR_PROC : process(RESET, CLK) +begin + if (RESET = '1') then + bytes_rec_ctr <= (others => '0'); + elsif rising_edge(CLK) then + if (FR_FRAME_VALID_IN = '1') then + bytes_rec_ctr <= bytes_rec_ctr + FR_FRAME_SIZE_IN; + else + bytes_rec_ctr <= bytes_rec_ctr; + end if; + end if; +end process BYTES_REC_CTR_PROC; + +SAVED_PROTO_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (load_current_state = READY) then + if (and_all(proto_code) = '0') then + saved_proto <= proto_code; + else + saved_proto <= (others => '0'); + end if; + else + saved_proto <= saved_proto; + end if; + end if; +end process SAVED_PROTO_PROC; +-- end of debug + + +end trb_net16_gbe_receive_control; + + diff --git a/gbe_trb/base/trb_net16_gbe_setup.vhd b/gbe_trb/base/trb_net16_gbe_setup.vhd new file mode 100644 index 0000000..5fd4d0b --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_setup.vhd @@ -0,0 +1,439 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +--use work.version.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +entity gbe_setup is +port( + CLK : in std_logic; + RESET : in std_logic; + + -- interface to regio bus + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + BUS_WRITE_EN_IN : in std_logic; + BUS_READ_EN_IN : in std_logic; + BUS_ACK_OUT : out std_logic; + + -- output to gbe_buf + GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0); + GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0); + GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0); + GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0); + GBE_USE_GBE_OUT : out std_logic; + GBE_USE_TRBNET_OUT : out std_logic; + GBE_USE_MULTIEVENTS_OUT : out std_logic; + GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); + GBE_READOUT_CTR_VALID_OUT : out std_logic; + GBE_ALLOW_RX_OUT : out std_logic; + GBE_ADDITIONAL_HDR_OUT : out std_logic; + GBE_INSERT_TTYPE_OUT : out std_logic; + GBE_SOFT_RESET_OUT : out std_logic; + GBE_MAX_REPLY_OUT : out std_logic_vector(31 downto 0); + + GBE_MAX_SUB_OUT : out std_logic_vector(15 downto 0); + GBE_MAX_QUEUE_OUT : out std_logic_vector(15 downto 0); + GBE_MAX_SUBS_IN_QUEUE_OUT : out std_logic_vector(15 downto 0); + GBE_MAX_SINGLE_SUB_OUT : out std_logic_vector(15 downto 0); + + MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0); + MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0); + MONITOR_TX_BYTES_IN : in std_logic_vector(31 downto 0); + MONITOR_TX_FRAMES_IN : in std_logic_vector(31 downto 0); + MONITOR_TX_PACKETS_IN : in std_logic_vector(31 downto 0); + MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0); + + MONITOR_SELECT_REC_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_REC_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_IN_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_OUT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_GEN_DBG_IN : in std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); + + DUMMY_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0); + DUMMY_TRIGGERED_MODE_OUT : out std_logic; + + DATA_HIST_IN : in hist_array; + SCTRL_HIST_IN : in hist_array +); +end entity; + +architecture gbe_setup of gbe_setup is + +signal reset_values : std_logic; +signal subevent_id : std_logic_vector(31 downto 0); +signal subevent_dec : std_logic_vector(31 downto 0); +signal queue_dec : std_logic_vector(31 downto 0); +signal max_frame : std_logic_vector(15 downto 0); +signal use_gbe : std_logic; +signal use_trbnet : std_logic; +signal use_multievents : std_logic; +signal readout_ctr : std_logic_vector(23 downto 0); +signal readout_ctr_valid : std_logic; +signal ack : std_logic; +signal ack_q : std_logic; +signal data_out : std_logic_vector(31 downto 0); +signal allow_rx : std_logic; +signal additional_hdr : std_logic; +signal insert_ttype : std_logic; +signal max_reply : std_logic_vector(31 downto 0); + signal max_sub, max_queue, max_subs_in_queue, max_single_sub : std_logic_vector(15 downto 0); + signal dummy_event : std_logic_vector(15 downto 0); + signal dummy_mode : std_logic; + +begin + +OUT_PROC : process(CLK) +begin + if rising_edge(CLK) then + GBE_SUBEVENT_ID_OUT <= subevent_id; + GBE_SUBEVENT_DEC_OUT <= subevent_dec; + GBE_QUEUE_DEC_OUT <= queue_dec; + GBE_MAX_FRAME_OUT <= max_frame; + GBE_USE_GBE_OUT <= use_gbe; + GBE_USE_TRBNET_OUT <= use_trbnet; + GBE_USE_MULTIEVENTS_OUT <= use_multievents; + GBE_READOUT_CTR_OUT <= readout_ctr; + GBE_READOUT_CTR_VALID_OUT <= readout_ctr_valid; + BUS_ACK_OUT <= ack_q; + ack_q <= ack; + BUS_DATA_OUT <= data_out; + GBE_ALLOW_RX_OUT <= '1'; --allow_rx; + GBE_INSERT_TTYPE_OUT <= insert_ttype; + GBE_ADDITIONAL_HDR_OUT <= additional_hdr; + GBE_MAX_SUB_OUT <= max_sub; + GBE_MAX_QUEUE_OUT <= max_queue; + GBE_MAX_SUBS_IN_QUEUE_OUT <= max_subs_in_queue; + GBE_MAX_SINGLE_SUB_OUT <= max_single_sub; + GBE_MAX_REPLY_OUT <= max_reply; + DUMMY_EVENT_SIZE_OUT <= dummy_event; + DUMMY_TRIGGERED_MODE_OUT <= dummy_mode; + end if; +end process OUT_PROC; + +ACK_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + ack <= '0'; + elsif ((BUS_WRITE_EN_IN = '1') or (BUS_READ_EN_IN = '1')) then + ack <= '1'; + else + ack <= '0'; + end if; + end if; +end process ACK_PROC; + +WRITE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if ( (RESET = '1') or (reset_values = '1') ) then + subevent_id <= x"0000_00cf"; + subevent_dec <= x"0002_0001"; + queue_dec <= x"0003_0062"; + max_frame <= x"0578"; + use_gbe <= '0'; + use_trbnet <= '0'; + use_multievents <= '0'; + reset_values <= '0'; + readout_ctr <= x"00_0000"; + readout_ctr_valid <= '0'; + allow_rx <= '1'; + insert_ttype <= '0'; + additional_hdr <= '1'; + GBE_SOFT_RESET_OUT <= '0'; + max_sub <= x"e998"; -- 59800 + max_queue <= x"ea60"; -- 60000 + max_subs_in_queue <= x"00c8"; -- 200 + max_single_sub <= x"7d00"; -- 32000 + max_reply <= x"0000_fa00"; + dummy_event <= x"0100"; + dummy_mode <= '0'; + + elsif (BUS_WRITE_EN_IN = '1') then + + GBE_SOFT_RESET_OUT <= '0'; + + case BUS_ADDR_IN is + + when x"00" => + subevent_id <= BUS_DATA_IN; + + when x"01" => + subevent_dec <= BUS_DATA_IN; + + when x"02" => + queue_dec <= BUS_DATA_IN; + + when x"04" => + max_frame <= BUS_DATA_IN(15 downto 0); + + when x"05" => + if (BUS_DATA_IN = x"0000_0000") then + use_gbe <= '0'; + else + use_gbe <= '1'; + end if; + + when x"06" => + if (BUS_DATA_IN = x"0000_0000") then + use_trbnet <= '0'; + else + use_trbnet <= '1'; + end if; + + when x"07" => + if (BUS_DATA_IN = x"0000_0000") then + use_multievents <= '0'; + else + use_multievents <= '1'; + end if; + + when x"08" => + readout_ctr <= BUS_DATA_IN(23 downto 0); + readout_ctr_valid <= '1'; + + when x"09" => + allow_rx <= BUS_DATA_IN(0); + + when x"0a" => + additional_hdr <= BUS_DATA_IN(0); + + when x"0b" => + insert_ttype <= BUS_DATA_IN(0); + + when x"0c" => + max_sub <= BUS_DATA_IN(15 downto 0); + + when x"10" => + max_queue <= BUS_DATA_IN(15 downto 0); + + when x"0e" => + max_subs_in_queue <= BUS_DATA_IN(15 downto 0); + + when x"0f" => + max_single_sub <= BUS_DATA_IN(15 downto 0); + + when x"11" => + max_reply <= BUS_DATA_IN; + + when x"12" => + dummy_event <= BUS_DATA_IN(15 downto 0); + + when x"13" => + dummy_mode <= BUS_DATA_IN(0); + + when x"ff" => + if (BUS_DATA_IN = x"ffff_ffff") then + reset_values <= '0'; + GBE_SOFT_RESET_OUT <= '1'; + else + reset_values <= '0'; + GBE_SOFT_RESET_OUT <= '0'; + end if; + + when others => + subevent_id <= subevent_id; + subevent_dec <= subevent_dec; + queue_dec <= queue_dec; + max_frame <= max_frame; + use_gbe <= use_gbe; + use_trbnet <= use_trbnet; + use_multievents <= use_multievents; + reset_values <= reset_values; + readout_ctr <= readout_ctr; + readout_ctr_valid <= readout_ctr_valid; + allow_rx <= allow_rx; + additional_hdr <= additional_hdr; + insert_ttype <= insert_ttype; + max_sub <= max_sub; + max_queue <= max_queue; + max_subs_in_queue <= max_subs_in_queue; + max_single_sub <= max_single_sub; + max_reply <= max_reply; + dummy_event <= dummy_event; + dummy_mode <= dummy_mode; + end case; + else + reset_values <= '0'; + readout_ctr_valid <= '0'; + GBE_SOFT_RESET_OUT <= '0'; + end if; + end if; +end process WRITE_PROC; + +READ_PROC : process(CLK) + variable address : integer range 0 to 255; +begin + if rising_edge(CLK) then + if (RESET = '1') then + data_out <= (others => '0'); + elsif (BUS_READ_EN_IN = '1') then + + address := to_integer(unsigned(BUS_ADDR_IN)); + + case address is + + when 0 => + data_out <= subevent_id; + + when 1 => + data_out <= subevent_dec; + + when 2 => + data_out <= queue_dec; + + when 4 => + data_out(15 downto 0) <= max_frame; + data_out(31 downto 16) <= (others => '0'); + + when 5 => + if (use_gbe = '0') then + data_out <= x"0000_0000"; + else + data_out <= x"0000_0001"; + end if; + + when 6 => + if (use_trbnet = '0') then + data_out <= x"0000_0000"; + else + data_out <= x"0000_0001"; + end if; + + when 7 => + if (use_multievents = '0') then + data_out <= x"0000_0000"; + else + data_out <= x"0000_0001"; + end if; + + when 9 => + data_out(0) <= allow_rx; + data_out(31 downto 1) <= (others => '0'); + + when 10 => + data_out(0) <= additional_hdr; + data_out(31 downto 1) <= (others => '0'); + + when 11 => + data_out(0) <= insert_ttype; + data_out(31 downto 1) <= (others => '0'); + + when 12 => + data_out(15 downto 0) <= max_sub; + data_out(31 downto 16) <= (others => '0'); + + when 14 => + data_out(15 downto 0) <= max_subs_in_queue; + data_out(31 downto 16) <= (others => '0'); + + when 15 => + data_out(15 downto 0) <= max_single_sub; + data_out(31 downto 16) <= (others => '0'); + + when 16 => + data_out(15 downto 0) <= max_queue; + data_out(31 downto 16) <= (others => '0'); + + when 17 => + data_out <= max_reply; + + when 18 => + data_out(15 downto 0) <= dummy_event; + data_out(31 downto 16) <= (others => '0'); + + when 19 => + data_out(0) <= dummy_mode; + data_out(31 downto 1) <= (others => '0'); + + + -- Histogram of sctrl data sizes + when 96 to 127 => + data_out <= SCTRL_HIST_IN(address - 96); + + -- Histogram of TrbNetData data sizes + when 128 to 159 => + data_out <= DATA_HIST_IN(address - 128); + + -- General statistics + when 224 => + data_out <= MONITOR_RX_BYTES_IN; + + when 225 => + data_out <= MONITOR_RX_FRAMES_IN; + + when 226 => + data_out <= MONITOR_TX_BYTES_IN; + + when 227 => + data_out <= MONITOR_TX_FRAMES_IN; + + when 228 => + data_out <= MONITOR_TX_PACKETS_IN; + + when 229 => + data_out <= MONITOR_DROPPED_IN; + + -- Sctrl + when 160 => + data_out <= MONITOR_SELECT_REC_IN(3 * 32 - 1 downto 2 * 32); + when 161 => + data_out <= MONITOR_SELECT_REC_BYTES_IN(3 * 32 - 1 downto 2 * 32); + when 162 => + data_out <= MONITOR_SELECT_SENT_IN(3 * 32 - 1 downto 2 * 32); + when 163 => + data_out <= MONITOR_SELECT_SENT_BYTES_IN(3 * 32 - 1 downto 2 * 32); + when 164 => + data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 - 32 downto 2 * 64); + when 165 => + data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 downto 2 * 64 + 32); + when 166 => + data_out <= MONITOR_SELECT_DROP_IN_IN(3 * 32 - 1 downto 2 * 32); + when 167 => + data_out <= MONITOR_SELECT_DROP_OUT_IN(3 * 32 - 1 downto 2 * 32); + + -- TrbnetData + when 176 => + data_out <= MONITOR_SELECT_REC_IN(4 * 32 - 1 downto 3 * 32); + when 177 => + data_out <= MONITOR_SELECT_REC_BYTES_IN(4 * 32 - 1 downto 3 * 32); + when 178 => + data_out <= MONITOR_SELECT_SENT_IN(4 * 32 - 1 downto 3 * 32); + when 179 => + data_out <= MONITOR_SELECT_SENT_BYTES_IN(4 * 32 - 1 downto 3 * 32); + when 180 => + data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 - 32 downto 3 * 64); + when 181 => + data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 downto 3 * 64 + 32); + when 182 => + data_out <= MONITOR_SELECT_DROP_IN_IN(4 * 32 - 1 downto 3 * 32); + when 183 => + data_out <= MONITOR_SELECT_DROP_OUT_IN(4 * 32 - 1 downto 3 * 32); + + -- for older network monitors + when 243 => + data_out <= MONITOR_TX_BYTES_IN; + + when 244 => + data_out <= MONITOR_TX_FRAMES_IN; + + when others => + data_out <= (others => '0'); + end case; + end if; + end if; +end process READ_PROC; + +end architecture; \ No newline at end of file diff --git a/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd b/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd new file mode 100644 index 0000000..f48d76a --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd @@ -0,0 +1,319 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_protocols.all; + +--******** +-- performs response constructors readout and splitting into frames + +entity trb_net16_gbe_transmit_control2 is +port ( + CLK : in std_logic; + RESET : in std_logic; + +-- signal to/from main controller + TC_DATAREADY_IN : in std_logic; + TC_RD_EN_OUT : out std_logic; + TC_DATA_IN : in std_logic_vector(7 downto 0); + TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); + TC_DEST_MAC_IN : in std_logic_vector(47 downto 0); + TC_DEST_IP_IN : in std_logic_vector(31 downto 0); + TC_DEST_UDP_IN : in std_logic_vector(15 downto 0); + TC_SRC_MAC_IN : in std_logic_vector(47 downto 0); + TC_SRC_IP_IN : in std_logic_vector(31 downto 0); + TC_SRC_UDP_IN : in std_logic_vector(15 downto 0); + TC_TRANSMISSION_DONE_OUT : out std_logic; + TC_IDENT_IN : in std_logic_vector(15 downto 0); + TC_MAX_FRAME_IN : in std_logic_vector(15 downto 0); + +-- signal to/from frame constructor + FC_DATA_OUT : out std_logic_vector(7 downto 0); + FC_WR_EN_OUT : out std_logic; + FC_READY_IN : in std_logic; + FC_H_READY_IN : in std_logic; + FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter + FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + FC_SOD_OUT : out std_logic; + FC_EOD_OUT : out std_logic; + FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + + DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + + MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_transmit_control2; + + +architecture trb_net16_gbe_transmit_control2 of trb_net16_gbe_transmit_control2 is + +attribute syn_encoding : string; + +type transmit_states is (IDLE, PREPARE_HEADERS, WAIT_FOR_H, TRANSMIT, SEND_ONE, SEND_TWO, CLOSE, WAIT_FOR_TRANS, DIVIDE, CLEANUP); +signal transmit_current_state, transmit_next_state : transmit_states; +attribute syn_encoding of transmit_current_state : signal is "onehot"; + +signal tc_rd, tc_rd_q, tc_rd_qq : std_logic; +signal local_end : std_logic_vector(15 downto 0); + +signal actual_frame_bytes, full_packet_size, ip_size, packet_loaded_bytes : std_logic_vector(15 downto 0); +signal go_to_divide, more_fragments : std_logic; +signal first_frame : std_logic; +signal mon_packets_sent_ctr : std_logic_vector(31 downto 0); + +begin + +TRANSMIT_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + transmit_current_state <= IDLE; + elsif rising_edge(CLK) then + transmit_current_state <= transmit_next_state; + end if; +end process TRANSMIT_MACHINE_PROC; + +TRANSMIT_MACHINE : process(transmit_current_state, FC_H_READY_IN, TC_DATAREADY_IN, FC_READY_IN, local_end, TC_MAX_FRAME_IN, actual_frame_bytes, go_to_divide) +begin + case transmit_current_state is + + when IDLE => + if (TC_DATAREADY_IN = '1') then + transmit_next_state <= PREPARE_HEADERS; + else + transmit_next_state <= IDLE; + end if; + + when PREPARE_HEADERS => + transmit_next_state<= WAIT_FOR_H; + + when WAIT_FOR_H => + if (FC_H_READY_IN = '1') then + transmit_next_state <= TRANSMIT; + else + transmit_next_state <= WAIT_FOR_H; + end if; + + when TRANSMIT => + if (local_end = x"0000") then + transmit_next_state <= SEND_ONE; + else + if (actual_frame_bytes = TC_MAX_FRAME_IN - x"1") then + transmit_next_state <= SEND_ONE; + else + transmit_next_state <= TRANSMIT; + end if; + end if; + + when SEND_ONE => + transmit_next_state <= SEND_TWO; + + when SEND_TWO => + transmit_next_state <= CLOSE; + + when CLOSE => + transmit_next_state <= WAIT_FOR_TRANS; + + when WAIT_FOR_TRANS => + if (FC_READY_IN = '1') then + if (go_to_divide = '1') then + transmit_next_state <= DIVIDE; + else + transmit_next_state <= CLEANUP; + end if; + else + transmit_next_state <= WAIT_FOR_TRANS; + end if; + + when DIVIDE => + transmit_next_state <= PREPARE_HEADERS; + + when CLEANUP => + transmit_next_state <= IDLE; + + end case; +end process TRANSMIT_MACHINE; + +tc_rd <= '1' when transmit_current_state = TRANSMIT else '0'; + +TC_RD_EN_OUT <= tc_rd; + +SYNC_PROC : process(CLK) +begin + if rising_edge(CLK) then + +-- if (transmit_current_state = TRANSMIT) then +-- tc_rd <= '1'; +-- else +-- tc_rd <= '0'; +-- end if; + + tc_rd_q <= tc_rd; + tc_rd_qq <= tc_rd_q; + FC_WR_EN_OUT <= tc_rd_qq; + end if; +end process SYNC_PROC; + +ACTUAL_FRAME_BYTES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (transmit_current_state = IDLE or transmit_current_state = DIVIDE) then + actual_frame_bytes <= (others => '0'); + elsif (transmit_current_state = TRANSMIT) then + actual_frame_bytes <= actual_frame_bytes + x"1"; + else + actual_frame_bytes <= actual_frame_bytes; + end if; + end if; +end process ACTUAL_FRAME_BYTES_PROC; + +GO_TO_DIVIDE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (transmit_current_state = IDLE or transmit_current_state = DIVIDE) then + go_to_divide <= '0'; + elsif (transmit_current_state = TRANSMIT and actual_frame_bytes = TC_MAX_FRAME_IN - x"1") then + go_to_divide <= '1'; +-- elsif (transmit_current_state = SEND_ONE and full_packet_size < packet_loaded_bytes - x"1") then +-- go_to_divide <= '1'; +-- elsif (transmit_current_state = SEND_TWO and full_packet_size < packet_loaded_bytes - x"1") then +-- go_to_divide <= '1'; + elsif (transmit_current_state = SEND_ONE and full_packet_size = packet_loaded_bytes) then + go_to_divide <= '0'; + else + go_to_divide <= go_to_divide; + end if; + end if; +end process GO_TO_DIVIDE_PROC; + +LOCAL_END_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (transmit_current_state = IDLE and TC_DATAREADY_IN = '1') then + local_end <= TC_FRAME_SIZE_IN - x"1"; + full_packet_size <= TC_FRAME_SIZE_IN; + elsif (transmit_current_state = TRANSMIT) then + local_end <= local_end - x"1"; + full_packet_size <= full_packet_size; + else + local_end <= local_end; + full_packet_size <= full_packet_size; + end if; + end if; +end process LOCAL_END_PROC; + +FC_DATA_OUT <= TC_DATA_IN; +FC_SOD_OUT <= '1' when transmit_current_state = WAIT_FOR_H else '0'; +FC_EOD_OUT <= '1' when transmit_current_state = CLOSE else '0'; + +process(CLK) +begin + if rising_edge(CLK) then + if (transmit_current_state = PREPARE_HEADERS) then + if (local_end >= TC_MAX_FRAME_IN) then + ip_size <= TC_MAX_FRAME_IN; + else + ip_size <= local_end + x"1"; + end if; + else + ip_size <= ip_size; + end if; + end if; +end process; +FC_IP_SIZE_OUT <= ip_size; +FC_UDP_SIZE_OUT <= full_packet_size; --TC_FRAME_SIZE_IN; + +FC_FLAGS_OFFSET_OUT(15 downto 14) <= "00"; +FC_FLAGS_OFFSET_OUT(13) <= more_fragments; +MORE_FRAGMENTS_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (transmit_current_state = PREPARE_HEADERS) then + if (local_end >= TC_MAX_FRAME_IN) then + more_fragments <= '1'; + else + more_fragments <= '0'; + end if; + else + more_fragments <= more_fragments; + end if; + end if; +end process MORE_FRAGMENTS_PROC; +FC_FLAGS_OFFSET_OUT(12 downto 0) <= ('0' & x"000") when first_frame = '1' else (packet_loaded_bytes(15 downto 3) + x"1"); + +PACKET_LOADED_BYTES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (transmit_current_state = IDLE) then + packet_loaded_bytes <= x"0000"; + elsif (transmit_current_state = TRANSMIT) then + packet_loaded_bytes <= packet_loaded_bytes + x"1"; +-- elsif (transmit_current_state = DIVIDE and first_frame = '1') then +-- packet_loaded_bytes <= packet_loaded_bytes + x"8"; -- 8bytes for udp headers added for the first offset + else + packet_loaded_bytes <= packet_loaded_bytes; + end if; + end if; +end process PACKET_LOADED_BYTES_PROC; + +FIRST_FRAME_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (transmit_current_state = IDLE) then + first_frame <= '1'; + elsif (transmit_current_state = DIVIDE) then + first_frame <= '0'; + else + first_frame <= first_frame; + end if; + end if; +end process FIRST_FRAME_PROC; + + +TC_TRANSMISSION_DONE_OUT <= '1' when transmit_current_state = CLEANUP else '0'; + +FC_FRAME_TYPE_OUT <= TC_FRAME_TYPE_IN; +FC_IP_PROTOCOL_OUT <= TC_IP_PROTOCOL_IN; +DEST_MAC_ADDRESS_OUT <= TC_DEST_MAC_IN; +DEST_IP_ADDRESS_OUT <= TC_DEST_IP_IN; +DEST_UDP_PORT_OUT <= TC_DEST_UDP_IN; +SRC_MAC_ADDRESS_OUT <= TC_SRC_MAC_IN; +SRC_IP_ADDRESS_OUT <= TC_SRC_IP_IN; +SRC_UDP_PORT_OUT <= TC_SRC_UDP_IN; +FC_IDENT_OUT <= TC_IDENT_IN; + +-- monitoring + +process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + mon_packets_sent_ctr <= (others => '0'); + elsif (transmit_current_state = CLEANUP) then + mon_packets_sent_ctr <= mon_packets_sent_ctr + x"1"; + else + mon_packets_sent_ctr <= mon_packets_sent_ctr; + end if; + end if; +end process; + +MONITOR_TX_PACKETS_OUT <= mon_packets_sent_ctr; + +end trb_net16_gbe_transmit_control2; + + diff --git a/gbe_trb/base/trb_net16_gbe_type_validator.vhd b/gbe_trb/base/trb_net16_gbe_type_validator.vhd new file mode 100644 index 0000000..23bab0d --- /dev/null +++ b/gbe_trb/base/trb_net16_gbe_type_validator.vhd @@ -0,0 +1,141 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + + +--******** +-- contains valid frame types codes and performs checking of type and vlan id +-- by default there is place for 32 frame type which is hardcoded value +-- due to allow register which is set by slow control + +entity trb_net16_gbe_type_validator is +port ( + CLK : in std_logic; -- 125MHz clock input + RESET : in std_logic; + -- ethernet level + FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type + SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id + ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup + VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup + + -- IP level + IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0); + ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0); + + -- UDP level + UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0); + ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0); + + VALID_OUT : out std_logic +); +end trb_net16_gbe_type_validator; + + +architecture trb_net16_gbe_type_validator of trb_net16_gbe_type_validator is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_type_validator : architecture is "GBE_MAIN_group"; + +signal result : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0); +signal ip_result : std_logic_vector(c_MAX_IP_PROTOCOLS - 1 downto 0); +signal udp_result : std_logic_vector(c_MAX_UDP_PROTOCOLS - 1 downto 0); +signal partially_valid : std_logic; -- only protocols, vlan to be checked +signal zeros : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0); + +begin + + zeros <= (others => '0'); + +-- DO NOT TOUCH +IP_RESULTS_GEN : for i in 0 to c_MAX_IP_PROTOCOLS - 1 generate +process(CLK) +begin + if rising_edge(CLK) then + if IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and ALLOWED_IP_PROTOCOLS_IN(i) = '1' then + ip_result(i) <= '1'; + else + ip_result(i) <= '0'; + end if; + end if; +end process; +end generate IP_RESULTS_GEN; + +UDP_RESULTS_GEN : for i in 0 to c_MAX_UDP_PROTOCOLS - 1 generate +process(CLK) +begin + if rising_edge(CLK) then + if UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and ALLOWED_UDP_PROTOCOLS_IN(i) = '1' then + udp_result(i) <= '1'; + else + udp_result(i) <= '0'; + end if; + end if; +end process; +end generate UDP_RESULTS_GEN; + + +RESULT_GEN : for i in 0 to c_MAX_FRAME_TYPES - 1 generate +process(CLK) +begin + if rising_edge(CLK) then + if FRAME_TYPES(i) = FRAME_TYPE_IN and ALLOWED_TYPES_IN(i) = '1' then + result(i) <= '1'; + else + result(i) <= '0'; + end if; + end if; +end process; +end generate RESULT_GEN; + +PARTIALLY_VALID_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + partially_valid <= '0'; + elsif (FRAME_TYPE_IN = x"0800") then -- ip frame + if (IP_PROTOCOLS_IN = x"11") then -- in case of udp inside ip + partially_valid <= or_all(udp_result); + elsif (IP_PROTOCOLS_IN = x"01" or IP_PROTOCOLS_IN = x"dd" or IP_PROTOCOLS_IN = x"ee") then -- in case of ICMP + partially_valid <= '1'; + else -- do not accept other protocols than udp and icmp inside ip + partially_valid <= '0'; + end if; + elsif (result /= zeros) then-- other frame + partially_valid <= '1'; + else + partially_valid <= '0'; + end if; + end if; +end process PARTIALLY_VALID_PROC; + +VALID_OUT_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (partially_valid = '1') then + if (SAVED_VLAN_ID_IN = x"0000") then + VALID_OUT <= '1'; + elsif (VLAN_ID_IN = x"0000_0000") then + VALID_OUT <= '0'; + elsif (SAVED_VLAN_ID_IN = VLAN_ID_IN(15 downto 0) or SAVED_VLAN_ID_IN = VLAN_ID_IN(31 downto 16)) then + VALID_OUT <= '1'; + else + VALID_OUT <= '0'; + end if; + else + VALID_OUT <= '0'; + end if; + end if; +end process VALID_OUT_PROC; + +end trb_net16_gbe_type_validator; + + diff --git a/gbe_trb/base/trb_net_gbe_components.vhd b/gbe_trb/base/trb_net_gbe_components.vhd new file mode 100644 index 0000000..738c320 --- /dev/null +++ b/gbe_trb/base/trb_net_gbe_components.vhd @@ -0,0 +1,1351 @@ +library ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +library work; +use work.trb_net_std.all; + +use work.trb_net_gbe_protocols.all; + +package trb_net_gbe_components is + + + +component trb_net16_gbe_transmit_control2 is +port ( + CLK : in std_logic; + RESET : in std_logic; + +-- signal to/from main controller + TC_DATAREADY_IN : in std_logic; + TC_RD_EN_OUT : out std_logic; + TC_DATA_IN : in std_logic_vector(7 downto 0); + TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); + TC_DEST_MAC_IN : in std_logic_vector(47 downto 0); + TC_DEST_IP_IN : in std_logic_vector(31 downto 0); + TC_DEST_UDP_IN : in std_logic_vector(15 downto 0); + TC_SRC_MAC_IN : in std_logic_vector(47 downto 0); + TC_SRC_IP_IN : in std_logic_vector(31 downto 0); + TC_SRC_UDP_IN : in std_logic_vector(15 downto 0); + TC_IDENT_IN : in std_logic_vector(15 downto 0); + TC_TRANSMISSION_DONE_OUT : out std_logic; + TC_MAX_FRAME_IN : in std_logic_vector(15 downto 0); + +-- signal to/from frame constructor + FC_DATA_OUT : out std_logic_vector(7 downto 0); + FC_WR_EN_OUT : out std_logic; + FC_READY_IN : in std_logic; + FC_H_READY_IN : in std_logic; + FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter + FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + FC_SOD_OUT : out std_logic; + FC_EOD_OUT : out std_logic; + FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + + DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + + MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0) +); +end component; + +component trb_net16_gbe_event_constr is +generic ( + READOUT_BUFFER_SIZE : integer range 1 to 4 := 1 +); +port( + RESET : in std_logic; + CLK : in std_logic; + -- ports for user logic + PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic + PC_DATA_IN : in std_logic_vector(7 downto 0); + PC_READY_OUT : out std_logic; + PC_START_OF_SUB_IN : in std_logic; + PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 + PC_END_OF_QUEUE_IN : in std_logic; + -- queue and subevent layer headers + PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap + PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap + PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap + PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! + PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); + PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap + PC_INSERT_TTYPE_IN : in std_logic; + -- FrameConstructor ports + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_SOD_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component gbe_ipu_dummy is + generic ( + DO_SIMULATION : integer range 0 to 1 := 0; + FIXED_SIZE_MODE : integer range 0 to 1 := 1; + INCREMENTAL_MODE : integer range 0 to 1 := 0; + FIXED_SIZE : integer range 0 to 65535 := 10; + FIXED_DELAY_MODE : integer range 0 to 1 := 1; + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; + FIXED_DELAY : integer range 0 to 16777215 := 16777215 + ); + port ( + clk : in std_logic; + rst : in std_logic; + GBE_READY_IN : in std_logic; + + CFG_EVENT_SIZE_IN : in std_logic_vector(15 downto 0); + CFG_TRIGGERED_MODE_IN : in std_logic; + TRIGGER_IN : in std_logic; + + CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); + CTS_CODE_OUT : out std_logic_vector (7 downto 0); + CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + CTS_START_READOUT_OUT : out std_logic; + CTS_DATA_IN : in std_logic_vector (31 downto 0); + CTS_DATAREADY_IN : in std_logic; + CTS_READOUT_FINISHED_IN : in std_logic; + CTS_READ_OUT : out std_logic; + CTS_LENGTH_IN : in std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_OUT : out std_logic_vector (15 downto 0); + FEE_DATAREADY_OUT : out std_logic; + FEE_READ_IN : in std_logic; + FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + FEE_BUSY_OUT : out std_logic + ); +end component; + +component gbe_sctrl_dummy is + generic ( + DO_SIMULATION : integer range 0 to 1 := 0; + FIXED_DELAY_MODE : integer range 0 to 1 := 1; + FIXED_DELAY : integer range 0 to 65535 := 4096 + ); + port ( + clk : in std_logic; + rst : in std_logic; + + RC_RD_EN_IN : in std_logic; + RC_Q_OUT : out std_logic_vector(8 downto 0); + RC_FRAME_WAITING_OUT : out std_logic; + RC_LOADING_DONE_IN : in std_logic; + RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + + GSC_REPLY_DATAREADY_OUT : out std_logic; + GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_REPLY_READ_IN : in std_logic; + GSC_BUSY_OUT : out std_logic + ); +end component; + +component trb_net16_gbe_buf is +generic( + DO_SIMULATION : integer range 0 to 1 := 1; + RX_PATH_ENABLE : integer range 0 to 1 := 1; + USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1; + + FIXED_SIZE_MODE : integer range 0 to 1 := 1; + INCREMENTAL_MODE : integer range 0 to 1 := 0; + FIXED_SIZE : integer range 0 to 65535 := 10; + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; + FIXED_DELAY_MODE : integer range 0 to 1 := 1; + FIXED_DELAY : integer range 0 to 16777215 := 16777215 +); +port( + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode + RESET : in std_logic; + GSR_N : in std_logic; + -- Debug + STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); + STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); + -- configuration interface + IP_CFG_START_IN : in std_logic; + IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); + IP_CFG_DONE_OUT : out std_logic; + IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); + IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); + IP_CFG_MEM_CLK_OUT : out std_logic; + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_RESTART_IN : in std_logic; + -- gk 29.03.10 + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 + BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 + BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 + BUS_ACK_OUT : out std_logic; -- gk 26.04.10 + -- gk 23.04.10 + LED_PACKET_SENT_OUT : out std_logic; + LED_AN_DONE_N_OUT : out std_logic; + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + --SFP Connection + SFP_RXD_P_IN : in std_logic; + SFP_RXD_N_IN : in std_logic; + SFP_TXD_P_OUT : out std_logic; + SFP_TXD_N_OUT : out std_logic; + SFP_REFCLK_P_IN : in std_logic; + SFP_REFCLK_N_IN : in std_logic; + SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT : out std_logic; -- SFP disable + + -- interface between main_controller and hub logic + MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + + MAKE_RESET_OUT : out std_logic; + + -- for simulation of receiving part only + MAC_RX_EOF_IN : in std_logic; + MAC_RXD_IN : in std_logic_vector(7 downto 0); + MAC_RX_EN_IN : in std_logic; + + + -- debug ports + ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + + +component trb_net16_gbe_protocol_prioritizer is +port ( + CLK : in std_logic; + RESET : in std_logic; + + FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type + PROTOCOL_CODE_IN : in std_logic_vector(7 downto 0); -- ip protocol + UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0); + + CODE_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0) +); +end component; + +component trb_net16_gbe_type_validator is +port ( + CLK : in std_logic; + RESET : in std_logic; + FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type + SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id + ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup + VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup + + -- IP level + IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0); + ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0); + + -- UDP level + UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0); + ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0); + + VALID_OUT : out std_logic +); +end component; + +component trb_net16_gbe_protocol_selector is +generic( + RX_PATH_ENABLE : integer range 0 to 1 := 1; + DO_SIMULATION : integer range 0 to 1 := 0; + + INCLUDE_READOUT : std_logic := '0'; + INCLUDE_SLOWCTRL : std_logic := '0'; + INCLUDE_DHCP : std_logic := '0'; + INCLUDE_ARP : std_logic := '0'; + INCLUDE_PING : std_logic := '0'; + + READOUT_BUFFER_SIZE : integer range 1 to 4; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 + ); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + RESET_FOR_DHCP : in std_logic; + +-- signals to/from main controller + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + PS_RESPONSE_READY_OUT : out std_logic; + + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + +-- singals to/from transmi controller with constructed response + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_RD_EN_IN : in std_logic; + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + MC_BUSY_IN : in std_logic; + + -- misc signals for response constructors + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_OUT : out std_logic_vector(31 downto 0); + DHCP_START_IN : in std_logic; + DHCP_DONE_OUT : out std_logic; + + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + + MAKE_RESET_OUT : out std_logic; + + -- signal for data readout + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + -- ip configurator + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + + -- input for statistics from outside + STAT_DATA_IN : in std_logic_vector(31 downto 0); + STAT_ADDR_IN : in std_logic_vector(7 downto 0); + STAT_DATA_RDY_IN : in std_logic; + STAT_DATA_ACK_OUT : out std_logic; + + MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); + + DATA_HIST_OUT : out hist_array; + SCTRL_HIST_OUT : out hist_array +); +end component; + +component trb_net16_gbe_mac_control is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- signals to/from main controller + MC_TSMAC_READY_OUT : out std_logic; + MC_RECONF_IN : in std_logic; + MC_GBE_EN_IN : in std_logic; + MC_RX_DISCARD_FCS : in std_logic; + MC_PROMISC_IN : in std_logic; + MC_MAC_ADDR_IN : in std_logic_vector(47 downto 0); + +-- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT : out std_logic_vector(7 downto 0); + TSM_HDATA_OUT : out std_logic_vector(7 downto 0); + TSM_HCS_N_OUT : out std_logic; + TSM_HWRITE_N_OUT : out std_logic; + TSM_HREAD_N_OUT : out std_logic; + TSM_HREADY_N_IN : in std_logic; + TSM_HDATA_EN_N_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_main_control is +generic( + RX_PATH_ENABLE : integer range 0 to 1 := 1; + DO_SIMULATION : integer range 0 to 1 := 0; + + INCLUDE_READOUT : std_logic := '0'; + INCLUDE_SLOWCTRL : std_logic := '0'; + INCLUDE_DHCP : std_logic := '0'; + INCLUDE_ARP : std_logic := '0'; + INCLUDE_PING : std_logic := '0'; + + READOUT_BUFFER_SIZE : integer range 1 to 4; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 + ); +port ( + CLK : in std_logic; -- system clock + CLK_125 : in std_logic; + RESET : in std_logic; + + MC_LINK_OK_OUT : out std_logic; + MC_RESET_LINK_IN : in std_logic; + MC_IDLE_TOO_LONG_OUT : out std_logic; + MC_DHCP_DONE_OUT : out std_logic; + MC_MY_MAC_OUT : out std_logic_vector(47 downto 0); + MC_MY_MAC_IN : in std_logic_vector(47 downto 0); + +-- signals to/from receive controller + RC_FRAME_WAITING_IN : in std_logic; + RC_LOADING_DONE_OUT : out std_logic; + RC_DATA_IN : in std_logic_vector(8 downto 0); + RC_RD_EN_OUT : out std_logic; + RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + +-- signals to/from transmit controller + TC_TRANSMIT_CTRL_OUT : out std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_RD_EN_IN : in std_logic; + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_TRANSMIT_DONE_IN : in std_logic; + +-- signals to/from sgmii/gbe pcs_an_complete + PCS_AN_COMPLETE_IN : in std_logic; + +-- signals to/from hub + MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); + + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + + -- signal for data readout + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + -- ip configurator + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + + MAKE_RESET_OUT : out std_logic; + +-- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT : out std_logic_vector(7 downto 0); + TSM_HDATA_OUT : out std_logic_vector(7 downto 0); + TSM_HCS_N_OUT : out std_logic; + TSM_HWRITE_N_OUT : out std_logic; + TSM_HREAD_N_OUT : out std_logic; + TSM_HREADY_N_IN : in std_logic; + TSM_HDATA_EN_N_IN : in std_logic; + TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); + TSM_RX_STAT_EN_IN : in std_logic; + + MAC_READY_CONF_IN : in std_logic; + MAC_RECONF_OUT : out std_logic; + + + MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); + + DATA_HIST_OUT : out hist_array; + SCTRL_HIST_OUT : out hist_array +); +end component; + +component trb_net16_gbe_transmit_control is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- signal to/from main controller + MC_TRANSMIT_CTRL_IN : in std_logic; -- slow control frame is waiting to be built and sent + MC_DATA_IN : in std_logic_vector(8 downto 0); + MC_DATA_NOT_VALID_IN : in std_logic; + MC_WR_EN_IN : in std_logic; + MC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + MC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0); + + MC_DEST_MAC_IN : in std_logic_vector(47 downto 0); + MC_DEST_IP_IN : in std_logic_vector(31 downto 0); + MC_DEST_UDP_IN : in std_logic_vector(15 downto 0); + MC_SRC_MAC_IN : in std_logic_vector(47 downto 0); + MC_SRC_IP_IN : in std_logic_vector(31 downto 0); + MC_SRC_UDP_IN : in std_logic_vector(15 downto 0); + + MC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); + MC_IDENT_IN : in std_logic_vector(15 downto 0); + + MC_IP_SIZE_IN : in std_logic_vector(15 downto 0); + MC_UDP_SIZE_IN : in std_logic_vector(15 downto 0); + MC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); + + MC_FC_H_READY_OUT : out std_logic; + MC_FC_READY_OUT : out std_logic; + MC_FC_WR_EN_IN : in std_logic; + + MC_BUSY_OUT : out std_logic; + MC_TRANSMIT_DONE_OUT : out std_logic; + +-- signal to/from frame constructor + FC_DATA_OUT : out std_logic_vector(7 downto 0); + FC_WR_EN_OUT : out std_logic; + FC_READY_IN : in std_logic; + FC_H_READY_IN : in std_logic; + FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter + FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + FC_SOD_OUT : out std_logic; + FC_EOD_OUT : out std_logic; + FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + + DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_receive_control is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- signals to/from frame_receiver + RC_DATA_IN : in std_logic_vector(8 downto 0); + FR_RD_EN_OUT : out std_logic; + FR_FRAME_VALID_IN : in std_logic; + FR_GET_FRAME_OUT : out std_logic; + FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0); + FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); + + FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + +-- signals to the rest of the logic + RC_RD_EN_IN : in std_logic; + RC_Q_OUT : out std_logic_vector(8 downto 0); + RC_FRAME_WAITING_OUT : out std_logic; + RC_LOADING_DONE_IN : in std_logic; + RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + +-- statistics + FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0); + BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0); + + + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_frame_receiver is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + LINK_OK_IN : in std_logic; + ALLOW_RX_IN : in std_logic; + RX_MAC_CLK : in std_logic; -- receiver serdes clock + MY_MAC_IN : in std_logic_vector(47 downto 0); + +-- input signals from TS_MAC + MAC_RX_EOF_IN : in std_logic; + MAC_RX_ER_IN : in std_logic; + MAC_RXD_IN : in std_logic_vector(7 downto 0); + MAC_RX_EN_IN : in std_logic; + MAC_RX_FIFO_ERR_IN : in std_logic; + MAC_RX_FIFO_FULL_OUT : out std_logic; + MAC_RX_STAT_EN_IN : in std_logic; + MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); +-- output signal to control logic + FR_Q_OUT : out std_logic_vector(8 downto 0); + FR_RD_EN_IN : in std_logic; + FR_FRAME_VALID_OUT : out std_logic; + FR_GET_FRAME_IN : in std_logic; + FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0); + FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); + FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0); + FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0); + FR_VLAN_ID_IN : in std_logic_vector(31 downto 0); + + FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + + MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0); + MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0) +); +end component; + +-- gk 01.07.10 +component trb_net16_ipu2gbe is +port( + CLK : in std_logic; + RESET : in std_logic; + -- IPU interface directed toward the CTS + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_READ_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data from Frontends + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_BUSY_IN : in std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + -- slow control interface + START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size + BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address + CONFIG_DONE_IN : in std_logic; -- configuration finished + DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE + DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet + MULT_EVT_ENABLE_IN : in std_logic; + MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 + MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 + READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 + READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 + +-- SCTRL_DUMMY_SIZE_IN : in std_logic_vector(15 downto 0); +-- SCTRL_DUMMY_PAUSE_IN : in std_logic_vector(31 downto 0); + + -- PacketConstructor interface + ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10 + PC_WR_EN_OUT : out std_logic; + PC_DATA_OUT : out std_logic_vector (7 downto 0); + PC_READY_IN : in std_logic; + PC_SOS_OUT : out std_logic; + PC_EOS_OUT : out std_logic; -- gk 07.10.10 + PC_EOD_OUT : out std_logic; + PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); + PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); + PC_PADDING_OUT : out std_logic; + MONITOR_OUT : out std_logic_vector(223 downto 0); + DEBUG_OUT : out std_logic_vector(383 downto 0) +); +end component; + +component trb_net16_gbe_packet_constr is +port( + RESET : in std_logic; + CLK : in std_logic; + MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10 + -- ports for user logic + PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic + PC_DATA_IN : in std_logic_vector(7 downto 0); + PC_READY_OUT : out std_logic; + PC_START_OF_SUB_IN : in std_logic; + PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 + PC_END_OF_DATA_IN : in std_logic; + PC_TRANSMIT_ON_OUT : out std_logic; + -- queue and subevent layer headers + PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap + PC_PADDING_IN : in std_logic; -- gk 29.03.10 + PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap + PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap + PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! + PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap + PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP + PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 + -- FrameConstructor ports + TC_WR_EN_OUT : out std_logic; + TC_DATA_OUT : out std_logic_vector(7 downto 0); + TC_H_READY_IN : in std_logic; + TC_READY_IN : in std_logic; + TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + TC_SOD_OUT : out std_logic; + TC_EOD_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_frame_constr is +generic ( + FRAME_BUFFER_SIZE : integer range 1 to 4 := 1 +); +port( + -- ports for user logic + RESET : in std_logic; + CLK : in std_logic; + LINK_OK_IN : in std_logic; -- gk 03.08.10 + -- + WR_EN_IN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + START_OF_DATA_IN : in std_logic; + END_OF_DATA_IN : in std_logic; + IP_F_SIZE_IN : in std_logic_vector(15 downto 0); + UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation + HEADERS_READY_OUT : out std_logic; + READY_OUT : out std_logic; + DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + FRAME_TYPE_IN : in std_logic_vector(15 downto 0); + IHL_VERSION_IN : in std_logic_vector(7 downto 0); + TOS_IN : in std_logic_vector(7 downto 0); + IDENTIFICATION_IN : in std_logic_vector(15 downto 0); + FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); + TTL_IN : in std_logic_vector(7 downto 0); + PROTOCOL_IN : in std_logic_vector(7 downto 0); + FRAME_DELAY_IN : in std_logic_vector(31 downto 0); + -- ports for packetTransmitter + RD_CLK : in std_logic; -- 125MHz clock!!! + FT_DATA_OUT : out std_logic_vector(8 downto 0); + FT_TX_EMPTY_OUT : out std_logic; + FT_TX_RD_EN_IN : in std_logic; + FT_START_OF_PACKET_OUT : out std_logic; + FT_TX_DONE_IN : in std_logic; + FT_TX_DISCFRM_IN : in std_logic; + + MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0) +); +end component; + +component trb_net16_gbe_frame_trans is +port ( + CLK : in std_logic; + RESET : in std_logic; + LINK_OK_IN : in std_logic; -- gk 03.08.10 + TX_MAC_CLK : in std_logic; + TX_EMPTY_IN : in std_logic; + START_OF_PACKET_IN : in std_logic; + DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC + -- NEW PORTS +-- HADDR_OUT : out std_logic_vector(7 downto 0); +-- HDATA_OUT : out std_logic_vector(7 downto 0); +-- HCS_OUT : out std_logic; +-- HWRITE_OUT : out std_logic; +-- HREAD_OUT : out std_logic; +-- HREADY_IN : in std_logic; +-- HDATA_EN_IN : in std_logic; + TX_FIFOAVAIL_OUT : out std_logic; + TX_FIFOEOF_OUT : out std_logic; + TX_FIFOEMPTY_OUT : out std_logic; + TX_DONE_IN : in std_logic; + TX_STAT_EN_IN : in std_logic; + TX_STATVEC_IN : in std_logic_vector(30 downto 0); + TX_DISCFRM_IN : in std_logic; + -- Debug + BSM_INIT_OUT : out std_logic_vector(3 downto 0); + BSM_MAC_OUT : out std_logic_vector(3 downto 0); + BSM_TRANS_OUT : out std_logic_vector(3 downto 0); + DBG_RD_DONE_OUT : out std_logic; + DBG_INIT_DONE_OUT : out std_logic; + DBG_ENABLED_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_med_ecp_sfp_gbe_8b is +-- gk 28.04.10 +generic ( + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 +); +port( + RESET : in std_logic; + GSR_N : in std_logic; + CLK_125_OUT : out std_logic; + CLK_125_RX_OUT : out std_logic; + CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk + --SGMII connection to frame transmitter (tsmac) + FT_TX_CLK_EN_OUT : out std_logic; + FT_RX_CLK_EN_OUT : out std_logic; + FT_COL_OUT : out std_logic; + FT_CRS_OUT : out std_logic; + FT_TXD_IN : in std_logic_vector(7 downto 0); + FT_TX_EN_IN : in std_logic; + FT_TX_ER_IN : in std_logic; + FT_RXD_OUT : out std_logic_vector(7 downto 0); + FT_RX_EN_OUT : out std_logic; + FT_RX_ER_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Autonegotiation stuff + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); + MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); + MR_AN_PAGE_RX_OUT : out std_logic; + MR_AN_COMPLETE_OUT : out std_logic; + MR_AN_ENABLE_IN : in std_logic; + MR_RESTART_AN_IN : in std_logic; + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) +); +end component; + +component gbe_setup is +port( + CLK : in std_logic; + RESET : in std_logic; + + -- interface to regio bus + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + BUS_WRITE_EN_IN : in std_logic; + BUS_READ_EN_IN : in std_logic; + BUS_ACK_OUT : out std_logic; + + -- output to gbe_buf + GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0); + GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0); + GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0); + GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0); + GBE_USE_GBE_OUT : out std_logic; + GBE_USE_TRBNET_OUT : out std_logic; + GBE_USE_MULTIEVENTS_OUT : out std_logic; + GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); + GBE_READOUT_CTR_VALID_OUT : out std_logic; + GBE_ALLOW_RX_OUT : out std_logic; + GBE_ADDITIONAL_HDR_OUT : out std_logic; + GBE_INSERT_TTYPE_OUT : out std_logic; + GBE_SOFT_RESET_OUT : out std_logic; + GBE_MAX_REPLY_OUT : out std_logic_vector(31 downto 0); + + GBE_MAX_SUB_OUT : out std_logic_vector(15 downto 0); + GBE_MAX_QUEUE_OUT : out std_logic_vector(15 downto 0); + GBE_MAX_SUBS_IN_QUEUE_OUT : out std_logic_vector(15 downto 0); + GBE_MAX_SINGLE_SUB_OUT : out std_logic_vector(15 downto 0); + + MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0); + MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0); + MONITOR_TX_BYTES_IN : in std_logic_vector(31 downto 0); + MONITOR_TX_FRAMES_IN : in std_logic_vector(31 downto 0); + MONITOR_TX_PACKETS_IN : in std_logic_vector(31 downto 0); + MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0); + + MONITOR_SELECT_REC_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_REC_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_IN_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_OUT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_GEN_DBG_IN : in std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); + + DUMMY_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0); + DUMMY_TRIGGERED_MODE_OUT : out std_logic; + + DATA_HIST_IN : in hist_array; + SCTRL_HIST_IN : in hist_array +); +end component; + + +component ip_configurator is +port( + CLK : in std_logic; + RESET : in std_logic; + -- configuration interface + START_CONFIG_IN : in std_logic; -- start configuration run + BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank + CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used + MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for + MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory + MEM_CLK_OUT : out std_logic; -- clock for BlockRAM + -- information for IP cores + DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address + DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address + DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port + SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address + SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address + SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port + MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size) + -- Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component; + +component fifo_4096x9 is +port( + Data : in std_logic_vector(8 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_2048x8 is +port( + Data : in std_logic_vector(7 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_4096x32 is +port( + Data : in std_logic_vector(31 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(31 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_512x32 is +port( + Data : in std_logic_vector(31 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(31 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_512x72 is +port( + Data : in std_logic_vector(71 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(71 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_1024x16x8 is +port( + Data : in std_logic_vector(17 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_65536x18x9 is +port( + Data : in std_logic_vector(17 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_4kx18x9 is +port( + Data : in std_logic_vector(17 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + + +component fifo_2048x8x16 is +port( + Data : in std_logic_vector(8 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(17 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_4kx8_ecp3 is +port( + Data : in std_logic_vector(7 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component statts_mem is + port ( + WrAddress: in std_logic_vector(7 downto 0); + RdAddress: in std_logic_vector(9 downto 0); + Data: in std_logic_vector(31 downto 0); + WE: in std_logic; + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + WrClock: in std_logic; + WrClockEn: in std_logic; + Q: out std_logic_vector(7 downto 0)); +end component; + +--component slv_mac_memory is +--port( +-- CLK : in std_logic; +-- RESET : in std_logic; +-- BUSY_IN : in std_logic; +-- -- Slave bus +-- SLV_ADDR_IN : in std_logic_vector(7 downto 0); +-- SLV_READ_IN : in std_logic; +-- SLV_WRITE_IN : in std_logic; +-- SLV_BUSY_OUT : out std_logic; +-- SLV_ACK_OUT : out std_logic; +-- SLV_DATA_IN : in std_logic_vector(31 downto 0); +-- SLV_DATA_OUT : out std_logic_vector(31 downto 0); +-- -- I/O to the backend +-- MEM_CLK_IN : in std_logic; +-- MEM_ADDR_IN : in std_logic_vector(7 downto 0); +-- MEM_DATA_OUT : out std_logic_vector(31 downto 0); +-- -- Status lines +-- STAT : out std_logic_vector(31 downto 0) -- DEBUG +--); +--end component; + +component fifo_32kx16x8_mb2 +port( + Data : in std_logic_vector(17 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + AmEmptyThresh : in std_logic_vector(15 downto 0); + AmFullThresh : in std_logic_vector(14 downto 0); + Q : out std_logic_vector(8 downto 0); + WCNT : out std_logic_vector(15 downto 0); + RCNT : out std_logic_vector(16 downto 0); + Empty : out std_logic; + AlmostEmpty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic +); +end component; + +component fifo_64kx9 +port ( + Data : in std_logic_vector(8 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_16kx18x9 is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + AmEmptyThresh: in std_logic_vector(14 downto 0); + AmFullThresh: in std_logic_vector(13 downto 0); + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end component; + +component fifo_32kx9_flags is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull : out std_logic); +end component; + + +component fifo_512x32x8 +port ( + Data : in std_logic_vector(31 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component fifo_512x8 +port ( + Data : in std_logic_vector(7 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +end package; \ No newline at end of file diff --git a/gbe_trb/base/trb_net_gbe_protocols.vhd b/gbe_trb/base/trb_net_gbe_protocols.vhd new file mode 100644 index 0000000..a322450 --- /dev/null +++ b/gbe_trb/base/trb_net_gbe_protocols.vhd @@ -0,0 +1,656 @@ +library ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +library work; +use work.trb_net_std.all; + +package trb_net_gbe_protocols is + +type hist_array is array(31 downto 0) of std_logic_vector(31 downto 0); + +--signal g_SIMULATE : integer range 0 to 1 := 0; + +---- g_MY_IP is being set by DHCP Response Constructor +--signal g_MY_IP : std_logic_vector(31 downto 0); +---- g_MY_MAC is being set by Main Controller +--signal g_MY_MAC : std_logic_vector(47 downto 0) := x"001122334455"; + +constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 2; +constant c_MAX_PROTOCOLS : integer range 1 to 16 := 5; --5; --4; --5; +constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 2; +constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 4; + +type frame_types_a is array(c_MAX_FRAME_TYPES - 1 downto 0) of std_logic_vector(15 downto 0); +constant FRAME_TYPES : frame_types_a := (x"0800", x"0806"); +-- IPv4, ARP + +type ip_protos_a is array(c_MAX_IP_PROTOCOLS - 1 downto 0) of std_logic_vector(7 downto 0); +constant IP_PROTOCOLS : ip_protos_a := (x"11", x"01"); +-- UDP, ICMP + +-- this are the destination ports of the incoming packet +type udp_protos_a is array(c_MAX_UDP_PROTOCOLS - 1 downto 0) of std_logic_vector(15 downto 0); +constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"6590", x"7530", x"7531"); --x"6590", x"7530", x"7531"); --x"61a8", x"7530", x"7531"); +-- DHCP client, SCTRL, STATs + +component trb_net16_gbe_response_constructor_Forward is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_WR_EN_OUT : out std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + TC_BUSY_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_response_constructor_ARP is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_response_constructor_Test is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_WR_EN_OUT : out std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + TC_BUSY_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_response_constructor_Trash is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_SIZE_LEFT_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + TC_BUSY_IN : in std_logic; + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_response_constructor_DHCP is +generic ( + STAT_ADDRESS_BASE : integer := 0; + DO_SIMULATION : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + + MY_IP_OUT : out std_logic_vector(31 downto 0); + DHCP_START_IN : in std_logic; + DHCP_DONE_OUT : out std_logic; +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_response_constructor_Ping is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_response_constructor_PseudoPing is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_response_constructor_Test1 is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_WR_EN_OUT : out std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + TC_BUSY_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_response_constructor_SCTRL is +generic ( STAT_ADDRESS_BASE : integer := 0; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1 +); + port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + + -- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(63 downto 0); + -- END OF INTERFACE + + -- protocol specific ports + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + MAKE_RESET_OUT : out std_logic; + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + -- end of protocol specific ports + + MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0); + + DATA_HIST_OUT : out hist_array + ); +end component; + +component trb_net16_gbe_response_constructor_Stat is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_WR_EN_OUT : out std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + TC_BUSY_IN : in std_logic; + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + + STAT_DATA_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0); + STAT_ADDR_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0); + STAT_DATA_RDY_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0); + STAT_DATA_ACK_OUT : out std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0); + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component trb_net16_gbe_response_constructor_TrbNetData is +generic ( + RX_PATH_ENABLE : integer range 0 to 1 := 1; + DO_SIMULATION : integer range 0 to 1 := 0; + + READOUT_BUFFER_SIZE : integer range 1 to 4 := 1 + ); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(63 downto 0); + +-- END OF INTERFACE + + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + -- ip configurator + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + + MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(31 downto 0); + + DATA_HIST_OUT : out hist_array +); +end component; + +end package; diff --git a/gbe_trb/ipcores/ecp3/debug_fifo_2kx16.vhd b/gbe_trb/ipcores/ecp3/debug_fifo_2kx16.vhd new file mode 100644 index 0000000..e10ee86 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/debug_fifo_2kx16.vhd @@ -0,0 +1,1965 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 16 -depth 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -e + +-- Wed Jul 21 14:35:10 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity debug_fifo_2kx16 is + port ( + Data: in std_logic_vector(15 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(15 downto 0); + Empty: out std_logic; + Full: out std_logic); +end debug_fifo_2kx16; + +architecture Structure of debug_fifo_2kx16 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal wcount_11: std_logic; + signal co4: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co5_1: std_logic; + signal rcount_11: std_logic; + signal co4_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_10: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_31 : label is "0x6996"; + attribute initval of LUT4_30 : label is "0x6996"; + attribute initval of LUT4_29 : label is "0x6996"; + attribute initval of LUT4_28 : label is "0x6996"; + attribute initval of LUT4_27 : label is "0x6996"; + attribute initval of LUT4_26 : label is "0x6996"; + attribute initval of LUT4_25 : label is "0x6996"; + attribute initval of LUT4_24 : label is "0x6996"; + attribute initval of LUT4_23 : label is "0x6996"; + attribute initval of LUT4_22 : label is "0x6996"; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "debug_fifo_2kx16.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "debug_fifo_2kx16.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute CSDECODE_B of pdp_ram_0_1_0 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_1_0 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_1_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_1_0 : label is "NORMAL"; + attribute GSR of pdp_ram_0_1_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_1_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_1_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_1_0 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_1_0 : label is "9"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t24: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t23: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t22: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t21: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t20: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t19: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t18: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t17: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t16: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t15: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t14: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t13: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t12: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t11: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t10: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t9: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t8: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t7: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t6: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t5: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t4: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t3: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t2: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t1: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t0: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + LUT4_31: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_30: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_29: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_28: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_27: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_26: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_25: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_24: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_23: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_22: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, + DO0=>r_g2b_xor_cluster_0); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, + DO0=>r_g2b_xor_cluster_1); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, + DO0=>r_g2b_xor_cluster_2); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), + DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_1_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(9), + DOB1=>Q(10), DOB2=>Q(11), DOB3=>Q(12), DOB4=>Q(13), + DOB5=>Q(14), DOB6=>Q(15), DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + FF_121: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_111: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_85: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_49: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_48: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_47: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_46: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_45: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_44: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_43: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_42: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_41: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_40: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_39: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_38: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, + B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, + B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of debug_fifo_2kx16 is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_1024x16x8.lpc b/gbe_trb/ipcores/ecp3/fifo_1024x16x8.lpc new file mode 100644 index 0000000..0bcc570 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_1024x16x8.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_1024x16x8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/05/2011 +Time=18:27:25 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=1024 +Width=18 +RDepth=2048 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_1024x16x8.vhd b/gbe_trb/ipcores/ecp3/fifo_1024x16x8.vhd new file mode 100644 index 0000000..956f91e --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_1024x16x8.vhd @@ -0,0 +1,1366 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 18 -depth 1024 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + +-- Mon Dec 5 18:27:25 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_1024x16x8 is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_1024x16x8; + +architecture Structure of fifo_1024x16x8 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal co5: std_logic; + signal wcount_10: std_logic; + signal co4: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co5_1: std_logic; + signal rcount_11: std_logic; + signal co4_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r8: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r9: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_10: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w7: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w9: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_1024x16x8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t23: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t22: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t21: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t20: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t19: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t18: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t17: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t16: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t15: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t14: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t13: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t12: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t11: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t10: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t9: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t8: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t7: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t6: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t5: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t4: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t3: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t2: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t1: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t0: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>w_gcount_r210, + DO0=>w_g2b_xor_cluster_0); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_gcount_r26, + DO0=>w_g2b_xor_cluster_1); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r4); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r21, AD0=>w_gcount_r22, DO0=>wcount_r1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, + DO0=>r_g2b_xor_cluster_0); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, + DO0=>r_g2b_xor_cluster_1); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, + DO0=>r_g2b_xor_cluster_2); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), + DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_116: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_115: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_114: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_113: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_112: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_111: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_110: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_109: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_108: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_107: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_106: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_105: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_104: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_103: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_102: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_101: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_100: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_99: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_98: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_97: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_96: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_95: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_94: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_93: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_92: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_91: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_90: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_89: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_88: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_87: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_86: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_85: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_84: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_83: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_82: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_81: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_80: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_79: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_78: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_77: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_76: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_75: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_74: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_73: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_72: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_71: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_70: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_69: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_68: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_67: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_66: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_65: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_64: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_63: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_62: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_61: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_60: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_59: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_58: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_57: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_56: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_55: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_54: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_53: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_52: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_51: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_50: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_49: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_48: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_47: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_46: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_45: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_44: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_43: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_42: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_41: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_40: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_39: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_38: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_37: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_36: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_35: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_34: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_33: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_32: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_31: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_30: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_29: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_28: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_27: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_26: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_25: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_24: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_23: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_22: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_21: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_20: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_19: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_18: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_17: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_16: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_15: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_14: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_13: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_12: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_11: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_10: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_9: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_8: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_7: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_6: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_5: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_4: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_3: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_2: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5, + NC0=>iwcount_10, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r8, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r9, + B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>r_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, + B1=>rcount_w10, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co4_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_1024x16x8 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_16kx8.vhd b/gbe_trb/ipcores/ecp3/fifo_16kx8.vhd new file mode 100644 index 0000000..12a3160 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_16kx8.vhd @@ -0,0 +1,2711 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.4 +--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 8 -depth 16384 -rdata_width 8 -no_enable -pe -1 -pf -1 -e + +-- Mon Dec 6 19:08:10 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_16kx8 is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_16kx8; + +architecture Structure of fifo_16kx8 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal co7: std_logic; + signal wcount_14: std_logic; + signal co6: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal co7_1: std_logic; + signal rcount_14: std_logic; + signal co6_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal wcount_r12: std_logic; + signal wcount_r13: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal rcount_w12: std_logic; + signal rcount_w13: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_41 : label is "0x6996"; + attribute initval of LUT4_40 : label is "0x6996"; + attribute initval of LUT4_39 : label is "0x6996"; + attribute initval of LUT4_38 : label is "0x6996"; + attribute initval of LUT4_37 : label is "0x6996"; + attribute initval of LUT4_36 : label is "0x6996"; + attribute initval of LUT4_35 : label is "0x6996"; + attribute initval of LUT4_34 : label is "0x6996"; + attribute initval of LUT4_33 : label is "0x6996"; + attribute initval of LUT4_32 : label is "0x6996"; + attribute initval of LUT4_31 : label is "0x6996"; + attribute initval of LUT4_30 : label is "0x6996"; + attribute initval of LUT4_29 : label is "0x6996"; + attribute initval of LUT4_28 : label is "0x6996"; + attribute initval of LUT4_27 : label is "0x6996"; + attribute initval of LUT4_26 : label is "0x6996"; + attribute initval of LUT4_25 : label is "0x6996"; + attribute initval of LUT4_24 : label is "0x6996"; + attribute initval of LUT4_23 : label is "0x6996"; + attribute initval of LUT4_22 : label is "0x6996"; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_16kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_7 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_16kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; + attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL"; + attribute GSR of pdp_ram_0_1_6 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_16kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; + attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL"; + attribute GSR of pdp_ram_0_2_5 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_16kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; + attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL"; + attribute GSR of pdp_ram_0_3_4 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_16kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; + attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL"; + attribute GSR of pdp_ram_0_4_3 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_16kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; + attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL"; + attribute GSR of pdp_ram_0_5_2 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_16kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; + attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL"; + attribute GSR of pdp_ram_0_6_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "1"; + attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_16kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; + attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL"; + attribute GSR of pdp_ram_0_7_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "1"; + attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "1"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t30: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t29: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t28: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t27: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t26: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t25: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t24: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t23: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t22: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t21: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t20: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t19: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t18: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t17: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t16: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t15: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t14: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t13: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t12: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t11: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t10: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t9: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t8: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t7: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t6: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t5: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t4: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t3: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t2: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t1: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t0: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + LUT4_41: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>w_gcount_r214, + DO0=>w_g2b_xor_cluster_0); + + LUT4_40: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>w_gcount_r210, + DO0=>w_g2b_xor_cluster_1); + + LUT4_39: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_gcount_r26, + DO0=>w_g2b_xor_cluster_2); + + LUT4_38: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_37: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>scuba_vlo, DO0=>wcount_r12); + + LUT4_36: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_35: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9); + + LUT4_34: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r8); + + LUT4_33: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_32: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_31: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>wcount_r5); + + LUT4_30: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_29: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_28: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_27: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r22, DO0=>wcount_r2); + + LUT4_26: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3); + + LUT4_25: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r1); + + LUT4_24: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_1); + + LUT4_23: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r0); + + LUT4_22: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>r_gcount_w214, + DO0=>r_g2b_xor_cluster_0); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_gcount_w210, + DO0=>r_g2b_xor_cluster_1); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_2); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w13); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>scuba_vlo, DO0=>rcount_w12); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w8); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, DO0=>rcount_w5); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w22, DO0=>rcount_w2); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_1); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w0); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_7: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_1_6: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(1), DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_2_5: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(2), DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_3_4: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(3), DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_4_3: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(4), DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_5_2: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(5), DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_6_1: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(6), DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_7_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + -- synopsys translate_on + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(7), DOB1=>open, DOB2=>open, DOB3=>open, + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_151: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_150: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_149: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_148: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_147: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_146: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_145: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_144: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_143: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_142: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_141: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_140: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_139: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_138: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_137: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_136: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_135: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_134: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_133: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_132: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_131: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_130: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_129: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_128: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_127: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_126: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_125: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_124: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_123: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_122: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_121: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_111: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_106: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_61: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_60: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_59: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_58: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_57: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_56: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_55: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_54: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_53: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_52: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_51: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_50: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_49: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_48: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_47: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_46: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_45: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_44: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_43: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_42: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_41: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_40: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_39: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_38: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7, + NC0=>iwcount_14, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_1, + NC0=>ircount_14, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>w_g2b_xor_cluster_0, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, + B1=>wcount_r13, CI=>co5_2, GE=>co6_2); + + empty_cmp_7: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co6_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>r_g2b_xor_cluster_0, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, + B1=>rcount_w13, CI=>co5_3, GE=>co6_3); + + full_cmp_7: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co6_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_16kx8 is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_2048x8.lpc b/gbe_trb/ipcores/ecp3/fifo_2048x8.lpc new file mode 100755 index 0000000..7c0b6de --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_2048x8.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_2048x8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:23:58 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=8 +RDepth=2048 +RWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_2048x8.vhd b/gbe_trb/ipcores/ecp3/fifo_2048x8.vhd new file mode 100755 index 0000000..82dac9a --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_2048x8.vhd @@ -0,0 +1,1415 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:23:58 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_2048x8 is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_2048x8; + +architecture Structure of fifo_2048x8 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal wcount_11: std_logic; + signal co4: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co5_1: std_logic; + signal rcount_11: std_logic; + signal co4_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_10: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t24: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t23: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t22: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t21: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t20: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t19: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t18: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t17: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t16: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t15: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t14: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t13: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t12: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t11: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t10: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t9: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t8: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t7: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t6: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t5: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t4: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t3: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t2: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t1: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t0: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, + DO0=>r_g2b_xor_cluster_0); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, + DO0=>r_g2b_xor_cluster_1); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, + DO0=>r_g2b_xor_cluster_2); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), + DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_121: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_120: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_119: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_118: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_117: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_116: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_115: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_114: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_113: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_112: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_111: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_110: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_109: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_108: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_107: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_106: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_105: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_104: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_103: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_102: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_101: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_100: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_99: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_98: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_97: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_96: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_95: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_94: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_93: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_92: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_91: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_90: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_89: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_88: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_87: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_86: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_85: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_84: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_83: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_82: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_81: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_80: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_79: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_78: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_77: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_76: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_75: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_74: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_73: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_72: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_71: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_70: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_69: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_68: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_67: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_66: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_65: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_64: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_63: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_62: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_61: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_60: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_59: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_58: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_57: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_56: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_55: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_54: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_53: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_52: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_51: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_50: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_49: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_48: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_47: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_46: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_45: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_44: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_43: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_42: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_41: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_40: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_39: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_38: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_37: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_36: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_35: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_34: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_33: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_32: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_31: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_30: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_29: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_28: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_27: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_26: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_25: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_24: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_23: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_22: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_21: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_20: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_19: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_18: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_17: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_16: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_15: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_14: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_13: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_12: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_11: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_10: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_9: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_8: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_7: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_6: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_5: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_4: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_3: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_2: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, + B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, + B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_2048x8 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_2048x8x16.lpc b/gbe_trb/ipcores/ecp3/fifo_2048x8x16.lpc new file mode 100644 index 0000000..4f4da58 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_2048x8x16.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_2048x8x16 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/05/2011 +Time=18:26:53 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=9 +RDepth=1024 +RWidth=18 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd b/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd new file mode 100644 index 0000000..4486567 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd @@ -0,0 +1,1367 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 9 -depth 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -e + +-- Mon Dec 5 18:26:53 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_2048x8x16 is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_2048x8x16; + +architecture Structure of fifo_2048x8x16 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal wcount_11: std_logic; + signal co4: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal co5_1: std_logic; + signal rcount_10: std_logic; + signal co4_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r7: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w8: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w9: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8x16.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t23: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t22: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t21: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t20: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t19: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t18: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t17: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t16: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t15: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t14: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t13: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t12: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t11: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t10: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t9: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t8: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t7: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t6: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t5: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t4: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t3: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t2: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t1: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t0: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_gcount_w210, + DO0=>r_g2b_xor_cluster_0); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_1); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo, + ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3, + ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, ADB11=>rptr_7, + ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), + DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), + DOB11=>Q(11), DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), + DOB15=>Q(15), DOB16=>Q(16), DOB17=>Q(17)); + + FF_116: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_115: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_114: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_113: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_112: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_111: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_110: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_109: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_108: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_107: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_106: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_105: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_104: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_103: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_102: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_101: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_100: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_99: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_98: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_97: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_96: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_95: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_94: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_93: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_92: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_91: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_90: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_89: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_88: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_87: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_86: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_85: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_84: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_83: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_82: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_81: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_80: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_79: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_78: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_77: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_76: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_75: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_74: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_73: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_72: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_71: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_70: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_69: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_68: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_67: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_66: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_65: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_64: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_63: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_62: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_61: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_60: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_59: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_58: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_57: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_56: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_55: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_54: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_53: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_52: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_51: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_50: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_49: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_48: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_47: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_46: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_45: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_44: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_43: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_42: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_41: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_40: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_39: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_38: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_37: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_36: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_35: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_34: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_33: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_32: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_31: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_30: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_29: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_28: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_27: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_26: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_25: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_24: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_23: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_22: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_21: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_20: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_19: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_18: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_17: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_16: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_15: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_14: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_13: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_12: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_11: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_10: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_9: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_8: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_7: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_6: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_5: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_4: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_3: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_2: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1, + NC0=>ircount_10, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r1, + B1=>wcount_r2, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r3, + B1=>wcount_r4, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r5, + B1=>wcount_r6, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r7, + B1=>w_g2b_xor_cluster_0, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r9, + B1=>wcount_r10, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co4_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>rcount_w0, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w1, + B1=>rcount_w2, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w3, + B1=>rcount_w4, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w5, + B1=>rcount_w6, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w8, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w9, + B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_2048x8x16 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb.lpc b/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb.lpc new file mode 100755 index 0000000..aa233bb --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_32kx16x8_mb +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:22:35 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=16 +RDepth=65536 +RWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Dynamic - Single Threshold +PeAssert=16 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=32752 +PfDeassert=506 +RDataCount=1 +WDataCount=1 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb.vhd b/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb.vhd new file mode 100755 index 0000000..a24a3e6 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb.vhd @@ -0,0 +1,3997 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e + +-- Thu Sep 22 11:22:35 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_32kx16x8_mb is + port ( + Data: in std_logic_vector(15 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + AmEmptyThresh: in std_logic_vector(15 downto 0); + AmFullThresh: in std_logic_vector(14 downto 0); + Q: out std_logic_vector(7 downto 0); + WCNT: out std_logic_vector(15 downto 0); + RCNT: out std_logic_vector(16 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_32kx16x8_mb; + +architecture Structure of fifo_32kx16x8_mb is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal rcount_w0: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal rcnt_reg_15_inv: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal wptr_15: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_16: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal rcnt_reg_16: std_logic; + signal empty_i: std_logic; + signal full_i: std_logic; + signal rRst: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co7: std_logic; + signal wcount_15: std_logic; + signal co6: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8: std_logic; + signal rcount_16: std_logic; + signal co7_1: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal wcnt_sub_0: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal co0_2: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal co1_2: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal co2_2: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal co3_2: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_10: std_logic; + signal co4_2: std_logic; + signal wcnt_sub_11: std_logic; + signal wcnt_sub_12: std_logic; + signal co5_2: std_logic; + signal wcnt_sub_13: std_logic; + signal wcnt_sub_14: std_logic; + signal co6_2: std_logic; + signal wcnt_sub_15: std_logic; + signal co7_2: std_logic; + signal wcnt_sub_msb: std_logic; + signal rcnt_sub_0: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; + signal co0_3: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; + signal co1_3: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; + signal co2_3: std_logic; + signal rcnt_sub_7: std_logic; + signal rcnt_sub_8: std_logic; + signal co3_3: std_logic; + signal rcnt_sub_9: std_logic; + signal rcnt_sub_10: std_logic; + signal co4_3: std_logic; + signal rcnt_sub_11: std_logic; + signal rcnt_sub_12: std_logic; + signal co5_3: std_logic; + signal rcnt_sub_13: std_logic; + signal rcnt_sub_14: std_logic; + signal co6_3: std_logic; + signal rcnt_sub_15: std_logic; + signal rcnt_sub_16: std_logic; + signal co7_3: std_logic; + signal rcnt_sub_msb: std_logic; + signal co8_1d: std_logic; + signal co8_1: std_logic; + signal wfill_sub_0: std_logic; + signal wptr_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_4: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_4: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_4: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_4: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_11: std_logic; + signal wfill_sub_12: std_logic; + signal co5_4: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wfill_sub_13: std_logic; + signal wfill_sub_14: std_logic; + signal co6_4: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wfill_sub_15: std_logic; + signal co7_4: std_logic; + signal wfill_sub_msb: std_logic; + signal rfill_sub_0: std_logic; + signal rptr_0: std_logic; + signal scuba_vhi: std_logic; + signal rfill_sub_1: std_logic; + signal rfill_sub_2: std_logic; + signal co0_5: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rfill_sub_3: std_logic; + signal rfill_sub_4: std_logic; + signal co1_5: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rfill_sub_5: std_logic; + signal rfill_sub_6: std_logic; + signal co2_5: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rfill_sub_7: std_logic; + signal rfill_sub_8: std_logic; + signal co3_5: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rfill_sub_9: std_logic; + signal rfill_sub_10: std_logic; + signal co4_5: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rfill_sub_11: std_logic; + signal rfill_sub_12: std_logic; + signal co5_5: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rfill_sub_13: std_logic; + signal rfill_sub_14: std_logic; + signal co6_5: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rfill_sub_15: std_logic; + signal rfill_sub_16: std_logic; + signal co7_5: std_logic; + signal rptr_15: std_logic; + signal rfill_sub_msb: std_logic; + signal co8_2d: std_logic; + signal co8_2: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_6: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_6: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_6: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_6: std_logic; + signal wcount_r7: std_logic; + signal wcount_r8: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_6: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_6: std_logic; + signal wcount_r11: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_6: std_logic; + signal wcount_r13: std_logic; + signal wcount_r14: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_6: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_7: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_7: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_7: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_7: std_logic; + signal rcount_w9: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_7: std_logic; + signal rcount_w11: std_logic; + signal rcount_w12: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_7: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w14: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_7: std_logic; + signal rcount_w15: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_14: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal rden_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; + signal co0_8: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; + signal co1_8: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; + signal co2_8: std_logic; + signal rcnt_reg_6: std_logic; + signal rcnt_reg_7: std_logic; + signal co3_8: std_logic; + signal rcnt_reg_8: std_logic; + signal rcnt_reg_9: std_logic; + signal co4_8: std_logic; + signal rcnt_reg_10: std_logic; + signal rcnt_reg_11: std_logic; + signal co5_8: std_logic; + signal rcnt_reg_12: std_logic; + signal rcnt_reg_13: std_logic; + signal co6_8: std_logic; + signal rcnt_reg_14: std_logic; + signal rcnt_reg_15: std_logic; + signal co7_7: std_logic; + signal ae_clrsig: std_logic; + signal ae_setsig: std_logic; + signal ae_d: std_logic; + signal ae_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_9: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_9: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_9: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_9: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal co4_9: std_logic; + signal wcnt_reg_10: std_logic; + signal wcnt_reg_11: std_logic; + signal co5_9: std_logic; + signal wcnt_reg_12: std_logic; + signal wcnt_reg_13: std_logic; + signal co6_9: std_logic; + signal wcnt_reg_14: std_logic; + signal wcnt_reg_15: std_logic; + signal af_d: std_logic; + signal af_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX41 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; SD1: in std_logic; SD2: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; + attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; + attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; + attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; + attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; + attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; + attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; + attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; + attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; + attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is ""; + attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is ""; + attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is ""; + attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is ""; + attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is ""; + attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is ""; + attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is ""; + attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is ""; + attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is ""; + attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is ""; + attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is ""; + attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is ""; + attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is ""; + attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is ""; + attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is ""; + attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is ""; + attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is ""; + attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is ""; + attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is ""; + attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is ""; + attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is ""; + attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_32kx16x8_mb.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is ""; + attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC"; + attribute GSR of FF_236 : label is "ENABLED"; + attribute GSR of FF_235 : label is "ENABLED"; + attribute GSR of FF_234 : label is "ENABLED"; + attribute GSR of FF_233 : label is "ENABLED"; + attribute GSR of FF_232 : label is "ENABLED"; + attribute GSR of FF_231 : label is "ENABLED"; + attribute GSR of FF_230 : label is "ENABLED"; + attribute GSR of FF_229 : label is "ENABLED"; + attribute GSR of FF_228 : label is "ENABLED"; + attribute GSR of FF_227 : label is "ENABLED"; + attribute GSR of FF_226 : label is "ENABLED"; + attribute GSR of FF_225 : label is "ENABLED"; + attribute GSR of FF_224 : label is "ENABLED"; + attribute GSR of FF_223 : label is "ENABLED"; + attribute GSR of FF_222 : label is "ENABLED"; + attribute GSR of FF_221 : label is "ENABLED"; + attribute GSR of FF_220 : label is "ENABLED"; + attribute GSR of FF_219 : label is "ENABLED"; + attribute GSR of FF_218 : label is "ENABLED"; + attribute GSR of FF_217 : label is "ENABLED"; + attribute GSR of FF_216 : label is "ENABLED"; + attribute GSR of FF_215 : label is "ENABLED"; + attribute GSR of FF_214 : label is "ENABLED"; + attribute GSR of FF_213 : label is "ENABLED"; + attribute GSR of FF_212 : label is "ENABLED"; + attribute GSR of FF_211 : label is "ENABLED"; + attribute GSR of FF_210 : label is "ENABLED"; + attribute GSR of FF_209 : label is "ENABLED"; + attribute GSR of FF_208 : label is "ENABLED"; + attribute GSR of FF_207 : label is "ENABLED"; + attribute GSR of FF_206 : label is "ENABLED"; + attribute GSR of FF_205 : label is "ENABLED"; + attribute GSR of FF_204 : label is "ENABLED"; + attribute GSR of FF_203 : label is "ENABLED"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t39: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_2: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t38: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_1: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t37: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t36: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t35: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t34: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t33: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t32: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t31: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t30: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t29: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t28: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t27: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t26: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t25: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t24: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t23: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t22: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t21: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t20: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t19: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t18: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t17: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t16: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t15: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t14: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t13: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t12: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t11: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t10: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t9: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t8: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t7: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t6: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, + DO0=>w_g2b_xor_cluster_0); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_1); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_2); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_3); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r2); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r1); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + XOR2_t5: XOR2 + port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); + + XOR2_t4: XOR2 + port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); + + XOR2_t3: XOR2 + port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); + + XOR2_t2: XOR2 + port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + INV_0: INV + port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); + + AND2_t1: AND2 + port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_1_30: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_2_29: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_3_28: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_4_27: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_5_26: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_6_25: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_7_24: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_1_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_2_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_3_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_4_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_5_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_6_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_7_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_15: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_1_14: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_2_13: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_3_12: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_4_11: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_5_10: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_6_9: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_7_8: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_7: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_1_6: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_2_5: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_3_4: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_4_3: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_5_2: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_6_1: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_7_0: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 2) + port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, + ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, + ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, + ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_236: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_235: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_234: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_233: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_232: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_231: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_230: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_229: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_228: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_227: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_226: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_225: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_224: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_223: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_222: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_221: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_220: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_219: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_218: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_217: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_216: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_215: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_214: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_213: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_212: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_211: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_210: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_209: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_208: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_207: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_206: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_205: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_204: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_203: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_202: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_201: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_200: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_199: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_198: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_197: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_196: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_195: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_194: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_193: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_192: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_191: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_190: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_189: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_188: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_187: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_186: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_185: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_184: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_183: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_182: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_181: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_180: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_179: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_178: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_177: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_176: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_175: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_174: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_173: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_172: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_171: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_170: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_169: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_168: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_167: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_166: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_165: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_164: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_163: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_162: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_161: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_160: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_159: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_158: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_157: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_156: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_155: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_154: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_153: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_152: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_151: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_150: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_149: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_148: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_147: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_146: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_145: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_144: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_143: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_142: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_141: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_140: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_139: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_138: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_137: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_136: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_135: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_134: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_133: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_132: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_131: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_130: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_129: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_128: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_127: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_126: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_125: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_124: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_123: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_122: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_121: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_120: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_119: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_118: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_117: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_116: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_115: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_114: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_113: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_112: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_111: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_110: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_109: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_108: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_107: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_106: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_105: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_104: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_103: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_102: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_101: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_100: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_99: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_98: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_97: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_96: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_95: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_94: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_93: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_92: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_91: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_90: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_89: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_88: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_87: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_86: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_85: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_84: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_83: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_82: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_81: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_80: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_79: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_78: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_77: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_76: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_75: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_74: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_73: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_72: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_71: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_70: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_69: FD1S3DX + port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); + + FF_68: FD1S3DX + port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); + + FF_67: FD1S3DX + port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); + + FF_66: FD1S3DX + port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); + + FF_65: FD1S3DX + port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); + + FF_64: FD1S3DX + port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); + + FF_63: FD1S3DX + port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); + + FF_62: FD1S3DX + port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); + + FF_61: FD1S3DX + port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); + + FF_60: FD1S3DX + port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); + + FF_59: FD1S3DX + port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); + + FF_58: FD1S3DX + port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); + + FF_57: FD1S3DX + port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); + + FF_56: FD1S3DX + port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); + + FF_55: FD1S3DX + port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); + + FF_54: FD1S3DX + port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); + + FF_53: FD1S3DX + port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); + + FF_52: FD1S3DX + port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); + + FF_51: FD1S3DX + port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); + + FF_50: FD1S3DX + port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); + + FF_49: FD1S3DX + port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); + + FF_48: FD1S3DX + port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); + + FF_47: FD1S3DX + port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); + + FF_46: FD1S3DX + port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); + + FF_45: FD1S3DX + port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); + + FF_44: FD1S3DX + port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); + + FF_43: FD1S3DX + port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); + + FF_42: FD1S3DX + port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); + + FF_41: FD1S3DX + port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); + + FF_40: FD1S3DX + port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); + + FF_39: FD1S3DX + port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); + + FF_38: FD1S3DX + port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); + + FF_37: FD1S3DX + port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); + + FF_36: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_35: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_34: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_33: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_32: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_31: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_30: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_29: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_28: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_27: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_26: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_25: FD1S3DX + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_24: FD1S3DX + port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); + + FF_23: FD1S3DX + port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); + + FF_22: FD1S3DX + port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); + + FF_21: FD1S3DX + port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); + + FF_20: FD1S3DX + port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); + + FF_19: FD1S3DX + port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); + + FF_18: FD1S3DX + port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); + + FF_17: FD1S3DX + port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); + + FF_16: FD1S3DX + port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); + + FF_15: FD1S3DX + port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); + + FF_14: FD1S3DX + port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); + + FF_13: FD1S3DX + port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); + + FF_12: FD1S3DX + port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); + + FF_11: FD1S3DX + port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); + + FF_10: FD1S3DX + port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); + + FF_9: FD1S3DX + port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); + + FF_8: FD1S3DX + port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); + + FF_7: FD1S3DX + port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); + + FF_6: FD1S3DX + port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); + + FF_5: FD1S3DX + port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); + + FF_4: FD1S3DX + port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); + + FF_3: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_2: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_1: FD1S3BX + port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>ircount_16, NC1=>open); + + mux_7: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); + + mux_6: MUX41 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); + + mux_5: MUX41 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); + + mux_4: MUX41 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); + + mux_3: MUX41 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); + + mux_2: MUX41 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); + + mux_1: MUX41 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); + + mux_0: MUX41 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); + + wcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, + S1=>wcnt_sub_0); + + wcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, + B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, + S1=>wcnt_sub_2); + + wcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, + B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, + S1=>wcnt_sub_4); + + wcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, + B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, + S1=>wcnt_sub_6); + + wcnt_4: FSUB2B + port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, + B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, + S1=>wcnt_sub_8); + + wcnt_5: FSUB2B + port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, + S1=>wcnt_sub_10); + + wcnt_6: FSUB2B + port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, + S0=>wcnt_sub_11, S1=>wcnt_sub_12); + + wcnt_7: FSUB2B + port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, + B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, + S1=>wcnt_sub_14); + + wcnt_8: FSUB2B + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, + S1=>open); + + rcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, + S1=>rcnt_sub_0); + + rcnt_1: FSUB2B + port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, + B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, + S1=>rcnt_sub_2); + + rcnt_2: FSUB2B + port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, + B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, + S1=>rcnt_sub_4); + + rcnt_3: FSUB2B + port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, + B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, + S1=>rcnt_sub_6); + + rcnt_4: FSUB2B + port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, + B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, + S1=>rcnt_sub_8); + + rcnt_5: FSUB2B + port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, + B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, + S1=>rcnt_sub_10); + + rcnt_6: FSUB2B + port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, + B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, + S1=>rcnt_sub_12); + + rcnt_7: FSUB2B + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, + B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, + S1=>rcnt_sub_14); + + rcnt_8: FSUB2B + port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, + B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, + S1=>rcnt_sub_16); + + rcntd: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, + BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, + BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, + BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, + BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, + S1=>wfill_sub_10); + + wfill_6: FSUB2B + port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, + S0=>wfill_sub_11, S1=>wfill_sub_12); + + wfill_7: FSUB2B + port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, + B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, + S1=>wfill_sub_14); + + wfill_8: FSUB2B + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + rfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, + S1=>rfill_sub_0); + + rfill_1: FSUB2B + port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2, + BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2); + + rfill_2: FSUB2B + port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4, + BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4); + + rfill_3: FSUB2B + port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6, + BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6); + + rfill_4: FSUB2B + port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8, + BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8); + + rfill_5: FSUB2B + port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10, + BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10); + + rfill_6: FSUB2B + port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11, + B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11, + S1=>rfill_sub_12); + + rfill_7: FSUB2B + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13, + B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13, + S1=>rfill_sub_14); + + rfill_8: FSUB2B + port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15, + B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15, + S1=>rfill_sub_16); + + rfilld: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, CI=>co0_6, GE=>co1_6); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, CI=>co1_6, GE=>co2_6); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, CI=>co2_6, GE=>co3_6); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>wcount_r8, CI=>co3_6, GE=>co4_6); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>wcount_r10, CI=>co4_6, GE=>co5_6); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, + B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, + B1=>wcount_r14, CI=>co6_6, GE=>co7_6); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, CI=>co0_7, GE=>co1_7); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, CI=>co1_7, GE=>co2_7); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, CI=>co2_7, GE=>co3_7); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, + B1=>rcount_w10, CI=>co3_7, GE=>co4_7); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, + B1=>rcount_w12, CI=>co4_7, GE=>co5_7); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w14, CI=>co5_7, GE=>co6_7); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, + B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + ae_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + ae_cmp_0: AGEB2 + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8); + + ae_cmp_1: AGEB2 + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8); + + ae_cmp_2: AGEB2 + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8); + + ae_cmp_3: AGEB2 + port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), + B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8); + + ae_cmp_4: AGEB2 + port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), + B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8); + + ae_cmp_5: AGEB2 + port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), + B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8); + + ae_cmp_6: AGEB2 + port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), + B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8); + + ae_cmp_7: AGEB2 + port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), + B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7); + + ae_cmp_8: AGEB2 + port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, + B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); + + af_d_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_d_cmp_0: AGEB2 + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9); + + af_d_cmp_1: AGEB2 + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9); + + af_d_cmp_2: AGEB2 + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9); + + af_d_cmp_3: AGEB2 + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9); + + af_d_cmp_4: AGEB2 + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9); + + af_d_cmp_5: AGEB2 + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9); + + af_d_cmp_6: AGEB2 + port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), + B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9); + + af_d_cmp_7: AGEB2 + port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), + B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_32kx16x8_mb is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX41 use entity ecp3.MUX41(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.lpc b/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.lpc new file mode 100644 index 0000000..4ac80c1 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_32kx16x8_mb2 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:22:54 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=18 +RDepth=65536 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Dynamic - Single Threshold +PeAssert=16 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=32752 +PfDeassert=506 +RDataCount=1 +WDataCount=1 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd b/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd new file mode 100644 index 0000000..fef0b67 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd @@ -0,0 +1,5224 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e + +-- Thu Sep 22 11:22:54 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_32kx16x8_mb2 is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + AmEmptyThresh: in std_logic_vector(15 downto 0); + AmFullThresh: in std_logic_vector(14 downto 0); + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(15 downto 0); + RCNT: out std_logic_vector(16 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_32kx16x8_mb2; + +architecture Structure of fifo_32kx16x8_mb2 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal func_and_inet_13: std_logic; + signal func_and_inet_14: std_logic; + signal func_and_inet_15: std_logic; + signal func_and_inet_16: std_logic; + signal func_and_inet_17: std_logic; + signal func_and_inet_18: std_logic; + signal func_and_inet_19: std_logic; + signal func_and_inet_20: std_logic; + signal func_and_inet_21: std_logic; + signal func_and_inet_22: std_logic; + signal func_and_inet_23: std_logic; + signal func_and_inet_24: std_logic; + signal func_and_inet_25: std_logic; + signal func_and_inet_26: std_logic; + signal func_and_inet_27: std_logic; + signal func_and_inet_28: std_logic; + signal func_and_inet_29: std_logic; + signal wptr_14_inv: std_logic; + signal func_and_inet_30: std_logic; + signal rptr_15_inv: std_logic; + signal func_and_inet_31: std_logic; + signal func_and_inet_32: std_logic; + signal func_and_inet_33: std_logic; + signal func_and_inet_34: std_logic; + signal func_and_inet_35: std_logic; + signal func_and_inet_36: std_logic; + signal func_and_inet_37: std_logic; + signal func_and_inet_38: std_logic; + signal func_and_inet_39: std_logic; + signal func_and_inet_40: std_logic; + signal func_and_inet_41: std_logic; + signal func_and_inet_42: std_logic; + signal func_and_inet_43: std_logic; + signal func_and_inet_44: std_logic; + signal func_and_inet_45: std_logic; + signal wptr_13_inv: std_logic; + signal func_and_inet_46: std_logic; + signal rptr_14_inv: std_logic; + signal func_and_inet_47: std_logic; + signal func_and_inet_48: std_logic; + signal func_and_inet_49: std_logic; + signal func_and_inet_50: std_logic; + signal func_and_inet_51: std_logic; + signal func_and_inet_52: std_logic; + signal func_and_inet_53: std_logic; + signal wptr_12_inv: std_logic; + signal func_and_inet_54: std_logic; + signal rptr_13_inv: std_logic; + signal func_and_inet_55: std_logic; + signal func_and_inet_56: std_logic; + signal func_and_inet_57: std_logic; + signal wptr_11_inv: std_logic; + signal func_and_inet_58: std_logic; + signal rptr_12_inv: std_logic; + signal func_and_inet_59: std_logic; + signal wptr_10_inv: std_logic; + signal func_and_inet_60: std_logic; + signal rptr_11_inv: std_logic; + signal func_and_inet_61: std_logic; + signal func_and_inet_62: std_logic; + signal func_and_inet_63: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal rcount_w0: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal rcnt_reg_15_inv: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r11: std_logic; + signal dec2_p01: std_logic; + signal dec5_r12: std_logic; + signal dec4_p02: std_logic; + signal dec7_r13: std_logic; + signal dec6_p03: std_logic; + signal dec9_r14: std_logic; + signal dec8_p04: std_logic; + signal dec11_r15: std_logic; + signal dec10_p05: std_logic; + signal dec13_r16: std_logic; + signal dec12_p06: std_logic; + signal dec15_r17: std_logic; + signal dec14_p07: std_logic; + signal dec17_r18: std_logic; + signal dec16_p08: std_logic; + signal dec19_r19: std_logic; + signal dec18_p09: std_logic; + signal dec21_r110: std_logic; + signal dec20_p010: std_logic; + signal dec23_r111: std_logic; + signal dec22_p011: std_logic; + signal dec25_r112: std_logic; + signal dec24_p012: std_logic; + signal dec27_r113: std_logic; + signal dec26_p013: std_logic; + signal dec29_r114: std_logic; + signal dec28_p014: std_logic; + signal dec31_r115: std_logic; + signal dec30_p015: std_logic; + signal dec33_r116: std_logic; + signal dec32_p016: std_logic; + signal dec35_r117: std_logic; + signal dec34_p017: std_logic; + signal dec37_r118: std_logic; + signal dec36_p018: std_logic; + signal dec39_r119: std_logic; + signal dec38_p019: std_logic; + signal dec41_r120: std_logic; + signal dec40_p020: std_logic; + signal dec43_r121: std_logic; + signal dec42_p021: std_logic; + signal dec45_r122: std_logic; + signal dec44_p022: std_logic; + signal dec47_r123: std_logic; + signal dec46_p023: std_logic; + signal dec49_r124: std_logic; + signal dec48_p024: std_logic; + signal dec51_r125: std_logic; + signal dec50_p025: std_logic; + signal dec53_r126: std_logic; + signal dec52_p026: std_logic; + signal dec55_r127: std_logic; + signal dec54_p027: std_logic; + signal dec57_r128: std_logic; + signal dec56_p028: std_logic; + signal dec59_r129: std_logic; + signal dec58_p029: std_logic; + signal dec61_r130: std_logic; + signal dec60_p030: std_logic; + signal dec63_r131: std_logic; + signal dec62_p031: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal wptr_15: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_16: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal rcnt_reg_16: std_logic; + signal empty_i: std_logic; + signal full_i: std_logic; + signal rRst: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co7: std_logic; + signal wcount_15: std_logic; + signal co6: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8: std_logic; + signal rcount_16: std_logic; + signal co7_1: std_logic; + signal mdout1_31_0: std_logic; + signal mdout1_30_0: std_logic; + signal mdout1_29_0: std_logic; + signal mdout1_28_0: std_logic; + signal mdout1_27_0: std_logic; + signal mdout1_26_0: std_logic; + signal mdout1_25_0: std_logic; + signal mdout1_24_0: std_logic; + signal mdout1_23_0: std_logic; + signal mdout1_22_0: std_logic; + signal mdout1_21_0: std_logic; + signal mdout1_20_0: std_logic; + signal mdout1_19_0: std_logic; + signal mdout1_18_0: std_logic; + signal mdout1_17_0: std_logic; + signal mdout1_16_0: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_31_1: std_logic; + signal mdout1_30_1: std_logic; + signal mdout1_29_1: std_logic; + signal mdout1_28_1: std_logic; + signal mdout1_27_1: std_logic; + signal mdout1_26_1: std_logic; + signal mdout1_25_1: std_logic; + signal mdout1_24_1: std_logic; + signal mdout1_23_1: std_logic; + signal mdout1_22_1: std_logic; + signal mdout1_21_1: std_logic; + signal mdout1_20_1: std_logic; + signal mdout1_19_1: std_logic; + signal mdout1_18_1: std_logic; + signal mdout1_17_1: std_logic; + signal mdout1_16_1: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_31_2: std_logic; + signal mdout1_30_2: std_logic; + signal mdout1_29_2: std_logic; + signal mdout1_28_2: std_logic; + signal mdout1_27_2: std_logic; + signal mdout1_26_2: std_logic; + signal mdout1_25_2: std_logic; + signal mdout1_24_2: std_logic; + signal mdout1_23_2: std_logic; + signal mdout1_22_2: std_logic; + signal mdout1_21_2: std_logic; + signal mdout1_20_2: std_logic; + signal mdout1_19_2: std_logic; + signal mdout1_18_2: std_logic; + signal mdout1_17_2: std_logic; + signal mdout1_16_2: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_31_3: std_logic; + signal mdout1_30_3: std_logic; + signal mdout1_29_3: std_logic; + signal mdout1_28_3: std_logic; + signal mdout1_27_3: std_logic; + signal mdout1_26_3: std_logic; + signal mdout1_25_3: std_logic; + signal mdout1_24_3: std_logic; + signal mdout1_23_3: std_logic; + signal mdout1_22_3: std_logic; + signal mdout1_21_3: std_logic; + signal mdout1_20_3: std_logic; + signal mdout1_19_3: std_logic; + signal mdout1_18_3: std_logic; + signal mdout1_17_3: std_logic; + signal mdout1_16_3: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_31_4: std_logic; + signal mdout1_30_4: std_logic; + signal mdout1_29_4: std_logic; + signal mdout1_28_4: std_logic; + signal mdout1_27_4: std_logic; + signal mdout1_26_4: std_logic; + signal mdout1_25_4: std_logic; + signal mdout1_24_4: std_logic; + signal mdout1_23_4: std_logic; + signal mdout1_22_4: std_logic; + signal mdout1_21_4: std_logic; + signal mdout1_20_4: std_logic; + signal mdout1_19_4: std_logic; + signal mdout1_18_4: std_logic; + signal mdout1_17_4: std_logic; + signal mdout1_16_4: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_31_5: std_logic; + signal mdout1_30_5: std_logic; + signal mdout1_29_5: std_logic; + signal mdout1_28_5: std_logic; + signal mdout1_27_5: std_logic; + signal mdout1_26_5: std_logic; + signal mdout1_25_5: std_logic; + signal mdout1_24_5: std_logic; + signal mdout1_23_5: std_logic; + signal mdout1_22_5: std_logic; + signal mdout1_21_5: std_logic; + signal mdout1_20_5: std_logic; + signal mdout1_19_5: std_logic; + signal mdout1_18_5: std_logic; + signal mdout1_17_5: std_logic; + signal mdout1_16_5: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_31_6: std_logic; + signal mdout1_30_6: std_logic; + signal mdout1_29_6: std_logic; + signal mdout1_28_6: std_logic; + signal mdout1_27_6: std_logic; + signal mdout1_26_6: std_logic; + signal mdout1_25_6: std_logic; + signal mdout1_24_6: std_logic; + signal mdout1_23_6: std_logic; + signal mdout1_22_6: std_logic; + signal mdout1_21_6: std_logic; + signal mdout1_20_6: std_logic; + signal mdout1_19_6: std_logic; + signal mdout1_18_6: std_logic; + signal mdout1_17_6: std_logic; + signal mdout1_16_6: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_31_7: std_logic; + signal mdout1_30_7: std_logic; + signal mdout1_29_7: std_logic; + signal mdout1_28_7: std_logic; + signal mdout1_27_7: std_logic; + signal mdout1_26_7: std_logic; + signal mdout1_25_7: std_logic; + signal mdout1_24_7: std_logic; + signal mdout1_23_7: std_logic; + signal mdout1_22_7: std_logic; + signal mdout1_21_7: std_logic; + signal mdout1_20_7: std_logic; + signal mdout1_19_7: std_logic; + signal mdout1_18_7: std_logic; + signal mdout1_17_7: std_logic; + signal mdout1_16_7: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_31_8: std_logic; + signal mdout1_30_8: std_logic; + signal mdout1_29_8: std_logic; + signal mdout1_28_8: std_logic; + signal mdout1_27_8: std_logic; + signal mdout1_26_8: std_logic; + signal mdout1_25_8: std_logic; + signal mdout1_24_8: std_logic; + signal mdout1_23_8: std_logic; + signal mdout1_22_8: std_logic; + signal mdout1_21_8: std_logic; + signal mdout1_20_8: std_logic; + signal mdout1_19_8: std_logic; + signal mdout1_18_8: std_logic; + signal mdout1_17_8: std_logic; + signal mdout1_16_8: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal wcnt_sub_0: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal co0_2: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal co1_2: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal co2_2: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal co3_2: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_10: std_logic; + signal co4_2: std_logic; + signal wcnt_sub_11: std_logic; + signal wcnt_sub_12: std_logic; + signal co5_2: std_logic; + signal wcnt_sub_13: std_logic; + signal wcnt_sub_14: std_logic; + signal co6_2: std_logic; + signal wcnt_sub_15: std_logic; + signal co7_2: std_logic; + signal wcnt_sub_msb: std_logic; + signal rcnt_sub_0: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; + signal co0_3: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; + signal co1_3: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; + signal co2_3: std_logic; + signal rcnt_sub_7: std_logic; + signal rcnt_sub_8: std_logic; + signal co3_3: std_logic; + signal rcnt_sub_9: std_logic; + signal rcnt_sub_10: std_logic; + signal co4_3: std_logic; + signal rcnt_sub_11: std_logic; + signal rcnt_sub_12: std_logic; + signal co5_3: std_logic; + signal rcnt_sub_13: std_logic; + signal rcnt_sub_14: std_logic; + signal co6_3: std_logic; + signal rcnt_sub_15: std_logic; + signal rcnt_sub_16: std_logic; + signal co7_3: std_logic; + signal rcnt_sub_msb: std_logic; + signal co8_1d: std_logic; + signal co8_1: std_logic; + signal wfill_sub_0: std_logic; + signal wptr_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_4: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_4: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_4: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_4: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_11: std_logic; + signal wfill_sub_12: std_logic; + signal co5_4: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wfill_sub_13: std_logic; + signal wfill_sub_14: std_logic; + signal co6_4: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wfill_sub_15: std_logic; + signal co7_4: std_logic; + signal wfill_sub_msb: std_logic; + signal rfill_sub_0: std_logic; + signal rptr_0: std_logic; + signal scuba_vhi: std_logic; + signal rfill_sub_1: std_logic; + signal rfill_sub_2: std_logic; + signal co0_5: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rfill_sub_3: std_logic; + signal rfill_sub_4: std_logic; + signal co1_5: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rfill_sub_5: std_logic; + signal rfill_sub_6: std_logic; + signal co2_5: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rfill_sub_7: std_logic; + signal rfill_sub_8: std_logic; + signal co3_5: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rfill_sub_9: std_logic; + signal rfill_sub_10: std_logic; + signal co4_5: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rfill_sub_11: std_logic; + signal rfill_sub_12: std_logic; + signal co5_5: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rfill_sub_13: std_logic; + signal rfill_sub_14: std_logic; + signal co6_5: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rfill_sub_15: std_logic; + signal rfill_sub_16: std_logic; + signal co7_5: std_logic; + signal rptr_15: std_logic; + signal rfill_sub_msb: std_logic; + signal co8_2d: std_logic; + signal co8_2: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_6: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_6: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_6: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_6: std_logic; + signal wcount_r7: std_logic; + signal wcount_r8: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_6: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_6: std_logic; + signal wcount_r11: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_6: std_logic; + signal wcount_r13: std_logic; + signal wcount_r14: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_6: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_7: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_7: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_7: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_7: std_logic; + signal rcount_w9: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_7: std_logic; + signal rcount_w11: std_logic; + signal rcount_w12: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_7: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w14: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_7: std_logic; + signal rcount_w15: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_14: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal rden_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; + signal co0_8: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; + signal co1_8: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; + signal co2_8: std_logic; + signal rcnt_reg_6: std_logic; + signal rcnt_reg_7: std_logic; + signal co3_8: std_logic; + signal rcnt_reg_8: std_logic; + signal rcnt_reg_9: std_logic; + signal co4_8: std_logic; + signal rcnt_reg_10: std_logic; + signal rcnt_reg_11: std_logic; + signal co5_8: std_logic; + signal rcnt_reg_12: std_logic; + signal rcnt_reg_13: std_logic; + signal co6_8: std_logic; + signal rcnt_reg_14: std_logic; + signal rcnt_reg_15: std_logic; + signal co7_7: std_logic; + signal ae_clrsig: std_logic; + signal ae_setsig: std_logic; + signal ae_d: std_logic; + signal ae_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_9: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_9: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_9: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_9: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal co4_9: std_logic; + signal wcnt_reg_10: std_logic; + signal wcnt_reg_11: std_logic; + signal co5_9: std_logic; + signal wcnt_reg_12: std_logic; + signal wcnt_reg_13: std_logic; + signal co6_9: std_logic; + signal wcnt_reg_14: std_logic; + signal wcnt_reg_15: std_logic; + signal af_d: std_logic; + signal af_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX321 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; D16: in std_logic; D17: in std_logic; + D18: in std_logic; D19: in std_logic; D20: in std_logic; + D21: in std_logic; D22: in std_logic; D23: in std_logic; + D24: in std_logic; D25: in std_logic; D26: in std_logic; + D27: in std_logic; D28: in std_logic; D29: in std_logic; + D30: in std_logic; D31: in std_logic; SD1: in std_logic; + SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; + SD5: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; + attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; + attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; + attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; + attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; + attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; + attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; + attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; + attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; + attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; + attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; + attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; + attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; + attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; + attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; + attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; + attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; + attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; + attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; + attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; + attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; + attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; + attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; + attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; + attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; + attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; + attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; + attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; + attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; + attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; + attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_32kx16x8_mb2.lpc"; + attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; + attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; + attribute GSR of FF_239 : label is "ENABLED"; + attribute GSR of FF_238 : label is "ENABLED"; + attribute GSR of FF_237 : label is "ENABLED"; + attribute GSR of FF_236 : label is "ENABLED"; + attribute GSR of FF_235 : label is "ENABLED"; + attribute GSR of FF_234 : label is "ENABLED"; + attribute GSR of FF_233 : label is "ENABLED"; + attribute GSR of FF_232 : label is "ENABLED"; + attribute GSR of FF_231 : label is "ENABLED"; + attribute GSR of FF_230 : label is "ENABLED"; + attribute GSR of FF_229 : label is "ENABLED"; + attribute GSR of FF_228 : label is "ENABLED"; + attribute GSR of FF_227 : label is "ENABLED"; + attribute GSR of FF_226 : label is "ENABLED"; + attribute GSR of FF_225 : label is "ENABLED"; + attribute GSR of FF_224 : label is "ENABLED"; + attribute GSR of FF_223 : label is "ENABLED"; + attribute GSR of FF_222 : label is "ENABLED"; + attribute GSR of FF_221 : label is "ENABLED"; + attribute GSR of FF_220 : label is "ENABLED"; + attribute GSR of FF_219 : label is "ENABLED"; + attribute GSR of FF_218 : label is "ENABLED"; + attribute GSR of FF_217 : label is "ENABLED"; + attribute GSR of FF_216 : label is "ENABLED"; + attribute GSR of FF_215 : label is "ENABLED"; + attribute GSR of FF_214 : label is "ENABLED"; + attribute GSR of FF_213 : label is "ENABLED"; + attribute GSR of FF_212 : label is "ENABLED"; + attribute GSR of FF_211 : label is "ENABLED"; + attribute GSR of FF_210 : label is "ENABLED"; + attribute GSR of FF_209 : label is "ENABLED"; + attribute GSR of FF_208 : label is "ENABLED"; + attribute GSR of FF_207 : label is "ENABLED"; + attribute GSR of FF_206 : label is "ENABLED"; + attribute GSR of FF_205 : label is "ENABLED"; + attribute GSR of FF_204 : label is "ENABLED"; + attribute GSR of FF_203 : label is "ENABLED"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t39: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_12: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t38: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_11: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t37: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t36: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t35: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t34: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t33: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t32: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t31: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t30: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t29: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t28: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t27: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t26: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t25: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t24: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t23: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t22: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t21: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t20: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t19: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t18: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t17: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t16: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t15: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t14: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t13: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t12: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t11: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t10: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t9: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t8: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t7: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t6: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + INV_10: INV + port map (A=>wptr_10, Z=>wptr_10_inv); + + INV_9: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_8: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_7: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_6: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + LUT4_180: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet); + + LUT4_179: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_p00); + + INV_5: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_4: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_3: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_2: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + INV_1: INV + port map (A=>rptr_15, Z=>rptr_15_inv); + + LUT4_178: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_1); + + LUT4_177: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec1_r10); + + LUT4_176: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_2); + + LUT4_175: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec2_p01); + + LUT4_174: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_3); + + LUT4_173: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec3_r11); + + LUT4_172: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_4); + + LUT4_171: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec4_p02); + + LUT4_170: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_5); + + LUT4_169: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec5_r12); + + LUT4_168: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_6); + + LUT4_167: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec6_p03); + + LUT4_166: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_7); + + LUT4_165: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec7_r13); + + LUT4_164: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_8); + + LUT4_163: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec8_p04); + + LUT4_162: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_9); + + LUT4_161: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec9_r14); + + LUT4_160: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_10); + + LUT4_159: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); + + LUT4_158: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_11); + + LUT4_157: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); + + LUT4_156: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_12); + + LUT4_155: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); + + LUT4_154: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_13); + + LUT4_153: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); + + LUT4_152: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_14); + + LUT4_151: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); + + LUT4_150: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_15); + + LUT4_149: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); + + LUT4_148: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_16); + + LUT4_147: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); + + LUT4_146: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_17); + + LUT4_145: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); + + LUT4_144: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_18); + + LUT4_143: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); + + LUT4_142: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_19); + + LUT4_141: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); + + LUT4_140: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_20); + + LUT4_139: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); + + LUT4_138: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_21); + + LUT4_137: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); + + LUT4_136: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_22); + + LUT4_135: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); + + LUT4_134: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_23); + + LUT4_133: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); + + LUT4_132: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_24); + + LUT4_131: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); + + LUT4_130: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_25); + + LUT4_129: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); + + LUT4_128: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_26); + + LUT4_127: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); + + LUT4_126: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_27); + + LUT4_125: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); + + LUT4_124: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_28); + + LUT4_123: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); + + LUT4_122: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_29); + + LUT4_121: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); + + LUT4_120: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_30); + + LUT4_119: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); + + LUT4_118: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_31); + + LUT4_117: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); + + LUT4_116: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_32); + + LUT4_115: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec32_p016); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_33); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec33_r116); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_34); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec34_p017); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_35); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec35_r117); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_36); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec36_p018); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_37); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec37_r118); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_38); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec38_p019); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_39); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec39_r119); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_40); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec40_p020); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_41); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec41_r120); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_42); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec42_p021); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_43); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec43_r121); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_44); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec44_p022); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_45); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec45_r122); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_46); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec46_p023); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_47); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec47_r123); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_48); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec48_p024); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_49); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec49_r124); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_50); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec50_p025); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_51); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec51_r125); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_52); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec52_p026); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_53); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec53_r126); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_54); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec54_p027); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_55); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec55_r127); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_56); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec56_p028); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_57); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec57_r128); + + LUT4_64: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_58); + + LUT4_63: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec58_p029); + + LUT4_62: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_59); + + LUT4_61: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec59_r129); + + LUT4_60: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_60); + + LUT4_59: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec60_p030); + + LUT4_58: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_61); + + LUT4_57: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec61_r130); + + LUT4_56: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_62); + + LUT4_55: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec62_p031); + + LUT4_54: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_63); + + LUT4_53: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec63_r131); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, + DO0=>w_g2b_xor_cluster_0); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_1); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_2); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_3); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r2); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r1); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + XOR2_t5: XOR2 + port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); + + XOR2_t4: XOR2 + port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); + + XOR2_t3: XOR2 + port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); + + XOR2_t2: XOR2 + port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + INV_0: INV + port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); + + AND2_t1: AND2 + port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, + DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, + DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, + DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_11_0_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, + DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, + DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, + DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_12_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, + DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, + DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, + DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_13_0_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1, + DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4, + DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7, + DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_14_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1, + DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4, + DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7, + DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_15_0_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1, + DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4, + DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7, + DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_16_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1, + DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4, + DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7, + DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_17_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1, + DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4, + DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7, + DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_18_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1, + DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4, + DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7, + DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_19_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1, + DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4, + DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7, + DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_20_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1, + DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4, + DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7, + DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_21_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1, + DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4, + DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7, + DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_22_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1, + DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4, + DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7, + DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_23_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1, + DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4, + DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7, + DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_24_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1, + DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4, + DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7, + DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_25_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1, + DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4, + DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7, + DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_26_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1, + DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4, + DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7, + DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_27_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1, + DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4, + DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7, + DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_28_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1, + DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4, + DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7, + DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_29_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1, + DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4, + DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7, + DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_30_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1, + DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4, + DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7, + DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_31_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1, + DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4, + DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7, + DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_239: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_238: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_237: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_236: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_235: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_234: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_233: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_232: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_231: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_230: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_229: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_228: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_227: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_226: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_225: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_224: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_223: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_222: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_221: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_220: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_219: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_218: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_217: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_216: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_215: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_214: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_213: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_212: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_211: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_210: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_209: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_208: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_207: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_206: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_205: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_204: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_203: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_202: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_201: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_200: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_199: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_198: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_197: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_196: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_195: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_194: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_193: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_192: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_191: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_190: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_189: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_188: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_187: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_186: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_185: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_184: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_183: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_182: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_181: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_180: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_179: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_178: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_177: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_176: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_175: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_174: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_173: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_172: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_171: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_170: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_169: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_168: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_167: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_166: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_165: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_164: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_163: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_162: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_161: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_160: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_159: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_158: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_157: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_156: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_155: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_154: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_153: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_152: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_151: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_150: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_149: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_148: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_147: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_146: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_145: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_144: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_143: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_142: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_141: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_140: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_139: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_138: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_137: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_136: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_135: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_134: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_133: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_132: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_131: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_130: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_129: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_128: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_127: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_126: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_125: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_124: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_123: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_122: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_121: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_120: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_119: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_118: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_117: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_116: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_115: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_114: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_113: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_112: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_111: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_110: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_109: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_108: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_107: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_106: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_105: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_104: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_103: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_102: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_101: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_100: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_99: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_98: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_97: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_96: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_95: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_94: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_93: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_92: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_91: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_90: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_89: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_88: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_87: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_86: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_85: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_84: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_83: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_82: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_81: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_80: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_79: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_78: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_77: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_76: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_75: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_74: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_73: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_72: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_71: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_70: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_69: FD1S3DX + port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); + + FF_68: FD1S3DX + port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); + + FF_67: FD1S3DX + port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); + + FF_66: FD1S3DX + port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); + + FF_65: FD1S3DX + port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); + + FF_64: FD1S3DX + port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); + + FF_63: FD1S3DX + port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); + + FF_62: FD1S3DX + port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); + + FF_61: FD1S3DX + port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); + + FF_60: FD1S3DX + port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); + + FF_59: FD1S3DX + port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); + + FF_58: FD1S3DX + port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); + + FF_57: FD1S3DX + port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); + + FF_56: FD1S3DX + port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); + + FF_55: FD1S3DX + port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); + + FF_54: FD1S3DX + port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); + + FF_53: FD1S3DX + port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); + + FF_52: FD1S3DX + port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); + + FF_51: FD1S3DX + port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); + + FF_50: FD1S3DX + port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); + + FF_49: FD1S3DX + port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); + + FF_48: FD1S3DX + port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); + + FF_47: FD1S3DX + port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); + + FF_46: FD1S3DX + port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); + + FF_45: FD1S3DX + port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); + + FF_44: FD1S3DX + port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); + + FF_43: FD1S3DX + port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); + + FF_42: FD1S3DX + port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); + + FF_41: FD1S3DX + port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); + + FF_40: FD1S3DX + port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); + + FF_39: FD1S3DX + port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); + + FF_38: FD1S3DX + port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); + + FF_37: FD1S3DX + port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); + + FF_36: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_35: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_34: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_33: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_32: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_31: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_30: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_29: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_28: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_27: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_26: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_25: FD1S3DX + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_24: FD1S3DX + port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); + + FF_23: FD1S3DX + port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); + + FF_22: FD1S3DX + port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); + + FF_21: FD1S3DX + port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); + + FF_20: FD1S3DX + port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); + + FF_19: FD1S3DX + port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); + + FF_18: FD1S3DX + port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); + + FF_17: FD1S3DX + port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); + + FF_16: FD1S3DX + port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); + + FF_15: FD1S3DX + port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); + + FF_14: FD1S3DX + port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); + + FF_13: FD1S3DX + port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); + + FF_12: FD1S3DX + port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); + + FF_11: FD1S3DX + port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); + + FF_10: FD1S3DX + port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); + + FF_9: FD1S3DX + port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); + + FF_8: FD1S3DX + port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); + + FF_7: FD1S3DX + port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); + + FF_6: FD1S3DX + port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); + + FF_5: FD1S3DX + port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); + + FF_4: FD1S3DX + port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); + + FF_3: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_2: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_1: FD1S3BX + port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>ircount_16, NC1=>open); + + mux_8: MUX321 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, + D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, + D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, + D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, + D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, + D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(0)); + + mux_7: MUX321 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, + D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, + D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, + D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, + D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, + D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(1)); + + mux_6: MUX321 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, + D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, + D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, + D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, + D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, + D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(2)); + + mux_5: MUX321 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, + D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, + D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, + D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, + D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, + D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(3)); + + mux_4: MUX321 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, + D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, + D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, + D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, + D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, + D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(4)); + + mux_3: MUX321 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, + D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, + D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, + D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, + D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, + D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(5)); + + mux_2: MUX321 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, + D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, + D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, + D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, + D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, + D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(6)); + + mux_1: MUX321 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, + D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, + D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, + D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, + D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, + D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(7)); + + mux_0: MUX321 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, + D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, + D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, + D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, + D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, + D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(8)); + + wcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, + S1=>wcnt_sub_0); + + wcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, + B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, + S1=>wcnt_sub_2); + + wcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, + B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, + S1=>wcnt_sub_4); + + wcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, + B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, + S1=>wcnt_sub_6); + + wcnt_4: FSUB2B + port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, + B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, + S1=>wcnt_sub_8); + + wcnt_5: FSUB2B + port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, + S1=>wcnt_sub_10); + + wcnt_6: FSUB2B + port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, + S0=>wcnt_sub_11, S1=>wcnt_sub_12); + + wcnt_7: FSUB2B + port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, + B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, + S1=>wcnt_sub_14); + + wcnt_8: FSUB2B + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, + S1=>open); + + rcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, + S1=>rcnt_sub_0); + + rcnt_1: FSUB2B + port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, + B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, + S1=>rcnt_sub_2); + + rcnt_2: FSUB2B + port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, + B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, + S1=>rcnt_sub_4); + + rcnt_3: FSUB2B + port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, + B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, + S1=>rcnt_sub_6); + + rcnt_4: FSUB2B + port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, + B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, + S1=>rcnt_sub_8); + + rcnt_5: FSUB2B + port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, + B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, + S1=>rcnt_sub_10); + + rcnt_6: FSUB2B + port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, + B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, + S1=>rcnt_sub_12); + + rcnt_7: FSUB2B + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, + B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, + S1=>rcnt_sub_14); + + rcnt_8: FSUB2B + port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, + B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, + S1=>rcnt_sub_16); + + rcntd: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, + BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, + BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, + BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, + BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, + S1=>wfill_sub_10); + + wfill_6: FSUB2B + port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, + S0=>wfill_sub_11, S1=>wfill_sub_12); + + wfill_7: FSUB2B + port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, + B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, + S1=>wfill_sub_14); + + wfill_8: FSUB2B + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + rfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, + S1=>rfill_sub_0); + + rfill_1: FSUB2B + port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2, + BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2); + + rfill_2: FSUB2B + port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4, + BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4); + + rfill_3: FSUB2B + port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6, + BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6); + + rfill_4: FSUB2B + port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8, + BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8); + + rfill_5: FSUB2B + port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10, + BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10); + + rfill_6: FSUB2B + port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11, + B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11, + S1=>rfill_sub_12); + + rfill_7: FSUB2B + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13, + B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13, + S1=>rfill_sub_14); + + rfill_8: FSUB2B + port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15, + B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15, + S1=>rfill_sub_16); + + rfilld: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, CI=>co0_6, GE=>co1_6); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, CI=>co1_6, GE=>co2_6); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, CI=>co2_6, GE=>co3_6); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>wcount_r8, CI=>co3_6, GE=>co4_6); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>wcount_r10, CI=>co4_6, GE=>co5_6); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, + B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, + B1=>wcount_r14, CI=>co6_6, GE=>co7_6); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, CI=>co0_7, GE=>co1_7); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, CI=>co1_7, GE=>co2_7); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, CI=>co2_7, GE=>co3_7); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, + B1=>rcount_w10, CI=>co3_7, GE=>co4_7); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, + B1=>rcount_w12, CI=>co4_7, GE=>co5_7); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w14, CI=>co5_7, GE=>co6_7); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, + B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + ae_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + ae_cmp_0: AGEB2 + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8); + + ae_cmp_1: AGEB2 + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8); + + ae_cmp_2: AGEB2 + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8); + + ae_cmp_3: AGEB2 + port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), + B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8); + + ae_cmp_4: AGEB2 + port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), + B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8); + + ae_cmp_5: AGEB2 + port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), + B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8); + + ae_cmp_6: AGEB2 + port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), + B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8); + + ae_cmp_7: AGEB2 + port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), + B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7); + + ae_cmp_8: AGEB2 + port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, + B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); + + af_d_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_d_cmp_0: AGEB2 + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9); + + af_d_cmp_1: AGEB2 + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9); + + af_d_cmp_2: AGEB2 + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9); + + af_d_cmp_3: AGEB2 + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9); + + af_d_cmp_4: AGEB2 + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9); + + af_d_cmp_5: AGEB2 + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9); + + af_d_cmp_6: AGEB2 + port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), + B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9); + + af_d_cmp_7: AGEB2 + port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), + B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_32kx16x8_mb2 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX321 use entity ecp3.MUX321(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_32kx9_flags.vhd b/gbe_trb/ipcores/ecp3/fifo_32kx9_flags.vhd new file mode 100644 index 0000000..cdfbc7a --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_32kx9_flags.vhd @@ -0,0 +1,3400 @@ +-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99) +-- Module Version: 5.5 +--/home/soft/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx9_flags -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 9 -depth 32768 -rdata_width 9 -no_enable -pe -1 -pf 30000 -pf2 29990 -e + +-- Wed Nov 6 19:54:22 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_32kx9_flags is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_32kx9_flags; + +architecture Structure of fifo_32kx9_flags is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal wptr_14_inv: std_logic; + signal rptr_14_inv: std_logic; + signal wptr_13_inv: std_logic; + signal rptr_13_inv: std_logic; + signal wptr_12_inv: std_logic; + signal rptr_12_inv: std_logic; + signal wptr_11_inv: std_logic; + signal rptr_11_inv: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r11: std_logic; + signal dec2_p01: std_logic; + signal dec5_r12: std_logic; + signal dec4_p02: std_logic; + signal dec7_r13: std_logic; + signal dec6_p03: std_logic; + signal dec9_r14: std_logic; + signal dec8_p04: std_logic; + signal dec11_r15: std_logic; + signal dec10_p05: std_logic; + signal dec13_r16: std_logic; + signal dec12_p06: std_logic; + signal dec15_r17: std_logic; + signal dec14_p07: std_logic; + signal dec17_r18: std_logic; + signal dec16_p08: std_logic; + signal dec19_r19: std_logic; + signal dec18_p09: std_logic; + signal dec21_r110: std_logic; + signal dec20_p010: std_logic; + signal dec23_r111: std_logic; + signal dec22_p011: std_logic; + signal dec25_r112: std_logic; + signal dec24_p012: std_logic; + signal dec27_r113: std_logic; + signal dec26_p013: std_logic; + signal dec29_r114: std_logic; + signal dec28_p014: std_logic; + signal dec31_r115: std_logic; + signal dec30_p015: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wptr_15: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_15: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal af: std_logic; + signal af_d: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co7: std_logic; + signal co6: std_logic; + signal wcount_15: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co7_1: std_logic; + signal co6_1: std_logic; + signal rcount_15: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_14_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r13: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_2: std_logic; + signal wcount_r14: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_14: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_3: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_14: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co1_4: std_logic; + signal iaf_setcount_6: std_logic; + signal iaf_setcount_7: std_logic; + signal co2_4: std_logic; + signal iaf_setcount_8: std_logic; + signal iaf_setcount_9: std_logic; + signal co3_4: std_logic; + signal iaf_setcount_10: std_logic; + signal iaf_setcount_11: std_logic; + signal co4_4: std_logic; + signal iaf_setcount_12: std_logic; + signal iaf_setcount_13: std_logic; + signal co5_4: std_logic; + signal iaf_setcount_14: std_logic; + signal iaf_setcount_15: std_logic; + signal co7_2: std_logic; + signal co6_4: std_logic; + signal af_setcount_15: std_logic; + signal cmp_ci_2: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal af_setcount_4: std_logic; + signal af_setcount_5: std_logic; + signal co2_5: std_logic; + signal af_setcount_6: std_logic; + signal af_setcount_7: std_logic; + signal co3_5: std_logic; + signal af_setcount_8: std_logic; + signal af_setcount_9: std_logic; + signal co4_5: std_logic; + signal af_setcount_10: std_logic; + signal af_setcount_11: std_logic; + signal co5_5: std_logic; + signal af_setcount_12: std_logic; + signal af_setcount_13: std_logic; + signal co6_5: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_setcount_14: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_clrcount_0: std_logic; + signal iaf_clrcount_1: std_logic; + signal af_clr_ctr_ci: std_logic; + signal iaf_clrcount_2: std_logic; + signal iaf_clrcount_3: std_logic; + signal co0_6: std_logic; + signal iaf_clrcount_4: std_logic; + signal iaf_clrcount_5: std_logic; + signal co1_6: std_logic; + signal iaf_clrcount_6: std_logic; + signal iaf_clrcount_7: std_logic; + signal co2_6: std_logic; + signal iaf_clrcount_8: std_logic; + signal iaf_clrcount_9: std_logic; + signal co3_6: std_logic; + signal iaf_clrcount_10: std_logic; + signal iaf_clrcount_11: std_logic; + signal co4_6: std_logic; + signal iaf_clrcount_12: std_logic; + signal iaf_clrcount_13: std_logic; + signal co5_6: std_logic; + signal iaf_clrcount_14: std_logic; + signal iaf_clrcount_15: std_logic; + signal co7_3: std_logic; + signal co6_6: std_logic; + signal af_clrcount_15: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_clrcount_0: std_logic; + signal af_clrcount_1: std_logic; + signal co0_7: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_clrcount_2: std_logic; + signal af_clrcount_3: std_logic; + signal co1_7: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal af_clrcount_4: std_logic; + signal af_clrcount_5: std_logic; + signal co2_7: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal af_clrcount_6: std_logic; + signal af_clrcount_7: std_logic; + signal co3_7: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal af_clrcount_8: std_logic; + signal af_clrcount_9: std_logic; + signal co4_7: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal af_clrcount_10: std_logic; + signal af_clrcount_11: std_logic; + signal co5_7: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w13: std_logic; + signal af_clrcount_12: std_logic; + signal af_clrcount_13: std_logic; + signal co6_7: std_logic; + signal rcount_w14: std_logic; + signal af_clr_cmp_clr: std_logic; + signal af_clrcount_14: std_logic; + signal af_clr_cmp_set: std_logic; + signal af_clr: std_logic; + signal af_clr_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX161 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; SD1: in std_logic; SD2: in std_logic; + SD3: in std_logic; SD4: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_15 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_15 : label is ""; + attribute RESETMODE of pdp_ram_0_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_14 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_14 : label is ""; + attribute RESETMODE of pdp_ram_1_0_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_13 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_13 : label is ""; + attribute RESETMODE of pdp_ram_2_0_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_12 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_12 : label is ""; + attribute RESETMODE of pdp_ram_3_0_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_0_11 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_11 : label is ""; + attribute RESETMODE of pdp_ram_4_0_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_0_10 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_10 : label is ""; + attribute RESETMODE of pdp_ram_5_0_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_0_9 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_9 : label is ""; + attribute RESETMODE of pdp_ram_6_0_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_0_8 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_8 : label is ""; + attribute RESETMODE of pdp_ram_7_0_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_0_7 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_7 : label is ""; + attribute RESETMODE of pdp_ram_8_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_0_6 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_6 : label is ""; + attribute RESETMODE of pdp_ram_9_0_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_0_5 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_5 : label is ""; + attribute RESETMODE of pdp_ram_10_0_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_0_4 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_4 : label is ""; + attribute RESETMODE of pdp_ram_11_0_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_0_3 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_3 : label is ""; + attribute RESETMODE of pdp_ram_12_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_0_2 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_2 : label is ""; + attribute RESETMODE of pdp_ram_13_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_0_1 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_1 : label is ""; + attribute RESETMODE of pdp_ram_14_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_0_0 : label is "fifo_32kx9_flags.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_0 : label is ""; + attribute RESETMODE of pdp_ram_15_0_0 : label is "SYNC"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t32: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_9: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t31: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_8: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t30: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t29: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t28: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t27: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t26: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t25: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t24: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t23: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t22: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t21: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t20: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t19: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t18: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t17: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t16: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t15: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t14: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t13: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t12: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t11: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t10: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t9: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t8: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t7: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t6: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t5: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t4: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t3: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t2: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t1: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t0: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + INV_7: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_6: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_5: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_4: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec0_p00); + + INV_3: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_2: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_1: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_0: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec1_r10); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec2_p01); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec3_r11); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec4_p02); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec5_r12); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec6_p03); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec7_r13); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec8_p04); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec9_r14); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec10_p05); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec11_r15); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec12_p06); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec13_r16); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec14_p07); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec15_r17); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec16_p08); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec17_r18); + + LUT4_64: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec18_p09); + + LUT4_63: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec19_r19); + + LUT4_62: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec20_p010); + + LUT4_61: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec21_r110); + + LUT4_60: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec22_p011); + + LUT4_59: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec23_r111); + + LUT4_58: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec24_p012); + + LUT4_57: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec25_r112); + + LUT4_56: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec26_p013); + + LUT4_55: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec27_r113); + + LUT4_54: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec28_p014); + + LUT4_53: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec29_r114); + + LUT4_52: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>dec30_p015); + + LUT4_51: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>dec31_r115); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, + DO0=>w_g2b_xor_cluster_0); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_1); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_2); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_3); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r2); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r1); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, + DO0=>r_g2b_xor_cluster_0); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, + DO0=>r_g2b_xor_cluster_1); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, + DO0=>r_g2b_xor_cluster_2); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, + DO0=>r_g2b_xor_cluster_3); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>scuba_vlo, DO0=>rcount_w13); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w9); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w23, DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w1); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w0); + + LUT4_8: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_15, AD2=>rcount_15, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_7: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_15, AD2=>rcount_15, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_6: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w215, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_5: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w215, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_4: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_15, AD2=>wcount_15, + AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_set_cmp_set); + + LUT4_3: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_15, AD2=>wcount_15, + AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_set_cmp_clr); + + LUT4_2: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_clrcount_15, AD2=>wcount_15, + AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_clr_cmp_set); + + LUT4_1: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_clrcount_15, AD2=>wcount_15, + AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_clr_cmp_clr); + + LUT4_0: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>af, AD2=>af_set, AD1=>af_clr, AD0=>scuba_vlo, + DO0=>af_d); + + pdp_ram_0_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, + DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, + DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, + DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_11_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, + DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, + DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, + DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_12_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, + DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, + DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, + DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_13_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, + DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, + DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, + DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_14_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, + DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, + DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, + DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_15_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, + DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, + DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, + DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + FF_198: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_197: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_196: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_195: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_194: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_193: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_192: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_191: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_190: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_189: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_188: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_187: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_186: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_185: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_184: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_183: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_182: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_181: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_180: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_179: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_178: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_177: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_176: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_175: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_174: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_173: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_172: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_171: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_170: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_169: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_168: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_167: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_166: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_165: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_164: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_163: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_162: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_161: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_160: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_159: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_158: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_157: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_156: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_155: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_154: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_153: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_152: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_151: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_150: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_149: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_148: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_147: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_146: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_145: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_144: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_143: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_142: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_141: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_140: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_139: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_138: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_137: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_136: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_135: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_134: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_133: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_132: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_131: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_130: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_129: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_128: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_127: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_126: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_125: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_124: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_123: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_122: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_121: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_120: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_119: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_118: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_117: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_116: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_115: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_114: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_113: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_112: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_111: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_110: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_109: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_108: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_107: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_106: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_105: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_104: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_103: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_102: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_101: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_100: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_99: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_98: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_97: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_96: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_95: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_94: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_93: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_92: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_91: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_90: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_89: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_88: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_87: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_86: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_85: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_84: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_83: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_82: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_81: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_80: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_79: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_78: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_77: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_76: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_75: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_74: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_73: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_72: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_71: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_70: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_69: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_68: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_67: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_66: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_65: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_64: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_63: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_62: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_61: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_60: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_59: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_58: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_57: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_56: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_55: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_54: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_53: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_52: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_51: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_50: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_49: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_48: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_47: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_46: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_45: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_44: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_43: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_42: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_41: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_40: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_39: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_38: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_37: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_36: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_35: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_34: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_33: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_32: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); + + FF_31: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); + + FF_30: FD1P3DX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_2); + + FF_29: FD1P3DX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_3); + + FF_28: FD1P3BX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_4); + + FF_27: FD1P3DX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_5); + + FF_26: FD1P3BX + port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_6); + + FF_25: FD1P3BX + port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_7); + + FF_24: FD1P3DX + port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_8); + + FF_23: FD1P3BX + port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_9); + + FF_22: FD1P3DX + port map (D=>iaf_setcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_10); + + FF_21: FD1P3BX + port map (D=>iaf_setcount_11, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_11); + + FF_20: FD1P3DX + port map (D=>iaf_setcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_12); + + FF_19: FD1P3DX + port map (D=>iaf_setcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_13); + + FF_18: FD1P3DX + port map (D=>iaf_setcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_14); + + FF_17: FD1P3DX + port map (D=>iaf_setcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_15); + + FF_16: FD1P3BX + port map (D=>iaf_clrcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_0); + + FF_15: FD1P3BX + port map (D=>iaf_clrcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_1); + + FF_14: FD1P3DX + port map (D=>iaf_clrcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_2); + + FF_13: FD1P3BX + port map (D=>iaf_clrcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_3); + + FF_12: FD1P3BX + port map (D=>iaf_clrcount_4, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_4); + + FF_11: FD1P3DX + port map (D=>iaf_clrcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_5); + + FF_10: FD1P3BX + port map (D=>iaf_clrcount_6, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_6); + + FF_9: FD1P3BX + port map (D=>iaf_clrcount_7, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_7); + + FF_8: FD1P3DX + port map (D=>iaf_clrcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_8); + + FF_7: FD1P3BX + port map (D=>iaf_clrcount_9, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_9); + + FF_6: FD1P3DX + port map (D=>iaf_clrcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_10); + + FF_5: FD1P3BX + port map (D=>iaf_clrcount_11, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_11); + + FF_4: FD1P3DX + port map (D=>iaf_clrcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_12); + + FF_3: FD1P3DX + port map (D=>iaf_clrcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_13); + + FF_2: FD1P3DX + port map (D=>iaf_clrcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_14); + + FF_1: FD1P3DX + port map (D=>iaf_clrcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_15); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>af); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + mux_8: MUX161 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(0)); + + mux_7: MUX161 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(1)); + + mux_6: MUX161 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(2)); + + mux_5: MUX161 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(3)); + + mux_4: MUX161 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(4)); + + mux_3: MUX161 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(5)); + + mux_2: MUX161 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(6)); + + mux_1: MUX161 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(7)); + + mux_0: MUX161 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(8)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r13, CI=>co5_2, GE=>co6_2); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>empty_cmp_set, B0=>wcount_r14, + B1=>empty_cmp_clr, CI=>co6_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w13, CI=>co5_3, GE=>co6_3); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w14, + B1=>full_cmp_clr, CI=>co6_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, + CO=>co2_4, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); + + af_set_ctr_3: CU2 + port map (CI=>co2_4, PC0=>af_setcount_6, PC1=>af_setcount_7, + CO=>co3_4, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7); + + af_set_ctr_4: CU2 + port map (CI=>co3_4, PC0=>af_setcount_8, PC1=>af_setcount_9, + CO=>co4_4, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9); + + af_set_ctr_5: CU2 + port map (CI=>co4_4, PC0=>af_setcount_10, PC1=>af_setcount_11, + CO=>co5_4, NC0=>iaf_setcount_10, NC1=>iaf_setcount_11); + + af_set_ctr_6: CU2 + port map (CI=>co5_4, PC0=>af_setcount_12, PC1=>af_setcount_13, + CO=>co6_4, NC0=>iaf_setcount_12, NC1=>iaf_setcount_13); + + af_set_ctr_7: CU2 + port map (CI=>co6_4, PC0=>af_setcount_14, PC1=>af_setcount_15, + CO=>co7_2, NC0=>iaf_setcount_14, NC1=>iaf_setcount_15); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_5, GE=>co2_5); + + af_set_cmp_3: AGEB2 + port map (A0=>af_setcount_6, A1=>af_setcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_5, GE=>co3_5); + + af_set_cmp_4: AGEB2 + port map (A0=>af_setcount_8, A1=>af_setcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_5, GE=>co4_5); + + af_set_cmp_5: AGEB2 + port map (A0=>af_setcount_10, A1=>af_setcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_5, GE=>co5_5); + + af_set_cmp_6: AGEB2 + port map (A0=>af_setcount_12, A1=>af_setcount_13, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w13, CI=>co5_5, + GE=>co6_5); + + af_set_cmp_7: AGEB2 + port map (A0=>af_setcount_14, A1=>af_set_cmp_set, B0=>rcount_w14, + B1=>af_set_cmp_clr, CI=>co6_5, GE=>af_set_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_clr_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_clr_ctr_ci, S0=>open, + S1=>open); + + af_clr_ctr_0: CU2 + port map (CI=>af_clr_ctr_ci, PC0=>af_clrcount_0, + PC1=>af_clrcount_1, CO=>co0_6, NC0=>iaf_clrcount_0, + NC1=>iaf_clrcount_1); + + af_clr_ctr_1: CU2 + port map (CI=>co0_6, PC0=>af_clrcount_2, PC1=>af_clrcount_3, + CO=>co1_6, NC0=>iaf_clrcount_2, NC1=>iaf_clrcount_3); + + af_clr_ctr_2: CU2 + port map (CI=>co1_6, PC0=>af_clrcount_4, PC1=>af_clrcount_5, + CO=>co2_6, NC0=>iaf_clrcount_4, NC1=>iaf_clrcount_5); + + af_clr_ctr_3: CU2 + port map (CI=>co2_6, PC0=>af_clrcount_6, PC1=>af_clrcount_7, + CO=>co3_6, NC0=>iaf_clrcount_6, NC1=>iaf_clrcount_7); + + af_clr_ctr_4: CU2 + port map (CI=>co3_6, PC0=>af_clrcount_8, PC1=>af_clrcount_9, + CO=>co4_6, NC0=>iaf_clrcount_8, NC1=>iaf_clrcount_9); + + af_clr_ctr_5: CU2 + port map (CI=>co4_6, PC0=>af_clrcount_10, PC1=>af_clrcount_11, + CO=>co5_6, NC0=>iaf_clrcount_10, NC1=>iaf_clrcount_11); + + af_clr_ctr_6: CU2 + port map (CI=>co5_6, PC0=>af_clrcount_12, PC1=>af_clrcount_13, + CO=>co6_6, NC0=>iaf_clrcount_12, NC1=>iaf_clrcount_13); + + af_clr_ctr_7: CU2 + port map (CI=>co6_6, PC0=>af_clrcount_14, PC1=>af_clrcount_15, + CO=>co7_3, NC0=>iaf_clrcount_14, NC1=>iaf_clrcount_15); + + af_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_clr_cmp_0: AGEB2 + port map (A0=>af_clrcount_0, A1=>af_clrcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_7); + + af_clr_cmp_1: AGEB2 + port map (A0=>af_clrcount_2, A1=>af_clrcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_7, GE=>co1_7); + + af_clr_cmp_2: AGEB2 + port map (A0=>af_clrcount_4, A1=>af_clrcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_7, GE=>co2_7); + + af_clr_cmp_3: AGEB2 + port map (A0=>af_clrcount_6, A1=>af_clrcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_7, GE=>co3_7); + + af_clr_cmp_4: AGEB2 + port map (A0=>af_clrcount_8, A1=>af_clrcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_7, GE=>co4_7); + + af_clr_cmp_5: AGEB2 + port map (A0=>af_clrcount_10, A1=>af_clrcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_7, GE=>co5_7); + + af_clr_cmp_6: AGEB2 + port map (A0=>af_clrcount_12, A1=>af_clrcount_13, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w13, CI=>co5_7, + GE=>co6_7); + + af_clr_cmp_7: AGEB2 + port map (A0=>af_clrcount_14, A1=>af_clr_cmp_set, B0=>rcount_w14, + B1=>af_clr_cmp_clr, CI=>co6_7, GE=>af_clr_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_clr_c, COUT=>open, S0=>af_clr, + S1=>open); + + Empty <= empty_i; + Full <= full_i; + AlmostFull <= af; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_32kx9_flags is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX161 use entity ecp3.MUX161(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_4096x32.lpc b/gbe_trb/ipcores/ecp3/fifo_4096x32.lpc new file mode 100755 index 0000000..39ae0d7 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4096x32.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_4096x32 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:24:15 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4096 +Width=32 +RDepth=4096 +RWidth=32 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_4096x32.vhd b/gbe_trb/ipcores/ecp3/fifo_4096x32.vhd new file mode 100755 index 0000000..2f52ee4 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4096x32.vhd @@ -0,0 +1,1803 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:24:15 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4096x32 is + port ( + Data: in std_logic_vector(31 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(31 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4096x32; + +architecture Structure of fifo_4096x32 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal co6: std_logic; + signal wcount_12: std_logic; + signal co5: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal co6_1: std_logic; + signal rcount_12: std_logic; + signal co5_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; + attribute RESETMODE of pdp_ram_0_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; + attribute RESETMODE of pdp_ram_0_1_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; + attribute RESETMODE of pdp_ram_0_2_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; + attribute RESETMODE of pdp_ram_0_3_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; + attribute RESETMODE of pdp_ram_0_4_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; + attribute RESETMODE of pdp_ram_0_5_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; + attribute RESETMODE of pdp_ram_0_6_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; + attribute RESETMODE of pdp_ram_0_7_0 : label is "SYNC"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t26: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t25: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t24: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t23: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t22: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t21: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t20: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t19: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t18: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t17: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t16: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t15: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t14: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t13: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t12: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t11: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t10: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t9: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t8: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t7: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t6: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t4: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t3: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t2: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t1: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t0: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_0); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_1); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_2); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_7: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_1_6: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), + DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), + DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_2_5: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10), + DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8), + DOB1=>Q(9), DOB2=>Q(10), DOB3=>Q(11), DOB4=>open, DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_3_4: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14), + DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(12), + DOB1=>Q(13), DOB2=>Q(14), DOB3=>Q(15), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_4_3: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18), + DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(16), + DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_5_2: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22), + DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(20), + DOB1=>Q(21), DOB2=>Q(22), DOB3=>Q(23), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_6_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26), + DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(24), + DOB1=>Q(25), DOB2=>Q(26), DOB3=>Q(27), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_7_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30), + DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(28), + DOB1=>Q(29), DOB2=>Q(30), DOB3=>Q(31), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + FF_131: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_130: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_129: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_128: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_127: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_126: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_125: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_124: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_123: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_122: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_121: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_120: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_119: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_118: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_117: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_116: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_115: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_114: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_113: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_112: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_111: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_110: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_109: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_108: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_107: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_106: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_105: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_104: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_103: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_102: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_101: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_100: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_99: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_98: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_97: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_96: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_95: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_94: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_93: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_92: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_91: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_90: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_89: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_88: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_87: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_86: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_85: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_84: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_83: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_82: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_81: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_80: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_79: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_78: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_77: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_76: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_75: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_74: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_73: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_72: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_71: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_70: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_69: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_68: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_67: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_66: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_65: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_64: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_63: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_62: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_61: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_60: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_59: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_58: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_57: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_56: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_55: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_54: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_53: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_52: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_51: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_50: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_49: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_48: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_47: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_46: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_45: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_44: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_43: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_42: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_41: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_40: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_39: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_38: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_37: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_36: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_35: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_34: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_33: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_32: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_31: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_30: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_29: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_28: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_27: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_26: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_25: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_24: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_23: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_22: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_21: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_20: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_19: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_18: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_17: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_16: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_15: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_14: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_13: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_12: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_11: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_10: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_9: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_8: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_7: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_6: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_5: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_4: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_3: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_2: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, + NC0=>iwcount_12, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, + NC0=>ircount_12, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4096x32 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_4096x9.lpc b/gbe_trb/ipcores/ecp3/fifo_4096x9.lpc new file mode 100755 index 0000000..6e382a8 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4096x9.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_4096x9 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:24:06 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4096 +Width=9 +RDepth=4096 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd b/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd new file mode 100755 index 0000000..75ae6c9 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd @@ -0,0 +1,1624 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:24:06 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4096x9 is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4096x9; + +architecture Structure of fifo_4096x9 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_12: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal co6: std_logic; + signal wcount_12: std_logic; + signal co5: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal co6_1: std_logic; + signal rcount_12: std_logic; + signal co5_1: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX21 + port (D0: in std_logic; D1: in std_logic; SD: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; + attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t26: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t25: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t24: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t23: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t22: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t21: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t20: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t19: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t18: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t17: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t16: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t15: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t14: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t13: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t12: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t11: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t10: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t9: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t8: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t7: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t6: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t4: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t3: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t2: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t1: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t0: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_0); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_1); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_2); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_132: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_131: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_130: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_129: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_128: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_127: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_126: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_125: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_124: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_123: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_122: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_121: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_120: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_119: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_118: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_117: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_116: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_115: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_114: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_113: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_112: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_111: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_110: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_109: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_108: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_107: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_106: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_105: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_104: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_103: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_102: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_101: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_100: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_99: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_98: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_97: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_96: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_95: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_94: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_93: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_92: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_91: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_90: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_89: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_88: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_87: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_86: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_85: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_84: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_83: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_82: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_81: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_80: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_79: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_78: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_77: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_76: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_75: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_74: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_73: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_72: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_71: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_70: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_69: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_68: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_67: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_66: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_65: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_64: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_63: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_62: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_61: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_60: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_59: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_58: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_57: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_56: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_55: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_54: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_53: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_52: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_51: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_50: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_49: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_48: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_47: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_46: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_45: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_44: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_43: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_42: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_41: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_40: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_39: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_38: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_37: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_36: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_35: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_34: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_33: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_32: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_31: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_30: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_29: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_28: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_27: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_26: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_25: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_24: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_23: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_22: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_21: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_20: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_19: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_18: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_17: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_16: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_15: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_14: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_13: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_12: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_11: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_10: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_9: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_8: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_7: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_6: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_5: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_4: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_3: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_2: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, + NC0=>iwcount_12, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, + NC0=>ircount_12, NC1=>open); + + mux_8: MUX21 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, + Z=>Q(0)); + + mux_7: MUX21 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, + Z=>Q(1)); + + mux_6: MUX21 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, + Z=>Q(2)); + + mux_5: MUX21 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, + Z=>Q(3)); + + mux_4: MUX21 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, + Z=>Q(4)); + + mux_3: MUX21 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, + Z=>Q(5)); + + mux_2: MUX21 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, + Z=>Q(6)); + + mux_1: MUX21 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, + Z=>Q(7)); + + mux_0: MUX21 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, + Z=>Q(8)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4096x9 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX21 use entity ecp3.MUX21(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_4kx18x9.vhd b/gbe_trb/ipcores/ecp3/fifo_4kx18x9.vhd new file mode 100644 index 0000000..73df06a --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4kx18x9.vhd @@ -0,0 +1,1573 @@ +-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99) +-- Module Version: 5.5 +--/home/soft/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fifo_4kx18x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 18 -depth 2048 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + +-- Wed Jun 26 14:33:30 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4kx18x9 is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4kx18x9; + +architecture Structure of fifo_4kx18x9 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_12: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal co4: std_logic; + signal wcount_11: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal co6: std_logic; + signal co5_1: std_logic; + signal rcount_12: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r7: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w11: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX21 + port (D0: in std_logic; D1: in std_logic; SD: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4kx18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4kx18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; + attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t25: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t24: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t23: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t22: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t21: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t20: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t19: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t18: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t17: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t16: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t15: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t14: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t13: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t12: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t11: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t10: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t9: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t8: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t7: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t6: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t4: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t3: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t2: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t1: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t0: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, + DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, + DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, + DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_1_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, + DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, + DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, + DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + FF_127: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_126: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_125: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_124: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_123: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_122: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_121: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_120: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_119: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_118: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_117: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_116: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_115: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_114: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_113: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_112: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_111: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_110: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_109: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_108: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_107: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_106: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_105: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_104: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_103: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_102: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_101: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_100: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_99: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_98: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_97: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_96: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_95: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_94: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_93: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_92: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_91: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_90: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_89: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_88: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_87: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_86: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_85: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_84: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_83: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_82: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_81: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_80: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_79: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_78: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_77: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_76: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_75: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_74: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_73: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_72: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_71: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_70: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_69: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_68: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_67: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_66: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_65: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_64: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_63: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_62: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_61: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_60: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_59: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_58: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_57: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_56: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_55: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_54: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_53: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_52: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_51: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_50: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_49: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_48: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_47: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_46: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_45: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_44: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_43: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_42: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_41: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_40: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_39: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_38: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_37: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_36: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_35: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_34: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_33: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_32: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_31: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_30: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_29: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_28: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_27: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_26: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_25: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_24: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_23: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_22: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_21: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_20: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_19: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_18: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_17: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_16: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_15: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_14: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_13: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_12: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_11: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_10: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_9: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_8: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_7: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_6: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_5: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_4: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_3: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_2: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6, + NC0=>ircount_12, NC1=>open); + + mux_8: MUX21 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, + Z=>Q(0)); + + mux_7: MUX21 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, + Z=>Q(1)); + + mux_6: MUX21 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, + Z=>Q(2)); + + mux_5: MUX21 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, + Z=>Q(3)); + + mux_4: MUX21 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, + Z=>Q(4)); + + mux_3: MUX21 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, + Z=>Q(5)); + + mux_2: MUX21 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, + Z=>Q(6)); + + mux_1: MUX21 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, + Z=>Q(7)); + + mux_0: MUX21 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, + Z=>Q(8)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>wcount_r10, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w10, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w11, + B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4kx18x9 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX21 use entity ecp3.MUX21(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_4kx8_ecp3.vhd b/gbe_trb/ipcores/ecp3/fifo_4kx8_ecp3.vhd new file mode 100644 index 0000000..f282f7a --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4kx8_ecp3.vhd @@ -0,0 +1,1559 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 5.4 +--/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 8 -depth 4096 -rdata_width 8 -no_enable -pe -1 -pf -1 -e + +-- Tue Apr 23 14:34:09 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4kx8_ecp3 is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4kx8_ecp3; + +architecture Structure of fifo_4kx8_ecp3 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal co6: std_logic; + signal wcount_12: std_logic; + signal co5: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal co6_1: std_logic; + signal rcount_12: std_logic; + signal co5_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4kx8_ecp3.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_4kx8_ecp3.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t26: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t25: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t24: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t23: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t22: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t21: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t20: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t19: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t18: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t17: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t16: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t15: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t14: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t13: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t12: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t11: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t10: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t9: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t8: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t7: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t6: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t4: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t3: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t2: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t1: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t0: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_0); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_1); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_2); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_1_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), + DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), + DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + FF_131: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_130: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_129: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_128: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_127: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_126: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_125: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_124: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_123: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_122: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_121: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_120: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_119: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_118: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_117: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_116: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_115: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_114: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_113: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_112: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_111: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_110: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_109: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_108: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_107: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_106: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_105: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_104: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_103: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_102: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_101: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_100: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_99: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_98: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_97: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_96: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_95: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_94: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_93: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_92: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_91: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_90: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_89: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_88: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_87: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_86: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_85: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_84: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_83: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_82: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_81: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_80: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_79: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_78: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_77: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_76: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_75: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_74: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_73: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_72: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_71: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_70: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_69: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_68: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_67: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_66: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_65: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_64: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_63: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_62: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_61: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_60: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_59: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_58: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_57: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_56: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_55: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_54: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_53: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_52: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_51: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_50: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_49: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_48: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_47: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_46: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_45: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_44: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_43: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_42: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_41: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_40: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_39: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_38: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_37: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_36: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_35: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_34: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_33: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_32: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_31: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_30: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_29: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_28: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_27: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_26: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_25: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_24: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_23: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_22: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_21: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_20: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_19: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_18: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_17: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_16: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_15: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_14: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_13: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_12: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_11: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_10: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_9: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_8: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_7: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_6: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_5: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_4: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_3: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_2: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, + NC0=>iwcount_12, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, + NC0=>ircount_12, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4kx8_ecp3 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_512x32.lpc b/gbe_trb/ipcores/ecp3/fifo_512x32.lpc new file mode 100644 index 0000000..67057ca --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_512x32.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_512x32 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:13:43 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=512 +Width=32 +RDepth=512 +RWidth=32 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_512x32.vhd b/gbe_trb/ipcores/ecp3/fifo_512x32.vhd new file mode 100644 index 0000000..73e04d7 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_512x32.vhd @@ -0,0 +1,1193 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:13:43 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_512x32 is + port ( + Data: in std_logic_vector(31 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(31 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_512x32; + +architecture Structure of fifo_512x32 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4: std_logic; + signal wcount_9: std_logic; + signal co3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co4_1: std_logic; + signal rcount_9: std_logic; + signal co3_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_8: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_8: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t20: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t19: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t18: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t17: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t16: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t15: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t14: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t13: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t12: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t11: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t10: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t9: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t8: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t7: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t6: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t5: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t4: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t3: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t2: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t1: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t0: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_gcount_r29, + DO0=>w_g2b_xor_cluster_0); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_1); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_gcount_w29, + DO0=>r_g2b_xor_cluster_0); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_1); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, + DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, + ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, + ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, + ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, + ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), + DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), + DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), + DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open, + DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), + DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), + DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), + DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); + + FF_101: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_100: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_99: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_98: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_97: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_96: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_95: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_94: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_93: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_92: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_91: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_90: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_89: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_88: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_87: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_86: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_85: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_84: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_83: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_82: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_81: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_80: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_79: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_78: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_77: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_76: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_75: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_74: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_73: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_72: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_71: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_70: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_69: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_68: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_67: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_66: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_65: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_64: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_63: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_62: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_61: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_60: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_59: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_58: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_57: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_56: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_55: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_54: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_53: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_52: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_51: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_50: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_49: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_48: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_47: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_46: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_45: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_44: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_43: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_42: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_41: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_40: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_39: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_38: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_37: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_36: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_35: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_34: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_33: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_32: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_31: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_30: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_29: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_28: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_27: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_26: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_25: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_24: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_23: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_22: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_21: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_20: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_19: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_18: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_17: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_16: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_15: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_14: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_13: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_12: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_11: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_10: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_9: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_8: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_7: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_6: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_5: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_4: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_3: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_2: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, + B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, + B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_512x32 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd b/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd new file mode 100644 index 0000000..fef9988 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd @@ -0,0 +1,1298 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 5.4 +--/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 8 -no_enable -pe -1 -pf -1 -e + +-- Tue Jun 11 11:02:45 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_512x32x8 is + port ( + Data: in std_logic_vector(31 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_512x32x8; + +architecture Structure of fifo_512x32x8 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal rcount_w1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4: std_logic; + signal wcount_9: std_logic; + signal co3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co5: std_logic; + signal rcount_11: std_logic; + signal co4_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r7: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r8: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_10: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w9: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w10: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_8: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32x8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t22: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t21: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t20: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t19: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t18: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t17: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t16: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t15: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t14: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t13: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t12: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t11: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t10: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t9: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t8: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t7: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t6: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t5: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t4: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t3: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t2: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t1: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t0: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_gcount_r29, + DO0=>w_g2b_xor_cluster_0); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_1); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, + DO0=>r_g2b_xor_cluster_0); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, + DO0=>r_g2b_xor_cluster_1); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, + DO0=>r_g2b_xor_cluster_2); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>scuba_vlo, DI9=>Data(8), DI10=>Data(9), DI11=>Data(10), + DI12=>Data(11), DI13=>Data(12), DI14=>Data(13), + DI15=>Data(14), DI16=>Data(15), DI17=>scuba_vlo, + DI18=>Data(16), DI19=>Data(17), DI20=>Data(18), + DI21=>Data(19), DI22=>Data(20), DI23=>Data(21), + DI24=>Data(22), DI25=>Data(23), DI26=>scuba_vlo, + DI27=>Data(24), DI28=>Data(25), DI29=>Data(26), + DI30=>Data(27), DI31=>Data(28), DI32=>Data(29), + DI33=>Data(30), DI34=>Data(31), DI35=>scuba_vlo, + ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, + ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, + ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1, + ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5, + ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9, + ADR13=>rptr_10, CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo, + CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), + DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), + DO6=>Q(6), DO7=>Q(7), DO8=>open, DO9=>open, DO10=>open, + DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open, + DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open, + DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open, + DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open, + DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open); + + FF_111: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_110: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_109: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_108: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_107: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_106: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_105: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_104: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_103: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_102: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_101: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_100: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_99: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_98: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_97: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_96: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_95: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_94: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_93: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_92: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_91: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_90: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_89: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_88: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_87: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_86: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_85: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_84: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_83: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_82: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_81: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_80: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_79: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_78: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_77: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_76: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_75: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_74: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_73: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_72: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_71: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_70: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_69: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_68: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_67: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_66: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_65: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_64: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_63: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_62: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_61: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_60: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_59: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_58: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_57: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_56: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_55: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_54: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_53: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_52: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_51: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_50: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_49: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_48: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_47: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_46: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_45: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_44: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_43: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_42: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_41: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_40: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_39: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_38: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_37: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_36: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_35: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_34: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_33: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_32: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_31: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_30: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_29: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_28: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_27: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_26: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_25: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_24: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_23: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_22: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_21: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_20: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_19: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_18: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_17: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_16: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_15: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_14: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_13: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_12: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_11: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_10: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_9: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_8: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_7: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_6: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_5: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_4: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_3: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_2: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5, + NC0=>ircount_10, NC1=>ircount_11); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r0, + B1=>wcount_r1, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r2, + B1=>wcount_r3, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r4, + B1=>wcount_r5, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r7, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r8, + B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w2, + B1=>rcount_w3, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w4, + B1=>rcount_w5, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w6, + B1=>rcount_w7, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w9, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w10, + B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_512x32x8 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_512x64.lpc b/gbe_trb/ipcores/ecp3/fifo_512x64.lpc new file mode 100644 index 0000000..f17569e --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_512x64.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_512x64 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:23:40 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=512 +Width=72 +RDepth=512 +RWidth=72 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_512x64.vhd b/gbe_trb/ipcores/ecp3/fifo_512x64.vhd new file mode 100644 index 0000000..dae4c8f --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_512x64.vhd @@ -0,0 +1,1231 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:23:40 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_512x64 is + port ( + Data: in std_logic_vector(71 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(71 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_512x64; + +architecture Structure of fifo_512x64 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4: std_logic; + signal wcount_9: std_logic; + signal co3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co4_1: std_logic; + signal rcount_9: std_logic; + signal co3_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_8: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_8: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x64.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x64.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t20: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t19: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t18: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t17: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t16: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t15: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t14: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t13: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t12: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t11: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t10: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t9: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t8: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t7: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t6: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t5: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t4: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t3: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t2: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t1: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t0: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_gcount_r29, + DO0=>w_g2b_xor_cluster_0); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_1); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_gcount_w29, + DO0=>r_g2b_xor_cluster_0); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_1); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, + ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, + ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), + DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), + DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), + DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), + DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), + DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), + DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), + DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), + DO35=>Q(17)); + + pdp_ram_0_1_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), + DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), + DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), + DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), + DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), + DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), + DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), + DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), + DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, + ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, + ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, + BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, + CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, + ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, + ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, + ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, + ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, + CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), + DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), + DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), + DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), + DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), + DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), + DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), + DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), + DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); + + FF_101: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_100: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_99: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_98: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_97: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_96: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_95: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_94: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_93: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_92: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_91: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_90: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_89: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_88: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_87: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_86: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_85: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_84: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_83: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_82: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_81: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_80: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_79: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_78: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_77: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_76: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_75: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_74: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_73: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_72: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_71: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_70: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_69: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_68: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_67: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_66: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_65: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_64: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_63: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_62: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_61: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_60: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_59: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_58: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_57: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_56: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_55: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_54: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_53: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_52: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_51: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_50: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_49: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_48: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_47: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_46: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_45: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_44: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_43: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_42: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_41: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_40: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_39: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_38: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_37: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_36: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_35: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_34: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_33: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_32: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_31: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_30: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_29: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_28: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_27: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_26: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_25: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_24: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_23: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_22: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_21: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_20: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_19: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_18: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_17: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_16: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_15: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_14: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_13: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_12: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_11: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_10: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_9: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_8: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_7: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_6: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_5: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_4: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_3: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_2: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, + B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, + B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_512x64 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_512x72.lpc b/gbe_trb/ipcores/ecp3/fifo_512x72.lpc new file mode 100644 index 0000000..1467961 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_512x72.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_512x72 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:14:03 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=512 +Width=72 +RDepth=512 +RWidth=72 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_512x72.vhd b/gbe_trb/ipcores/ecp3/fifo_512x72.vhd new file mode 100644 index 0000000..4ffa914 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_512x72.vhd @@ -0,0 +1,1231 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:14:04 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_512x72 is + port ( + Data: in std_logic_vector(71 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(71 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_512x72; + +architecture Structure of fifo_512x72 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4: std_logic; + signal wcount_9: std_logic; + signal co3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co4_1: std_logic; + signal rcount_9: std_logic; + signal co3_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_8: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_8: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x72.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x72.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t20: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t19: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t18: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t17: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t16: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t15: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t14: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t13: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t12: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t11: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t10: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t9: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t8: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t7: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t6: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t5: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t4: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t3: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t2: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t1: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t0: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_gcount_r29, + DO0=>w_g2b_xor_cluster_0); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_1); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_gcount_w29, + DO0=>r_g2b_xor_cluster_0); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_1); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, + ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, + ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), + DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), + DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), + DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), + DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), + DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), + DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), + DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), + DO35=>Q(17)); + + pdp_ram_0_1_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), + DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), + DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), + DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), + DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), + DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), + DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), + DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), + DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, + ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, + ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, + BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, + CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, + ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, + ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, + ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, + ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, + CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), + DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), + DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), + DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), + DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), + DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), + DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), + DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), + DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); + + FF_101: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_100: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_99: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_98: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_97: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_96: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_95: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_94: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_93: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_92: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_91: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_90: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_89: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_88: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_87: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_86: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_85: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_84: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_83: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_82: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_81: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_80: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_79: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_78: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_77: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_76: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_75: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_74: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_73: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_72: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_71: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_70: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_69: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_68: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_67: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_66: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_65: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_64: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_63: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_62: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_61: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_60: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_59: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_58: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_57: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_56: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_55: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_54: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_53: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_52: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_51: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_50: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_49: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_48: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_47: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_46: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_45: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_44: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_43: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_42: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_41: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_40: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_39: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_38: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_37: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_36: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_35: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_34: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_33: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_32: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_31: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_30: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_29: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_28: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_27: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_26: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_25: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_24: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_23: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_22: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_21: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_20: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_19: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_18: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_17: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_16: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_15: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_14: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_13: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_12: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_11: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_10: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_9: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_8: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_7: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_6: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_5: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_4: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_3: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_2: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, + B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, + B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_512x72 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx8.lpc b/gbe_trb/ipcores/ecp3/fifo_64kx8.lpc new file mode 100755 index 0000000..badffb2 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx8.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_64kx8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:23:03 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=65536 +Width=8 +RDepth=65536 +RWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx8.vhd b/gbe_trb/ipcores/ecp3/fifo_64kx8.vhd new file mode 100755 index 0000000..8d65547 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx8.vhd @@ -0,0 +1,3355 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 8 -depth 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:23:03 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_64kx8 is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_64kx8; + +architecture Structure of fifo_64kx8 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_9: std_logic; + signal func_xor_inet_8: std_logic; + signal func_xor_inet_7: std_logic; + signal func_xor_inet_6: std_logic; + signal func_xor_inet_10: std_logic; + signal func_xor_inet_11: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal w_gdata_15: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wptr_15: std_logic; + signal wptr_16: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_16: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal w_gcount_16: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal w_gcount_r216: std_logic; + signal w_gcount_r16: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co6: std_logic; + signal iwcount_16: std_logic; + signal co8: std_logic; + signal wcount_16: std_logic; + signal co7: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8_1: std_logic; + signal rcount_16: std_logic; + signal co7_1: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal wcount_r12: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_2: std_logic; + signal wcount_r14: std_logic; + signal wcount_r15: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal rcount_w12: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_3: std_logic; + signal rcount_w14: std_logic; + signal rcount_w15: std_logic; + signal wcount_14: std_logic; + signal wcount_15: std_logic; + signal co7_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX41 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; SD1: in std_logic; SD2: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; + attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; + attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; + attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; + attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; + attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; + attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; + attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; + attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; + attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is ""; + attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is ""; + attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is ""; + attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is ""; + attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is ""; + attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is ""; + attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is ""; + attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is ""; + attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is ""; + attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is ""; + attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is ""; + attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is ""; + attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is ""; + attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is ""; + attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is ""; + attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is ""; + attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is ""; + attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is ""; + attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is ""; + attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is ""; + attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is ""; + attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is ""; + attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t34: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t33: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t32: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t31: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t30: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t29: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t28: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t27: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t26: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t25: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t24: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t23: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t22: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t21: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t20: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t19: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t18: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t17: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t16: XOR2 + port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); + + XOR2_t15: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t14: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t13: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t12: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t11: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t10: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t9: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t8: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t7: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t6: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t5: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t4: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t3: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t2: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t1: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t0: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + LUT4_59: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>w_gcount_r216, + DO0=>w_g2b_xor_cluster_0); + + LUT4_58: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_1); + + LUT4_57: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_2); + + LUT4_56: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_3); + + LUT4_55: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r15); + + LUT4_54: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, + AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_53: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, + DO0=>wcount_r10); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r3); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r2); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r1); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_10); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, + AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, + DO0=>func_xor_inet_11); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_1_30: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_2_29: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_3_28: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_4_27: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_5_26: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_6_25: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_7_24: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_1_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_2_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_3_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_4_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_5_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_6_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_7_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_15: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_1_14: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_2_13: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_3_12: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_4_11: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_5_10: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_6_9: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_7_8: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_7: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_1_6: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_2_5: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_3_4: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_4_3: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_5_2: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_6_1: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_7_0: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_173: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_172: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_171: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_170: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_169: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_168: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_167: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_166: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_165: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_164: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_163: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_162: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_161: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_160: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_159: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_158: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_157: FD1P3DX + port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_16); + + FF_156: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_155: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_154: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_153: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_152: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_151: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_150: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_149: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_148: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_147: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_146: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_145: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_144: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_143: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_142: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_141: FD1P3DX + port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_140: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_16); + + FF_139: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_138: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_137: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_136: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_135: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_134: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_133: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_132: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_131: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_130: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_129: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_128: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_127: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_126: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_125: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_124: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_123: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_16); + + FF_122: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_121: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_120: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_119: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_118: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_117: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_116: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_115: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_114: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_113: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_112: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_111: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_110: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_109: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_108: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_107: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_106: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_105: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_104: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_103: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_102: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_101: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_100: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_99: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_98: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_97: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_96: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_95: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_94: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_93: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_92: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_91: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_90: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_89: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_88: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_87: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_86: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_85: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_84: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_83: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_82: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_81: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_80: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_79: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_78: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_77: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_76: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_75: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_74: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_73: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_72: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_71: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_70: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_69: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_68: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_67: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_66: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_65: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_64: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_63: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_62: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_61: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_60: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_59: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_58: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_57: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_56: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_55: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_54: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_53: FD1S3DX + port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r16); + + FF_52: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_51: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_50: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_49: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_48: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_47: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_46: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_45: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_44: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_43: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_42: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_41: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_40: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_39: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_38: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_37: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_36: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_35: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_34: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_33: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_32: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_31: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_30: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_29: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_28: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_27: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_26: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_25: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_24: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_23: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_22: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_21: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_20: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_19: FD1S3DX + port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r216); + + FF_18: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_17: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_16: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_15: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_14: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_13: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_12: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_11: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_10: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_9: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_8: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_7: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_6: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_5: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_4: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_3: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_2: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + w_gctr_8: CU2 + port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>iwcount_16, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, + NC0=>ircount_16, NC1=>open); + + mux_7: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); + + mux_6: MUX41 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); + + mux_5: MUX41 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); + + mux_4: MUX41 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); + + mux_3: MUX41 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); + + mux_2: MUX41 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); + + mux_1: MUX41 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); + + mux_0: MUX41 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, + B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, + B1=>wcount_r15, CI=>co6_2, GE=>co7_2); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_3, GE=>co7_3); + + full_cmp_8: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_64kx8 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX41 use entity ecp3.MUX41(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx9.lpc b/gbe_trb/ipcores/ecp3/fifo_64kx9.lpc new file mode 100644 index 0000000..a9ca96b --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx9.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_64kx9 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:23:21 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=65536 +Width=9 +RDepth=65536 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd b/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd new file mode 100644 index 0000000..9ad1f19 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd @@ -0,0 +1,4582 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:23:21 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_64kx9 is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_64kx9; + +architecture Structure of fifo_64kx9 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal func_and_inet_13: std_logic; + signal func_and_inet_14: std_logic; + signal func_and_inet_15: std_logic; + signal func_and_inet_16: std_logic; + signal func_and_inet_17: std_logic; + signal func_and_inet_18: std_logic; + signal func_and_inet_19: std_logic; + signal func_and_inet_20: std_logic; + signal func_and_inet_21: std_logic; + signal func_and_inet_22: std_logic; + signal func_and_inet_23: std_logic; + signal func_and_inet_24: std_logic; + signal func_and_inet_25: std_logic; + signal func_and_inet_26: std_logic; + signal func_and_inet_27: std_logic; + signal func_and_inet_28: std_logic; + signal func_and_inet_29: std_logic; + signal wptr_15_inv: std_logic; + signal func_and_inet_30: std_logic; + signal rptr_15_inv: std_logic; + signal func_and_inet_31: std_logic; + signal func_and_inet_32: std_logic; + signal func_and_inet_33: std_logic; + signal func_and_inet_34: std_logic; + signal func_and_inet_35: std_logic; + signal func_and_inet_36: std_logic; + signal func_and_inet_37: std_logic; + signal func_and_inet_38: std_logic; + signal func_and_inet_39: std_logic; + signal func_and_inet_40: std_logic; + signal func_and_inet_41: std_logic; + signal func_and_inet_42: std_logic; + signal func_and_inet_43: std_logic; + signal func_and_inet_44: std_logic; + signal func_and_inet_45: std_logic; + signal wptr_14_inv: std_logic; + signal func_and_inet_46: std_logic; + signal rptr_14_inv: std_logic; + signal func_and_inet_47: std_logic; + signal func_and_inet_48: std_logic; + signal func_and_inet_49: std_logic; + signal func_and_inet_50: std_logic; + signal func_and_inet_51: std_logic; + signal func_and_inet_52: std_logic; + signal func_and_inet_53: std_logic; + signal wptr_13_inv: std_logic; + signal func_and_inet_54: std_logic; + signal rptr_13_inv: std_logic; + signal func_and_inet_55: std_logic; + signal func_and_inet_56: std_logic; + signal func_and_inet_57: std_logic; + signal wptr_12_inv: std_logic; + signal func_and_inet_58: std_logic; + signal rptr_12_inv: std_logic; + signal func_and_inet_59: std_logic; + signal wptr_11_inv: std_logic; + signal func_and_inet_60: std_logic; + signal rptr_11_inv: std_logic; + signal func_and_inet_61: std_logic; + signal func_and_inet_62: std_logic; + signal func_and_inet_63: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_9: std_logic; + signal func_xor_inet_8: std_logic; + signal func_xor_inet_7: std_logic; + signal func_xor_inet_6: std_logic; + signal func_xor_inet_10: std_logic; + signal func_xor_inet_11: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r11: std_logic; + signal dec2_p01: std_logic; + signal dec5_r12: std_logic; + signal dec4_p02: std_logic; + signal dec7_r13: std_logic; + signal dec6_p03: std_logic; + signal dec9_r14: std_logic; + signal dec8_p04: std_logic; + signal dec11_r15: std_logic; + signal dec10_p05: std_logic; + signal dec13_r16: std_logic; + signal dec12_p06: std_logic; + signal dec15_r17: std_logic; + signal dec14_p07: std_logic; + signal dec17_r18: std_logic; + signal dec16_p08: std_logic; + signal dec19_r19: std_logic; + signal dec18_p09: std_logic; + signal dec21_r110: std_logic; + signal dec20_p010: std_logic; + signal dec23_r111: std_logic; + signal dec22_p011: std_logic; + signal dec25_r112: std_logic; + signal dec24_p012: std_logic; + signal dec27_r113: std_logic; + signal dec26_p013: std_logic; + signal dec29_r114: std_logic; + signal dec28_p014: std_logic; + signal dec31_r115: std_logic; + signal dec30_p015: std_logic; + signal dec33_r116: std_logic; + signal dec32_p016: std_logic; + signal dec35_r117: std_logic; + signal dec34_p017: std_logic; + signal dec37_r118: std_logic; + signal dec36_p018: std_logic; + signal dec39_r119: std_logic; + signal dec38_p019: std_logic; + signal dec41_r120: std_logic; + signal dec40_p020: std_logic; + signal dec43_r121: std_logic; + signal dec42_p021: std_logic; + signal dec45_r122: std_logic; + signal dec44_p022: std_logic; + signal dec47_r123: std_logic; + signal dec46_p023: std_logic; + signal dec49_r124: std_logic; + signal dec48_p024: std_logic; + signal dec51_r125: std_logic; + signal dec50_p025: std_logic; + signal dec53_r126: std_logic; + signal dec52_p026: std_logic; + signal dec55_r127: std_logic; + signal dec54_p027: std_logic; + signal dec57_r128: std_logic; + signal dec56_p028: std_logic; + signal dec59_r129: std_logic; + signal dec58_p029: std_logic; + signal dec61_r130: std_logic; + signal dec60_p030: std_logic; + signal dec63_r131: std_logic; + signal dec62_p031: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal w_gdata_15: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wptr_15: std_logic; + signal wptr_16: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_16: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal w_gcount_16: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal w_gcount_r216: std_logic; + signal w_gcount_r16: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co6: std_logic; + signal iwcount_16: std_logic; + signal co8: std_logic; + signal wcount_16: std_logic; + signal co7: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8_1: std_logic; + signal rcount_16: std_logic; + signal co7_1: std_logic; + signal mdout1_31_0: std_logic; + signal mdout1_30_0: std_logic; + signal mdout1_29_0: std_logic; + signal mdout1_28_0: std_logic; + signal mdout1_27_0: std_logic; + signal mdout1_26_0: std_logic; + signal mdout1_25_0: std_logic; + signal mdout1_24_0: std_logic; + signal mdout1_23_0: std_logic; + signal mdout1_22_0: std_logic; + signal mdout1_21_0: std_logic; + signal mdout1_20_0: std_logic; + signal mdout1_19_0: std_logic; + signal mdout1_18_0: std_logic; + signal mdout1_17_0: std_logic; + signal mdout1_16_0: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_31_1: std_logic; + signal mdout1_30_1: std_logic; + signal mdout1_29_1: std_logic; + signal mdout1_28_1: std_logic; + signal mdout1_27_1: std_logic; + signal mdout1_26_1: std_logic; + signal mdout1_25_1: std_logic; + signal mdout1_24_1: std_logic; + signal mdout1_23_1: std_logic; + signal mdout1_22_1: std_logic; + signal mdout1_21_1: std_logic; + signal mdout1_20_1: std_logic; + signal mdout1_19_1: std_logic; + signal mdout1_18_1: std_logic; + signal mdout1_17_1: std_logic; + signal mdout1_16_1: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_31_2: std_logic; + signal mdout1_30_2: std_logic; + signal mdout1_29_2: std_logic; + signal mdout1_28_2: std_logic; + signal mdout1_27_2: std_logic; + signal mdout1_26_2: std_logic; + signal mdout1_25_2: std_logic; + signal mdout1_24_2: std_logic; + signal mdout1_23_2: std_logic; + signal mdout1_22_2: std_logic; + signal mdout1_21_2: std_logic; + signal mdout1_20_2: std_logic; + signal mdout1_19_2: std_logic; + signal mdout1_18_2: std_logic; + signal mdout1_17_2: std_logic; + signal mdout1_16_2: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_31_3: std_logic; + signal mdout1_30_3: std_logic; + signal mdout1_29_3: std_logic; + signal mdout1_28_3: std_logic; + signal mdout1_27_3: std_logic; + signal mdout1_26_3: std_logic; + signal mdout1_25_3: std_logic; + signal mdout1_24_3: std_logic; + signal mdout1_23_3: std_logic; + signal mdout1_22_3: std_logic; + signal mdout1_21_3: std_logic; + signal mdout1_20_3: std_logic; + signal mdout1_19_3: std_logic; + signal mdout1_18_3: std_logic; + signal mdout1_17_3: std_logic; + signal mdout1_16_3: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_31_4: std_logic; + signal mdout1_30_4: std_logic; + signal mdout1_29_4: std_logic; + signal mdout1_28_4: std_logic; + signal mdout1_27_4: std_logic; + signal mdout1_26_4: std_logic; + signal mdout1_25_4: std_logic; + signal mdout1_24_4: std_logic; + signal mdout1_23_4: std_logic; + signal mdout1_22_4: std_logic; + signal mdout1_21_4: std_logic; + signal mdout1_20_4: std_logic; + signal mdout1_19_4: std_logic; + signal mdout1_18_4: std_logic; + signal mdout1_17_4: std_logic; + signal mdout1_16_4: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_31_5: std_logic; + signal mdout1_30_5: std_logic; + signal mdout1_29_5: std_logic; + signal mdout1_28_5: std_logic; + signal mdout1_27_5: std_logic; + signal mdout1_26_5: std_logic; + signal mdout1_25_5: std_logic; + signal mdout1_24_5: std_logic; + signal mdout1_23_5: std_logic; + signal mdout1_22_5: std_logic; + signal mdout1_21_5: std_logic; + signal mdout1_20_5: std_logic; + signal mdout1_19_5: std_logic; + signal mdout1_18_5: std_logic; + signal mdout1_17_5: std_logic; + signal mdout1_16_5: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_31_6: std_logic; + signal mdout1_30_6: std_logic; + signal mdout1_29_6: std_logic; + signal mdout1_28_6: std_logic; + signal mdout1_27_6: std_logic; + signal mdout1_26_6: std_logic; + signal mdout1_25_6: std_logic; + signal mdout1_24_6: std_logic; + signal mdout1_23_6: std_logic; + signal mdout1_22_6: std_logic; + signal mdout1_21_6: std_logic; + signal mdout1_20_6: std_logic; + signal mdout1_19_6: std_logic; + signal mdout1_18_6: std_logic; + signal mdout1_17_6: std_logic; + signal mdout1_16_6: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_31_7: std_logic; + signal mdout1_30_7: std_logic; + signal mdout1_29_7: std_logic; + signal mdout1_28_7: std_logic; + signal mdout1_27_7: std_logic; + signal mdout1_26_7: std_logic; + signal mdout1_25_7: std_logic; + signal mdout1_24_7: std_logic; + signal mdout1_23_7: std_logic; + signal mdout1_22_7: std_logic; + signal mdout1_21_7: std_logic; + signal mdout1_20_7: std_logic; + signal mdout1_19_7: std_logic; + signal mdout1_18_7: std_logic; + signal mdout1_17_7: std_logic; + signal mdout1_16_7: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_31_8: std_logic; + signal mdout1_30_8: std_logic; + signal mdout1_29_8: std_logic; + signal mdout1_28_8: std_logic; + signal mdout1_27_8: std_logic; + signal mdout1_26_8: std_logic; + signal mdout1_25_8: std_logic; + signal mdout1_24_8: std_logic; + signal mdout1_23_8: std_logic; + signal mdout1_22_8: std_logic; + signal mdout1_21_8: std_logic; + signal mdout1_20_8: std_logic; + signal mdout1_19_8: std_logic; + signal mdout1_18_8: std_logic; + signal mdout1_17_8: std_logic; + signal mdout1_16_8: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal wcount_r12: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_2: std_logic; + signal wcount_r14: std_logic; + signal wcount_r15: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal rcount_w12: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_3: std_logic; + signal rcount_w14: std_logic; + signal rcount_w15: std_logic; + signal wcount_14: std_logic; + signal wcount_15: std_logic; + signal co7_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX321 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; D16: in std_logic; D17: in std_logic; + D18: in std_logic; D19: in std_logic; D20: in std_logic; + D21: in std_logic; D22: in std_logic; D23: in std_logic; + D24: in std_logic; D25: in std_logic; D26: in std_logic; + D27: in std_logic; D28: in std_logic; D29: in std_logic; + D30: in std_logic; D31: in std_logic; SD1: in std_logic; + SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; + SD5: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; + attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; + attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; + attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; + attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; + attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; + attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; + attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; + attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; + attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; + attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; + attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; + attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; + attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; + attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; + attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; + attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; + attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; + attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; + attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; + attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; + attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; + attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; + attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; + attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; + attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; + attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; + attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; + attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; + attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; + attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; + attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t34: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_11: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t33: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_10: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t32: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t31: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t30: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t29: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t28: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t27: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t26: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t25: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t24: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t23: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t22: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t21: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t20: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t19: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t18: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t17: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t16: XOR2 + port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); + + XOR2_t15: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t14: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t13: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t12: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t11: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t10: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t9: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t8: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t7: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t6: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t5: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t4: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t3: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t2: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t1: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t0: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + INV_9: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_8: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_7: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_6: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + INV_5: INV + port map (A=>wptr_15, Z=>wptr_15_inv); + + LUT4_187: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet); + + LUT4_186: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_p00); + + INV_4: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_3: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_2: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_1: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + INV_0: INV + port map (A=>rptr_15, Z=>rptr_15_inv); + + LUT4_185: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_1); + + LUT4_184: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec1_r10); + + LUT4_183: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_2); + + LUT4_182: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec2_p01); + + LUT4_181: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_3); + + LUT4_180: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec3_r11); + + LUT4_179: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_4); + + LUT4_178: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec4_p02); + + LUT4_177: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_5); + + LUT4_176: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec5_r12); + + LUT4_175: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_6); + + LUT4_174: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec6_p03); + + LUT4_173: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_7); + + LUT4_172: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec7_r13); + + LUT4_171: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_8); + + LUT4_170: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec8_p04); + + LUT4_169: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_9); + + LUT4_168: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec9_r14); + + LUT4_167: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_10); + + LUT4_166: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); + + LUT4_165: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_11); + + LUT4_164: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); + + LUT4_163: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_12); + + LUT4_162: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); + + LUT4_161: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_13); + + LUT4_160: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); + + LUT4_159: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_14); + + LUT4_158: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); + + LUT4_157: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_15); + + LUT4_156: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); + + LUT4_155: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_16); + + LUT4_154: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); + + LUT4_153: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_17); + + LUT4_152: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); + + LUT4_151: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_18); + + LUT4_150: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); + + LUT4_149: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_19); + + LUT4_148: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); + + LUT4_147: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_20); + + LUT4_146: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); + + LUT4_145: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_21); + + LUT4_144: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); + + LUT4_143: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_22); + + LUT4_142: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); + + LUT4_141: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_23); + + LUT4_140: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); + + LUT4_139: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_24); + + LUT4_138: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); + + LUT4_137: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_25); + + LUT4_136: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); + + LUT4_135: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_26); + + LUT4_134: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); + + LUT4_133: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_27); + + LUT4_132: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); + + LUT4_131: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_28); + + LUT4_130: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); + + LUT4_129: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_29); + + LUT4_128: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); + + LUT4_127: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>func_and_inet_30); + + LUT4_126: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); + + LUT4_125: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_31); + + LUT4_124: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); + + LUT4_123: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_32); + + LUT4_122: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec32_p016); + + LUT4_121: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_33); + + LUT4_120: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec33_r116); + + LUT4_119: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_34); + + LUT4_118: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec34_p017); + + LUT4_117: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_35); + + LUT4_116: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec35_r117); + + LUT4_115: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_36); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec36_p018); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_37); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec37_r118); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_38); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec38_p019); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_39); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec39_r119); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_40); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec40_p020); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_41); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec41_r120); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_42); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec42_p021); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_43); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec43_r121); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_44); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec44_p022); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_45); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec45_r122); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_46); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec46_p023); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_47); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec47_r123); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_48); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec48_p024); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_49); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec49_r124); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_50); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec50_p025); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_51); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec51_r125); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_52); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec52_p026); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_53); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec53_r126); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_54); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec54_p027); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_55); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec55_r127); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_56); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec56_p028); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_57); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec57_r128); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_58); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec58_p029); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_59); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec59_r129); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_60); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec60_p030); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_61); + + LUT4_64: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec61_r130); + + LUT4_63: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>func_and_inet_62); + + LUT4_62: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec62_p031); + + LUT4_61: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_63); + + LUT4_60: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec63_r131); + + LUT4_59: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>w_gcount_r216, + DO0=>w_g2b_xor_cluster_0); + + LUT4_58: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_1); + + LUT4_57: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_2); + + LUT4_56: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_3); + + LUT4_55: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r15); + + LUT4_54: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, + AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_53: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, + DO0=>wcount_r10); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r3); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r2); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r1); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_10); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, + AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, + DO0=>func_xor_inet_11); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, + DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, + DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, + DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_11_0_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, + DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, + DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, + DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_12_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, + DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, + DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, + DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_13_0_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, + DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, + DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, + DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_14_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, + DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, + DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, + DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_15_0_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, + DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, + DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, + DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_16_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec32_p016, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec33_r116, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, + DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, + DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, + DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_17_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec34_p017, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec35_r117, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, + DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, + DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, + DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_18_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec36_p018, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec37_r118, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, + DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, + DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, + DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_19_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec38_p019, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec39_r119, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, + DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, + DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, + DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_20_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec40_p020, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec41_r120, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, + DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, + DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, + DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_21_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec42_p021, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec43_r121, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, + DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, + DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, + DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_22_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec44_p022, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec45_r122, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, + DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, + DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, + DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_23_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec46_p023, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec47_r123, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, + DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, + DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, + DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_24_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec48_p024, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec49_r124, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, + DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, + DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, + DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_25_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec50_p025, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec51_r125, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, + DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, + DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, + DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_26_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec52_p026, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec53_r126, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, + DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, + DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, + DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_27_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec54_p027, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec55_r127, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, + DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, + DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, + DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_28_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec56_p028, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec57_r128, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, + DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, + DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, + DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_29_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec58_p029, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec59_r129, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, + DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, + DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, + DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_30_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec60_p030, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec61_r130, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, + DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, + DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, + DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_31_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec62_p031, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec63_r131, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, + DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, + DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, + DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + FF_176: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_175: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_174: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_173: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_172: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_171: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_170: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_169: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_168: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_167: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_166: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_165: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_164: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_163: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_162: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_161: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_160: FD1P3DX + port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_16); + + FF_159: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_158: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_157: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_156: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_155: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_154: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_153: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_152: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_151: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_150: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_149: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_148: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_147: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_146: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_145: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_144: FD1P3DX + port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_143: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_16); + + FF_142: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_141: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_140: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_139: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_138: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_137: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_136: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_135: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_134: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_133: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_132: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_131: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_130: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_129: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_128: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_127: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_126: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_16); + + FF_125: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_124: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_123: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_122: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_121: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_120: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_119: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_118: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_117: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_116: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_115: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_114: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_113: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_112: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_111: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_110: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_109: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_108: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_107: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_106: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_105: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_104: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_103: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_102: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_101: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_100: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_99: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_98: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_97: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_96: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_95: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_94: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_93: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_92: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_91: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_90: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_89: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_88: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_87: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_86: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_85: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_84: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_83: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_82: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_81: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_80: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_79: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_78: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_77: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_76: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_75: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_74: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_73: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_72: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_71: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_70: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_69: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_68: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_67: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_66: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_65: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_64: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_63: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_62: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_61: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_60: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_59: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_58: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_57: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_56: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_55: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_54: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_53: FD1S3DX + port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r16); + + FF_52: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_51: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_50: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_49: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_48: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_47: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_46: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_45: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_44: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_43: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_42: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_41: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_40: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_39: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_38: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_37: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_36: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_35: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_34: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_33: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_32: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_31: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_30: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_29: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_28: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_27: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_26: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_25: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_24: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_23: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_22: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_21: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_20: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_19: FD1S3DX + port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r216); + + FF_18: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_17: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_16: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_15: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_14: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_13: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_12: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_11: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_10: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_9: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_8: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_7: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_6: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_5: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_4: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_3: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_2: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + w_gctr_8: CU2 + port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>iwcount_16, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, + NC0=>ircount_16, NC1=>open); + + mux_8: MUX321 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, + D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, + D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, + D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, + D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, + D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(0)); + + mux_7: MUX321 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, + D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, + D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, + D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, + D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, + D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(1)); + + mux_6: MUX321 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, + D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, + D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, + D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, + D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, + D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(2)); + + mux_5: MUX321 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, + D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, + D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, + D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, + D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, + D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(3)); + + mux_4: MUX321 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, + D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, + D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, + D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, + D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, + D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(4)); + + mux_3: MUX321 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, + D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, + D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, + D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, + D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, + D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(5)); + + mux_2: MUX321 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, + D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, + D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, + D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, + D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, + D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(6)); + + mux_1: MUX321 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, + D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, + D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, + D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, + D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, + D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(7)); + + mux_0: MUX321 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, + D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, + D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, + D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, + D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, + D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(8)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, + B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, + B1=>wcount_r15, CI=>co6_2, GE=>co7_2); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_3, GE=>co7_3); + + full_cmp_8: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_64kx9 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX321 use entity ecp3.MUX321(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx9_af.lpc b/gbe_trb/ipcores/ecp3/fifo_64kx9_af.lpc new file mode 100644 index 0000000..c140a9c --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx9_af.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_64kx9_af +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/05/2015 +Time=16:55:11 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=65536 +Width=9 +RDepth=65536 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Dual Threshold +PfAssert=65500 +PfDeassert=65490 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_64kx9_af -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf 65500 -pf2 65490 diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd b/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd new file mode 100644 index 0000000..d1f37c6 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd @@ -0,0 +1,5075 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n fifo_64kx9_af -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf 65500 -pf2 65490 + +-- Wed Aug 5 16:55:11 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_64kx9_af is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_64kx9_af; + +architecture Structure of fifo_64kx9_af is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal func_and_inet_13: std_logic; + signal func_and_inet_14: std_logic; + signal func_and_inet_15: std_logic; + signal func_and_inet_16: std_logic; + signal func_and_inet_17: std_logic; + signal func_and_inet_18: std_logic; + signal func_and_inet_19: std_logic; + signal func_and_inet_20: std_logic; + signal func_and_inet_21: std_logic; + signal func_and_inet_22: std_logic; + signal func_and_inet_23: std_logic; + signal func_and_inet_24: std_logic; + signal func_and_inet_25: std_logic; + signal func_and_inet_26: std_logic; + signal func_and_inet_27: std_logic; + signal func_and_inet_28: std_logic; + signal func_and_inet_29: std_logic; + signal wptr_15_inv: std_logic; + signal func_and_inet_30: std_logic; + signal rptr_15_inv: std_logic; + signal func_and_inet_31: std_logic; + signal func_and_inet_32: std_logic; + signal func_and_inet_33: std_logic; + signal func_and_inet_34: std_logic; + signal func_and_inet_35: std_logic; + signal func_and_inet_36: std_logic; + signal func_and_inet_37: std_logic; + signal func_and_inet_38: std_logic; + signal func_and_inet_39: std_logic; + signal func_and_inet_40: std_logic; + signal func_and_inet_41: std_logic; + signal func_and_inet_42: std_logic; + signal func_and_inet_43: std_logic; + signal func_and_inet_44: std_logic; + signal func_and_inet_45: std_logic; + signal wptr_14_inv: std_logic; + signal func_and_inet_46: std_logic; + signal rptr_14_inv: std_logic; + signal func_and_inet_47: std_logic; + signal func_and_inet_48: std_logic; + signal func_and_inet_49: std_logic; + signal func_and_inet_50: std_logic; + signal func_and_inet_51: std_logic; + signal func_and_inet_52: std_logic; + signal func_and_inet_53: std_logic; + signal wptr_13_inv: std_logic; + signal func_and_inet_54: std_logic; + signal rptr_13_inv: std_logic; + signal func_and_inet_55: std_logic; + signal func_and_inet_56: std_logic; + signal func_and_inet_57: std_logic; + signal wptr_12_inv: std_logic; + signal func_and_inet_58: std_logic; + signal rptr_12_inv: std_logic; + signal func_and_inet_59: std_logic; + signal wptr_11_inv: std_logic; + signal func_and_inet_60: std_logic; + signal rptr_11_inv: std_logic; + signal func_and_inet_61: std_logic; + signal func_and_inet_62: std_logic; + signal func_and_inet_63: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_9: std_logic; + signal func_xor_inet_8: std_logic; + signal func_xor_inet_7: std_logic; + signal func_xor_inet_6: std_logic; + signal func_xor_inet_10: std_logic; + signal func_xor_inet_11: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r11: std_logic; + signal dec2_p01: std_logic; + signal dec5_r12: std_logic; + signal dec4_p02: std_logic; + signal dec7_r13: std_logic; + signal dec6_p03: std_logic; + signal dec9_r14: std_logic; + signal dec8_p04: std_logic; + signal dec11_r15: std_logic; + signal dec10_p05: std_logic; + signal dec13_r16: std_logic; + signal dec12_p06: std_logic; + signal dec15_r17: std_logic; + signal dec14_p07: std_logic; + signal dec17_r18: std_logic; + signal dec16_p08: std_logic; + signal dec19_r19: std_logic; + signal dec18_p09: std_logic; + signal dec21_r110: std_logic; + signal dec20_p010: std_logic; + signal dec23_r111: std_logic; + signal dec22_p011: std_logic; + signal dec25_r112: std_logic; + signal dec24_p012: std_logic; + signal dec27_r113: std_logic; + signal dec26_p013: std_logic; + signal dec29_r114: std_logic; + signal dec28_p014: std_logic; + signal dec31_r115: std_logic; + signal dec30_p015: std_logic; + signal dec33_r116: std_logic; + signal dec32_p016: std_logic; + signal dec35_r117: std_logic; + signal dec34_p017: std_logic; + signal dec37_r118: std_logic; + signal dec36_p018: std_logic; + signal dec39_r119: std_logic; + signal dec38_p019: std_logic; + signal dec41_r120: std_logic; + signal dec40_p020: std_logic; + signal dec43_r121: std_logic; + signal dec42_p021: std_logic; + signal dec45_r122: std_logic; + signal dec44_p022: std_logic; + signal dec47_r123: std_logic; + signal dec46_p023: std_logic; + signal dec49_r124: std_logic; + signal dec48_p024: std_logic; + signal dec51_r125: std_logic; + signal dec50_p025: std_logic; + signal dec53_r126: std_logic; + signal dec52_p026: std_logic; + signal dec55_r127: std_logic; + signal dec54_p027: std_logic; + signal dec57_r128: std_logic; + signal dec56_p028: std_logic; + signal dec59_r129: std_logic; + signal dec58_p029: std_logic; + signal dec61_r130: std_logic; + signal dec60_p030: std_logic; + signal dec63_r131: std_logic; + signal dec62_p031: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal w_gdata_15: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wptr_15: std_logic; + signal wptr_16: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_16: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal w_gcount_16: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal w_gcount_r216: std_logic; + signal w_gcount_r16: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal af: std_logic; + signal af_d: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co6: std_logic; + signal iwcount_16: std_logic; + signal co8: std_logic; + signal co7: std_logic; + signal wcount_16: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8_1: std_logic; + signal co7_1: std_logic; + signal rcount_16: std_logic; + signal mdout1_31_0: std_logic; + signal mdout1_30_0: std_logic; + signal mdout1_29_0: std_logic; + signal mdout1_28_0: std_logic; + signal mdout1_27_0: std_logic; + signal mdout1_26_0: std_logic; + signal mdout1_25_0: std_logic; + signal mdout1_24_0: std_logic; + signal mdout1_23_0: std_logic; + signal mdout1_22_0: std_logic; + signal mdout1_21_0: std_logic; + signal mdout1_20_0: std_logic; + signal mdout1_19_0: std_logic; + signal mdout1_18_0: std_logic; + signal mdout1_17_0: std_logic; + signal mdout1_16_0: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_31_1: std_logic; + signal mdout1_30_1: std_logic; + signal mdout1_29_1: std_logic; + signal mdout1_28_1: std_logic; + signal mdout1_27_1: std_logic; + signal mdout1_26_1: std_logic; + signal mdout1_25_1: std_logic; + signal mdout1_24_1: std_logic; + signal mdout1_23_1: std_logic; + signal mdout1_22_1: std_logic; + signal mdout1_21_1: std_logic; + signal mdout1_20_1: std_logic; + signal mdout1_19_1: std_logic; + signal mdout1_18_1: std_logic; + signal mdout1_17_1: std_logic; + signal mdout1_16_1: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_31_2: std_logic; + signal mdout1_30_2: std_logic; + signal mdout1_29_2: std_logic; + signal mdout1_28_2: std_logic; + signal mdout1_27_2: std_logic; + signal mdout1_26_2: std_logic; + signal mdout1_25_2: std_logic; + signal mdout1_24_2: std_logic; + signal mdout1_23_2: std_logic; + signal mdout1_22_2: std_logic; + signal mdout1_21_2: std_logic; + signal mdout1_20_2: std_logic; + signal mdout1_19_2: std_logic; + signal mdout1_18_2: std_logic; + signal mdout1_17_2: std_logic; + signal mdout1_16_2: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_31_3: std_logic; + signal mdout1_30_3: std_logic; + signal mdout1_29_3: std_logic; + signal mdout1_28_3: std_logic; + signal mdout1_27_3: std_logic; + signal mdout1_26_3: std_logic; + signal mdout1_25_3: std_logic; + signal mdout1_24_3: std_logic; + signal mdout1_23_3: std_logic; + signal mdout1_22_3: std_logic; + signal mdout1_21_3: std_logic; + signal mdout1_20_3: std_logic; + signal mdout1_19_3: std_logic; + signal mdout1_18_3: std_logic; + signal mdout1_17_3: std_logic; + signal mdout1_16_3: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_31_4: std_logic; + signal mdout1_30_4: std_logic; + signal mdout1_29_4: std_logic; + signal mdout1_28_4: std_logic; + signal mdout1_27_4: std_logic; + signal mdout1_26_4: std_logic; + signal mdout1_25_4: std_logic; + signal mdout1_24_4: std_logic; + signal mdout1_23_4: std_logic; + signal mdout1_22_4: std_logic; + signal mdout1_21_4: std_logic; + signal mdout1_20_4: std_logic; + signal mdout1_19_4: std_logic; + signal mdout1_18_4: std_logic; + signal mdout1_17_4: std_logic; + signal mdout1_16_4: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_31_5: std_logic; + signal mdout1_30_5: std_logic; + signal mdout1_29_5: std_logic; + signal mdout1_28_5: std_logic; + signal mdout1_27_5: std_logic; + signal mdout1_26_5: std_logic; + signal mdout1_25_5: std_logic; + signal mdout1_24_5: std_logic; + signal mdout1_23_5: std_logic; + signal mdout1_22_5: std_logic; + signal mdout1_21_5: std_logic; + signal mdout1_20_5: std_logic; + signal mdout1_19_5: std_logic; + signal mdout1_18_5: std_logic; + signal mdout1_17_5: std_logic; + signal mdout1_16_5: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_31_6: std_logic; + signal mdout1_30_6: std_logic; + signal mdout1_29_6: std_logic; + signal mdout1_28_6: std_logic; + signal mdout1_27_6: std_logic; + signal mdout1_26_6: std_logic; + signal mdout1_25_6: std_logic; + signal mdout1_24_6: std_logic; + signal mdout1_23_6: std_logic; + signal mdout1_22_6: std_logic; + signal mdout1_21_6: std_logic; + signal mdout1_20_6: std_logic; + signal mdout1_19_6: std_logic; + signal mdout1_18_6: std_logic; + signal mdout1_17_6: std_logic; + signal mdout1_16_6: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_31_7: std_logic; + signal mdout1_30_7: std_logic; + signal mdout1_29_7: std_logic; + signal mdout1_28_7: std_logic; + signal mdout1_27_7: std_logic; + signal mdout1_26_7: std_logic; + signal mdout1_25_7: std_logic; + signal mdout1_24_7: std_logic; + signal mdout1_23_7: std_logic; + signal mdout1_22_7: std_logic; + signal mdout1_21_7: std_logic; + signal mdout1_20_7: std_logic; + signal mdout1_19_7: std_logic; + signal mdout1_18_7: std_logic; + signal mdout1_17_7: std_logic; + signal mdout1_16_7: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_31_8: std_logic; + signal mdout1_30_8: std_logic; + signal mdout1_29_8: std_logic; + signal mdout1_28_8: std_logic; + signal mdout1_27_8: std_logic; + signal mdout1_26_8: std_logic; + signal mdout1_25_8: std_logic; + signal mdout1_24_8: std_logic; + signal mdout1_23_8: std_logic; + signal mdout1_22_8: std_logic; + signal mdout1_21_8: std_logic; + signal mdout1_20_8: std_logic; + signal mdout1_19_8: std_logic; + signal mdout1_18_8: std_logic; + signal mdout1_17_8: std_logic; + signal mdout1_16_8: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal wcount_r12: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_2: std_logic; + signal wcount_r14: std_logic; + signal wcount_r15: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_3: std_logic; + signal wcount_14: std_logic; + signal wcount_15: std_logic; + signal co7_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co1_4: std_logic; + signal iaf_setcount_6: std_logic; + signal iaf_setcount_7: std_logic; + signal co2_4: std_logic; + signal iaf_setcount_8: std_logic; + signal iaf_setcount_9: std_logic; + signal co3_4: std_logic; + signal iaf_setcount_10: std_logic; + signal iaf_setcount_11: std_logic; + signal co4_4: std_logic; + signal iaf_setcount_12: std_logic; + signal iaf_setcount_13: std_logic; + signal co5_4: std_logic; + signal iaf_setcount_14: std_logic; + signal iaf_setcount_15: std_logic; + signal co6_4: std_logic; + signal iaf_setcount_16: std_logic; + signal co8_2: std_logic; + signal co7_4: std_logic; + signal af_setcount_16: std_logic; + signal cmp_ci_2: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal af_setcount_4: std_logic; + signal af_setcount_5: std_logic; + signal co2_5: std_logic; + signal af_setcount_6: std_logic; + signal af_setcount_7: std_logic; + signal co3_5: std_logic; + signal af_setcount_8: std_logic; + signal af_setcount_9: std_logic; + signal co4_5: std_logic; + signal af_setcount_10: std_logic; + signal af_setcount_11: std_logic; + signal co5_5: std_logic; + signal af_setcount_12: std_logic; + signal af_setcount_13: std_logic; + signal co6_5: std_logic; + signal af_setcount_14: std_logic; + signal af_setcount_15: std_logic; + signal co7_5: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_clrcount_0: std_logic; + signal iaf_clrcount_1: std_logic; + signal af_clr_ctr_ci: std_logic; + signal iaf_clrcount_2: std_logic; + signal iaf_clrcount_3: std_logic; + signal co0_6: std_logic; + signal iaf_clrcount_4: std_logic; + signal iaf_clrcount_5: std_logic; + signal co1_6: std_logic; + signal iaf_clrcount_6: std_logic; + signal iaf_clrcount_7: std_logic; + signal co2_6: std_logic; + signal iaf_clrcount_8: std_logic; + signal iaf_clrcount_9: std_logic; + signal co3_6: std_logic; + signal iaf_clrcount_10: std_logic; + signal iaf_clrcount_11: std_logic; + signal co4_6: std_logic; + signal iaf_clrcount_12: std_logic; + signal iaf_clrcount_13: std_logic; + signal co5_6: std_logic; + signal iaf_clrcount_14: std_logic; + signal iaf_clrcount_15: std_logic; + signal co6_6: std_logic; + signal iaf_clrcount_16: std_logic; + signal co8_3: std_logic; + signal co7_6: std_logic; + signal af_clrcount_16: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_clrcount_0: std_logic; + signal af_clrcount_1: std_logic; + signal co0_7: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_clrcount_2: std_logic; + signal af_clrcount_3: std_logic; + signal co1_7: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal af_clrcount_4: std_logic; + signal af_clrcount_5: std_logic; + signal co2_7: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal af_clrcount_6: std_logic; + signal af_clrcount_7: std_logic; + signal co3_7: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal af_clrcount_8: std_logic; + signal af_clrcount_9: std_logic; + signal co4_7: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal af_clrcount_10: std_logic; + signal af_clrcount_11: std_logic; + signal co5_7: std_logic; + signal rcount_w12: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal af_clrcount_12: std_logic; + signal af_clrcount_13: std_logic; + signal co6_7: std_logic; + signal rcount_w14: std_logic; + signal rcount_w15: std_logic; + signal af_clrcount_14: std_logic; + signal af_clrcount_15: std_logic; + signal co7_7: std_logic; + signal af_clr_cmp_clr: std_logic; + signal af_clr_cmp_set: std_logic; + signal af_clr: std_logic; + signal af_clr_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX321 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; D16: in std_logic; D17: in std_logic; + D18: in std_logic; D19: in std_logic; D20: in std_logic; + D21: in std_logic; D22: in std_logic; D23: in std_logic; + D24: in std_logic; D25: in std_logic; D26: in std_logic; + D27: in std_logic; D28: in std_logic; D29: in std_logic; + D30: in std_logic; D31: in std_logic; SD1: in std_logic; + SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; + SD5: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; + attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; + attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; + attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; + attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; + attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; + attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; + attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; + attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; + attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; + attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; + attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; + attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; + attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; + attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; + attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; + attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; + attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; + attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; + attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; + attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; + attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; + attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; + attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; + attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; + attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; + attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; + attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; + attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; + attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; + attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9_af.lpc"; + attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; + attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; + attribute GSR of FF_211 : label is "ENABLED"; + attribute GSR of FF_210 : label is "ENABLED"; + attribute GSR of FF_209 : label is "ENABLED"; + attribute GSR of FF_208 : label is "ENABLED"; + attribute GSR of FF_207 : label is "ENABLED"; + attribute GSR of FF_206 : label is "ENABLED"; + attribute GSR of FF_205 : label is "ENABLED"; + attribute GSR of FF_204 : label is "ENABLED"; + attribute GSR of FF_203 : label is "ENABLED"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t34: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_11: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t33: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_10: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t32: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t31: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t30: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t29: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t28: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t27: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t26: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t25: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t24: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t23: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t22: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t21: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t20: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t19: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t18: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t17: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t16: XOR2 + port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); + + XOR2_t15: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t14: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t13: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t12: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t11: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t10: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t9: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t8: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t7: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t6: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t5: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t4: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t3: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t2: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t1: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t0: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + INV_9: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_8: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_7: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_6: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + INV_5: INV + port map (A=>wptr_15, Z=>wptr_15_inv); + + LUT4_192: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet); + + LUT4_191: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_p00); + + INV_4: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_3: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_2: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_1: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + INV_0: INV + port map (A=>rptr_15, Z=>rptr_15_inv); + + LUT4_190: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_1); + + LUT4_189: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec1_r10); + + LUT4_188: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_2); + + LUT4_187: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec2_p01); + + LUT4_186: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_3); + + LUT4_185: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec3_r11); + + LUT4_184: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_4); + + LUT4_183: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec4_p02); + + LUT4_182: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_5); + + LUT4_181: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec5_r12); + + LUT4_180: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_6); + + LUT4_179: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec6_p03); + + LUT4_178: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_7); + + LUT4_177: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec7_r13); + + LUT4_176: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_8); + + LUT4_175: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec8_p04); + + LUT4_174: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_9); + + LUT4_173: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec9_r14); + + LUT4_172: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_10); + + LUT4_171: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); + + LUT4_170: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_11); + + LUT4_169: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); + + LUT4_168: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_12); + + LUT4_167: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); + + LUT4_166: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_13); + + LUT4_165: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); + + LUT4_164: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_14); + + LUT4_163: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); + + LUT4_162: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_15); + + LUT4_161: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); + + LUT4_160: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_16); + + LUT4_159: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); + + LUT4_158: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_17); + + LUT4_157: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); + + LUT4_156: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_18); + + LUT4_155: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); + + LUT4_154: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_19); + + LUT4_153: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); + + LUT4_152: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_20); + + LUT4_151: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); + + LUT4_150: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_21); + + LUT4_149: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); + + LUT4_148: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_22); + + LUT4_147: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); + + LUT4_146: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_23); + + LUT4_145: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); + + LUT4_144: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_24); + + LUT4_143: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); + + LUT4_142: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_25); + + LUT4_141: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); + + LUT4_140: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_26); + + LUT4_139: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); + + LUT4_138: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_27); + + LUT4_137: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); + + LUT4_136: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_28); + + LUT4_135: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); + + LUT4_134: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_29); + + LUT4_133: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); + + LUT4_132: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>func_and_inet_30); + + LUT4_131: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); + + LUT4_130: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_31); + + LUT4_129: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); + + LUT4_128: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_32); + + LUT4_127: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec32_p016); + + LUT4_126: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_33); + + LUT4_125: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec33_r116); + + LUT4_124: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_34); + + LUT4_123: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec34_p017); + + LUT4_122: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_35); + + LUT4_121: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec35_r117); + + LUT4_120: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_36); + + LUT4_119: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec36_p018); + + LUT4_118: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_37); + + LUT4_117: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec37_r118); + + LUT4_116: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_38); + + LUT4_115: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec38_p019); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_39); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec39_r119); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_40); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec40_p020); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_41); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec41_r120); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_42); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec42_p021); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_43); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec43_r121); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_44); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec44_p022); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_45); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec45_r122); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_46); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec46_p023); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_47); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec47_r123); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_48); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec48_p024); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_49); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec49_r124); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_50); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec50_p025); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_51); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec51_r125); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_52); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec52_p026); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_53); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec53_r126); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_54); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec54_p027); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_55); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec55_r127); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_56); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec56_p028); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_57); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec57_r128); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_58); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec58_p029); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_59); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec59_r129); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_60); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec60_p030); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_61); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec61_r130); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>func_and_inet_62); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec62_p031); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_63); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec63_r131); + + LUT4_64: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>w_gcount_r216, + DO0=>w_g2b_xor_cluster_0); + + LUT4_63: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_1); + + LUT4_62: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_2); + + LUT4_61: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_3); + + LUT4_60: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r15); + + LUT4_59: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, + AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_58: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); + + LUT4_57: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_56: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, + DO0=>wcount_r10); + + LUT4_55: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_54: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_53: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r3); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r2); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r1); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_10); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, + AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, + DO0=>func_xor_inet_11); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_8: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_7: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_6: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_5: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_4: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_16, AD2=>wcount_16, + AD1=>r_gcount_w216, AD0=>wptr_16, DO0=>af_set_cmp_set); + + LUT4_3: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_16, AD2=>wcount_16, + AD1=>r_gcount_w216, AD0=>wptr_16, DO0=>af_set_cmp_clr); + + LUT4_2: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_clrcount_16, AD2=>wcount_16, + AD1=>r_gcount_w216, AD0=>wptr_16, DO0=>af_clr_cmp_set); + + LUT4_1: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_clrcount_16, AD2=>wcount_16, + AD1=>r_gcount_w216, AD0=>wptr_16, DO0=>af_clr_cmp_clr); + + LUT4_0: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>af, AD2=>af_set, AD1=>af_clr, AD0=>scuba_vlo, + DO0=>af_d); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, + DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, + DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, + DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_11_0_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, + DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, + DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, + DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_12_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, + DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, + DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, + DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_13_0_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, + DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, + DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, + DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_14_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, + DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, + DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, + DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_15_0_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, + DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, + DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, + DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_16_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec32_p016, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec33_r116, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, + DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, + DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, + DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_17_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec34_p017, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec35_r117, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, + DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, + DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, + DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_18_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec36_p018, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec37_r118, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, + DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, + DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, + DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_19_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec38_p019, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec39_r119, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, + DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, + DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, + DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_20_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec40_p020, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec41_r120, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, + DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, + DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, + DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_21_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec42_p021, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec43_r121, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, + DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, + DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, + DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_22_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec44_p022, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec45_r122, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, + DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, + DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, + DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_23_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec46_p023, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec47_r123, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, + DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, + DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, + DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_24_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec48_p024, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec49_r124, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, + DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, + DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, + DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_25_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec50_p025, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec51_r125, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, + DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, + DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, + DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_26_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec52_p026, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec53_r126, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, + DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, + DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, + DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_27_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec54_p027, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec55_r127, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, + DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, + DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, + DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_28_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec56_p028, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec57_r128, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, + DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, + DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, + DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_29_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec58_p029, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec59_r129, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, + DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, + DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, + DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_30_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec60_p030, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec61_r130, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, + DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, + DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, + DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_31_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec62_p031, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec63_r131, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, + DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, + DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, + DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + FF_211: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_210: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_209: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_208: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_207: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_206: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_205: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_204: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_203: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_202: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_201: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_200: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_199: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_198: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_197: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_196: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_195: FD1P3DX + port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_16); + + FF_194: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_193: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_192: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_191: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_190: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_189: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_188: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_187: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_186: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_185: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_184: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_183: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_182: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_181: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_180: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_179: FD1P3DX + port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_178: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_16); + + FF_177: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_176: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_175: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_174: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_173: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_172: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_171: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_170: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_169: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_168: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_167: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_166: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_165: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_164: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_163: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_162: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_161: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_16); + + FF_160: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_159: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_158: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_157: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_156: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_155: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_154: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_153: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_152: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_151: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_150: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_149: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_148: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_147: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_146: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_145: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_144: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_143: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_142: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_141: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_140: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_139: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_138: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_137: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_136: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_135: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_134: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_133: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_132: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_131: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_130: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_129: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_128: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_127: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_126: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_125: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_124: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_123: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_122: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_121: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_120: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_119: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_118: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_117: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_116: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_115: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_114: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_113: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_112: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_111: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_110: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_109: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_108: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_107: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_106: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_105: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_104: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_103: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_102: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_101: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_100: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_99: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_98: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_97: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_96: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_95: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_94: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_93: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_92: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_91: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_90: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_89: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_88: FD1S3DX + port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r16); + + FF_87: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_86: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_85: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_84: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_83: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_82: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_81: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_80: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_79: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_78: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_77: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_76: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_75: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_74: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_73: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_72: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_71: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_70: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_69: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_68: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_67: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_66: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_65: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_64: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_63: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_62: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_61: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_60: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_59: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_58: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_57: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_56: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_55: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_54: FD1S3DX + port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r216); + + FF_53: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_52: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_51: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_50: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_49: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_48: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_47: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_46: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_45: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_44: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_43: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_42: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_41: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_40: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_39: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_38: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_37: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_36: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_35: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_34: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); + + FF_33: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); + + FF_32: FD1P3BX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_2); + + FF_31: FD1P3DX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_3); + + FF_30: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_29: FD1P3BX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_5); + + FF_28: FD1P3DX + port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_6); + + FF_27: FD1P3DX + port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_7); + + FF_26: FD1P3DX + port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_8); + + FF_25: FD1P3DX + port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_9); + + FF_24: FD1P3DX + port map (D=>iaf_setcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_10); + + FF_23: FD1P3DX + port map (D=>iaf_setcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_11); + + FF_22: FD1P3DX + port map (D=>iaf_setcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_12); + + FF_21: FD1P3DX + port map (D=>iaf_setcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_13); + + FF_20: FD1P3DX + port map (D=>iaf_setcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_14); + + FF_19: FD1P3DX + port map (D=>iaf_setcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_15); + + FF_18: FD1P3DX + port map (D=>iaf_setcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_16); + + FF_17: FD1P3BX + port map (D=>iaf_clrcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_0); + + FF_16: FD1P3BX + port map (D=>iaf_clrcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_1); + + FF_15: FD1P3BX + port map (D=>iaf_clrcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_2); + + FF_14: FD1P3BX + port map (D=>iaf_clrcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_3); + + FF_13: FD1P3DX + port map (D=>iaf_clrcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_4); + + FF_12: FD1P3BX + port map (D=>iaf_clrcount_5, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_5); + + FF_11: FD1P3DX + port map (D=>iaf_clrcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_6); + + FF_10: FD1P3DX + port map (D=>iaf_clrcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_7); + + FF_9: FD1P3DX + port map (D=>iaf_clrcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_8); + + FF_8: FD1P3DX + port map (D=>iaf_clrcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_9); + + FF_7: FD1P3DX + port map (D=>iaf_clrcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_10); + + FF_6: FD1P3DX + port map (D=>iaf_clrcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_11); + + FF_5: FD1P3DX + port map (D=>iaf_clrcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_12); + + FF_4: FD1P3DX + port map (D=>iaf_clrcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_13); + + FF_3: FD1P3DX + port map (D=>iaf_clrcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_14); + + FF_2: FD1P3DX + port map (D=>iaf_clrcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_15); + + FF_1: FD1P3DX + port map (D=>iaf_clrcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_16); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>af); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + w_gctr_8: CU2 + port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>iwcount_16, NC1=>open); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, + NC0=>ircount_16, NC1=>open); + + mux_8: MUX321 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, + D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, + D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, + D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, + D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, + D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(0)); + + mux_7: MUX321 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, + D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, + D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, + D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, + D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, + D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(1)); + + mux_6: MUX321 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, + D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, + D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, + D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, + D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, + D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(2)); + + mux_5: MUX321 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, + D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, + D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, + D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, + D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, + D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(3)); + + mux_4: MUX321 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, + D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, + D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, + D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, + D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, + D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(4)); + + mux_3: MUX321 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, + D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, + D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, + D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, + D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, + D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(5)); + + mux_2: MUX321 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, + D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, + D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, + D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, + D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, + D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(6)); + + mux_1: MUX321 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, + D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, + D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, + D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, + D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, + D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(7)); + + mux_0: MUX321 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, + D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, + D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, + D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, + D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, + D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(8)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, + B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, + B1=>wcount_r15, CI=>co6_2, GE=>co7_2); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_3, GE=>co7_3); + + full_cmp_8: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, + CO=>co2_4, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); + + af_set_ctr_3: CU2 + port map (CI=>co2_4, PC0=>af_setcount_6, PC1=>af_setcount_7, + CO=>co3_4, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7); + + af_set_ctr_4: CU2 + port map (CI=>co3_4, PC0=>af_setcount_8, PC1=>af_setcount_9, + CO=>co4_4, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9); + + af_set_ctr_5: CU2 + port map (CI=>co4_4, PC0=>af_setcount_10, PC1=>af_setcount_11, + CO=>co5_4, NC0=>iaf_setcount_10, NC1=>iaf_setcount_11); + + af_set_ctr_6: CU2 + port map (CI=>co5_4, PC0=>af_setcount_12, PC1=>af_setcount_13, + CO=>co6_4, NC0=>iaf_setcount_12, NC1=>iaf_setcount_13); + + af_set_ctr_7: CU2 + port map (CI=>co6_4, PC0=>af_setcount_14, PC1=>af_setcount_15, + CO=>co7_4, NC0=>iaf_setcount_14, NC1=>iaf_setcount_15); + + af_set_ctr_8: CU2 + port map (CI=>co7_4, PC0=>af_setcount_16, PC1=>scuba_vlo, + CO=>co8_2, NC0=>iaf_setcount_16, NC1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_5, GE=>co2_5); + + af_set_cmp_3: AGEB2 + port map (A0=>af_setcount_6, A1=>af_setcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_5, GE=>co3_5); + + af_set_cmp_4: AGEB2 + port map (A0=>af_setcount_8, A1=>af_setcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_5, GE=>co4_5); + + af_set_cmp_5: AGEB2 + port map (A0=>af_setcount_10, A1=>af_setcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_5, GE=>co5_5); + + af_set_cmp_6: AGEB2 + port map (A0=>af_setcount_12, A1=>af_setcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_5, GE=>co6_5); + + af_set_cmp_7: AGEB2 + port map (A0=>af_setcount_14, A1=>af_setcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_5, GE=>co7_5); + + af_set_cmp_8: AGEB2 + port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr, + B1=>scuba_vlo, CI=>co7_5, GE=>af_set_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_clr_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_clr_ctr_ci, S0=>open, + S1=>open); + + af_clr_ctr_0: CU2 + port map (CI=>af_clr_ctr_ci, PC0=>af_clrcount_0, + PC1=>af_clrcount_1, CO=>co0_6, NC0=>iaf_clrcount_0, + NC1=>iaf_clrcount_1); + + af_clr_ctr_1: CU2 + port map (CI=>co0_6, PC0=>af_clrcount_2, PC1=>af_clrcount_3, + CO=>co1_6, NC0=>iaf_clrcount_2, NC1=>iaf_clrcount_3); + + af_clr_ctr_2: CU2 + port map (CI=>co1_6, PC0=>af_clrcount_4, PC1=>af_clrcount_5, + CO=>co2_6, NC0=>iaf_clrcount_4, NC1=>iaf_clrcount_5); + + af_clr_ctr_3: CU2 + port map (CI=>co2_6, PC0=>af_clrcount_6, PC1=>af_clrcount_7, + CO=>co3_6, NC0=>iaf_clrcount_6, NC1=>iaf_clrcount_7); + + af_clr_ctr_4: CU2 + port map (CI=>co3_6, PC0=>af_clrcount_8, PC1=>af_clrcount_9, + CO=>co4_6, NC0=>iaf_clrcount_8, NC1=>iaf_clrcount_9); + + af_clr_ctr_5: CU2 + port map (CI=>co4_6, PC0=>af_clrcount_10, PC1=>af_clrcount_11, + CO=>co5_6, NC0=>iaf_clrcount_10, NC1=>iaf_clrcount_11); + + af_clr_ctr_6: CU2 + port map (CI=>co5_6, PC0=>af_clrcount_12, PC1=>af_clrcount_13, + CO=>co6_6, NC0=>iaf_clrcount_12, NC1=>iaf_clrcount_13); + + af_clr_ctr_7: CU2 + port map (CI=>co6_6, PC0=>af_clrcount_14, PC1=>af_clrcount_15, + CO=>co7_6, NC0=>iaf_clrcount_14, NC1=>iaf_clrcount_15); + + af_clr_ctr_8: CU2 + port map (CI=>co7_6, PC0=>af_clrcount_16, PC1=>scuba_vlo, + CO=>co8_3, NC0=>iaf_clrcount_16, NC1=>open); + + af_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_clr_cmp_0: AGEB2 + port map (A0=>af_clrcount_0, A1=>af_clrcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_7); + + af_clr_cmp_1: AGEB2 + port map (A0=>af_clrcount_2, A1=>af_clrcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_7, GE=>co1_7); + + af_clr_cmp_2: AGEB2 + port map (A0=>af_clrcount_4, A1=>af_clrcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_7, GE=>co2_7); + + af_clr_cmp_3: AGEB2 + port map (A0=>af_clrcount_6, A1=>af_clrcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_7, GE=>co3_7); + + af_clr_cmp_4: AGEB2 + port map (A0=>af_clrcount_8, A1=>af_clrcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_7, GE=>co4_7); + + af_clr_cmp_5: AGEB2 + port map (A0=>af_clrcount_10, A1=>af_clrcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_7, GE=>co5_7); + + af_clr_cmp_6: AGEB2 + port map (A0=>af_clrcount_12, A1=>af_clrcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_7, GE=>co6_7); + + af_clr_cmp_7: AGEB2 + port map (A0=>af_clrcount_14, A1=>af_clrcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_7, GE=>co7_7); + + af_clr_cmp_8: AGEB2 + port map (A0=>af_clr_cmp_set, A1=>scuba_vlo, B0=>af_clr_cmp_clr, + B1=>scuba_vlo, CI=>co7_7, GE=>af_clr_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_clr_c, COUT=>open, S0=>af_clr, + S1=>open); + + Empty <= empty_i; + Full <= full_i; + AlmostFull <= af; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_64kx9_af is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX321 use entity ecp3.MUX321(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_65536x18x9.lpc b/gbe_trb/ipcores/ecp3/fifo_65536x18x9.lpc new file mode 100644 index 0000000..fc672fb --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_65536x18x9.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_65536x18x9 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/19/2012 +Time=15:06:37 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=18 +RDepth=65536 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd b/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd new file mode 100644 index 0000000..9360064 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd @@ -0,0 +1,4493 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + +-- Sat May 19 15:06:38 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_65536x18x9 is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_65536x18x9; + +architecture Structure of fifo_65536x18x9 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal func_and_inet_13: std_logic; + signal func_and_inet_14: std_logic; + signal func_and_inet_15: std_logic; + signal func_and_inet_16: std_logic; + signal func_and_inet_17: std_logic; + signal func_and_inet_18: std_logic; + signal func_and_inet_19: std_logic; + signal func_and_inet_20: std_logic; + signal func_and_inet_21: std_logic; + signal func_and_inet_22: std_logic; + signal func_and_inet_23: std_logic; + signal func_and_inet_24: std_logic; + signal func_and_inet_25: std_logic; + signal func_and_inet_26: std_logic; + signal func_and_inet_27: std_logic; + signal func_and_inet_28: std_logic; + signal func_and_inet_29: std_logic; + signal wptr_14_inv: std_logic; + signal func_and_inet_30: std_logic; + signal rptr_15_inv: std_logic; + signal func_and_inet_31: std_logic; + signal func_and_inet_32: std_logic; + signal func_and_inet_33: std_logic; + signal func_and_inet_34: std_logic; + signal func_and_inet_35: std_logic; + signal func_and_inet_36: std_logic; + signal func_and_inet_37: std_logic; + signal func_and_inet_38: std_logic; + signal func_and_inet_39: std_logic; + signal func_and_inet_40: std_logic; + signal func_and_inet_41: std_logic; + signal func_and_inet_42: std_logic; + signal func_and_inet_43: std_logic; + signal func_and_inet_44: std_logic; + signal func_and_inet_45: std_logic; + signal wptr_13_inv: std_logic; + signal func_and_inet_46: std_logic; + signal rptr_14_inv: std_logic; + signal func_and_inet_47: std_logic; + signal func_and_inet_48: std_logic; + signal func_and_inet_49: std_logic; + signal func_and_inet_50: std_logic; + signal func_and_inet_51: std_logic; + signal func_and_inet_52: std_logic; + signal func_and_inet_53: std_logic; + signal wptr_12_inv: std_logic; + signal func_and_inet_54: std_logic; + signal rptr_13_inv: std_logic; + signal func_and_inet_55: std_logic; + signal func_and_inet_56: std_logic; + signal func_and_inet_57: std_logic; + signal wptr_11_inv: std_logic; + signal func_and_inet_58: std_logic; + signal rptr_12_inv: std_logic; + signal func_and_inet_59: std_logic; + signal wptr_10_inv: std_logic; + signal func_and_inet_60: std_logic; + signal rptr_11_inv: std_logic; + signal func_and_inet_61: std_logic; + signal func_and_inet_62: std_logic; + signal func_and_inet_63: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal rcount_w0: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r11: std_logic; + signal dec2_p01: std_logic; + signal dec5_r12: std_logic; + signal dec4_p02: std_logic; + signal dec7_r13: std_logic; + signal dec6_p03: std_logic; + signal dec9_r14: std_logic; + signal dec8_p04: std_logic; + signal dec11_r15: std_logic; + signal dec10_p05: std_logic; + signal dec13_r16: std_logic; + signal dec12_p06: std_logic; + signal dec15_r17: std_logic; + signal dec14_p07: std_logic; + signal dec17_r18: std_logic; + signal dec16_p08: std_logic; + signal dec19_r19: std_logic; + signal dec18_p09: std_logic; + signal dec21_r110: std_logic; + signal dec20_p010: std_logic; + signal dec23_r111: std_logic; + signal dec22_p011: std_logic; + signal dec25_r112: std_logic; + signal dec24_p012: std_logic; + signal dec27_r113: std_logic; + signal dec26_p013: std_logic; + signal dec29_r114: std_logic; + signal dec28_p014: std_logic; + signal dec31_r115: std_logic; + signal dec30_p015: std_logic; + signal dec33_r116: std_logic; + signal dec32_p016: std_logic; + signal dec35_r117: std_logic; + signal dec34_p017: std_logic; + signal dec37_r118: std_logic; + signal dec36_p018: std_logic; + signal dec39_r119: std_logic; + signal dec38_p019: std_logic; + signal dec41_r120: std_logic; + signal dec40_p020: std_logic; + signal dec43_r121: std_logic; + signal dec42_p021: std_logic; + signal dec45_r122: std_logic; + signal dec44_p022: std_logic; + signal dec47_r123: std_logic; + signal dec46_p023: std_logic; + signal dec49_r124: std_logic; + signal dec48_p024: std_logic; + signal dec51_r125: std_logic; + signal dec50_p025: std_logic; + signal dec53_r126: std_logic; + signal dec52_p026: std_logic; + signal dec55_r127: std_logic; + signal dec54_p027: std_logic; + signal dec57_r128: std_logic; + signal dec56_p028: std_logic; + signal dec59_r129: std_logic; + signal dec58_p029: std_logic; + signal dec61_r130: std_logic; + signal dec60_p030: std_logic; + signal dec63_r131: std_logic; + signal dec62_p031: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wptr_15: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_16: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co7: std_logic; + signal wcount_15: std_logic; + signal co6: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8: std_logic; + signal rcount_16: std_logic; + signal co7_1: std_logic; + signal mdout1_31_0: std_logic; + signal mdout1_30_0: std_logic; + signal mdout1_29_0: std_logic; + signal mdout1_28_0: std_logic; + signal mdout1_27_0: std_logic; + signal mdout1_26_0: std_logic; + signal mdout1_25_0: std_logic; + signal mdout1_24_0: std_logic; + signal mdout1_23_0: std_logic; + signal mdout1_22_0: std_logic; + signal mdout1_21_0: std_logic; + signal mdout1_20_0: std_logic; + signal mdout1_19_0: std_logic; + signal mdout1_18_0: std_logic; + signal mdout1_17_0: std_logic; + signal mdout1_16_0: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_31_1: std_logic; + signal mdout1_30_1: std_logic; + signal mdout1_29_1: std_logic; + signal mdout1_28_1: std_logic; + signal mdout1_27_1: std_logic; + signal mdout1_26_1: std_logic; + signal mdout1_25_1: std_logic; + signal mdout1_24_1: std_logic; + signal mdout1_23_1: std_logic; + signal mdout1_22_1: std_logic; + signal mdout1_21_1: std_logic; + signal mdout1_20_1: std_logic; + signal mdout1_19_1: std_logic; + signal mdout1_18_1: std_logic; + signal mdout1_17_1: std_logic; + signal mdout1_16_1: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_31_2: std_logic; + signal mdout1_30_2: std_logic; + signal mdout1_29_2: std_logic; + signal mdout1_28_2: std_logic; + signal mdout1_27_2: std_logic; + signal mdout1_26_2: std_logic; + signal mdout1_25_2: std_logic; + signal mdout1_24_2: std_logic; + signal mdout1_23_2: std_logic; + signal mdout1_22_2: std_logic; + signal mdout1_21_2: std_logic; + signal mdout1_20_2: std_logic; + signal mdout1_19_2: std_logic; + signal mdout1_18_2: std_logic; + signal mdout1_17_2: std_logic; + signal mdout1_16_2: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_31_3: std_logic; + signal mdout1_30_3: std_logic; + signal mdout1_29_3: std_logic; + signal mdout1_28_3: std_logic; + signal mdout1_27_3: std_logic; + signal mdout1_26_3: std_logic; + signal mdout1_25_3: std_logic; + signal mdout1_24_3: std_logic; + signal mdout1_23_3: std_logic; + signal mdout1_22_3: std_logic; + signal mdout1_21_3: std_logic; + signal mdout1_20_3: std_logic; + signal mdout1_19_3: std_logic; + signal mdout1_18_3: std_logic; + signal mdout1_17_3: std_logic; + signal mdout1_16_3: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_31_4: std_logic; + signal mdout1_30_4: std_logic; + signal mdout1_29_4: std_logic; + signal mdout1_28_4: std_logic; + signal mdout1_27_4: std_logic; + signal mdout1_26_4: std_logic; + signal mdout1_25_4: std_logic; + signal mdout1_24_4: std_logic; + signal mdout1_23_4: std_logic; + signal mdout1_22_4: std_logic; + signal mdout1_21_4: std_logic; + signal mdout1_20_4: std_logic; + signal mdout1_19_4: std_logic; + signal mdout1_18_4: std_logic; + signal mdout1_17_4: std_logic; + signal mdout1_16_4: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_31_5: std_logic; + signal mdout1_30_5: std_logic; + signal mdout1_29_5: std_logic; + signal mdout1_28_5: std_logic; + signal mdout1_27_5: std_logic; + signal mdout1_26_5: std_logic; + signal mdout1_25_5: std_logic; + signal mdout1_24_5: std_logic; + signal mdout1_23_5: std_logic; + signal mdout1_22_5: std_logic; + signal mdout1_21_5: std_logic; + signal mdout1_20_5: std_logic; + signal mdout1_19_5: std_logic; + signal mdout1_18_5: std_logic; + signal mdout1_17_5: std_logic; + signal mdout1_16_5: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_31_6: std_logic; + signal mdout1_30_6: std_logic; + signal mdout1_29_6: std_logic; + signal mdout1_28_6: std_logic; + signal mdout1_27_6: std_logic; + signal mdout1_26_6: std_logic; + signal mdout1_25_6: std_logic; + signal mdout1_24_6: std_logic; + signal mdout1_23_6: std_logic; + signal mdout1_22_6: std_logic; + signal mdout1_21_6: std_logic; + signal mdout1_20_6: std_logic; + signal mdout1_19_6: std_logic; + signal mdout1_18_6: std_logic; + signal mdout1_17_6: std_logic; + signal mdout1_16_6: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_31_7: std_logic; + signal mdout1_30_7: std_logic; + signal mdout1_29_7: std_logic; + signal mdout1_28_7: std_logic; + signal mdout1_27_7: std_logic; + signal mdout1_26_7: std_logic; + signal mdout1_25_7: std_logic; + signal mdout1_24_7: std_logic; + signal mdout1_23_7: std_logic; + signal mdout1_22_7: std_logic; + signal mdout1_21_7: std_logic; + signal mdout1_20_7: std_logic; + signal mdout1_19_7: std_logic; + signal mdout1_18_7: std_logic; + signal mdout1_17_7: std_logic; + signal mdout1_16_7: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_31_8: std_logic; + signal mdout1_30_8: std_logic; + signal mdout1_29_8: std_logic; + signal mdout1_28_8: std_logic; + signal mdout1_27_8: std_logic; + signal mdout1_26_8: std_logic; + signal mdout1_25_8: std_logic; + signal mdout1_24_8: std_logic; + signal mdout1_23_8: std_logic; + signal mdout1_22_8: std_logic; + signal mdout1_21_8: std_logic; + signal mdout1_20_8: std_logic; + signal mdout1_19_8: std_logic; + signal mdout1_18_8: std_logic; + signal mdout1_17_8: std_logic; + signal mdout1_16_8: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r7: std_logic; + signal wcount_r8: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal wcount_r11: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_2: std_logic; + signal wcount_r13: std_logic; + signal wcount_r14: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w9: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w11: std_logic; + signal rcount_w12: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w14: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_3: std_logic; + signal rcount_w15: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_14: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX321 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; D16: in std_logic; D17: in std_logic; + D18: in std_logic; D19: in std_logic; D20: in std_logic; + D21: in std_logic; D22: in std_logic; D23: in std_logic; + D24: in std_logic; D25: in std_logic; D26: in std_logic; + D27: in std_logic; D28: in std_logic; D29: in std_logic; + D30: in std_logic; D31: in std_logic; SD1: in std_logic; + SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; + SD5: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; + attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; + attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; + attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; + attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; + attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; + attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; + attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; + attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; + attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; + attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; + attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; + attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; + attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; + attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; + attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; + attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; + attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; + attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; + attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; + attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; + attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; + attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; + attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; + attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; + attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; + attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; + attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; + attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; + attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; + attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_65536x18x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; + attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t33: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_11: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t32: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_10: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t31: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t30: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t29: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t28: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t27: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t26: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t25: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t24: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t23: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t22: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t21: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t20: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t19: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t18: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t17: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t16: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t15: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t14: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t13: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t12: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t11: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t10: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t9: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t8: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t7: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t6: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t5: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t4: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t3: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t2: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t1: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t0: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + INV_9: INV + port map (A=>wptr_10, Z=>wptr_10_inv); + + INV_8: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_7: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_6: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_5: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + LUT4_180: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet); + + LUT4_179: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_p00); + + INV_4: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_3: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_2: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_1: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + INV_0: INV + port map (A=>rptr_15, Z=>rptr_15_inv); + + LUT4_178: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_1); + + LUT4_177: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec1_r10); + + LUT4_176: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_2); + + LUT4_175: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec2_p01); + + LUT4_174: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_3); + + LUT4_173: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec3_r11); + + LUT4_172: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_4); + + LUT4_171: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec4_p02); + + LUT4_170: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_5); + + LUT4_169: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec5_r12); + + LUT4_168: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_6); + + LUT4_167: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec6_p03); + + LUT4_166: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_7); + + LUT4_165: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec7_r13); + + LUT4_164: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_8); + + LUT4_163: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec8_p04); + + LUT4_162: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_9); + + LUT4_161: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec9_r14); + + LUT4_160: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_10); + + LUT4_159: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); + + LUT4_158: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_11); + + LUT4_157: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); + + LUT4_156: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_12); + + LUT4_155: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); + + LUT4_154: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_13); + + LUT4_153: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); + + LUT4_152: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_14); + + LUT4_151: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); + + LUT4_150: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_15); + + LUT4_149: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); + + LUT4_148: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_16); + + LUT4_147: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); + + LUT4_146: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_17); + + LUT4_145: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); + + LUT4_144: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_18); + + LUT4_143: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); + + LUT4_142: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_19); + + LUT4_141: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); + + LUT4_140: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_20); + + LUT4_139: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); + + LUT4_138: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_21); + + LUT4_137: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); + + LUT4_136: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_22); + + LUT4_135: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); + + LUT4_134: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_23); + + LUT4_133: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); + + LUT4_132: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_24); + + LUT4_131: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); + + LUT4_130: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_25); + + LUT4_129: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); + + LUT4_128: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_26); + + LUT4_127: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); + + LUT4_126: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_27); + + LUT4_125: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); + + LUT4_124: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_28); + + LUT4_123: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); + + LUT4_122: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_29); + + LUT4_121: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); + + LUT4_120: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_30); + + LUT4_119: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); + + LUT4_118: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_31); + + LUT4_117: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); + + LUT4_116: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_32); + + LUT4_115: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec32_p016); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_33); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec33_r116); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_34); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec34_p017); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_35); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec35_r117); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_36); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec36_p018); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_37); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec37_r118); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_38); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec38_p019); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_39); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec39_r119); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_40); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec40_p020); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_41); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec41_r120); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_42); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec42_p021); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_43); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec43_r121); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_44); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec44_p022); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_45); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec45_r122); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_46); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec46_p023); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_47); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec47_r123); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_48); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec48_p024); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_49); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec49_r124); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_50); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec50_p025); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_51); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec51_r125); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_52); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec52_p026); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_53); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec53_r126); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_54); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec54_p027); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_55); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec55_r127); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_56); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec56_p028); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_57); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec57_r128); + + LUT4_64: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_58); + + LUT4_63: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec58_p029); + + LUT4_62: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_59); + + LUT4_61: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec59_r129); + + LUT4_60: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_60); + + LUT4_59: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec60_p030); + + LUT4_58: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_61); + + LUT4_57: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec61_r130); + + LUT4_56: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_62); + + LUT4_55: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec62_p031); + + LUT4_54: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_63); + + LUT4_53: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec63_r131); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, + DO0=>w_g2b_xor_cluster_0); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_1); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_2); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_3); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r2); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r1); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, + DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, + DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, + DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_11_0_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, + DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, + DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, + DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_12_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, + DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, + DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, + DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_13_0_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1, + DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4, + DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7, + DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_14_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1, + DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4, + DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7, + DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_15_0_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1, + DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4, + DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7, + DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_16_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1, + DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4, + DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7, + DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_17_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1, + DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4, + DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7, + DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_18_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1, + DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4, + DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7, + DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_19_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1, + DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4, + DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7, + DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_20_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1, + DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4, + DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7, + DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_21_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1, + DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4, + DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7, + DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_22_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1, + DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4, + DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7, + DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_23_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1, + DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4, + DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7, + DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_24_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1, + DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4, + DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7, + DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_25_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1, + DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4, + DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7, + DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_26_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1, + DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4, + DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7, + DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_27_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1, + DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4, + DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7, + DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_28_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1, + DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4, + DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7, + DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_29_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1, + DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4, + DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7, + DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_30_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1, + DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4, + DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7, + DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_31_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1, + DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4, + DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7, + DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_171: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_170: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_169: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_168: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_167: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_166: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_165: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_164: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_163: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_162: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_161: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_160: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_159: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_158: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_157: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_156: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_155: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_154: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_153: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_152: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_151: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_150: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_149: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_148: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_147: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_146: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_145: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_144: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_143: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_142: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_141: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_140: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_139: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_138: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_137: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_136: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_135: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_134: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_133: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_132: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_131: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_130: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_129: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_128: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_127: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_126: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_125: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_124: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_123: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_122: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_121: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_120: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_119: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_118: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_117: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_116: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_115: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_114: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_113: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_112: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_111: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_110: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_109: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_108: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_107: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_106: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_105: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_104: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_103: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_102: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_101: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_100: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_99: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_98: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_97: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_96: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_95: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_94: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_93: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_92: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_91: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_90: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_89: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_88: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_87: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_86: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_85: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_84: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_83: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_82: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_81: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_80: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_79: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_78: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_77: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_76: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_75: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_74: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_73: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_72: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_71: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_70: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_69: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_68: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_67: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_66: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_65: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_64: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_63: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_62: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_61: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_60: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_59: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_58: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_57: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_56: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_55: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_54: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_53: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_52: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_51: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_50: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_49: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_48: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_47: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_46: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_45: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_44: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_43: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_42: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_41: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_40: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_39: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_38: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_37: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_36: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_35: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_34: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_33: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_32: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_31: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_30: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_29: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_28: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_27: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_26: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_25: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_24: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_23: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_22: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_21: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_20: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_19: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_18: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_17: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_16: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_15: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_14: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_13: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_12: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_11: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_10: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_9: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_8: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_7: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_6: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_5: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_4: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_3: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_2: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>ircount_16, NC1=>open); + + mux_8: MUX321 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, + D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, + D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, + D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, + D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, + D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(0)); + + mux_7: MUX321 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, + D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, + D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, + D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, + D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, + D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(1)); + + mux_6: MUX321 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, + D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, + D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, + D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, + D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, + D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(2)); + + mux_5: MUX321 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, + D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, + D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, + D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, + D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, + D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(3)); + + mux_4: MUX321 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, + D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, + D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, + D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, + D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, + D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(4)); + + mux_3: MUX321 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, + D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, + D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, + D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, + D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, + D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(5)); + + mux_2: MUX321 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, + D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, + D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, + D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, + D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, + D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(6)); + + mux_1: MUX321 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, + D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, + D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, + D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, + D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, + D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(7)); + + mux_0: MUX321 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, + D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, + D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, + D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, + D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, + D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(8)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>wcount_r8, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>wcount_r10, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, + B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, + B1=>wcount_r14, CI=>co6_2, GE=>co7_2); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, + B1=>rcount_w10, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, + B1=>rcount_w12, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w14, CI=>co5_3, GE=>co6_3); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, + B1=>full_cmp_clr, CI=>co6_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_65536x18x9 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX321 use entity ecp3.MUX321(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd b/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd new file mode 100644 index 0000000..42570c3 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd @@ -0,0 +1,1830 @@ +-- VHDL netlist generated by SCUBA Diamond_3.0_Production (94) +-- Module Version: 5.5 +--/home/soft/lattice/diamond/3.0_x64/ispfpga/bin/lin64/scuba -w -n fifo_8kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 8192 -width 9 -depth 8192 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + +-- Fri Jan 9 15:00:10 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_8kx9 is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_8kx9; + +architecture Structure of fifo_8kx9 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_13: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co6: std_logic; + signal co5: std_logic; + signal wcount_13: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co6_1: std_logic; + signal co5_1: std_logic; + signal rcount_13: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal wcount_r12: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_12: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal rcount_w12: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_12: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX41 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; SD1: in std_logic; SD2: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_3 : label is "fifo_8kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_3 : label is ""; + attribute RESETMODE of pdp_ram_0_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_2 : label is "fifo_8kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_2 : label is ""; + attribute RESETMODE of pdp_ram_1_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_1 : label is "fifo_8kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_1 : label is ""; + attribute RESETMODE of pdp_ram_2_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_0 : label is "fifo_8kx9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_0 : label is ""; + attribute RESETMODE of pdp_ram_3_0_0 : label is "SYNC"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t28: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t27: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t26: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t25: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t24: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t23: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t22: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t21: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t20: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t19: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t18: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t17: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t16: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t15: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t14: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t13: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t12: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t11: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t10: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t9: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t8: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t7: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t6: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t5: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t4: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t3: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t2: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t1: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t0: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>w_gcount_r213, + DO0=>w_g2b_xor_cluster_0); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_gcount_r29, + DO0=>w_g2b_xor_cluster_1); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_2); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r12); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r7); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, DO0=>wcount_r4); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r21, DO0=>wcount_r1); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_gcount_w213, + DO0=>r_g2b_xor_cluster_0); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_gcount_w29, + DO0=>r_g2b_xor_cluster_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_2); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w12); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w7); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, DO0=>rcount_w4); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w21, DO0=>rcount_w1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_13, AD2=>rcount_13, AD1=>w_gcount_r213, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_13, AD2=>rcount_13, AD1=>w_gcount_r213, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_13, AD2=>wcount_13, AD1=>r_gcount_w213, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_13, AD2=>wcount_13, AD1=>r_gcount_w213, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_3: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_1: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_0: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_143: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_142: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_141: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_140: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_139: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_138: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_137: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_136: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_135: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_134: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_133: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_132: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_131: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_130: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_129: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_128: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_127: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_126: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_125: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_124: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_123: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_122: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_121: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_120: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_119: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_118: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_117: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_116: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_115: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_114: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_113: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_112: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_111: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_110: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_109: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_108: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_107: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_106: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_105: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_104: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_103: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_102: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_101: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_100: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_99: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_98: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_97: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_96: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_95: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_94: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_93: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_92: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_91: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_90: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_89: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_88: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_87: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_86: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_85: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_84: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_83: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_82: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_81: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_80: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_79: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_78: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_77: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_76: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_75: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_74: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_73: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_72: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_71: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_70: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_69: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_68: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_67: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_66: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_65: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_64: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_63: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_62: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_61: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_60: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_59: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_58: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_57: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_56: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_55: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_54: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_53: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_52: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_51: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_50: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_49: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_48: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_47: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_46: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_45: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_44: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_43: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_42: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_41: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_40: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_39: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_38: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_37: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_36: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_35: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_34: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_33: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_32: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_31: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_30: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_29: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_28: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_27: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_26: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_25: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_24: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_23: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_22: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_21: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_20: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_19: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_18: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_17: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_16: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_15: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_14: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_13: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_12: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_11: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_10: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_9: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_8: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_7: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_6: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_5: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_4: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_3: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_2: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + mux_8: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(0)); + + mux_7: MUX41 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(1)); + + mux_6: MUX41 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(2)); + + mux_5: MUX41 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(3)); + + mux_4: MUX41 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(4)); + + mux_3: MUX41 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(5)); + + mux_2: MUX41 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(6)); + + mux_1: MUX41 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(7)); + + mux_0: MUX41 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(8)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>empty_cmp_set, B0=>wcount_r12, + B1=>empty_cmp_clr, CI=>co5_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>full_cmp_set, B0=>rcount_w12, + B1=>full_cmp_clr, CI=>co5_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_8kx9 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX41 use entity ecp3.MUX41(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/ip_mem.lpc b/gbe_trb/ipcores/ecp3/ip_mem.lpc new file mode 100755 index 0000000..4c9ab25 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/ip_mem.lpc @@ -0,0 +1,60 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP_TRUE +CoreRevision=7.1 +ModuleName=ip_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:24:37 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +AAddress=256 +BAddress=256 +AData=32 +BData=32 +enByte=0 +ByteSize=9 +AadPipeline=0 +BadPipeline=0 +AinPipeline=0 +BinPipeline=0 +AoutPipeline=0 +BoutPipeline=1 +AMOR=0 +BMOR=0 +AInData=Registered +BInData=Registered +AAdControl=Registered +BAdControl=Registered +MemFile=ip_mem.mem +MemFormat=orca +Reset=Sync +GSR=Enabled +WriteA=Normal +WriteB=Normal +Pad=0 +EnECC=0 +Optimization=Speed +Pipeline=0 + +[FilesGenerated] +ip_mem.mem=mem diff --git a/gbe_trb/ipcores/ecp3/ip_mem.vhd b/gbe_trb/ipcores/ecp3/ip_mem.vhd new file mode 100755 index 0000000..5b2e06e --- /dev/null +++ b/gbe_trb/ipcores/ecp3/ip_mem.vhd @@ -0,0 +1,379 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 7.1 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e + +-- Thu Sep 22 11:24:37 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity ip_mem is + port ( + DataInA: in std_logic_vector(31 downto 0); + DataInB: in std_logic_vector(31 downto 0); + AddressA: in std_logic_vector(7 downto 0); + AddressB: in std_logic_vector(7 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(31 downto 0); + QB: out std_logic_vector(31 downto 0)); +end ip_mem; + +architecture Structure of ip_mem is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KC + generic (INITVAL_3F : in String; INITVAL_3E : in String; + INITVAL_3D : in String; INITVAL_3C : in String; + INITVAL_3B : in String; INITVAL_3A : in String; + INITVAL_39 : in String; INITVAL_38 : in String; + INITVAL_37 : in String; INITVAL_36 : in String; + INITVAL_35 : in String; INITVAL_34 : in String; + INITVAL_33 : in String; INITVAL_32 : in String; + INITVAL_31 : in String; INITVAL_30 : in String; + INITVAL_2F : in String; INITVAL_2E : in String; + INITVAL_2D : in String; INITVAL_2C : in String; + INITVAL_2B : in String; INITVAL_2A : in String; + INITVAL_29 : in String; INITVAL_28 : in String; + INITVAL_27 : in String; INITVAL_26 : in String; + INITVAL_25 : in String; INITVAL_24 : in String; + INITVAL_23 : in String; INITVAL_22 : in String; + INITVAL_21 : in String; INITVAL_20 : in String; + INITVAL_1F : in String; INITVAL_1E : in String; + INITVAL_1D : in String; INITVAL_1C : in String; + INITVAL_1B : in String; INITVAL_1A : in String; + INITVAL_19 : in String; INITVAL_18 : in String; + INITVAL_17 : in String; INITVAL_16 : in String; + INITVAL_15 : in String; INITVAL_14 : in String; + INITVAL_13 : in String; INITVAL_12 : in String; + INITVAL_11 : in String; INITVAL_10 : in String; + INITVAL_0F : in String; INITVAL_0E : in String; + INITVAL_0D : in String; INITVAL_0C : in String; + INITVAL_0B : in String; INITVAL_0A : in String; + INITVAL_09 : in String; INITVAL_08 : in String; + INITVAL_07 : in String; INITVAL_06 : in String; + INITVAL_05 : in String; INITVAL_04 : in String; + INITVAL_03 : in String; INITVAL_02 : in String; + INITVAL_01 : in String; INITVAL_00 : in String; + GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc"; + attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem"; + attribute RESETMODE of ip_mem_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc"; + attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem"; + attribute RESETMODE of ip_mem_0_1_0 : label is "SYNC"; + +begin + -- component instantiation statements + ip_mem_0_0_1: DP16KC + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9", + INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9", + INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9", + INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG", + REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18) + port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), + DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5), + DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8), + DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11), + DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14), + DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17), + ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, + ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), + ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), + ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7), + ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, + CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA, + DIB0=>DataInB(0), DIB1=>DataInB(1), DIB2=>DataInB(2), + DIB3=>DataInB(3), DIB4=>DataInB(4), DIB5=>DataInB(5), + DIB6=>DataInB(6), DIB7=>DataInB(7), DIB8=>DataInB(8), + DIB9=>DataInB(9), DIB10=>DataInB(10), DIB11=>DataInB(11), + DIB12=>DataInB(12), DIB13=>DataInB(13), DIB14=>DataInB(14), + DIB15=>DataInB(15), DIB16=>DataInB(16), DIB17=>DataInB(17), + ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1), + ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4), + ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7), + ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB, + CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(0), + DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4), + DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8), + DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12), + DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16), + DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2), + DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6), + DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10), + DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14), + DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17)); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + ip_mem_0_1_0: DP16KC + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG", + REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18) + port map (DIA0=>DataInA(18), DIA1=>DataInA(19), + DIA2=>DataInA(20), DIA3=>DataInA(21), DIA4=>DataInA(22), + DIA5=>DataInA(23), DIA6=>DataInA(24), DIA7=>DataInA(25), + DIA8=>DataInA(26), DIA9=>DataInA(27), DIA10=>DataInA(28), + DIA11=>DataInA(29), DIA12=>DataInA(30), DIA13=>DataInA(31), + DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo, + DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>AddressA(0), + ADA5=>AddressA(1), ADA6=>AddressA(2), ADA7=>AddressA(3), + ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6), + ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo, + CEA=>ClockEnA, CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>ResetA, DIB0=>DataInB(18), DIB1=>DataInB(19), + DIB2=>DataInB(20), DIB3=>DataInB(21), DIB4=>DataInB(22), + DIB5=>DataInB(23), DIB6=>DataInB(24), DIB7=>DataInB(25), + DIB8=>DataInB(26), DIB9=>DataInB(27), DIB10=>DataInB(28), + DIB11=>DataInB(29), DIB12=>DataInB(30), DIB13=>DataInB(31), + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vhi, ADB1=>scuba_vhi, + ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>AddressB(0), + ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3), + ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6), + ADB11=>AddressB(7), ADB12=>scuba_vlo, ADB13=>scuba_vlo, + CEB=>ClockEnB, CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19), DOA2=>QA(20), + DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23), DOA6=>QA(24), + DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27), DOA10=>QA(28), + DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31), DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>QB(18), + DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21), DOB4=>QB(22), + DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25), DOB8=>QB(26), + DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29), DOB12=>QB(30), + DOB13=>QB(31), DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of ip_mem is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/mac_init_mem.lpc b/gbe_trb/ipcores/ecp3/mac_init_mem.lpc new file mode 100755 index 0000000..42f57b0 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/mac_init_mem.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=ROM +CoreRevision=5.0 +ModuleName=mac_init_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:24:53 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Address=54 +Data=8 +adPipeline=0 +inPipeline=0 +outPipeline=1 +MOR=0 +InData=Registered +AdControl=Registered +MemFile=macInitDataInvWithMac.mem +MemFormat=bin +Reset=Sync +Pad=0 +GSR=Enabled +EnECC=0 +Optimization=Speed +Pipeline=0 + +[FilesGenerated] +macInitDataInvWithMac.mem=mem diff --git a/gbe_trb/ipcores/ecp3/mac_init_mem.vhd b/gbe_trb/ipcores/ecp3/mac_init_mem.vhd new file mode 100755 index 0000000..3934a61 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/mac_init_mem.vhd @@ -0,0 +1,262 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.0 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e + +-- Thu Sep 22 11:24:53 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity mac_init_mem is + port ( + Address: in std_logic_vector(5 downto 0); + OutClock: in std_logic; + OutClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(7 downto 0)); +end mac_init_mem; + +architecture Structure of mac_init_mem is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KC + generic (INITVAL_3F : in String; INITVAL_3E : in String; + INITVAL_3D : in String; INITVAL_3C : in String; + INITVAL_3B : in String; INITVAL_3A : in String; + INITVAL_39 : in String; INITVAL_38 : in String; + INITVAL_37 : in String; INITVAL_36 : in String; + INITVAL_35 : in String; INITVAL_34 : in String; + INITVAL_33 : in String; INITVAL_32 : in String; + INITVAL_31 : in String; INITVAL_30 : in String; + INITVAL_2F : in String; INITVAL_2E : in String; + INITVAL_2D : in String; INITVAL_2C : in String; + INITVAL_2B : in String; INITVAL_2A : in String; + INITVAL_29 : in String; INITVAL_28 : in String; + INITVAL_27 : in String; INITVAL_26 : in String; + INITVAL_25 : in String; INITVAL_24 : in String; + INITVAL_23 : in String; INITVAL_22 : in String; + INITVAL_21 : in String; INITVAL_20 : in String; + INITVAL_1F : in String; INITVAL_1E : in String; + INITVAL_1D : in String; INITVAL_1C : in String; + INITVAL_1B : in String; INITVAL_1A : in String; + INITVAL_19 : in String; INITVAL_18 : in String; + INITVAL_17 : in String; INITVAL_16 : in String; + INITVAL_15 : in String; INITVAL_14 : in String; + INITVAL_13 : in String; INITVAL_12 : in String; + INITVAL_11 : in String; INITVAL_10 : in String; + INITVAL_0F : in String; INITVAL_0E : in String; + INITVAL_0D : in String; INITVAL_0C : in String; + INITVAL_0B : in String; INITVAL_0A : in String; + INITVAL_09 : in String; INITVAL_08 : in String; + INITVAL_07 : in String; INITVAL_06 : in String; + INITVAL_05 : in String; INITVAL_04 : in String; + INITVAL_03 : in String; INITVAL_02 : in String; + INITVAL_01 : in String; INITVAL_00 : in String; + GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc"; + attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem"; + attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC"; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + mac_init_mem_0_0_0: DP16KC + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000", + INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F", + CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", + REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2), + ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5), + ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo, + ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn, + CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo, + ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo, + ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo, + ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, + CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1), + DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), + DOA7=>Q(7), DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open, + DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of mac_init_mem is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd b/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd new file mode 100755 index 0000000..bd74e03 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd @@ -0,0 +1,178 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; + +entity slv_mac_memory is +port( + CLK : in std_logic; + RESET : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(7 downto 0); + MEM_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end entity; + +architecture Behavioral of slv_mac_memory is + +component ip_mem is +port( + DataInA : in std_logic_vector(31 downto 0); + DataInB : in std_logic_vector(31 downto 0); + AddressA : in std_logic_vector(7 downto 0); + AddressB : in std_logic_vector(7 downto 0); + ClockA : in std_logic; + ClockB : in std_logic; + ClockEnA : in std_logic; + ClockEnB : in std_logic; + WrA : in std_logic; + WrB : in std_logic; + ResetA : in std_logic; + ResetB : in std_logic; + QA : out std_logic_vector(31 downto 0); + QB : out std_logic_vector(31 downto 0) +); +end component ip_mem; + +-- Signals +type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- slave bus signals +signal slv_busy_x : std_logic; +signal slv_busy : std_logic; +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; + +signal reg_busy : std_logic; + +begin + +-- Fake +reg_busy <= busy_in; +stat <= (others => '0'); + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk ) +begin + if( rising_edge(clk) ) then + if( reset = '1' ) then + CURRENT_STATE <= SLEEP; + slv_busy <= '0'; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_busy <= slv_busy_x; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) +begin + NEXT_STATE <= SLEEP; + slv_busy_x <= '0'; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( (reg_busy = '0') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + elsif( (reg_busy = '1') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_BSY; + elsif( (reg_busy = '1') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_BSY; + else + NEXT_STATE <= SLEEP; + end if; + when RD_RDY => NEXT_STATE <= RD_ACK; + when WR_RDY => NEXT_STATE <= WR_ACK; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when RD_BSY => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_BSY; + slv_busy_x <= '1'; + end if; + when WR_BSY => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_BSY; + slv_busy_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +THE_MAC_MEM: ip_mem +port map( + DataInA => slv_data_in, + AddressA => slv_addr_in, + ClockA => clk, + ClockEnA => '1', + QA => slv_data_out, + WrA => store_wr, + ResetA => reset, + DataInB => x"0000_0000", + AddressB => mem_addr_in, + ClockB => mem_clk_in, + ClockEnB => '1', + WrB => '0', -- never write + ResetB => reset, + QB => mem_data_out +); + +-- output signals +slv_ack_out <= slv_ack; +slv_busy_out <= slv_busy; + +end Behavioral; diff --git a/gbe_trb/ipcores/ecp3/statts_mem.lpc b/gbe_trb/ipcores/ecp3/statts_mem.lpc new file mode 100644 index 0000000..c24e581 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/statts_mem.lpc @@ -0,0 +1,53 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP +CoreRevision=6.1 +ModuleName=statts_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/05/2011 +Time=22:40:38 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +RAddress=1020 +RData=8 +WAddress=255 +WData=32 +enByte=0 +ByteSize=9 +adPipeline=0 +inPipeline=0 +outPipeline=0 +MOR=0 +InData=Registered +AdControl=Registered +MemFile= +MemFormat=bin +Reset=Sync +GSR=Enabled +Pad=0 +EnECC=0 +Optimization=Speed +EnSleep=ENABLED +Pipeline=0 + +[FilesGenerated] +=mem diff --git a/gbe_trb/ipcores/ecp3/statts_mem.vhd b/gbe_trb/ipcores/ecp3/statts_mem.vhd new file mode 100644 index 0000000..2a03d69 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/statts_mem.vhd @@ -0,0 +1,159 @@ +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 6.1 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 8 -data_width 32 -num_rows 255 -cascade -1 -e + +-- Mon Dec 5 22:40:38 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity statts_mem is + port ( + WrAddress: in std_logic_vector(7 downto 0); + RdAddress: in std_logic_vector(9 downto 0); + Data: in std_logic_vector(31 downto 0); + WE: in std_logic; + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + WrClock: in std_logic; + WrClockEn: in std_logic; + Q: out std_logic_vector(7 downto 0)); +end statts_mem; + +architecture Structure of statts_mem is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of statts_mem_0_0_0 : label is "statts_mem.lpc"; + attribute MEM_INIT_FILE of statts_mem_0_0_0 : label is ""; + attribute RESETMODE of statts_mem_0_0_0 : label is "SYNC"; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + statts_mem_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>scuba_vlo, DI9=>Data(8), DI10=>Data(9), DI11=>Data(10), + DI12=>Data(11), DI13=>Data(12), DI14=>Data(13), + DI15=>Data(14), DI16=>Data(15), DI17=>scuba_vlo, + DI18=>Data(16), DI19=>Data(17), DI20=>Data(18), + DI21=>Data(19), DI22=>Data(20), DI23=>Data(21), + DI24=>Data(22), DI25=>Data(23), DI26=>scuba_vlo, + DI27=>Data(24), DI28=>Data(25), DI29=>Data(26), + DI30=>Data(27), DI31=>Data(28), DI32=>Data(29), + DI33=>Data(30), DI34=>Data(31), DI35=>scuba_vlo, + ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2), + ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5), + ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>RdAddress(0), + ADR4=>RdAddress(1), ADR5=>RdAddress(2), ADR6=>RdAddress(3), + ADR7=>RdAddress(4), ADR8=>RdAddress(5), ADR9=>RdAddress(6), + ADR10=>RdAddress(7), ADR11=>RdAddress(8), + ADR12=>RdAddress(9), ADR13=>scuba_vlo, CER=>RdClockEn, + CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), + DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), + DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open, + DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, + DO18=>open, DO19=>open, DO20=>open, DO21=>open, DO22=>open, + DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open, + DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open, + DO33=>open, DO34=>open, DO35=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of statts_mem is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/media/rate_resolution.v b/gbe_trb/media/rate_resolution.v new file mode 100755 index 0000000..b9edbef --- /dev/null +++ b/gbe_trb/media/rate_resolution.v @@ -0,0 +1,66 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module rate_resolution ( + gbe_mode, + sgmii_mode, + an_enable, + advertised_rate, + link_partner_rate, + non_an_rate, + + operational_rate +); + +input gbe_mode; +input sgmii_mode; +input an_enable; +input [1:0] advertised_rate; // 00=10Mbps 01=100Mbps 10=1Gbps +input [1:0] link_partner_rate; +input [1:0] non_an_rate; + +output [1:0] operational_rate; +reg [1:0] operational_rate; + + + +always @(gbe_mode or sgmii_mode or an_enable or advertised_rate or link_partner_rate or non_an_rate) begin + if (gbe_mode) begin + operational_rate <= 2'b10; // 1Gbps + end + else begin + if (an_enable) begin + if (sgmii_mode) begin + // PHY Mode + operational_rate <= advertised_rate; + end + else begin + // MAC Mode + operational_rate <= link_partner_rate; + end + end + else begin + // If auto-negotiation disabled, then this becomes active rate + operational_rate <= non_an_rate; + end + end +end + + + +endmodule + diff --git a/gbe_trb/media/register_interface_hb.v b/gbe_trb/media/register_interface_hb.v new file mode 100755 index 0000000..73e0b86 --- /dev/null +++ b/gbe_trb/media/register_interface_hb.v @@ -0,0 +1,918 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module register_interface_hb ( + + // Control Signals + rst_n, + hclk, + gbe_mode, + sgmii_mode, + + // Host Bus + hcs_n, + hwrite_n, + haddr, + hdatain, + + hdataout, + hready_n, + + // Register Inputs + mr_an_enable, + mr_restart_an, + mr_adv_ability, + + // Register Outputs + mr_main_reset, + mr_an_complete, + mr_page_rx, + mr_lp_adv_ability + ); + + +input rst_n ; +input hclk ; +input gbe_mode ; +input sgmii_mode ; + +input hcs_n; +input hwrite_n; +input [3:0] haddr; +input [7:0] hdatain; + +output [7:0] hdataout; +output hready_n; + +input mr_an_complete; +input mr_page_rx; +input [15:0] mr_lp_adv_ability; + +output mr_an_enable; +output mr_restart_an; +output [15:0] mr_adv_ability; +output mr_main_reset; + +regs_hb regs ( + .rst_n (rst_n), + .hclk (hclk), + + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + + .hcs_n (hcs_n), + .hwrite_n (hwrite_n), + .haddr (haddr), + .hdatain (hdatain), + + .hdataout (hdataout), + .hready_n (hready_n), + + .mr_an_complete (mr_an_complete), + .mr_page_rx (mr_page_rx), + .mr_lp_adv_ability (mr_lp_adv_ability), + + .mr_main_reset (mr_main_reset), + .mr_an_enable (mr_an_enable), + .mr_restart_an (mr_restart_an), + .mr_adv_ability (mr_adv_ability) +); +endmodule + + + + + + +module register_0_hb ( + rst_n, + clk, + cs_0, + cs_1, + write, + ready, + data_in, + + data_out, + mr_main_reset, + mr_an_enable, + mr_restart_an +); + +input rst_n; +input clk; +input cs_0; +input cs_1; +input write; +input ready; +input [15:0] data_in; + +output [15:0] data_out; +output mr_main_reset; // bit D15 // R/W // Self Clearing +output mr_an_enable; // bit D12 // R/W +output mr_restart_an; // bit D09 // R/W // Self Clearing + +reg [15:0] data_out; +reg mr_main_reset; +reg mr_an_enable; +reg mr_restart_an; +reg m_m_r; +reg m_r_a; + + +// Write Operations + + // Low Portion of Register[D7:D0] has no + // implemented bits. Therefore, no write + // operations here. + + // High Portion of Register[D15:D8] + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_main_reset <= 0; // default value + mr_an_enable <= 1; // default value + mr_restart_an <= 0; // default value + m_m_r <= 0; + m_r_a <= 0; + end + else begin + + // Do the Writes + if (cs_1 && ready && write) begin + mr_main_reset <= data_in[15]; + mr_an_enable <= data_in[12]; + mr_restart_an <= data_in[9]; + end + + // Delay the Self Clearing Register Bits + m_m_r <= mr_main_reset; + m_r_a <= mr_restart_an; + + // Do the Self Clearing + if (m_m_r) + mr_main_reset <= 0; + + if (m_r_a) + mr_restart_an <= 0; + end + end + + + + + +// Read Operations + always @(*) begin + data_out[7:0] = 8'b00000000; + data_out[15] = mr_main_reset; + data_out[14] = 0; + data_out[13] = 0; + data_out[12] = mr_an_enable; + data_out[11] = 0; + data_out[10] = 0; + data_out[9] = mr_restart_an; + data_out[8] = 0; + end +endmodule + +module register_1_hb ( + rst_n, + cs_0, + cs_1, + mr_an_complete, + + data_out +); + +input rst_n; +input cs_0; +input cs_1; +input mr_an_complete; // bit D5 // Read-Only + +output [15:0] data_out; + +reg [15:0] data_out; + + +// Read Operations + + always @(*) begin + data_out[7] <= 0; + data_out[6] <= 0; + data_out[5] <= mr_an_complete; + data_out[4] <= 0; + data_out[3] <= 0; + data_out[2] <= 0; + data_out[1] <= 0; + data_out[0] <= 0; + data_out[15:8] <= 8'b00000000; + end +endmodule + +module register_4_hb ( + rst_n, + clk, + gbe_mode, + sgmii_mode, + cs_0, + cs_1, + write, + ready, + data_in, + + data_out, + mr_adv_ability +); + +parameter [15:0] initval_gbe = 16'h0020; +parameter [15:0] initval_phy = 16'hd801; +parameter [15:0] initval_mac = 16'h4001; + +input rst_n; +input clk; +input gbe_mode; +input sgmii_mode; +input cs_0; +input cs_1; +input write; +input ready; +input [15:0] data_in; + +output [15:0] data_out; +output [15:0] mr_adv_ability; // When sgmii_mode == 1 == PHY + // all bits D15-D0 are R/W, + /////////////////////////////////// + // D15 = Link Status (1=up, 0=down) + // D14 = Can be written but has no effect + // on autonegotiation. Instead + // the autonegotiation state machine + // controls the utilization of this bit. + // D12 = Duplex Mode (1=full, 0=half) + // D11:10 = Speed (11=reserved) + // (10=1000Mbps) + // (01=100 Mbps) + // (00=10 Mbps) + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// + //When sgmii_mode == 0 = MAC + // all bits D15-D0 are R/W, + // D14 = Can be written but has no effect + // on autonegotiation. Instead + // the autonegotiation state machine + // controls the utilization of this bit. + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// + + +reg [15:0] data_out; +reg [15:0] mr_adv_ability; +reg rst_d1; +reg rst_d2; +reg rst_d3; +reg rst_d4; +reg rst_d5; +reg rst_d6; +reg rst_d7; +reg rst_d8; +reg sync_reset; +reg sgmii_mode_d1; +reg sgmii_mode_d2; +reg sgmii_mode_d3; +reg sgmii_mode_d4; +reg sgmii_mode_change; +reg gbe_mode_d1; +reg gbe_mode_d2; +reg gbe_mode_d3; +reg gbe_mode_d4; +reg gbe_mode_change; + +// generate a synchronous reset signal +// note: this method is used so that +// an initval can be applied during +// device run-time, instead of at compile time +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + rst_d1 <= 0; + rst_d2 <= 0; + rst_d3 <= 0; + rst_d4 <= 0; + rst_d5 <= 0; + rst_d6 <= 0; + rst_d7 <= 0; + rst_d8 <= 0; + sync_reset <= 0; + end + else begin + rst_d1 <= 1; + rst_d2 <= rst_d1; + rst_d3 <= rst_d2; + rst_d4 <= rst_d3; + rst_d5 <= rst_d4; + rst_d6 <= rst_d5; + rst_d7 <= rst_d6; + rst_d8 <= rst_d7; + + // asserts on rising edge of rst_d8 + sync_reset <= !rst_d8 & rst_d7; + end +end + + +// Detect change in sgmii_mode +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + sgmii_mode_d1 <= 0; + sgmii_mode_d2 <= 0; + sgmii_mode_d3 <= 0; + sgmii_mode_d4 <= 0; + sgmii_mode_change <= 0; + end + else begin + + // deboggle + sgmii_mode_d1 <= sgmii_mode; + sgmii_mode_d2 <= sgmii_mode_d1; + + // delay + sgmii_mode_d3 <= sgmii_mode_d2; + sgmii_mode_d4 <= sgmii_mode_d3; + + // detect change + if (sgmii_mode_d3 != sgmii_mode_d4) + sgmii_mode_change <= 1; + else + sgmii_mode_change <= 0; + end +end + + +// Detect change in gbe_mode +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + gbe_mode_d1 <= 0; + gbe_mode_d2 <= 0; + gbe_mode_d3 <= 0; + gbe_mode_d4 <= 0; + gbe_mode_change <= 0; + end + else begin + + // deboggle + gbe_mode_d1 <= gbe_mode; + gbe_mode_d2 <= gbe_mode_d1; + + // delay + gbe_mode_d3 <= gbe_mode_d2; + gbe_mode_d4 <= gbe_mode_d3; + + // detect change + if (gbe_mode_d3 != gbe_mode_d4) + gbe_mode_change <= 1; + else + gbe_mode_change <= 0; + end +end + + +// Write Operations + // Low Portion of Register[D7:D0] + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_adv_ability[7:0] <= 8'h01; + end + else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin + if (gbe_mode_d4) + mr_adv_ability[7:0] <= initval_gbe[7:0]; + else if (sgmii_mode) + mr_adv_ability[7:0] <= initval_phy[7:0]; + else + mr_adv_ability[7:0] <= initval_mac[7:0]; + end + else begin + if (cs_0 && ready && write && (sgmii_mode || gbe_mode)) begin + mr_adv_ability[7:0] <= data_in[7:0]; + end + end + end + + + // High Portion of Register[D15:D8] + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_adv_ability[15:8] <= 8'h40; // default + end + else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin + if (gbe_mode_d4) + mr_adv_ability[15:8] <= initval_gbe[15:8]; + else if (sgmii_mode) + mr_adv_ability[15:8] <= initval_phy[15:8]; + else + mr_adv_ability[15:8] <= initval_mac[15:8]; + end + else begin + if (cs_1 && ready && write && (sgmii_mode || gbe_mode)) begin + mr_adv_ability[15:8] <= data_in[15:8]; + end + end + end + + + + + + + + + +// Read Operations + + always @(*) begin + data_out[7:0] <= mr_adv_ability[7:0]; + data_out[15:8] <= mr_adv_ability[15:8]; + end + +endmodule + + + + + + +module register_5_hb ( + rst_n, + mr_lp_adv_ability, + cs_0, + cs_1, + ready, + + data_out +); + +input rst_n; +input cs_0; +input cs_1; +input ready; +input [15:0] mr_lp_adv_ability; + // This entire register is read-only + /////////////////////////////////// + // When sgmii_mode == 0 == MAC + /////////////////////////////////// + // D15 = PHY Link Status (1=up, 0=down) + // D14 = PHY Autonegotiation Handshake + // D12 = PHY Duplex Mode (1=full, 0=half) + // D11:10 = PHY Speed (11=reserved) + // (10=1000Mbps) + // (01=100 Mbps) + // (00=10 Mbps) + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// + //When sgmii_mode == 1 = PHY + // D14 = MAC Autonegotiation Handshake + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// +output [15:0] data_out; + +reg [15:0] data_out; + +// Read Operations + + always @(*) begin + data_out[7:0] <= mr_lp_adv_ability[7:0]; + data_out[15:8] <= mr_lp_adv_ability[15:8]; + end +endmodule + +module register_6_hb ( + rst_n, + clk, + mr_page_rx, + cs_0, + cs_1, + write, + ready, + + data_out +); + +input rst_n; +input clk; +input cs_0; +input cs_1; +input write; +input ready; +input mr_page_rx; +output [15:0] data_out; + +reg [15:0] data_out; +reg mr_page_rx_latched; +reg clear_on_read; +reg read_detect; +reg rd_d1; +reg rd_d2; + +// generate clear-on-read signal + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + clear_on_read <= 0; + read_detect <= 0; + rd_d1 <= 0; + rd_d2 <= 0; + end + else begin + if (!write && ready && cs_0) + read_detect <= 1; + else + read_detect <= 0; + + rd_d1 <= read_detect; + rd_d2 <= rd_d1; + + // assert on falling edge of rd_d2 + clear_on_read <= !rd_d1 & rd_d2; + end + end + + +// Latch and Clear + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_page_rx_latched <= 0; + end + else begin + if (clear_on_read) + mr_page_rx_latched <= 0; + else if (mr_page_rx) + mr_page_rx_latched <= 1; + end + end + + +// Read Operations + + always @(*) begin + data_out[15:2] <= 14'd0; + data_out[1] <= mr_page_rx_latched; + data_out[0] <= 0; + end +endmodule + + +module regs_hb ( + rst_n, + hclk, + gbe_mode, + sgmii_mode, + hcs_n, + hwrite_n, + haddr, + hdatain, + + hdataout, + hready_n, + + mr_an_complete, + mr_page_rx, + mr_lp_adv_ability, + + mr_main_reset, + mr_an_enable, + mr_restart_an, + mr_adv_ability +); + +input rst_n; +input hclk; +input gbe_mode; +input sgmii_mode; +input hcs_n; +input hwrite_n; +input [3:0] haddr; +input [7:0] hdatain; + +output [7:0] hdataout; +output hready_n; + +input mr_an_complete; +input mr_page_rx; +input [15:0] mr_lp_adv_ability; + +output mr_main_reset; +output mr_an_enable; +output mr_restart_an; +output [15:0] mr_adv_ability; + +/////////////////////////////////// + + + +reg [7:0] hdataout; +reg hr; +reg hready_n; + +reg hcs_n_delayed; + +wire reg0_cs_0; +wire reg0_cs_1; + +wire reg1_cs_0; +wire reg1_cs_1; + +wire reg4_cs_0; +wire reg4_cs_1; + +wire reg5_cs_0; +wire reg5_cs_1; + +wire reg6_cs_0; +wire reg6_cs_1; + +wire [15:0] data_out_reg_0; +wire [15:0] data_out_reg_1; +wire [15:0] data_out_reg_4; +wire [15:0] data_out_reg_5; +wire [15:0] data_out_reg_6; + + + +register_addr_decoder ad_dec ( + .rst_n(rst_n), + .addr(haddr), + .cs_in(~hcs_n), + + .reg0_cs_0 (reg0_cs_0), + .reg0_cs_1 (reg0_cs_1), + .reg1_cs_0 (reg1_cs_0), + .reg1_cs_1 (reg1_cs_1), + .reg4_cs_0 (reg4_cs_0), + .reg4_cs_1 (reg4_cs_1), + .reg5_cs_0 (reg5_cs_0), + .reg5_cs_1 (reg5_cs_1), + .reg6_cs_0 (reg6_cs_0), + .reg6_cs_1 (reg6_cs_1) +); + + +register_0_hb register_0 ( + .rst_n (rst_n), + .clk (hclk), + .cs_0 (reg0_cs_0), + .cs_1 (reg0_cs_1), + .write (~hwrite_n), + .ready (1'b1), + .data_in ({hdatain, hdatain}), + + .data_out (data_out_reg_0), + .mr_main_reset (mr_main_reset), + .mr_an_enable (mr_an_enable), + .mr_restart_an (mr_restart_an) +); + + +register_1_hb register_1 ( + .rst_n (rst_n), + .cs_0 (reg1_cs_0), + .cs_1 (reg1_cs_1), + .mr_an_complete (mr_an_complete), + + .data_out (data_out_reg_1) +); + + +register_4_hb register_4 ( + .rst_n (rst_n), + .clk (hclk), + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .cs_0 (reg4_cs_0), + .cs_1 (reg4_cs_1), + .write (~hwrite_n), + .ready (1'b1), + .data_in ({hdatain, hdatain}), + + .data_out (data_out_reg_4), + .mr_adv_ability (mr_adv_ability) +); + + +register_5_hb register_5 ( + .rst_n (rst_n), + .mr_lp_adv_ability (mr_lp_adv_ability), + .cs_0 (reg5_cs_0), + .cs_1 (reg5_cs_1), + .ready (1'b1), + + .data_out (data_out_reg_5) +); + + +register_6_hb register_6 ( + .rst_n (rst_n), + .clk (hclk), + .mr_page_rx (mr_page_rx), + .cs_0 (reg6_cs_0), + .cs_1 (reg6_cs_1), + .write (~hwrite_n), + .ready (1'b1), + + .data_out (data_out_reg_6) +); + + + +// generate an ack +always @(posedge hclk or negedge rst_n) begin + if (rst_n == 1'b0) begin + hcs_n_delayed <= 1'b1; + hr <= 1'b1; + hready_n <= 1'b1; + end + else begin + hcs_n_delayed <= hcs_n; + + //assert on falling edge of delayed chip select + hr <= ~hcs_n & hcs_n_delayed; + hready_n <= ~hr; + end +end + + + +// Mux Register Read-Data Outputs +always @(posedge hclk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + hdataout <= 8'd0; + end + else begin + case (haddr[3:0]) + + 4'd0: + begin + hdataout <= data_out_reg_0[7:0]; + end + + + 4'd1: + begin + hdataout <= data_out_reg_0[15:8]; + end + + ///////////////////////////////////////////// + + 4'd2: + begin + hdataout <= data_out_reg_1[7:0]; + end + + + 4'd3: + begin + hdataout <= data_out_reg_1[15:8]; + end + + ///////////////////////////////////////////// + + 4'd8: + begin + hdataout <= data_out_reg_4[7:0]; + end + + + 4'd9: + begin + hdataout <= data_out_reg_4[15:8]; + end + + ///////////////////////////////////////////// + + 4'd10: + begin + hdataout <= data_out_reg_5[7:0]; + end + + + 4'd11: + begin + hdataout <= data_out_reg_5[15:8]; + end + + ///////////////////////////////////////////// + + 4'd12: + begin + hdataout <= data_out_reg_6[7:0]; + end + + + 4'd13: + begin + hdataout <= data_out_reg_6[15:8]; + end + + ///////////////////////////////////////////// + + default: + begin + hdataout <= 8'd0; + end + endcase + end +end + +endmodule + +module register_addr_decoder ( + rst_n, + addr, + cs_in, + + reg0_cs_0, + reg0_cs_1, + + reg1_cs_0, + reg1_cs_1, + + reg4_cs_0, + reg4_cs_1, + + reg5_cs_0, + reg5_cs_1, + + reg6_cs_0, + reg6_cs_1 +); + +input rst_n; +input cs_in; +input [3:0] addr; + +output reg0_cs_0; +output reg0_cs_1; + +output reg1_cs_0; +output reg1_cs_1; + +output reg4_cs_0; +output reg4_cs_1; + +output reg5_cs_0; +output reg5_cs_1; + +output reg6_cs_0; +output reg6_cs_1; + +////////////////////////// + +wire reg0_cs_0; +wire reg0_cs_1; + +wire reg1_cs_0; +wire reg1_cs_1; + +wire reg4_cs_0; +wire reg4_cs_1; + +wire reg5_cs_0; +wire reg5_cs_1; + +wire reg6_cs_0; +wire reg6_cs_1; + +////////////////////////// + +assign reg0_cs_0 = (addr == 4'h0) ? cs_in : 1'b0; +assign reg0_cs_1 = (addr == 4'h1) ? cs_in : 1'b0; + +assign reg1_cs_0 = (addr == 4'h2) ? cs_in : 1'b0; +assign reg1_cs_1 = (addr == 4'h3) ? cs_in : 1'b0; + +assign reg4_cs_0 = (addr == 4'h8) ? cs_in : 1'b0; +assign reg4_cs_1 = (addr == 4'h9) ? cs_in : 1'b0; + +assign reg5_cs_0 = (addr == 4'ha) ? cs_in : 1'b0; +assign reg5_cs_1 = (addr == 4'hb) ? cs_in : 1'b0; + +assign reg6_cs_0 = (addr == 4'hc) ? cs_in : 1'b0; +assign reg6_cs_1 = (addr == 4'hd) ? cs_in : 1'b0; + + +endmodule + diff --git a/gbe_trb/media/reset_controller_cdr.v b/gbe_trb/media/reset_controller_cdr.v new file mode 100755 index 0000000..fa0a645 --- /dev/null +++ b/gbe_trb/media/reset_controller_cdr.v @@ -0,0 +1,219 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +//////////////////////////////////////////////////////////////////////// +// This module forces a RESET to the SERDES CDR +// when the CDR either loses lock or loses signal +//////////////////////////////////////////////////////////////////////// + +`timescale 1ns/100ps + +module reset_controller_cdr ( + + rst_n, + clk, + + cdr_lol, + + cdr_rst_out + ); + +input rst_n; +input clk; // 125Mhz clock + +input cdr_lol; + +output cdr_rst_out; + + +/////////////////////////////////////// + +reg cdr_rst_out; + +reg cdr_lol_mstb_1; +reg cdr_lol_mstb_2; + + +reg sht_mx; +reg [5:0] sht_count; + +reg lng_mx; +reg [22:0] lng_count; + +reg cnt_rst; +parameter + ASSRT_RST = 3'd0, + WAIT_SHORT = 3'd1, + DSSRT_RST = 3'd2, + WAIT_LONG = 3'd3, + SEEK_CDR_ERR = 3'd4, + SEEK_SIGNAL_RESTORE = 3'd5; +reg[2:0] fsm; + +////////////////////////////////////// +// Mestastability Filter +////////////////////////////////////// +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + cdr_lol_mstb_1 <= 1'b1; + cdr_lol_mstb_2 <= 1'b1; + + + end + else begin + cdr_lol_mstb_1 <= cdr_lol; + cdr_lol_mstb_2 <= cdr_lol_mstb_1; + + end +end + + + +/////////////////////////////////////// +// Operate Short Timer (256 nsec) +/////////////////////////////////////// +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + sht_mx <= 1'b0; + sht_count <= 6'd0; + end + else begin + + // define max count + if (sht_count[5] && (!cnt_rst)) begin + sht_mx <= 1'b1; + end + else begin + sht_mx <= 1'b0; + end + + // operate counter + if (cnt_rst) begin + sht_count <= 6'd0; //clear + end + else if (sht_mx) begin + sht_count <= sht_count; //hold + end + else begin + sht_count <= sht_count + 1; //count + end + end +end + + +///////////////////////////////////// +// Operate Long Timer (33 msec) +///////////////////////////////////// +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + lng_mx <= 1'b0; + lng_count <= 23'd0; + end + else begin + + // define max count + if (lng_count[22] && (!cnt_rst)) begin + lng_mx <= 1'b1; + end + else begin + lng_mx <= 1'b0; + end + + // operate counter + if (cnt_rst) begin + lng_count <= 6'd0; //clear + end + else if (lng_mx) begin + lng_count <= lng_count; //hold + end + else begin + lng_count <= lng_count + 1; //count + end + end +end + + +///////////////////////////////////// +// State Machine +///////////////////////////////////// +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + cdr_rst_out <= 1'b1; + cnt_rst <= 1'b1; + fsm <= ASSRT_RST; + end + else begin + + // defaults + cnt_rst <= 1'b0; + + case (fsm) + ASSRT_RST: begin + cdr_rst_out <= 1'b1; // assert + cnt_rst <= 1'b1; + fsm <= WAIT_SHORT; + end + + WAIT_SHORT: begin + // wait for 256 nsec + if (sht_mx && (!cnt_rst)) begin + fsm <= DSSRT_RST; + end + end + + DSSRT_RST: begin + cdr_rst_out <= 1'b0; // de-assert + fsm <= WAIT_LONG; + end + + WAIT_LONG: begin + // wait for 33 msec + if (lng_mx && (!cnt_rst)) begin + fsm <= SEEK_CDR_ERR; + end + end + + SEEK_CDR_ERR: begin + + cnt_rst <= 1'b1; + + + // Wait for CDR to fail + if (cdr_lol_mstb_2) begin + fsm <= ASSRT_RST; + end + else begin + fsm <= SEEK_CDR_ERR; + end + end + + + + default: begin + fsm <= ASSRT_RST; + end + endcase + + end +end + + + +endmodule + diff --git a/gbe_trb/media/reset_controller_pcs.v b/gbe_trb/media/reset_controller_pcs.v new file mode 100755 index 0000000..9d2e584 --- /dev/null +++ b/gbe_trb/media/reset_controller_pcs.v @@ -0,0 +1,226 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +//////////////////////////////////////////////////////////////////////// +// This module implements the SERDES/PCS reset sequence as specified +// in Figure 47 of Lattice Technical Note TN1176 +//////////////////////////////////////////////////////////////////////// + +`timescale 1ns/100ps + +module reset_controller_pcs ( + + rst_n, + clk, + + tx_plol, + rx_cdr_lol, + + quad_rst_out, + tx_pcs_rst_out, + rx_pcs_rst_out + ); + +input rst_n; +input clk; // 125Mhz clock + +input tx_plol; +input rx_cdr_lol; + +output quad_rst_out; +output tx_pcs_rst_out; +output rx_pcs_rst_out; + + +/////////////////////////////////////// + +reg quad_rst_out; +reg tx_pcs_rst_out; +reg rx_pcs_rst_out; + +reg q_mx; +reg [3:0] q_count; + +reg rx_cdr_lol_mstb_1; +reg rx_cdr_lol_mstb_2; + +reg wd_mx; +reg wd_mx_d1; +reg wd_mx_re; +reg [22:0] wd_count; +reg watchdog_flag; + +//////////////////////////////////////////////////////// +// Assert Quad RST For 8 Clocks After Device Hard Reset +//////////////////////////////////////////////////////// +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + q_mx <= 1'b0; + q_count <= 4'd0; + quad_rst_out <= 1'b1; // assert + end + else begin + + // define max count + if (q_count[3]) begin + q_mx <= 1'b1; + end + else begin + q_mx <= 1'b0; + end + + // operate counter + if (q_mx) begin + q_count <= q_count; //hold + end + else begin + q_count <= q_count + 1; //count + end + + // operate quad reset + if (q_mx) begin + quad_rst_out <= 1'b0; //de-assert on max-count + end + else begin + quad_rst_out <= 1'b1; //assert otherwise + end + end +end + + +//////////////////////////////////////////////////////////////////// +// Watchdog Timer -- In Case PLLs Don't Acquire Lock Within 33msec +//////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + wd_mx <= 1'b0; + wd_mx_d1 <= 1'b0; + wd_mx_re <= 1'b0; + wd_count <= 23'd0; + watchdog_flag <= 1'b0; + end + else begin + + // define max count + if (wd_count[22]) begin + wd_mx <= 1'b1; + end + else begin + wd_mx <= 1'b0; + end + + // operate counter + if (quad_rst_out) begin + wd_count <= 23'd0; //clear + end + else if (wd_mx) begin + wd_count <= wd_count; //hold + end + else begin + wd_count <= wd_count + 1; //count + end + + // detect rising edge of max_count flag + wd_mx_d1 <= wd_mx; + + wd_mx_re <= wd_mx & (!wd_mx_d1); + + // generate watchdog flag + watchdog_flag <= wd_mx_re; + end +end + + + + +//////////////////////////////////////////////// +// De-Assert TX PCS After TX PLL Acquires Lock +//////////////////////////////////////////////// +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + tx_pcs_rst_out <= 1'b1; // assert + end + else begin + + case (tx_pcs_rst_out) + 1'b1: begin + // if asserted, wait for PLL to acquire lock + if ((!quad_rst_out && (!tx_plol)) || watchdog_flag) begin + tx_pcs_rst_out <= 1'b0; // deassert + end + end + + 1'b0: begin + // if de-asserted, stay that way + tx_pcs_rst_out <= 1'b0; // deassert + end + + default: begin + tx_pcs_rst_out <= 1'b1; // assert + end + endcase + + end +end + + + + + +/////////////////////////////////////////////////////// +// De-Assert RX PCS-Chan-0 After RX CDR Acquires Lock +/////////////////////////////////////////////////////// +always @(posedge clk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + rx_pcs_rst_out <= 1'b1; // assert + rx_cdr_lol_mstb_1 <= 1'b1; + rx_cdr_lol_mstb_2 <= 1'b1; + end + else begin + + // metastability - filter + rx_cdr_lol_mstb_1 <= rx_cdr_lol; + rx_cdr_lol_mstb_2 <= rx_cdr_lol_mstb_1; + + case (rx_pcs_rst_out) + 1'b1: begin + // if asserted, wait for CDR to acquire lock + if ((!quad_rst_out && (!rx_cdr_lol_mstb_2)) || watchdog_flag) begin + rx_pcs_rst_out <= 1'b0; // deassert + end + end + + 1'b0: begin + // if de-asserted, stay that way + rx_pcs_rst_out <= 1'b0; // deassert + end + + default: begin + rx_pcs_rst_out <= 1'b1; // assert + end + endcase + + end +end + + + + +endmodule + diff --git a/gbe_trb/media/serdes_gbe_4ch.vhd b/gbe_trb/media/serdes_gbe_4ch.vhd new file mode 100644 index 0000000..4ea00c9 --- /dev/null +++ b/gbe_trb/media/serdes_gbe_4ch.vhd @@ -0,0 +1,2792 @@ + + + +--synopsys translate_off + +library pcsd_work; +use pcsd_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSD is +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String := "REFCLK_EXT"; + CH1_CDR_SRC : String := "REFCLK_EXT"; + CH2_CDR_SRC : String := "REFCLK_EXT"; + CH3_CDR_SRC : String := "REFCLK_EXT"; + PLL_SRC : String +-- CONFIG_FILE : String := "serdes_gbe_4ch.txt"; +-- QUAD_MODE : String := "SINGLE"; +-- CH0_CDR_SRC : String := "REFCLK_CORE"; +-- CH1_CDR_SRC : String := "REFCLK_CORE"; +-- CH2_CDR_SRC : String := "REFCLK_CORE"; +-- CH3_CDR_SRC : String := "REFCLK_CORE"; +-- PLL_SRC : String := "REFCLK_CORE" + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); + +end PCSD; + +architecture PCSD_arch of PCSD is + + +component PCSD_sim +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String; + CH1_CDR_SRC : String; + CH2_CDR_SRC : String; + CH3_CDR_SRC : String; + PLL_SRC : String + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); +end component; + +begin + +PCSD_sim_inst : PCSD_sim +generic map ( + CONFIG_FILE => CONFIG_FILE, + QUAD_MODE => QUAD_MODE, + CH0_CDR_SRC => CH0_CDR_SRC, + CH1_CDR_SRC => CH1_CDR_SRC, + CH2_CDR_SRC => CH2_CDR_SRC, + CH3_CDR_SRC => CH3_CDR_SRC, + PLL_SRC => PLL_SRC + ) +port map ( + HDINN0 => HDINN0, + HDINN1 => HDINN1, + HDINN2 => HDINN2, + HDINN3 => HDINN3, + HDINP0 => HDINP0, + HDINP1 => HDINP1, + HDINP2 => HDINP2, + HDINP3 => HDINP3, + REFCLKN => REFCLKN, + REFCLKP => REFCLKP, + CIN11 => CIN11, + CIN10 => CIN10, + CIN9 => CIN9, + CIN8 => CIN8, + CIN7 => CIN7, + CIN6 => CIN6, + CIN5 => CIN5, + CIN4 => CIN4, + CIN3 => CIN3, + CIN2 => CIN2, + CIN1 => CIN1, + CIN0 => CIN0, + CYAWSTN => CYAWSTN, + FF_EBRD_CLK_3 => FF_EBRD_CLK_3, + FF_EBRD_CLK_2 => FF_EBRD_CLK_2, + FF_EBRD_CLK_1 => FF_EBRD_CLK_1, + FF_EBRD_CLK_0 => FF_EBRD_CLK_0, + FF_RXI_CLK_3 => FF_RXI_CLK_3, + FF_RXI_CLK_2 => FF_RXI_CLK_2, + FF_RXI_CLK_1 => FF_RXI_CLK_1, + FF_RXI_CLK_0 => FF_RXI_CLK_0, + FF_TX_D_0_0 => FF_TX_D_0_0, + FF_TX_D_0_1 => FF_TX_D_0_1, + FF_TX_D_0_2 => FF_TX_D_0_2, + FF_TX_D_0_3 => FF_TX_D_0_3, + FF_TX_D_0_4 => FF_TX_D_0_4, + FF_TX_D_0_5 => FF_TX_D_0_5, + FF_TX_D_0_6 => FF_TX_D_0_6, + FF_TX_D_0_7 => FF_TX_D_0_7, + FF_TX_D_0_8 => FF_TX_D_0_8, + FF_TX_D_0_9 => FF_TX_D_0_9, + FF_TX_D_0_10 => FF_TX_D_0_10, + FF_TX_D_0_11 => FF_TX_D_0_11, + FF_TX_D_0_12 => FF_TX_D_0_12, + FF_TX_D_0_13 => FF_TX_D_0_13, + FF_TX_D_0_14 => FF_TX_D_0_14, + FF_TX_D_0_15 => FF_TX_D_0_15, + FF_TX_D_0_16 => FF_TX_D_0_16, + FF_TX_D_0_17 => FF_TX_D_0_17, + FF_TX_D_0_18 => FF_TX_D_0_18, + FF_TX_D_0_19 => FF_TX_D_0_19, + FF_TX_D_0_20 => FF_TX_D_0_20, + FF_TX_D_0_21 => FF_TX_D_0_21, + FF_TX_D_0_22 => FF_TX_D_0_22, + FF_TX_D_0_23 => FF_TX_D_0_23, + FF_TX_D_1_0 => FF_TX_D_1_0, + FF_TX_D_1_1 => FF_TX_D_1_1, + FF_TX_D_1_2 => FF_TX_D_1_2, + FF_TX_D_1_3 => FF_TX_D_1_3, + FF_TX_D_1_4 => FF_TX_D_1_4, + FF_TX_D_1_5 => FF_TX_D_1_5, + FF_TX_D_1_6 => FF_TX_D_1_6, + FF_TX_D_1_7 => FF_TX_D_1_7, + FF_TX_D_1_8 => FF_TX_D_1_8, + FF_TX_D_1_9 => FF_TX_D_1_9, + FF_TX_D_1_10 => FF_TX_D_1_10, + FF_TX_D_1_11 => FF_TX_D_1_11, + FF_TX_D_1_12 => FF_TX_D_1_12, + FF_TX_D_1_13 => FF_TX_D_1_13, + FF_TX_D_1_14 => FF_TX_D_1_14, + FF_TX_D_1_15 => FF_TX_D_1_15, + FF_TX_D_1_16 => FF_TX_D_1_16, + FF_TX_D_1_17 => FF_TX_D_1_17, + FF_TX_D_1_18 => FF_TX_D_1_18, + FF_TX_D_1_19 => FF_TX_D_1_19, + FF_TX_D_1_20 => FF_TX_D_1_20, + FF_TX_D_1_21 => FF_TX_D_1_21, + FF_TX_D_1_22 => FF_TX_D_1_22, + FF_TX_D_1_23 => FF_TX_D_1_23, + FF_TX_D_2_0 => FF_TX_D_2_0, + FF_TX_D_2_1 => FF_TX_D_2_1, + FF_TX_D_2_2 => FF_TX_D_2_2, + FF_TX_D_2_3 => FF_TX_D_2_3, + FF_TX_D_2_4 => FF_TX_D_2_4, + FF_TX_D_2_5 => FF_TX_D_2_5, + FF_TX_D_2_6 => FF_TX_D_2_6, + FF_TX_D_2_7 => FF_TX_D_2_7, + FF_TX_D_2_8 => FF_TX_D_2_8, + FF_TX_D_2_9 => FF_TX_D_2_9, + FF_TX_D_2_10 => FF_TX_D_2_10, + FF_TX_D_2_11 => FF_TX_D_2_11, + FF_TX_D_2_12 => FF_TX_D_2_12, + FF_TX_D_2_13 => FF_TX_D_2_13, + FF_TX_D_2_14 => FF_TX_D_2_14, + FF_TX_D_2_15 => FF_TX_D_2_15, + FF_TX_D_2_16 => FF_TX_D_2_16, + FF_TX_D_2_17 => FF_TX_D_2_17, + FF_TX_D_2_18 => FF_TX_D_2_18, + FF_TX_D_2_19 => FF_TX_D_2_19, + FF_TX_D_2_20 => FF_TX_D_2_20, + FF_TX_D_2_21 => FF_TX_D_2_21, + FF_TX_D_2_22 => FF_TX_D_2_22, + FF_TX_D_2_23 => FF_TX_D_2_23, + FF_TX_D_3_0 => FF_TX_D_3_0, + FF_TX_D_3_1 => FF_TX_D_3_1, + FF_TX_D_3_2 => FF_TX_D_3_2, + FF_TX_D_3_3 => FF_TX_D_3_3, + FF_TX_D_3_4 => FF_TX_D_3_4, + FF_TX_D_3_5 => FF_TX_D_3_5, + FF_TX_D_3_6 => FF_TX_D_3_6, + FF_TX_D_3_7 => FF_TX_D_3_7, + FF_TX_D_3_8 => FF_TX_D_3_8, + FF_TX_D_3_9 => FF_TX_D_3_9, + FF_TX_D_3_10 => FF_TX_D_3_10, + FF_TX_D_3_11 => FF_TX_D_3_11, + FF_TX_D_3_12 => FF_TX_D_3_12, + FF_TX_D_3_13 => FF_TX_D_3_13, + FF_TX_D_3_14 => FF_TX_D_3_14, + FF_TX_D_3_15 => FF_TX_D_3_15, + FF_TX_D_3_16 => FF_TX_D_3_16, + FF_TX_D_3_17 => FF_TX_D_3_17, + FF_TX_D_3_18 => FF_TX_D_3_18, + FF_TX_D_3_19 => FF_TX_D_3_19, + FF_TX_D_3_20 => FF_TX_D_3_20, + FF_TX_D_3_21 => FF_TX_D_3_21, + FF_TX_D_3_22 => FF_TX_D_3_22, + FF_TX_D_3_23 => FF_TX_D_3_23, + FF_TXI_CLK_0 => FF_TXI_CLK_0, + FF_TXI_CLK_1 => FF_TXI_CLK_1, + FF_TXI_CLK_2 => FF_TXI_CLK_2, + FF_TXI_CLK_3 => FF_TXI_CLK_3, + FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, + FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, + FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, + FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_EI_EN_0 => FFC_EI_EN_0, + FFC_EI_EN_1 => FFC_EI_EN_1, + FFC_EI_EN_2 => FFC_EI_EN_2, + FFC_EI_EN_3 => FFC_EI_EN_3, + FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, + FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, + FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, + FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, + FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, + FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, + FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, + FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, + FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, + FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, + FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, + FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, + FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, + FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, + FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, + FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, + FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, + FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, + FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, + FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, + FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, + FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_RRST_0 => FFC_RRST_0, + FFC_RRST_1 => FFC_RRST_1, + FFC_RRST_2 => FFC_RRST_2, + FFC_RRST_3 => FFC_RRST_3, + FFC_RXPWDNB_0 => FFC_RXPWDNB_0, + FFC_RXPWDNB_1 => FFC_RXPWDNB_1, + FFC_RXPWDNB_2 => FFC_RXPWDNB_2, + FFC_RXPWDNB_3 => FFC_RXPWDNB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, + FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, + FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, + FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, + FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, + FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, + FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, + FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, + FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, + FFC_TRST => FFC_TRST, + FFC_TXPWDNB_0 => FFC_TXPWDNB_0, + FFC_TXPWDNB_1 => FFC_TXPWDNB_1, + FFC_TXPWDNB_2 => FFC_TXPWDNB_2, + FFC_TXPWDNB_3 => FFC_TXPWDNB_3, + FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, + FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, + FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, + FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, + FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, + FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, + FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, + FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, + FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, + FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, + FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, + FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, + FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, + FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, + FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, + FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, + LDR_CORE2TX_0 => LDR_CORE2TX_0, + LDR_CORE2TX_1 => LDR_CORE2TX_1, + LDR_CORE2TX_2 => LDR_CORE2TX_2, + LDR_CORE2TX_3 => LDR_CORE2TX_3, + FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, + FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, + FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, + FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, + PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, + PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, + PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, + PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, + PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, + PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, + PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, + PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, + PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, + PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, + PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, + PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, + PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, + PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, + PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, + PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, + PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, + PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, + PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, + PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, + SCIADDR0 => SCIADDR0, + SCIADDR1 => SCIADDR1, + SCIADDR2 => SCIADDR2, + SCIADDR3 => SCIADDR3, + SCIADDR4 => SCIADDR4, + SCIADDR5 => SCIADDR5, + SCIENAUX => SCIENAUX, + SCIENCH0 => SCIENCH0, + SCIENCH1 => SCIENCH1, + SCIENCH2 => SCIENCH2, + SCIENCH3 => SCIENCH3, + SCIRD => SCIRD, + SCISELAUX => SCISELAUX, + SCISELCH0 => SCISELCH0, + SCISELCH1 => SCISELCH1, + SCISELCH2 => SCISELCH2, + SCISELCH3 => SCISELCH3, + SCIWDATA0 => SCIWDATA0, + SCIWDATA1 => SCIWDATA1, + SCIWDATA2 => SCIWDATA2, + SCIWDATA3 => SCIWDATA3, + SCIWDATA4 => SCIWDATA4, + SCIWDATA5 => SCIWDATA5, + SCIWDATA6 => SCIWDATA6, + SCIWDATA7 => SCIWDATA7, + SCIWSTN => SCIWSTN, + HDOUTN0 => HDOUTN0, + HDOUTN1 => HDOUTN1, + HDOUTN2 => HDOUTN2, + HDOUTN3 => HDOUTN3, + HDOUTP0 => HDOUTP0, + HDOUTP1 => HDOUTP1, + HDOUTP2 => HDOUTP2, + HDOUTP3 => HDOUTP3, + COUT19 => COUT19, + COUT18 => COUT18, + COUT17 => COUT17, + COUT16 => COUT16, + COUT15 => COUT15, + COUT14 => COUT14, + COUT13 => COUT13, + COUT12 => COUT12, + COUT11 => COUT11, + COUT10 => COUT10, + COUT9 => COUT9, + COUT8 => COUT8, + COUT7 => COUT7, + COUT6 => COUT6, + COUT5 => COUT5, + COUT4 => COUT4, + COUT3 => COUT3, + COUT2 => COUT2, + COUT1 => COUT1, + COUT0 => COUT0, + FF_RX_D_0_0 => FF_RX_D_0_0, + FF_RX_D_0_1 => FF_RX_D_0_1, + FF_RX_D_0_2 => FF_RX_D_0_2, + FF_RX_D_0_3 => FF_RX_D_0_3, + FF_RX_D_0_4 => FF_RX_D_0_4, + FF_RX_D_0_5 => FF_RX_D_0_5, + FF_RX_D_0_6 => FF_RX_D_0_6, + FF_RX_D_0_7 => FF_RX_D_0_7, + FF_RX_D_0_8 => FF_RX_D_0_8, + FF_RX_D_0_9 => FF_RX_D_0_9, + FF_RX_D_0_10 => FF_RX_D_0_10, + FF_RX_D_0_11 => FF_RX_D_0_11, + FF_RX_D_0_12 => FF_RX_D_0_12, + FF_RX_D_0_13 => FF_RX_D_0_13, + FF_RX_D_0_14 => FF_RX_D_0_14, + FF_RX_D_0_15 => FF_RX_D_0_15, + FF_RX_D_0_16 => FF_RX_D_0_16, + FF_RX_D_0_17 => FF_RX_D_0_17, + FF_RX_D_0_18 => FF_RX_D_0_18, + FF_RX_D_0_19 => FF_RX_D_0_19, + FF_RX_D_0_20 => FF_RX_D_0_20, + FF_RX_D_0_21 => FF_RX_D_0_21, + FF_RX_D_0_22 => FF_RX_D_0_22, + FF_RX_D_0_23 => FF_RX_D_0_23, + FF_RX_D_1_0 => FF_RX_D_1_0, + FF_RX_D_1_1 => FF_RX_D_1_1, + FF_RX_D_1_2 => FF_RX_D_1_2, + FF_RX_D_1_3 => FF_RX_D_1_3, + FF_RX_D_1_4 => FF_RX_D_1_4, + FF_RX_D_1_5 => FF_RX_D_1_5, + FF_RX_D_1_6 => FF_RX_D_1_6, + FF_RX_D_1_7 => FF_RX_D_1_7, + FF_RX_D_1_8 => FF_RX_D_1_8, + FF_RX_D_1_9 => FF_RX_D_1_9, + FF_RX_D_1_10 => FF_RX_D_1_10, + FF_RX_D_1_11 => FF_RX_D_1_11, + FF_RX_D_1_12 => FF_RX_D_1_12, + FF_RX_D_1_13 => FF_RX_D_1_13, + FF_RX_D_1_14 => FF_RX_D_1_14, + FF_RX_D_1_15 => FF_RX_D_1_15, + FF_RX_D_1_16 => FF_RX_D_1_16, + FF_RX_D_1_17 => FF_RX_D_1_17, + FF_RX_D_1_18 => FF_RX_D_1_18, + FF_RX_D_1_19 => FF_RX_D_1_19, + FF_RX_D_1_20 => FF_RX_D_1_20, + FF_RX_D_1_21 => FF_RX_D_1_21, + FF_RX_D_1_22 => FF_RX_D_1_22, + FF_RX_D_1_23 => FF_RX_D_1_23, + FF_RX_D_2_0 => FF_RX_D_2_0, + FF_RX_D_2_1 => FF_RX_D_2_1, + FF_RX_D_2_2 => FF_RX_D_2_2, + FF_RX_D_2_3 => FF_RX_D_2_3, + FF_RX_D_2_4 => FF_RX_D_2_4, + FF_RX_D_2_5 => FF_RX_D_2_5, + FF_RX_D_2_6 => FF_RX_D_2_6, + FF_RX_D_2_7 => FF_RX_D_2_7, + FF_RX_D_2_8 => FF_RX_D_2_8, + FF_RX_D_2_9 => FF_RX_D_2_9, + FF_RX_D_2_10 => FF_RX_D_2_10, + FF_RX_D_2_11 => FF_RX_D_2_11, + FF_RX_D_2_12 => FF_RX_D_2_12, + FF_RX_D_2_13 => FF_RX_D_2_13, + FF_RX_D_2_14 => FF_RX_D_2_14, + FF_RX_D_2_15 => FF_RX_D_2_15, + FF_RX_D_2_16 => FF_RX_D_2_16, + FF_RX_D_2_17 => FF_RX_D_2_17, + FF_RX_D_2_18 => FF_RX_D_2_18, + FF_RX_D_2_19 => FF_RX_D_2_19, + FF_RX_D_2_20 => FF_RX_D_2_20, + FF_RX_D_2_21 => FF_RX_D_2_21, + FF_RX_D_2_22 => FF_RX_D_2_22, + FF_RX_D_2_23 => FF_RX_D_2_23, + FF_RX_D_3_0 => FF_RX_D_3_0, + FF_RX_D_3_1 => FF_RX_D_3_1, + FF_RX_D_3_2 => FF_RX_D_3_2, + FF_RX_D_3_3 => FF_RX_D_3_3, + FF_RX_D_3_4 => FF_RX_D_3_4, + FF_RX_D_3_5 => FF_RX_D_3_5, + FF_RX_D_3_6 => FF_RX_D_3_6, + FF_RX_D_3_7 => FF_RX_D_3_7, + FF_RX_D_3_8 => FF_RX_D_3_8, + FF_RX_D_3_9 => FF_RX_D_3_9, + FF_RX_D_3_10 => FF_RX_D_3_10, + FF_RX_D_3_11 => FF_RX_D_3_11, + FF_RX_D_3_12 => FF_RX_D_3_12, + FF_RX_D_3_13 => FF_RX_D_3_13, + FF_RX_D_3_14 => FF_RX_D_3_14, + FF_RX_D_3_15 => FF_RX_D_3_15, + FF_RX_D_3_16 => FF_RX_D_3_16, + FF_RX_D_3_17 => FF_RX_D_3_17, + FF_RX_D_3_18 => FF_RX_D_3_18, + FF_RX_D_3_19 => FF_RX_D_3_19, + FF_RX_D_3_20 => FF_RX_D_3_20, + FF_RX_D_3_21 => FF_RX_D_3_21, + FF_RX_D_3_22 => FF_RX_D_3_22, + FF_RX_D_3_23 => FF_RX_D_3_23, + FF_RX_F_CLK_0 => FF_RX_F_CLK_0, + FF_RX_F_CLK_1 => FF_RX_F_CLK_1, + FF_RX_F_CLK_2 => FF_RX_F_CLK_2, + FF_RX_F_CLK_3 => FF_RX_F_CLK_3, + FF_RX_H_CLK_0 => FF_RX_H_CLK_0, + FF_RX_H_CLK_1 => FF_RX_H_CLK_1, + FF_RX_H_CLK_2 => FF_RX_H_CLK_2, + FF_RX_H_CLK_3 => FF_RX_H_CLK_3, + FF_TX_F_CLK_0 => FF_TX_F_CLK_0, + FF_TX_F_CLK_1 => FF_TX_F_CLK_1, + FF_TX_F_CLK_2 => FF_TX_F_CLK_2, + FF_TX_F_CLK_3 => FF_TX_F_CLK_3, + FF_TX_H_CLK_0 => FF_TX_H_CLK_0, + FF_TX_H_CLK_1 => FF_TX_H_CLK_1, + FF_TX_H_CLK_2 => FF_TX_H_CLK_2, + FF_TX_H_CLK_3 => FF_TX_H_CLK_3, + FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, + FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, + FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, + FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, + FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, + FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, + FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, + FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, + FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, + FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, + FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, + FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, + FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, + FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, + FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, + FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFS_PLOL => FFS_PLOL, + FFS_RLOL_0 => FFS_RLOL_0, + FFS_RLOL_1 => FFS_RLOL_1, + FFS_RLOL_2 => FFS_RLOL_2, + FFS_RLOL_3 => FFS_RLOL_3, + FFS_RLOS_HI_0 => FFS_RLOS_HI_0, + FFS_RLOS_HI_1 => FFS_RLOS_HI_1, + FFS_RLOS_HI_2 => FFS_RLOS_HI_2, + FFS_RLOS_HI_3 => FFS_RLOS_HI_3, + FFS_RLOS_LO_0 => FFS_RLOS_LO_0, + FFS_RLOS_LO_1 => FFS_RLOS_LO_1, + FFS_RLOS_LO_2 => FFS_RLOS_LO_2, + FFS_RLOS_LO_3 => FFS_RLOS_LO_3, + FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, + FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, + FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, + FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, + FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, + FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, + FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, + FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, + PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, + PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, + PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, + PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, + PCIE_RXVALID_0 => PCIE_RXVALID_0, + PCIE_RXVALID_1 => PCIE_RXVALID_1, + PCIE_RXVALID_2 => PCIE_RXVALID_2, + PCIE_RXVALID_3 => PCIE_RXVALID_3, + FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, + FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, + FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, + FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, + FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, + FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, + FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, + FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, + LDR_RX2CORE_0 => LDR_RX2CORE_0, + LDR_RX2CORE_1 => LDR_RX2CORE_1, + LDR_RX2CORE_2 => LDR_RX2CORE_2, + LDR_RX2CORE_3 => LDR_RX2CORE_3, + REFCK2CORE => REFCK2CORE, + SCIINT => SCIINT, + SCIRDATA0 => SCIRDATA0, + SCIRDATA1 => SCIRDATA1, + SCIRDATA2 => SCIRDATA2, + SCIRDATA3 => SCIRDATA3, + SCIRDATA4 => SCIRDATA4, + SCIRDATA5 => SCIRDATA5, + SCIRDATA6 => SCIRDATA6, + SCIRDATA7 => SCIRDATA7, + REFCLK_FROM_NQ => REFCLK_FROM_NQ, + REFCLK_TO_NQ => REFCLK_TO_NQ + ); + +end PCSD_arch; + +--synopsys translate_on + + + + +--synopsys translate_off +library ECP3; +use ECP3.components.all; +--synopsys translate_on + + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + +entity serdes_gbe_4ch is + GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_4ch.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (7 downto 0); + tx_k_ch0 : in std_logic; + xmit_ch0 : in std_logic; + tx_disp_correct_ch0 : in std_logic; + rxdata_ch0 : out std_logic_vector (7 downto 0); + rx_k_ch0 : out std_logic; + rx_disp_err_ch0 : out std_logic; + rx_cv_err_ch0 : out std_logic; + rx_serdes_rst_ch0_c : in std_logic; + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pcs_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pcs_rst_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; +-- CH1 -- + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (7 downto 0); + tx_k_ch1 : in std_logic; + xmit_ch1 : in std_logic; + tx_disp_correct_ch1 : in std_logic; + rxdata_ch1 : out std_logic_vector (7 downto 0); + rx_k_ch1 : out std_logic; + rx_disp_err_ch1 : out std_logic; + rx_cv_err_ch1 : out std_logic; + rx_serdes_rst_ch1_c : in std_logic; + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pcs_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pcs_rst_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; +-- CH2 -- + hdinp_ch2, hdinn_ch2 : in std_logic; + hdoutp_ch2, hdoutn_ch2 : out std_logic; + rxiclk_ch2 : in std_logic; + txiclk_ch2 : in std_logic; + rx_full_clk_ch2 : out std_logic; + rx_half_clk_ch2 : out std_logic; + tx_full_clk_ch2 : out std_logic; + tx_half_clk_ch2 : out std_logic; + fpga_rxrefclk_ch2 : in std_logic; + txdata_ch2 : in std_logic_vector (7 downto 0); + tx_k_ch2 : in std_logic; + xmit_ch2 : in std_logic; + tx_disp_correct_ch2 : in std_logic; + rxdata_ch2 : out std_logic_vector (7 downto 0); + rx_k_ch2 : out std_logic; + rx_disp_err_ch2 : out std_logic; + rx_cv_err_ch2 : out std_logic; + rx_serdes_rst_ch2_c : in std_logic; + sb_felb_ch2_c : in std_logic; + sb_felb_rst_ch2_c : in std_logic; + tx_pcs_rst_ch2_c : in std_logic; + tx_pwrup_ch2_c : in std_logic; + rx_pcs_rst_ch2_c : in std_logic; + rx_pwrup_ch2_c : in std_logic; + rx_los_low_ch2_s : out std_logic; + lsm_status_ch2_s : out std_logic; + rx_cdr_lol_ch2_s : out std_logic; +-- CH3 -- + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + rxiclk_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (7 downto 0); + tx_k_ch3 : in std_logic; + xmit_ch3 : in std_logic; + tx_disp_correct_ch3 : in std_logic; + rxdata_ch3 : out std_logic_vector (7 downto 0); + rx_k_ch3 : out std_logic; + rx_disp_err_ch3 : out std_logic; + rx_cv_err_ch3 : out std_logic; + rx_serdes_rst_ch3_c : in std_logic; + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pcs_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pcs_rst_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; +---- Miscillaneous ports + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + tx_sync_qd_c : in std_logic; + rst_qd_c : in std_logic; + serdes_rst_qd_c : in std_logic); + +end serdes_gbe_4ch; + + +architecture serdes_gbe_4ch_arch of serdes_gbe_4ch is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; + + + +component PCSD +--synopsys translate_off +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String := "REFCLK_EXT"; + CH1_CDR_SRC : String := "REFCLK_EXT"; + CH2_CDR_SRC : String := "REFCLK_EXT"; + CH3_CDR_SRC : String := "REFCLK_EXT"; + PLL_SRC : String + ); +--synopsys translate_on +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); +end component; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; + attribute QUAD_MODE: string; + attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; + attribute PLL_SRC: string; + attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute CH0_CDR_SRC: string; + attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute CH1_CDR_SRC: string; + attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute CH2_CDR_SRC: string; + attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute CH3_CDR_SRC: string; + attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000"; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; + +signal refclk_from_nq : std_logic := '0'; +signal fpsc_vlo : std_logic := '0'; +signal fpsc_vhi : std_logic := '1'; +signal cin : std_logic_vector (11 downto 0) := "000000000000"; +signal cout : std_logic_vector (19 downto 0); +signal tx_full_clk_ch0_sig : std_logic; +signal tx_full_clk_ch1_sig : std_logic; +signal tx_full_clk_ch2_sig : std_logic; +signal tx_full_clk_ch3_sig : std_logic; + +signal refclk2fpga_sig : std_logic; +signal tx_pll_lol_qd_sig : std_logic; +signal rx_los_low_ch0_sig : std_logic; +signal rx_los_low_ch1_sig : std_logic; +signal rx_los_low_ch2_sig : std_logic; +signal rx_los_low_ch3_sig : std_logic; +signal rx_cdr_lol_ch0_sig : std_logic; +signal rx_cdr_lol_ch1_sig : std_logic; +signal rx_cdr_lol_ch2_sig : std_logic; +signal rx_cdr_lol_ch3_sig : std_logic; + + + + + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); +vhi_inst : VHI port map(Z => fpsc_vhi); + + rx_los_low_ch0_s <= rx_los_low_ch0_sig; + rx_los_low_ch1_s <= rx_los_low_ch1_sig; + rx_los_low_ch2_s <= rx_los_low_ch2_sig; + rx_los_low_ch3_s <= rx_los_low_ch3_sig; + rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; + rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig; + rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig; + rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig; + tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; + tx_full_clk_ch0 <= tx_full_clk_ch0_sig; + tx_full_clk_ch1 <= tx_full_clk_ch1_sig; + tx_full_clk_ch2 <= tx_full_clk_ch2_sig; + tx_full_clk_ch3 <= tx_full_clk_ch3_sig; + +-- pcs_quad instance +PCSD_INST : PCSD +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE, + QUAD_MODE => "SINGLE", + CH0_CDR_SRC => "REFCLK_CORE", + CH1_CDR_SRC => "REFCLK_CORE", + CH2_CDR_SRC => "REFCLK_CORE", + CH3_CDR_SRC => "REFCLK_CORE", + PLL_SRC => "REFCLK_CORE" + ) +--synopsys translate_on +port map ( + REFCLKP => fpsc_vlo, + REFCLKN => fpsc_vlo, + +----- CH0 ----- + HDOUTP0 => hdoutp_ch0, + HDOUTN0 => hdoutn_ch0, + HDINP0 => hdinp_ch0, + HDINN0 => hdinn_ch0, + PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, + PCIE_TXCOMPLIANCE_0 => fpsc_vlo, + PCIE_RXPOLARITY_0 => fpsc_vlo, + PCIE_POWERDOWN_0_0 => fpsc_vlo, + PCIE_POWERDOWN_0_1 => fpsc_vlo, + PCIE_RXVALID_0 => open, + PCIE_PHYSTATUS_0 => open, + SCISELCH0 => fpsc_vlo, + SCIENCH0 => fpsc_vlo, + FF_RXI_CLK_0 => rxiclk_ch0, + FF_TXI_CLK_0 => txiclk_ch0, + FF_EBRD_CLK_0 => fpsc_vlo, + FF_RX_F_CLK_0 => rx_full_clk_ch0, + FF_RX_H_CLK_0 => rx_half_clk_ch0, + FF_TX_F_CLK_0 => tx_full_clk_ch0_sig, + FF_TX_H_CLK_0 => tx_half_clk_ch0, + FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0, + FF_TX_D_0_0 => txdata_ch0(0), + FF_TX_D_0_1 => txdata_ch0(1), + FF_TX_D_0_2 => txdata_ch0(2), + FF_TX_D_0_3 => txdata_ch0(3), + FF_TX_D_0_4 => txdata_ch0(4), + FF_TX_D_0_5 => txdata_ch0(5), + FF_TX_D_0_6 => txdata_ch0(6), + FF_TX_D_0_7 => txdata_ch0(7), + FF_TX_D_0_8 => tx_k_ch0, + FF_TX_D_0_9 => fpsc_vlo, + FF_TX_D_0_10 => xmit_ch0, + FF_TX_D_0_11 => tx_disp_correct_ch0, + FF_TX_D_0_12 => fpsc_vlo, + FF_TX_D_0_13 => fpsc_vlo, + FF_TX_D_0_14 => fpsc_vlo, + FF_TX_D_0_15 => fpsc_vlo, + FF_TX_D_0_16 => fpsc_vlo, + FF_TX_D_0_17 => fpsc_vlo, + FF_TX_D_0_18 => fpsc_vlo, + FF_TX_D_0_19 => fpsc_vlo, + FF_TX_D_0_20 => fpsc_vlo, + FF_TX_D_0_21 => fpsc_vlo, + FF_TX_D_0_22 => fpsc_vlo, + FF_TX_D_0_23 => fpsc_vlo, + FF_RX_D_0_0 => rxdata_ch0(0), + FF_RX_D_0_1 => rxdata_ch0(1), + FF_RX_D_0_2 => rxdata_ch0(2), + FF_RX_D_0_3 => rxdata_ch0(3), + FF_RX_D_0_4 => rxdata_ch0(4), + FF_RX_D_0_5 => rxdata_ch0(5), + FF_RX_D_0_6 => rxdata_ch0(6), + FF_RX_D_0_7 => rxdata_ch0(7), + FF_RX_D_0_8 => rx_k_ch0, + FF_RX_D_0_9 => rx_disp_err_ch0, + FF_RX_D_0_10 => rx_cv_err_ch0, + FF_RX_D_0_11 => open, + FF_RX_D_0_12 => open, + FF_RX_D_0_13 => open, + FF_RX_D_0_14 => open, + FF_RX_D_0_15 => open, + FF_RX_D_0_16 => open, + FF_RX_D_0_17 => open, + FF_RX_D_0_18 => open, + FF_RX_D_0_19 => open, + FF_RX_D_0_20 => open, + FF_RX_D_0_21 => open, + FF_RX_D_0_22 => open, + FF_RX_D_0_23 => open, + + FFC_RRST_0 => rx_serdes_rst_ch0_c, + FFC_SIGNAL_DETECT_0 => fpsc_vlo, + FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c, + FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCI_DET_EN_0 => fpsc_vlo, + FFC_FB_LOOPBACK_0 => fpsc_vlo, + FFC_ENABLE_CGALIGN_0 => fpsc_vlo, + FFC_EI_EN_0 => fpsc_vlo, + FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c, + FFC_TXPWDNB_0 => tx_pwrup_ch0_c, + FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c, + FFC_RXPWDNB_0 => rx_pwrup_ch0_c, + FFS_RLOS_LO_0 => rx_los_low_ch0_sig, + FFS_RLOS_HI_0 => open, + FFS_PCIE_CON_0 => open, + FFS_PCIE_DONE_0 => open, + FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s, + FFS_CC_OVERRUN_0 => open, + FFS_CC_UNDERRUN_0 => open, + FFS_SKP_ADDED_0 => open, + FFS_SKP_DELETED_0 => open, + FFS_RLOL_0 => rx_cdr_lol_ch0_sig, + FFS_RXFBFIFO_ERROR_0 => open, + FFS_TXFBFIFO_ERROR_0 => open, + LDR_CORE2TX_0 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, + LDR_RX2CORE_0 => open, + FFS_CDR_TRAIN_DONE_0 => open, + FFC_DIV11_MODE_TX_0 => fpsc_vlo, + FFC_RATE_MODE_TX_0 => fpsc_vlo, + FFC_DIV11_MODE_RX_0 => fpsc_vlo, + FFC_RATE_MODE_RX_0 => fpsc_vlo, + +----- CH1 ----- + HDOUTP1 => hdoutp_ch1, + HDOUTN1 => hdoutn_ch1, + HDINP1 => hdinp_ch1, + HDINN1 => hdinn_ch1, + PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, + PCIE_TXCOMPLIANCE_1 => fpsc_vlo, + PCIE_RXPOLARITY_1 => fpsc_vlo, + PCIE_POWERDOWN_1_0 => fpsc_vlo, + PCIE_POWERDOWN_1_1 => fpsc_vlo, + PCIE_RXVALID_1 => open, + PCIE_PHYSTATUS_1 => open, + SCISELCH1 => fpsc_vlo, + SCIENCH1 => fpsc_vlo, + FF_RXI_CLK_1 => rxiclk_ch1, + FF_TXI_CLK_1 => txiclk_ch1, + FF_EBRD_CLK_1 => fpsc_vlo, + FF_RX_F_CLK_1 => rx_full_clk_ch1, + FF_RX_H_CLK_1 => rx_half_clk_ch1, + FF_TX_F_CLK_1 => tx_full_clk_ch1_sig, + FF_TX_H_CLK_1 => tx_half_clk_ch1, + FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1, + FF_TX_D_1_0 => txdata_ch1(0), + FF_TX_D_1_1 => txdata_ch1(1), + FF_TX_D_1_2 => txdata_ch1(2), + FF_TX_D_1_3 => txdata_ch1(3), + FF_TX_D_1_4 => txdata_ch1(4), + FF_TX_D_1_5 => txdata_ch1(5), + FF_TX_D_1_6 => txdata_ch1(6), + FF_TX_D_1_7 => txdata_ch1(7), + FF_TX_D_1_8 => tx_k_ch1, + FF_TX_D_1_9 => fpsc_vlo, + FF_TX_D_1_10 => xmit_ch1, + FF_TX_D_1_11 => tx_disp_correct_ch1, + FF_TX_D_1_12 => fpsc_vlo, + FF_TX_D_1_13 => fpsc_vlo, + FF_TX_D_1_14 => fpsc_vlo, + FF_TX_D_1_15 => fpsc_vlo, + FF_TX_D_1_16 => fpsc_vlo, + FF_TX_D_1_17 => fpsc_vlo, + FF_TX_D_1_18 => fpsc_vlo, + FF_TX_D_1_19 => fpsc_vlo, + FF_TX_D_1_20 => fpsc_vlo, + FF_TX_D_1_21 => fpsc_vlo, + FF_TX_D_1_22 => fpsc_vlo, + FF_TX_D_1_23 => fpsc_vlo, + FF_RX_D_1_0 => rxdata_ch1(0), + FF_RX_D_1_1 => rxdata_ch1(1), + FF_RX_D_1_2 => rxdata_ch1(2), + FF_RX_D_1_3 => rxdata_ch1(3), + FF_RX_D_1_4 => rxdata_ch1(4), + FF_RX_D_1_5 => rxdata_ch1(5), + FF_RX_D_1_6 => rxdata_ch1(6), + FF_RX_D_1_7 => rxdata_ch1(7), + FF_RX_D_1_8 => rx_k_ch1, + FF_RX_D_1_9 => rx_disp_err_ch1, + FF_RX_D_1_10 => rx_cv_err_ch1, + FF_RX_D_1_11 => open, + FF_RX_D_1_12 => open, + FF_RX_D_1_13 => open, + FF_RX_D_1_14 => open, + FF_RX_D_1_15 => open, + FF_RX_D_1_16 => open, + FF_RX_D_1_17 => open, + FF_RX_D_1_18 => open, + FF_RX_D_1_19 => open, + FF_RX_D_1_20 => open, + FF_RX_D_1_21 => open, + FF_RX_D_1_22 => open, + FF_RX_D_1_23 => open, + + FFC_RRST_1 => rx_serdes_rst_ch1_c, + FFC_SIGNAL_DETECT_1 => fpsc_vlo, + FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c, + FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCI_DET_EN_1 => fpsc_vlo, + FFC_FB_LOOPBACK_1 => fpsc_vlo, + FFC_ENABLE_CGALIGN_1 => fpsc_vlo, + FFC_EI_EN_1 => fpsc_vlo, + FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c, + FFC_TXPWDNB_1 => tx_pwrup_ch1_c, + FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c, + FFC_RXPWDNB_1 => rx_pwrup_ch1_c, + FFS_RLOS_LO_1 => rx_los_low_ch1_sig, + FFS_RLOS_HI_1 => open, + FFS_PCIE_CON_1 => open, + FFS_PCIE_DONE_1 => open, + FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s, + FFS_CC_OVERRUN_1 => open, + FFS_CC_UNDERRUN_1 => open, + FFS_SKP_ADDED_1 => open, + FFS_SKP_DELETED_1 => open, + FFS_RLOL_1 => rx_cdr_lol_ch1_sig, + FFS_RXFBFIFO_ERROR_1 => open, + FFS_TXFBFIFO_ERROR_1 => open, + LDR_CORE2TX_1 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, + LDR_RX2CORE_1 => open, + FFS_CDR_TRAIN_DONE_1 => open, + FFC_DIV11_MODE_TX_1 => fpsc_vlo, + FFC_RATE_MODE_TX_1 => fpsc_vlo, + FFC_DIV11_MODE_RX_1 => fpsc_vlo, + FFC_RATE_MODE_RX_1 => fpsc_vlo, + +----- CH2 ----- + HDOUTP2 => hdoutp_ch2, + HDOUTN2 => hdoutn_ch2, + HDINP2 => hdinp_ch2, + HDINN2 => hdinn_ch2, + PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, + PCIE_TXCOMPLIANCE_2 => fpsc_vlo, + PCIE_RXPOLARITY_2 => fpsc_vlo, + PCIE_POWERDOWN_2_0 => fpsc_vlo, + PCIE_POWERDOWN_2_1 => fpsc_vlo, + PCIE_RXVALID_2 => open, + PCIE_PHYSTATUS_2 => open, + SCISELCH2 => fpsc_vlo, + SCIENCH2 => fpsc_vlo, + FF_RXI_CLK_2 => rxiclk_ch2, + FF_TXI_CLK_2 => txiclk_ch2, + FF_EBRD_CLK_2 => fpsc_vlo, + FF_RX_F_CLK_2 => rx_full_clk_ch2, + FF_RX_H_CLK_2 => rx_half_clk_ch2, + FF_TX_F_CLK_2 => tx_full_clk_ch2_sig, + FF_TX_H_CLK_2 => tx_half_clk_ch2, + FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2, + FF_TX_D_2_0 => txdata_ch2(0), + FF_TX_D_2_1 => txdata_ch2(1), + FF_TX_D_2_2 => txdata_ch2(2), + FF_TX_D_2_3 => txdata_ch2(3), + FF_TX_D_2_4 => txdata_ch2(4), + FF_TX_D_2_5 => txdata_ch2(5), + FF_TX_D_2_6 => txdata_ch2(6), + FF_TX_D_2_7 => txdata_ch2(7), + FF_TX_D_2_8 => tx_k_ch2, + FF_TX_D_2_9 => fpsc_vlo, + FF_TX_D_2_10 => xmit_ch2, + FF_TX_D_2_11 => tx_disp_correct_ch2, + FF_TX_D_2_12 => fpsc_vlo, + FF_TX_D_2_13 => fpsc_vlo, + FF_TX_D_2_14 => fpsc_vlo, + FF_TX_D_2_15 => fpsc_vlo, + FF_TX_D_2_16 => fpsc_vlo, + FF_TX_D_2_17 => fpsc_vlo, + FF_TX_D_2_18 => fpsc_vlo, + FF_TX_D_2_19 => fpsc_vlo, + FF_TX_D_2_20 => fpsc_vlo, + FF_TX_D_2_21 => fpsc_vlo, + FF_TX_D_2_22 => fpsc_vlo, + FF_TX_D_2_23 => fpsc_vlo, + FF_RX_D_2_0 => rxdata_ch2(0), + FF_RX_D_2_1 => rxdata_ch2(1), + FF_RX_D_2_2 => rxdata_ch2(2), + FF_RX_D_2_3 => rxdata_ch2(3), + FF_RX_D_2_4 => rxdata_ch2(4), + FF_RX_D_2_5 => rxdata_ch2(5), + FF_RX_D_2_6 => rxdata_ch2(6), + FF_RX_D_2_7 => rxdata_ch2(7), + FF_RX_D_2_8 => rx_k_ch2, + FF_RX_D_2_9 => rx_disp_err_ch2, + FF_RX_D_2_10 => rx_cv_err_ch2, + FF_RX_D_2_11 => open, + FF_RX_D_2_12 => open, + FF_RX_D_2_13 => open, + FF_RX_D_2_14 => open, + FF_RX_D_2_15 => open, + FF_RX_D_2_16 => open, + FF_RX_D_2_17 => open, + FF_RX_D_2_18 => open, + FF_RX_D_2_19 => open, + FF_RX_D_2_20 => open, + FF_RX_D_2_21 => open, + FF_RX_D_2_22 => open, + FF_RX_D_2_23 => open, + + FFC_RRST_2 => rx_serdes_rst_ch2_c, + FFC_SIGNAL_DETECT_2 => fpsc_vlo, + FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c, + FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCI_DET_EN_2 => fpsc_vlo, + FFC_FB_LOOPBACK_2 => fpsc_vlo, + FFC_ENABLE_CGALIGN_2 => fpsc_vlo, + FFC_EI_EN_2 => fpsc_vlo, + FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c, + FFC_TXPWDNB_2 => tx_pwrup_ch2_c, + FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c, + FFC_RXPWDNB_2 => rx_pwrup_ch2_c, + FFS_RLOS_LO_2 => rx_los_low_ch2_sig, + FFS_RLOS_HI_2 => open, + FFS_PCIE_CON_2 => open, + FFS_PCIE_DONE_2 => open, + FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s, + FFS_CC_OVERRUN_2 => open, + FFS_CC_UNDERRUN_2 => open, + FFS_SKP_ADDED_2 => open, + FFS_SKP_DELETED_2 => open, + FFS_RLOL_2 => rx_cdr_lol_ch2_sig, + FFS_RXFBFIFO_ERROR_2 => open, + FFS_TXFBFIFO_ERROR_2 => open, + LDR_CORE2TX_2 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, + LDR_RX2CORE_2 => open, + FFS_CDR_TRAIN_DONE_2 => open, + FFC_DIV11_MODE_TX_2 => fpsc_vlo, + FFC_RATE_MODE_TX_2 => fpsc_vlo, + FFC_DIV11_MODE_RX_2 => fpsc_vlo, + FFC_RATE_MODE_RX_2 => fpsc_vlo, + +----- CH3 ----- + HDOUTP3 => hdoutp_ch3, + HDOUTN3 => hdoutn_ch3, + HDINP3 => hdinp_ch3, + HDINN3 => hdinn_ch3, + PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, + PCIE_TXCOMPLIANCE_3 => fpsc_vlo, + PCIE_RXPOLARITY_3 => fpsc_vlo, + PCIE_POWERDOWN_3_0 => fpsc_vlo, + PCIE_POWERDOWN_3_1 => fpsc_vlo, + PCIE_RXVALID_3 => open, + PCIE_PHYSTATUS_3 => open, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, + FF_RXI_CLK_3 => rxiclk_ch3, + FF_TXI_CLK_3 => txiclk_ch3, + FF_EBRD_CLK_3 => fpsc_vlo, + FF_RX_F_CLK_3 => rx_full_clk_ch3, + FF_RX_H_CLK_3 => rx_half_clk_ch3, + FF_TX_F_CLK_3 => tx_full_clk_ch3_sig, + FF_TX_H_CLK_3 => tx_half_clk_ch3, + FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3, + FF_TX_D_3_0 => txdata_ch3(0), + FF_TX_D_3_1 => txdata_ch3(1), + FF_TX_D_3_2 => txdata_ch3(2), + FF_TX_D_3_3 => txdata_ch3(3), + FF_TX_D_3_4 => txdata_ch3(4), + FF_TX_D_3_5 => txdata_ch3(5), + FF_TX_D_3_6 => txdata_ch3(6), + FF_TX_D_3_7 => txdata_ch3(7), + FF_TX_D_3_8 => tx_k_ch3, + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => xmit_ch3, + FF_TX_D_3_11 => tx_disp_correct_ch3, + FF_TX_D_3_12 => fpsc_vlo, + FF_TX_D_3_13 => fpsc_vlo, + FF_TX_D_3_14 => fpsc_vlo, + FF_TX_D_3_15 => fpsc_vlo, + FF_TX_D_3_16 => fpsc_vlo, + FF_TX_D_3_17 => fpsc_vlo, + FF_TX_D_3_18 => fpsc_vlo, + FF_TX_D_3_19 => fpsc_vlo, + FF_TX_D_3_20 => fpsc_vlo, + FF_TX_D_3_21 => fpsc_vlo, + FF_TX_D_3_22 => fpsc_vlo, + FF_TX_D_3_23 => fpsc_vlo, + FF_RX_D_3_0 => rxdata_ch3(0), + FF_RX_D_3_1 => rxdata_ch3(1), + FF_RX_D_3_2 => rxdata_ch3(2), + FF_RX_D_3_3 => rxdata_ch3(3), + FF_RX_D_3_4 => rxdata_ch3(4), + FF_RX_D_3_5 => rxdata_ch3(5), + FF_RX_D_3_6 => rxdata_ch3(6), + FF_RX_D_3_7 => rxdata_ch3(7), + FF_RX_D_3_8 => rx_k_ch3, + FF_RX_D_3_9 => rx_disp_err_ch3, + FF_RX_D_3_10 => rx_cv_err_ch3, + FF_RX_D_3_11 => open, + FF_RX_D_3_12 => open, + FF_RX_D_3_13 => open, + FF_RX_D_3_14 => open, + FF_RX_D_3_15 => open, + FF_RX_D_3_16 => open, + FF_RX_D_3_17 => open, + FF_RX_D_3_18 => open, + FF_RX_D_3_19 => open, + FF_RX_D_3_20 => open, + FF_RX_D_3_21 => open, + FF_RX_D_3_22 => open, + FF_RX_D_3_23 => open, + + FFC_RRST_3 => rx_serdes_rst_ch3_c, + FFC_SIGNAL_DETECT_3 => fpsc_vlo, + FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c, + FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c, + FFC_SB_INV_RX_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCI_DET_EN_3 => fpsc_vlo, + FFC_FB_LOOPBACK_3 => fpsc_vlo, + FFC_ENABLE_CGALIGN_3 => fpsc_vlo, + FFC_EI_EN_3 => fpsc_vlo, + FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c, + FFC_TXPWDNB_3 => tx_pwrup_ch3_c, + FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c, + FFC_RXPWDNB_3 => rx_pwrup_ch3_c, + FFS_RLOS_LO_3 => rx_los_low_ch3_sig, + FFS_RLOS_HI_3 => open, + FFS_PCIE_CON_3 => open, + FFS_PCIE_DONE_3 => open, + FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s, + FFS_CC_OVERRUN_3 => open, + FFS_CC_UNDERRUN_3 => open, + FFS_SKP_ADDED_3 => open, + FFS_SKP_DELETED_3 => open, + FFS_RLOL_3 => rx_cdr_lol_ch3_sig, + FFS_RXFBFIFO_ERROR_3 => open, + FFS_TXFBFIFO_ERROR_3 => open, + LDR_CORE2TX_3 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, + LDR_RX2CORE_3 => open, + FFS_CDR_TRAIN_DONE_3 => open, + FFC_DIV11_MODE_TX_3 => fpsc_vlo, + FFC_RATE_MODE_TX_3 => fpsc_vlo, + FFC_DIV11_MODE_RX_3 => fpsc_vlo, + FFC_RATE_MODE_RX_3 => fpsc_vlo, + +----- Auxilliary ---- + SCIWDATA7 => fpsc_vlo, + SCIWDATA6 => fpsc_vlo, + SCIWDATA5 => fpsc_vlo, + SCIWDATA4 => fpsc_vlo, + SCIWDATA3 => fpsc_vlo, + SCIWDATA2 => fpsc_vlo, + SCIWDATA1 => fpsc_vlo, + SCIWDATA0 => fpsc_vlo, + SCIADDR5 => fpsc_vlo, + SCIADDR4 => fpsc_vlo, + SCIADDR3 => fpsc_vlo, + SCIADDR2 => fpsc_vlo, + SCIADDR1 => fpsc_vlo, + SCIADDR0 => fpsc_vlo, + SCIRDATA7 => open, + SCIRDATA6 => open, + SCIRDATA5 => open, + SCIRDATA4 => open, + SCIRDATA3 => open, + SCIRDATA2 => open, + SCIRDATA1 => open, + SCIRDATA0 => open, + SCIENAUX => fpsc_vlo, + SCISELAUX => fpsc_vlo, + SCIRD => fpsc_vlo, + SCIWSTN => fpsc_vlo, + CYAWSTN => fpsc_vlo, + SCIINT => open, + FFC_CK_CORE_TX => fpga_txrefclk, + FFC_MACRO_RST => serdes_rst_qd_c, + FFC_QUAD_RST => rst_qd_c, + FFC_TRST => tx_serdes_rst_c, + FFS_PLOL => tx_pll_lol_qd_sig, + FFC_SYNC_TOGGLE => tx_sync_qd_c, + REFCK2CORE => refclk2fpga_sig, + CIN0 => fpsc_vlo, + CIN1 => fpsc_vlo, + CIN2 => fpsc_vlo, + CIN3 => fpsc_vlo, + CIN4 => fpsc_vlo, + CIN5 => fpsc_vlo, + CIN6 => fpsc_vlo, + CIN7 => fpsc_vlo, + CIN8 => fpsc_vlo, + CIN9 => fpsc_vlo, + CIN10 => fpsc_vlo, + CIN11 => fpsc_vlo, + COUT0 => open, + COUT1 => open, + COUT2 => open, + COUT3 => open, + COUT4 => open, + COUT5 => open, + COUT6 => open, + COUT7 => open, + COUT8 => open, + COUT9 => open, + COUT10 => open, + COUT11 => open, + COUT12 => open, + COUT13 => open, + COUT14 => open, + COUT15 => open, + COUT16 => open, + COUT17 => open, + COUT18 => open, + COUT19 => open, + REFCLK_FROM_NQ => refclk_from_nq, + REFCLK_TO_NQ => open); + + + + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on +end serdes_gbe_4ch_arch ; diff --git a/gbe_trb/media/sgmii_channel_smi.v b/gbe_trb/media/sgmii_channel_smi.v new file mode 100644 index 0000000..a97ca4f --- /dev/null +++ b/gbe_trb/media/sgmii_channel_smi.v @@ -0,0 +1,237 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module sgmii_channel_smi ( + + // Control Interface + rst_n, + gbe_mode, + sgmii_mode, + signal_detect, + debug_link_timer_short, + rx_compensation_err, + non_an_rate, + + // G/MII Interface + in_clk_gmii, + in_clk_mii, + data_in_mii, + en_in_mii, + err_in_mii, + + out_clk_gmii, + out_clk_mii, + data_out_mii, + dv_out_mii, + err_out_mii, + col_out_mii, + crs_out_mii, + + // 8-bit Interface + data_out_8bi, + kcntl_out_8bi, + disparity_cntl_out_8bi, + + serdes_recovered_clk, + data_in_8bi, + kcntl_in_8bi, + even_in_8bi, + disp_err_in_8bi, + cv_err_in_8bi, + err_decode_mode_8bi, + + // MDIO Port + mdc, + mdio, + port_id + ); + + + +// I/O Declarations +input rst_n ; // System Reset, Active Low +input signal_detect ; +input gbe_mode ; // GBE Mode (0=SGMII 1=GBE) +input sgmii_mode ; // SGMII PCS Mode (0=MAC 1=PHY) +input debug_link_timer_short ; // (0=NORMAL 1=SHORT) +output rx_compensation_err; // Active high pulse indicating RX_CTC_FIFO either underflowed or overflowed +input [1:0] non_an_rate ; // MII Rate Used When Autonegotiation is Disabled (00=10Mbps; 01=100Mbps; 10=1Gbps) + +input in_clk_mii ; // G/MII Transmit clock 2.5Mhz/25Mhz/125Mhz +input [7:0] data_in_mii ; // G/MII Tx data +input en_in_mii ; // G/MII data valid +input err_in_mii ; // G/MII Tx error + +input out_clk_mii ; // G/MII Receice clock 2.5Mhz/25Mhz/125MHz +output [7:0] data_out_mii ; // G/MII Rx data +output dv_out_mii ; // G/MII Rx data valid +output err_out_mii ; // G/MII Rx error +output col_out_mii ; // G/MII collision detect +output crs_out_mii ; // G/MII carrier sense detect + +output [7:0] data_out_8bi ; // 8BI Tx Data +output kcntl_out_8bi ; // 8BI Tx Kcntl +output disparity_cntl_out_8bi ; // 8BI Tx Kcntl + +input serdes_recovered_clk ; +input [7:0] data_in_8bi ; // 8BI Rx Data +input kcntl_in_8bi ; // 8BI Rx Kcntl +input even_in_8bi ; // 8BI Rx Even +input disp_err_in_8bi ; // 8BI Rx Disparity Error +input cv_err_in_8bi ; // 8BI Rx Coding Violation Error +input err_decode_mode_8bi ; // 8BI Error Decode Mode (0=NORMAL, 1=DECODE_MODE) + +input in_clk_gmii ; // GMII Transmit clock 125Mhz +input out_clk_gmii ; // GMII Receive clock 125Mhz + +input mdc; +inout mdio; +input [4:0] port_id; + + +wire mdin; +wire mdout; +wire mdout_en; + +// Internal Signals + +wire mr_an_complete; +wire mr_page_rx; +wire [15:0] mr_lp_adv_ability; + +wire mr_main_reset; +wire mr_an_enable; +wire mr_restart_an; +wire [15:0] mr_adv_ability; + +wire [1:0] operational_rate; + + + + + + + + +// SGMII PCS +sgmii33 sgmii33_U ( + // Clock and Reset + .rst_n (rst_n ), + .signal_detect (signal_detect), + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .debug_link_timer_short (debug_link_timer_short), + .operational_rate (operational_rate), + .rx_compensation_err (rx_compensation_err), + .tx_clk_125 (in_clk_gmii), + .serdes_recovered_clk (serdes_recovered_clk), + .rx_clk_125 (out_clk_gmii), + + // Control + + + // (G)MII TX Port + .tx_clk_mii (in_clk_mii), + .tx_d (data_in_mii), + .tx_en (err_in_mii), + .tx_er (en_in_mii), + + // (G)MII RX Port + .rx_clk_mii (out_clk_mii), + .rx_d (data_out_mii), + .rx_dv (dv_out_mii), + .rx_er (err_out_mii), + .col (col_out_mii), + .crs (crs_out_mii), + + // 8BI TX Port + .tx_data (data_out_8bi), + .tx_kcntl (kcntl_out_8bi), + .tx_disparity_cntl (disparity_cntl_out_8bi), + + // 8BI RX Port + .rx_data (data_in_8bi), + .rx_kcntl (kcntl_in_8bi), + .rx_even (even_in_8bi), + .rx_disp_err (disp_err_in_8bi), + .rx_cv_err (cv_err_in_8bi), + .rx_err_decode_mode (err_decode_mode_8bi), + + // Management Interface I/O + .mr_adv_ability (mr_adv_ability), + .mr_an_enable (mr_an_enable), + .mr_main_reset (mr_main_reset), + .mr_restart_an (mr_restart_an), + + .mr_an_complete (mr_an_complete), + .mr_lp_adv_ability (mr_lp_adv_ability), + .mr_page_rx (mr_page_rx) + ); + + + +// SMI Register Interface for SGMII IP Core +register_interface_smi ri ( + + // Control Signals + .rst_n (rst_n), + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + + // MDIO Port + .mdc (mdc), + .mdin (mdin), + .mdout (mdout), + .mdout_en (mdout_en), + .port_id (port_id), + + // Register Outputs + .mr_an_enable (mr_an_enable), + .mr_restart_an (mr_restart_an), + .mr_main_reset (mr_main_reset), + .mr_adv_ability (mr_adv_ability), + + // Register Inputs + .mr_an_complete (mr_an_complete), + .mr_page_rx (mr_page_rx), + .mr_lp_adv_ability (mr_lp_adv_ability) + ); + + + +// (G)MII Rate Resolution for SGMII IP Core +rate_resolution rate_resolution ( + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .an_enable (mr_an_enable), + .advertised_rate (mr_adv_ability[11:10]), + .link_partner_rate (mr_lp_adv_ability[11:10]), + .non_an_rate (non_an_rate), + + .operational_rate (operational_rate) +); + + + + + +// Bidirectional Assignments +assign mdio = mdout_en ? mdout : 1'bz; // MDIO Output +assign mdin = mdio; // MDIO Input + +endmodule + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd new file mode 100644 index 0000000..3c8d457 --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd @@ -0,0 +1,420 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- creates a reply for an incoming ARP request + +entity trb_net16_gbe_response_constructor_ARP is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end trb_net16_gbe_response_constructor_ARP; + + +architecture trb_net16_gbe_response_constructor_ARP of trb_net16_gbe_response_constructor_ARP is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_response_constructor_ARP : architecture is "GBE_MAIN_group"; + +attribute syn_encoding : string; + +type dissect_states is (IDLE, READ_FRAME, DECIDE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP); +signal dissect_current_state, dissect_next_state : dissect_states; +attribute syn_encoding of dissect_current_state: signal is "onehot"; + +type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP); +signal stats_current_state, stats_next_state : stats_states; +attribute syn_encoding of stats_current_state : signal is "onehot"; + +signal saved_opcode : std_logic_vector(15 downto 0); +signal saved_sender_ip : std_logic_vector(31 downto 0); +signal saved_target_ip : std_logic_vector(31 downto 0); +signal data_ctr : integer range 0 to 30; +signal values : std_logic_vector(223 downto 0); +signal tc_data : std_logic_vector(8 downto 0); + +signal state : std_logic_vector(3 downto 0); +signal rec_frames : std_logic_vector(15 downto 0); +signal sent_frames : std_logic_vector(15 downto 0); +signal stat_data_temp : std_logic_vector(31 downto 0); + +signal tc_wr : std_logic; + +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_keep of state : signal is true; +attribute syn_preserve of state : signal is true; + +begin + +values(15 downto 0) <= x"0100"; -- hardware type +values(31 downto 16) <= x"0008"; -- protocol type +values(39 downto 32) <= x"06"; -- hardware size +values(47 downto 40) <= x"04"; -- protocol size +values(63 downto 48) <= x"0200"; --opcode (reply) +values(111 downto 64) <= MY_MAC_IN; -- sender (my) mac +values(143 downto 112) <= MY_IP_IN; +values(191 downto 144) <= PS_SRC_MAC_ADDRESS_IN; -- target mac +values(223 downto 192) <= saved_sender_ip; -- target ip + +DISSECT_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + dissect_current_state <= IDLE; + elsif rising_edge(CLK) then +-- if (RESET = '1') then +-- dissect_current_state <= IDLE; +-- else + dissect_current_state <= dissect_next_state; +-- end if; + end if; +end process DISSECT_MACHINE_PROC; + +DISSECT_MACHINE : process(dissect_current_state, MY_IP_IN, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, PS_SELECTED_IN, saved_target_ip) +begin + case dissect_current_state is + + when IDLE => + state <= x"1"; + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + dissect_next_state <= READ_FRAME; + else + dissect_next_state <= IDLE; + end if; + + when READ_FRAME => + state <= x"2"; + if (PS_DATA_IN(8) = '1') then + dissect_next_state <= DECIDE; + else + dissect_next_state <= READ_FRAME; + end if; + + when DECIDE => + state <= x"3"; + if (saved_target_ip = MY_IP_IN) then + dissect_next_state <= WAIT_FOR_LOAD; + -- in case the request is not for me, drop it + else + dissect_next_state <= IDLE; + end if; + + when WAIT_FOR_LOAD => + state <= x"4"; + if (PS_SELECTED_IN = '1') then + dissect_next_state <= LOAD_FRAME; + else + dissect_next_state <= WAIT_FOR_LOAD; + end if; + + when LOAD_FRAME => + state <= x"5"; + if (data_ctr = 28) then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= LOAD_FRAME; + end if; + + when CLEANUP => + state <= x"e"; + dissect_next_state <= IDLE; + + end case; +end process DISSECT_MACHINE; + +DATA_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (dissect_current_state = IDLE and PS_WR_EN_IN = '0') then + data_ctr <= 1; + elsif (dissect_current_state = WAIT_FOR_LOAD) then + data_ctr <= 1; + elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + data_ctr <= data_ctr + 1; + elsif (dissect_current_state = READ_FRAME and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- in case of saving data from incoming frame + data_ctr <= data_ctr + 1; + elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then -- in case of constructing response + data_ctr <= data_ctr + 1; + end if; + end if; +end process DATA_CTR_PROC; + +--TC_WR_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1') then +-- tc_wr <= '1'; +-- else +-- tc_wr <= '0'; +-- end if; +-- end if; +--end process TC_WR_PROC; + +SAVE_VALUES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + saved_opcode <= (others => '0'); + saved_sender_ip <= (others => '0'); + saved_target_ip <= (others => '0'); + elsif (dissect_current_state = READ_FRAME) then + case (data_ctr) is + + when 6 => + saved_opcode(7 downto 0) <= PS_DATA_IN(7 downto 0); + when 7 => + saved_opcode(15 downto 8) <= PS_DATA_IN(7 downto 0); + + + when 13 => + saved_sender_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); + when 14 => + saved_sender_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); + when 15 => + saved_sender_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); + when 16 => + saved_sender_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); + + when 23 => + saved_target_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); + when 24 => + saved_target_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); + when 25 => + saved_target_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); + when 26 => + saved_target_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); + + when others => null; + end case; + end if; + end if; +end process SAVE_VALUES_PROC; + +TC_DATA_PROC : process(CLK) +begin + if rising_edge(CLK) then + tc_data(8) <= '0'; + + if (dissect_current_state = LOAD_FRAME) then + for i in 0 to 7 loop + tc_data(i) <= values((data_ctr - 1) * 8 + i); + end loop; + -- mark the last byte + if (data_ctr = 28) then + tc_data(8) <= '1'; + end if; + else + tc_data(7 downto 0) <= (others => '0'); + end if; + + TC_DATA_OUT <= tc_data; + + end if; +end process TC_DATA_PROC; + +--TC_WR_EN_OUT <= tc_wr; + +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then + PS_RESPONSE_READY_OUT <= '1'; + else + PS_RESPONSE_READY_OUT <= '0'; + end if; + + if (dissect_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; + + + +TC_FRAME_SIZE_OUT <= x"001c"; -- fixed frame size + +TC_FRAME_TYPE_OUT <= x"0608"; +TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; +TC_DEST_IP_OUT <= x"00000000"; -- doesnt matter +TC_DEST_UDP_OUT <= x"0000"; -- doesnt matter +TC_SRC_MAC_OUT <= MY_MAC_IN; +TC_SRC_IP_OUT <= x"00000000"; -- doesnt matter +TC_SRC_UDP_OUT <= x"0000"; -- doesnt matter +TC_IP_PROTOCOL_OUT <= x"00"; -- doesnt matter +TC_IDENT_OUT <= (others => '0'); -- doesn't matter + + +-- **** statistice +--REC_FRAMES_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- rec_frames <= (others => '0'); +-- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then +-- rec_frames <= rec_frames + x"1"; +-- end if; +-- end if; +--end process REC_FRAMES_PROC; +-- +--SENT_FRAMES_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- sent_frames <= (others => '0'); +-- elsif (dissect_current_state = CLEANUP) then +-- sent_frames <= sent_frames + x"1"; +-- end if; +-- end if; +--end process SENT_FRAMES_PROC; +-- +--RECEIVED_FRAMES_OUT <= rec_frames; +--SENT_FRAMES_OUT <= sent_frames; +--STATS_MACHINE_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- stats_current_state <= IDLE; +-- else +-- stats_current_state <= stats_next_state; +-- end if; +-- end if; +--end process STATS_MACHINE_PROC; +-- +--STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state) +--begin +-- +-- case (stats_current_state) is +-- +-- when IDLE => +-- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then +-- stats_next_state <= LOAD_SENT; +-- else +-- stats_next_state <= IDLE; +-- end if; +-- +-- when LOAD_SENT => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= LOAD_RECEIVED; +-- else +-- stats_next_state <= LOAD_SENT; +-- end if; +-- +-- when LOAD_RECEIVED => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= CLEANUP; +-- else +-- stats_next_state <= LOAD_RECEIVED; +-- end if; +-- +-- when CLEANUP => +-- stats_next_state <= IDLE; +-- +-- end case; +-- +--end process STATS_MACHINE; +-- +--SELECTOR : process(CLK) +--begin +-- if rising_edge(CLK) then +-- case(stats_current_state) is +-- +-- when LOAD_SENT => +-- stat_data_temp <= x"0601" & sent_frames; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); +-- +-- when LOAD_RECEIVED => +-- stat_data_temp <= x"0602" & rec_frames; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); +-- +-- when others => +-- stat_data_temp <= (others => '0'); +-- STAT_ADDR_OUT <= (others => '0'); +-- +-- end case; +-- end if; +--end process SELECTOR; +-- +--STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); +--STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); +--STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); +--STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); +-- +--STAT_SYNC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then +-- STAT_DATA_RDY_OUT <= '1'; +-- else +-- STAT_DATA_RDY_OUT <= '0'; +-- end if; +-- end if; +--end process STAT_SYNC; +----STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; +-- +---- **** debug +--DEBUG_OUT(3 downto 0) <= state; +--DEBUG_OUT(4) <= '0'; +--DEBUG_OUT(7 downto 5) <= "000"; +--DEBUG_OUT(8) <= '0'; +--DEBUG_OUT(11 downto 9) <= "000"; +--DEBUG_OUT(31 downto 12) <= (others => '0'); +---- **** + +end trb_net16_gbe_response_constructor_ARP; + + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd new file mode 100644 index 0000000..eeadc34 --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd @@ -0,0 +1,837 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- + +entity trb_net16_gbe_response_constructor_DHCP is +generic ( + STAT_ADDRESS_BASE : integer := 0; + DO_SIMULATION : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + + MY_IP_OUT : out std_logic_vector(31 downto 0); + DHCP_START_IN : in std_logic; + DHCP_DONE_OUT : out std_logic; + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end trb_net16_gbe_response_constructor_DHCP; + + +architecture trb_net16_gbe_response_constructor_DHCP of trb_net16_gbe_response_constructor_DHCP is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_response_constructor_DHCP : architecture is "GBE_MAIN_group"; + +attribute syn_encoding : string; + +type main_states is (BOOTING, DELAY, SENDING_DISCOVER, WAITING_FOR_OFFER, SENDING_REQUEST, WAITING_FOR_ACK, ESTABLISHED); +signal main_current_state, main_next_state : main_states; +attribute syn_encoding of main_current_state: signal is "onehot"; + +type receive_states is (IDLE, DISCARD, CLEANUP, SAVE_VALUES); +signal receive_current_state, receive_next_state : receive_states; +attribute syn_encoding of receive_current_state: signal is "onehot"; + +type discover_states is (IDLE, WAIT_FOR_LOAD, BOOTP_HEADERS, CLIENT_IP, YOUR_IP, ZEROS1, MY_MAC, ZEROS2, VENDOR_VALS, VENDOR_VALS2, TERMINATION, CLEANUP); +signal construct_current_state, construct_next_state : discover_states; +attribute syn_encoding of construct_current_state: signal is "onehot"; + + +type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, LOAD_DISCARDED, CLEANUP); +signal stats_current_state, stats_next_state : stats_states; +attribute syn_encoding of stats_current_state : signal is "onehot"; + +signal state : std_logic_vector(3 downto 0); +signal rec_frames : std_logic_vector(15 downto 0); +signal sent_frames : std_logic_vector(15 downto 0); + +signal wait_ctr : std_logic_vector(31 downto 0); -- wait for 5 sec before sending request +signal load_ctr : integer range 0 to 600 := 0; + +signal bootp_hdr : std_logic_vector(95 downto 0); + +signal tc_data : std_logic_vector(8 downto 0); +signal vendor_values : std_logic_vector(175 downto 0); +signal save_ctr : integer range 0 to 600 := 0; +signal saved_transaction_id : std_logic_vector(31 downto 0); +signal saved_proposed_ip : std_logic_vector(31 downto 0); +signal saved_dhcp_type : std_logic_vector(23 downto 0); +signal saved_true_ip : std_logic_vector(31 downto 0); +signal transaction_id : std_logic_vector(31 downto 0); +signal client_ip_reg : std_logic_vector(31 downto 0); +signal your_ip_reg : std_logic_vector(31 downto 0); +signal saved_server_mac : std_logic_vector(47 downto 0); +signal saved_server_ip : std_logic_vector(31 downto 0); +signal state2 : std_logic_vector(3 downto 0); +signal state3 : std_logic_vector(3 downto 0); +signal vendor_values2 : std_logic_vector(47 downto 0); + +signal discarded_ctr : std_logic_vector(15 downto 0); + +signal stat_data_temp : std_logic_vector(31 downto 0); + +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_keep of state, state2 : signal is true; +attribute syn_preserve of state, state2 : signal is true; + +signal wait_value : std_logic_vector(31 downto 0); + +signal my_ip : std_logic_vector(31 downto 0); + +begin + + +-- **** +-- fixing the constant values for DHCP request headers +TC_DEST_MAC_OUT <= x"ffffffffffff" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else saved_server_mac; +TC_DEST_IP_OUT <= x"ffffffff" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else saved_server_ip; +TC_DEST_UDP_OUT <= x"4300"; +TC_SRC_MAC_OUT <= MY_MAC_IN; +TC_SRC_IP_OUT <= x"00000000" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else saved_proposed_ip; +TC_SRC_UDP_OUT <= x"4400"; +TC_IP_PROTOCOL_OUT <= x"11"; -- udp +bootp_hdr(7 downto 0) <= x"01"; -- message type(request) +bootp_hdr(15 downto 8) <= x"01"; -- hardware type (eth) +bootp_hdr(23 downto 16) <= x"06"; -- hardware address length +bootp_hdr(31 downto 24) <= x"00"; -- hops +bootp_hdr(63 downto 32) <= transaction_id; -- transaction id; +bootp_hdr(95 downto 64) <= x"0000_0000"; -- seconds elapsed/flags +transaction_id <= x"cefa" & MY_MAC_IN(47 downto 40) & MY_MAC_IN(23 downto 16); +vendor_values(31 downto 0) <= x"63538263"; -- magic cookie (dhcp message) +vendor_values(55 downto 32) <= x"010135" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else x"030135"; -- dhcp discover, then dhcp request +vendor_values(79 downto 56) <= x"01073d"; -- client identifier +vendor_values(127 downto 80) <= MY_MAC_IN; -- client identifier +vendor_values(143 downto 128) <= x"040c"; -- client name +vendor_values(175 downto 144) <= x"33425254"; -- client name (TRB3) +vendor_values2(15 downto 0) <= x"0436"; -- server identifier +vendor_values2(47 downto 16) <= saved_server_ip; + +--***************** +-- setting of global variable for IP address +--g_MY_IP <= saved_true_ip when main_current_state = ESTABLISHED else (others => '0'); +my_ip <= saved_true_ip when main_current_state = ESTABLISHED else (others => '0'); +MY_IP_OUT <= my_ip; +-- +--***************** + +SAVE_SERVER_ADDR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (main_current_state = BOOTING) then + saved_server_mac <= (others => '0'); + saved_server_ip <= (others => '0'); + elsif (main_current_state = WAITING_FOR_OFFER) and (receive_current_state = SAVE_VALUES and save_ctr = 1) then + saved_server_mac <= PS_SRC_MAC_ADDRESS_IN; + saved_server_ip <= PS_SRC_IP_ADDRESS_IN; + else + saved_server_mac <= saved_server_mac; + saved_server_ip <= saved_server_ip; + end if; + end if; +end process SAVE_SERVER_ADDR_PROC; + + +-- **** MAIN MACHINE PART + +MAIN_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + main_current_state <= BOOTING; + elsif rising_edge(CLK) then + main_current_state <= main_next_state; + end if; +end process MAIN_MACHINE_PROC; + +wait_value <= x"2000_0000" when DO_SIMULATION = 0 else x"0000_0010"; + +MAIN_MACHINE : process(main_current_state, DHCP_START_IN, construct_current_state, wait_ctr, receive_current_state, PS_DATA_IN, wait_value) +begin + + case (main_current_state) is + + when BOOTING => + state2 <= x"1"; + if (DHCP_START_IN = '1') then + main_next_state <= DELAY; + else + main_next_state <= BOOTING; + end if; + + when DELAY => + if (wait_ctr = wait_value) then + main_next_state <= SENDING_DISCOVER; + else + main_next_state <= DELAY; + end if; + + when SENDING_DISCOVER => + state2 <= x"2"; + if (construct_current_state = CLEANUP) then + main_next_state <= WAITING_FOR_OFFER; + else + main_next_state <= SENDING_DISCOVER; + end if; + + when WAITING_FOR_OFFER => + state2 <= x"3"; + if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then + main_next_state <= SENDING_REQUEST; + elsif (wait_ctr = x"2000_0000") then + main_next_state <= BOOTING; + else + main_next_state <= WAITING_FOR_OFFER; + end if; + + when SENDING_REQUEST => + state2 <= x"4"; + if (construct_current_state = CLEANUP) then + main_next_state <= WAITING_FOR_ACK; + else + main_next_state <= SENDING_REQUEST; + end if; + + when WAITING_FOR_ACK => + state2 <= x"5"; + if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then + main_next_state <= ESTABLISHED; + elsif (wait_ctr = x"2000_0000") then + main_next_state <= BOOTING; + else + main_next_state <= WAITING_FOR_ACK; + end if; + + when ESTABLISHED => + state2 <= x"6"; +-- if (wait_ctr = x"2000_0000") then +-- main_next_state <= SENDING_DISCOVER; +-- else + main_next_state <= ESTABLISHED; +-- end if; + + end case; + +end process MAIN_MACHINE; + +WAIT_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (main_current_state = SENDING_DISCOVER or main_current_state = SENDING_REQUEST or main_current_state = BOOTING) then + wait_ctr <= (others => '0'); + elsif (main_current_state = WAITING_FOR_ACK and receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') then + wait_ctr <= (others => '0'); + elsif (main_current_state = WAITING_FOR_ACK or main_current_state = WAITING_FOR_OFFER or main_current_state = DELAY or main_current_state = ESTABLISHED) then + wait_ctr <= wait_ctr + x"1"; + else + wait_ctr <= wait_ctr; + end if; + end if; +end process WAIT_CTR_PROC; + +DHCP_DONE_OUT <= '1' when main_current_state = ESTABLISHED else '0'; + + +-- **** MESSAGES RECEIVING PART + +RECEIVE_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + receive_current_state <= IDLE; + elsif rising_edge(CLK) then + receive_current_state <= receive_next_state; + end if; +end process RECEIVE_MACHINE_PROC; + +RECEIVE_MACHINE : process(receive_current_state, main_current_state, bootp_hdr, saved_dhcp_type, saved_transaction_id, PS_DATA_IN, PS_DEST_MAC_ADDRESS_IN, MY_MAC_IN, PS_ACTIVATE_IN, PS_WR_EN_IN, save_ctr) +begin + case receive_current_state is + + when IDLE => + state3 <= x"1"; + if (PS_ACTIVATE_IN = '1' and PS_WR_EN_IN = '1') then + if (main_current_state = WAITING_FOR_OFFER or main_current_state = WAITING_FOR_ACK) then -- ready to receive dhcp frame + if (PS_DEST_MAC_ADDRESS_IN = MY_MAC_IN) then -- check if i'm the addressee (discards broadcasts also) + receive_next_state <= SAVE_VALUES; + else + receive_next_state <= DISCARD; -- discard if the frame is not for me + end if; + else + receive_next_state <= DISCARD; -- discard if the frame arrived at wrong time + end if; + else + receive_next_state <= IDLE; + end if; + + when SAVE_VALUES => + state3 <= x"2"; + if (PS_DATA_IN(8) = '1') then + receive_next_state <= CLEANUP; + -- check if the same transaction + elsif (save_ctr = 9) and (saved_transaction_id /= bootp_hdr(63 downto 32)) then + receive_next_state <= DISCARD; + -- if the wrong message at the wrong time + elsif (main_current_state = WAITING_FOR_OFFER) and (save_ctr = 242) and (saved_dhcp_type /= x"020135") then + receive_next_state <= DISCARD; + -- if the wrong message at the wrong time + elsif (main_current_state = WAITING_FOR_ACK) and (save_ctr = 242) and (saved_dhcp_type /= x"050135") then + receive_next_state <= DISCARD; + else + receive_next_state <= SAVE_VALUES; + end if; + + when DISCARD => + state3 <= x"3"; + if (PS_DATA_IN(8) = '1') then + receive_next_state <= CLEANUP; + else + receive_next_state <= DISCARD; + end if; + + when CLEANUP => + state3 <= x"4"; + receive_next_state <= IDLE; + + end case; + +end process RECEIVE_MACHINE; + +SAVE_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (receive_current_state = IDLE) then + save_ctr <= 0; + elsif (receive_current_state = SAVE_VALUES and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + save_ctr <= save_ctr + 1; + else + save_ctr <= save_ctr; + end if; + end if; +end process SAVE_CTR_PROC; + +SAVE_VALUES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (main_current_state = BOOTING) then + saved_transaction_id <= (others => '0'); + saved_proposed_ip <= (others => '0'); + saved_true_ip <= (others => '0'); + saved_dhcp_type <= (others => '0'); + -- dissection of DHCP Offer message + elsif (main_current_state = WAITING_FOR_OFFER and receive_current_state = SAVE_VALUES) then + + saved_true_ip <= saved_true_ip; + + case save_ctr is + + when 3 => + saved_transaction_id(7 downto 0) <= PS_DATA_IN(7 downto 0); + + when 4 => + saved_transaction_id(15 downto 8) <= PS_DATA_IN(7 downto 0); + + when 5 => + saved_transaction_id(23 downto 16) <= PS_DATA_IN(7 downto 0); + + when 6 => + saved_transaction_id(31 downto 24) <= PS_DATA_IN(7 downto 0); + + + when 15 => + saved_proposed_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); + + when 16 => + saved_proposed_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); + + when 17 => + saved_proposed_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); + + when 18 => + saved_proposed_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); + + + when 239 => + saved_dhcp_type(7 downto 0) <= PS_DATA_IN(7 downto 0); + + when 240 => + saved_dhcp_type(15 downto 8) <= PS_DATA_IN(7 downto 0); + + when 241 => + saved_dhcp_type(23 downto 16) <= PS_DATA_IN(7 downto 0); + + when others => null; + + end case; + -- dissection on DHCP Ack message + elsif (main_current_state = WAITING_FOR_ACK and receive_current_state = SAVE_VALUES) then + + saved_proposed_ip <= saved_proposed_ip; + + case save_ctr is + + when 3 => + saved_transaction_id(7 downto 0) <= PS_DATA_IN(7 downto 0); + + when 4 => + saved_transaction_id(15 downto 8) <= PS_DATA_IN(7 downto 0); + + when 5 => + saved_transaction_id(23 downto 16) <= PS_DATA_IN(7 downto 0); + + when 6 => + saved_transaction_id(31 downto 24) <= PS_DATA_IN(7 downto 0); + + + when 15 => + saved_true_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); + + when 16 => + saved_true_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); + + when 17 => + saved_true_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); + + when 18 => + saved_true_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); + + + when 239 => + saved_dhcp_type(7 downto 0) <= PS_DATA_IN(7 downto 0); + + when 240 => + saved_dhcp_type(15 downto 8) <= PS_DATA_IN(7 downto 0); + + when 241 => + saved_dhcp_type(23 downto 16) <= PS_DATA_IN(7 downto 0); + + when others => null; + + end case; + else + saved_transaction_id <= saved_transaction_id; + saved_proposed_ip <= saved_proposed_ip; + saved_true_ip <= saved_true_ip; + saved_dhcp_type <= saved_dhcp_type; + end if; + end if; +end process SAVE_VALUES_PROC; + + +-- **** MESSAGES CONSTRUCTING PART + +CONSTRUCT_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + construct_current_state <= IDLE; + elsif rising_edge(CLK) then + if (main_current_state = BOOTING) then + construct_current_state <= IDLE; + else + construct_current_state <= construct_next_state; + end if; + end if; +end process CONSTRUCT_MACHINE_PROC; + +CONSTRUCT_MACHINE : process(construct_current_state, main_current_state, load_ctr, PS_SELECTED_IN) +begin + case construct_current_state is + + when IDLE => + state <= x"1"; + if (main_current_state = SENDING_DISCOVER) or (main_current_state = SENDING_REQUEST) then + construct_next_state <= WAIT_FOR_LOAD; + else + construct_next_state <= IDLE; + end if; + + when WAIT_FOR_LOAD => + state <= x"2"; + if (PS_SELECTED_IN = '1') then + construct_next_state <= BOOTP_HEADERS; + else + construct_next_state <= WAIT_FOR_LOAD; + end if; + + + when BOOTP_HEADERS => + state <= x"3"; + if (load_ctr = 11) then + construct_next_state <= CLIENT_IP; + else + construct_next_state <= BOOTP_HEADERS; + end if; + + when CLIENT_IP => + state <= x"5"; + if (load_ctr = 15) then + construct_next_state <= YOUR_IP; + else + construct_next_state <= CLIENT_IP; + end if; + + when YOUR_IP => + state <= x"b"; + if (load_ctr = 19) then + construct_next_state <= ZEROS1; + else + construct_next_state <= YOUR_IP; + end if; + + when ZEROS1 => + state <= x"c"; + if (load_ctr = 27) then + construct_next_state <= MY_MAC; + else + construct_next_state <= ZEROS1; + end if; + + when MY_MAC => + state <= x"6"; + if (load_ctr = 33) then + construct_next_state <= ZEROS2; + else + construct_next_state <= MY_MAC; + end if; + + when ZEROS2 => + state <= x"7"; + if (load_ctr = 235) then + construct_next_state <= VENDOR_VALS; + else + construct_next_state <= ZEROS2; + end if; + + when VENDOR_VALS => + state <= x"8"; + if (load_ctr = 257) then + -- for discover it's enough of values + if (main_current_state = SENDING_DISCOVER) then + construct_next_state <= TERMINATION; + -- for request there is some more values needed + else + construct_next_state <= VENDOR_VALS2; + end if; + else + construct_next_state <= VENDOR_VALS; + end if; + + when VENDOR_VALS2 => + state <= x"d"; + if (load_ctr = 263) then + construct_next_state <= TERMINATION; + else + construct_next_state <= VENDOR_VALS2; + end if; + + when TERMINATION => + state <= x"e"; + construct_next_state <= CLEANUP; + + when CLEANUP => + state <= x"9"; + construct_next_state <= IDLE; + + end case; +end process CONSTRUCT_MACHINE; + +LOAD_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (construct_current_state = IDLE) then + load_ctr <= 0; + elsif (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') then + load_ctr <= load_ctr + 1; + else + load_ctr <= load_ctr; + end if; + end if; +end process LOAD_CTR_PROC; + +TC_DATA_PROC : process(CLK) +begin + if rising_edge(CLK) then + case (construct_current_state) is + + when BOOTP_HEADERS => + for i in 0 to 7 loop + tc_data(i) <= bootp_hdr(load_ctr * 8 + i); + end loop; + tc_data(8) <= '0'; + + when CLIENT_IP => + if (main_current_state = SENDING_DISCOVER) then + tc_data(7 downto 0) <= x"00"; + elsif (main_current_state = SENDING_REQUEST) then + for i in 0 to 7 loop + tc_data(i) <= saved_proposed_ip((load_ctr - 12) * 8 + i); + end loop; + end if; + tc_data(8) <= '0'; + + when YOUR_IP => + tc_data(7 downto 0) <= x"00"; + tc_data(8) <= '0'; + + when ZEROS1 => + tc_data(7 downto 0) <= x"00"; + tc_data(8) <= '0'; + + when MY_MAC => + for i in 0 to 7 loop + tc_data(i) <= MY_MAC_IN((load_ctr - 28) * 8 + i); + end loop; + tc_data(8) <= '0'; + + when ZEROS2 => + tc_data(7 downto 0) <= x"00"; + tc_data(8) <= '0'; + + when VENDOR_VALS => + for i in 0 to 7 loop + tc_data(i) <= vendor_values((load_ctr - 236) * 8 + i); + end loop; + tc_data(8) <= '0'; + + -- needed only for DHCP Request message + when VENDOR_VALS2 => + for i in 0 to 7 loop + tc_data(i) <= vendor_values2((load_ctr - 258) * 8 + i); + end loop; + tc_data(8) <= '0'; + + when TERMINATION => + tc_data(7 downto 0) <= x"ff"; + tc_data(8) <= '1'; + + when others => + tc_data(7 downto 0) <= x"00"; + tc_data(8) <= '0'; + + end case; + + TC_DATA_OUT <= tc_data; + + end if; +end process; + +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (construct_current_state = IDLE or construct_current_state = CLEANUP) then + PS_RESPONSE_READY_OUT <= '0'; + else + PS_RESPONSE_READY_OUT <= '1'; + end if; + + if (construct_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; + +-- fixed sizes for discover and request messages +TC_FRAME_SIZE_OUT <= x"0103" when (main_current_state = SENDING_DISCOVER) else x"0109"; + +TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip + +TC_IDENT_OUT <= x"1" & sent_frames(11 downto 0); + + +-- **** statistics +--REC_FRAMES_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- rec_frames <= (others => '0'); +-- elsif (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') then +-- rec_frames <= rec_frames + x"1"; +-- end if; +-- end if; +--end process REC_FRAMES_PROC; +-- +-- needed for identification +SENT_FRAMES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + sent_frames <= (others => '0'); + elsif (construct_current_state = CLEANUP) then + sent_frames <= sent_frames + x"1"; + end if; + end if; +end process SENT_FRAMES_PROC; +-- +--RECEIVED_FRAMES_OUT <= rec_frames; +--SENT_FRAMES_OUT <= sent_frames; +-- +--STATS_MACHINE_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- stats_current_state <= IDLE; +-- else +-- stats_current_state <= stats_next_state; +-- end if; +-- end if; +--end process STATS_MACHINE_PROC; +-- +--STATS_MACHINE : process(stats_current_state, STAT_DATA_ACK_IN, PS_DATA_IN, construct_current_state, receive_current_state) +--begin +-- +-- case (stats_current_state) is +-- +-- when IDLE => +-- if (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') or (construct_current_state = CLEANUP) or (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then +-- stats_next_state <= LOAD_SENT; +-- else +-- stats_next_state <= IDLE; +-- end if; +-- +-- when LOAD_SENT => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= LOAD_RECEIVED; +-- else +-- stats_next_state <= LOAD_SENT; +-- end if; +-- +-- when LOAD_RECEIVED => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= LOAD_DISCARDED; +-- else +-- stats_next_state <= LOAD_RECEIVED; +-- end if; +-- +-- when LOAD_DISCARDED => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= CLEANUP; +-- else +-- stats_next_state <= LOAD_DISCARDED; +-- end if; +-- +-- when CLEANUP => +-- stats_next_state <= IDLE; +-- +-- end case; +-- +--end process STATS_MACHINE; +-- +--SELECTOR : process(CLK) +--begin +-- if rising_edge(CLK) then +-- case(stats_current_state) is +-- +-- when LOAD_SENT => +-- stat_data_temp <= x"0101" & sent_frames; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); +-- +-- when LOAD_RECEIVED => +-- stat_data_temp <= x"0102" & rec_frames; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); +-- +-- when LOAD_DISCARDED => +-- stat_data_temp <= x"0103" & discarded_ctr; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 2, 8)); +-- +-- when others => +-- stat_data_temp <= (others => '0'); +-- STAT_ADDR_OUT <= (others => '0'); +-- +-- end case; +-- end if; +-- +--end process SELECTOR; +-- +--STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); +--STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); +--STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); +--STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); +-- +--STAT_SYNC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then +-- STAT_DATA_RDY_OUT <= '1'; +-- else +-- STAT_DATA_RDY_OUT <= '0'; +-- end if; +-- end if; +--end process STAT_SYNC; +-- **** + + +-- **** debug +--DEBUG_OUT(3 downto 0) <= state; +--DEBUG_OUT(7 downto 4) <= state2; +--DEBUG_OUT(11 downto 8) <= state3; +--DEBUG_OUT(15 downto 12) <= (others => '0'); +--DEBUG_OUT(31 downto 16) <= discarded_ctr; +-- +--DISCARDED_CTR_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- discarded_ctr <= (others => '0'); +-- elsif (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then +-- discarded_ctr <= discarded_ctr + x"1"; +-- end if; +-- end if; +--end process DISCARDED_CTR_PROC; +-- **** + +end trb_net16_gbe_response_constructor_DHCP; + + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd new file mode 100644 index 0000000..813efee --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd @@ -0,0 +1,235 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; + +--******** +-- Response Constructor which forwards received frame back ceating a loopback +-- + +entity trb_net16_gbe_response_constructor_Forward is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + TC_BUSY_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_response_constructor_Forward; + + +architecture trb_net16_gbe_response_constructor_Forward of trb_net16_gbe_response_constructor_Forward is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_response_constructor_Forward : architecture is "GBE_MAIN_group"; + +attribute syn_encoding : string; + +type dissect_states is (IDLE, SAVE, WAIT_FOR_LOAD, LOAD, CLEANUP); +signal dissect_current_state, dissect_next_state : dissect_states; +attribute syn_encoding of dissect_current_state: signal is "safe,gray"; + +signal ff_wr_en : std_logic; +signal ff_rd_en : std_logic; +signal resp_bytes_ctr : std_logic_vector(15 downto 0); +signal ff_empty : std_logic; +signal ff_full : std_logic; +signal ff_q : std_logic_vector(8 downto 0); +signal ff_rd_lock : std_logic; + +signal state : std_logic_vector(3 downto 0); +signal rec_frames : std_logic_vector(15 downto 0); +signal sent_frames : std_logic_vector(15 downto 0); + +begin + +DISSECT_MACHINE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + dissect_current_state <= IDLE; + else + dissect_current_state <= dissect_next_state; + end if; + end if; +end process DISSECT_MACHINE_PROC; + +DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, ff_q, ff_rd_lock, TC_BUSY_IN) +begin + case dissect_current_state is + + when IDLE => + state <= x"1"; + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + dissect_next_state <= SAVE; + else + dissect_next_state <= IDLE; + end if; + + when SAVE => + state <= x"2"; + if (PS_DATA_IN(8) = '1') then + dissect_next_state <= WAIT_FOR_LOAD; + else + dissect_next_state <= SAVE; + end if; + + when WAIT_FOR_LOAD => + state <= x"3"; + if (TC_BUSY_IN = '0') then + dissect_next_state <= LOAD; + else + dissect_next_state <= WAIT_FOR_LOAD; + end if; + + when LOAD => + state <= x"4"; + if (ff_q(8) = '1') and (ff_rd_lock = '0') then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= LOAD; + end if; + + when CLEANUP => + state <= x"5"; + dissect_next_state <= IDLE; + + end case; +end process DISSECT_MACHINE; + +--PS_BUSY_OUT <= '1' when ff_wr_en = '1' else '0'; +PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; + +ff_wr_en <= '1' when (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') else '0'; + +FF_RD_LOCK_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + ff_rd_lock <= '1'; + elsif (dissect_current_state = LOAD and ff_rd_en = '1') then + ff_rd_lock <= '0'; + else + ff_rd_lock <= '1'; + end if; + end if; +end process FF_RD_LOCK_PROC; + +FRAME_FIFO: fifo_4096x9 +port map( + Data => PS_DATA_IN, + WrClock => CLK, + RdClock => CLK, + WrEn => ff_wr_en, + RdEn => ff_rd_en, + Reset => RESET, + RPReset => RESET, + Q => ff_q, + Empty => ff_empty, + Full => ff_full +); + +ff_rd_en <= '1' when (TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') else '0'; + +TC_DATA_OUT <= ff_q; + +PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) else '0'; + +TC_FRAME_SIZE_OUT <= resp_bytes_ctr + x"1"; + +TC_FRAME_TYPE_OUT <= x"0008"; +TC_DEST_MAC_OUT <= x"9a680f201300"; +TC_DEST_IP_OUT <= x"0100a8c0"; +TC_DEST_UDP_OUT <= x"50c3"; +TC_SRC_MAC_OUT <= x"efbeefbe0000"; +TC_SRC_IP_OUT <= x"0b00a8c0"; +TC_SRC_UDP_OUT <= x"50c3"; +TC_IP_PROTOCOL_OUT <= x"11"; + +RESP_BYTES_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (dissect_current_state = IDLE) then + resp_bytes_ctr <= (others => '0'); + elsif (dissect_current_state = SAVE) then + resp_bytes_ctr <= resp_bytes_ctr + x"1"; + end if; + end if; +end process RESP_BYTES_CTR_PROC; + +REC_FRAMES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + rec_frames <= (others => '0'); + elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + rec_frames <= rec_frames + x"1"; + end if; + end if; +end process REC_FRAMES_PROC; + +SENT_FRAMES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + sent_frames <= (others => '0'); + elsif (dissect_current_state = WAIT_FOR_LOAD and TC_BUSY_IN = '0') then + sent_frames <= sent_frames + x"1"; + end if; + end if; +end process SENT_FRAMES_PROC; + +RECEIVED_FRAMES_OUT <= rec_frames; +SENT_FRAMES_OUT <= sent_frames; + +-- **** debug +DEBUG_OUT(3 downto 0) <= state; +DEBUG_OUT(4) <= ff_empty; +DEBUG_OUT(7 downto 5) <= "000"; +DEBUG_OUT(8) <= ff_full; +DEBUG_OUT(11 downto 9) <= "000"; +DEBUG_OUT(31 downto 12) <= (others => '0'); +-- **** + +end trb_net16_gbe_response_constructor_Forward; + + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd new file mode 100644 index 0000000..0544e08 --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd @@ -0,0 +1,426 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- Response Constructor which responds to Ping messages +-- + +entity trb_net16_gbe_response_constructor_Ping is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end trb_net16_gbe_response_constructor_Ping; + + +architecture trb_net16_gbe_response_constructor_Ping of trb_net16_gbe_response_constructor_Ping is + +attribute syn_encoding : string; + +type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP); +signal dissect_current_state, dissect_next_state : dissect_states; +attribute syn_encoding of dissect_current_state: signal is "onehot"; + +type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP); +signal stats_current_state, stats_next_state : stats_states; +attribute syn_encoding of stats_current_state : signal is "onehot"; + +signal sent_frames : std_logic_vector(15 downto 0); + +signal saved_data : std_logic_vector(447 downto 0); +signal saved_headers : std_logic_vector(63 downto 0); + +signal data_ctr : integer range 1 to 1500; +signal data_length : integer range 1 to 1500; +signal tc_data : std_logic_vector(8 downto 0); + +signal checksum : std_logic_vector(15 downto 0); + +signal checksum_l, checksum_r : std_logic_vector(19 downto 0); +signal checksum_ll, checksum_rr : std_logic_vector(15 downto 0); +signal checksum_lll, checksum_rrr : std_logic_vector(15 downto 0); + +begin + +DISSECT_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + dissect_current_state <= IDLE; + elsif rising_edge(CLK) then + dissect_current_state <= dissect_next_state; + end if; +end process DISSECT_MACHINE_PROC; + +DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_SELECTED_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length) +begin + case dissect_current_state is + + when IDLE => + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + dissect_next_state <= READ_FRAME; + else + dissect_next_state <= IDLE; + end if; + + when READ_FRAME => + if (PS_DATA_IN(8) = '1') then + dissect_next_state <= WAIT_FOR_LOAD; + else + dissect_next_state <= READ_FRAME; + end if; + + when WAIT_FOR_LOAD => + if (PS_SELECTED_IN = '1') then + dissect_next_state <= LOAD_FRAME; + else + dissect_next_state <= WAIT_FOR_LOAD; + end if; + + when LOAD_FRAME => + if (data_ctr = data_length + 1) then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= LOAD_FRAME; + end if; + + when CLEANUP => + dissect_next_state <= IDLE; + + end case; +end process DISSECT_MACHINE; + +DATA_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (dissect_current_state = IDLE) or (dissect_current_state = WAIT_FOR_LOAD) then + data_ctr <= 2; + elsif (dissect_current_state = READ_FRAME and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- in case of saving data from incoming frame + data_ctr <= data_ctr + 1; + elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then -- in case of constructing response + data_ctr <= data_ctr + 1; + end if; + end if; +end process DATA_CTR_PROC; + +DATA_LENGTH_PROC: process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + data_length <= 1; + elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then + data_length <= data_ctr; + end if; + end if; +end process DATA_LENGTH_PROC; + +SAVE_VALUES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (dissect_current_state = IDLE) then + saved_headers <= (others => '0'); + saved_data <= (others => '0'); + elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + saved_headers(7 downto 0) <= PS_DATA_IN(7 downto 0); + elsif (dissect_current_state = READ_FRAME) then + if (data_ctr < 9) then -- headers + saved_headers(data_ctr * 8 - 1 downto (data_ctr - 1) * 8) <= PS_DATA_IN(7 downto 0); + elsif (data_ctr > 8) then -- data + saved_data((data_ctr - 8) * 8 - 1 downto (data_ctr - 8 - 1) * 8) <= PS_DATA_IN(7 downto 0); + end if; + elsif (dissect_current_state = LOAD_FRAME) then + saved_headers(7 downto 0) <= x"00"; + saved_headers(23 downto 16) <= checksum(7 downto 0); + saved_headers(31 downto 24) <= checksum(15 downto 8); + end if; + end if; +end process SAVE_VALUES_PROC; + +CS_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (dissect_current_state = IDLE) then + checksum_l(19 downto 0) <= (others => '0'); + checksum_r(19 downto 0) <= (others => '0'); + checksum_ll(15 downto 0) <= (others => '0'); + checksum_rr(15 downto 0) <= (others => '0'); + checksum_lll(15 downto 0) <= (others => '0'); + checksum_rrr(15 downto 0) <= (others => '0'); + elsif (dissect_current_state = READ_FRAME and data_ctr > 4) then + if (std_logic_vector(to_unsigned(data_ctr, 1)) = "0") then + checksum_l <= checksum_l + PS_DATA_IN(7 downto 0); + else + checksum_r <= checksum_r + PS_DATA_IN(7 downto 0); + end if; + checksum_ll <= checksum_ll; + checksum_lll <= checksum_lll; + checksum_rr <= checksum_rr; + checksum_rrr <= checksum_rrr; + elsif (dissect_current_state = WAIT_FOR_LOAD) then + checksum_ll <= x"0000" + checksum_l(7 downto 0) + checksum_r(19 downto 8); + checksum_rr <= x"0000" + checksum_r(7 downto 0) + checksum_l(19 downto 8); + checksum_l <= checksum_l; + checksum_lll <= checksum_lll; + checksum_r <= checksum_r; + checksum_rrr <= checksum_rrr; + elsif (dissect_current_state = LOAD_FRAME and data_ctr = 2) then + checksum_lll <= x"0000" + checksum_ll(7 downto 0) + checksum_rr(15 downto 8); + checksum_rrr <= x"0000" + checksum_rr(7 downto 0) + checksum_ll(15 downto 8); + checksum_l <= checksum_l; + checksum_ll <= checksum_ll; + checksum_r <= checksum_r; + checksum_rr <= checksum_rr; + else + checksum_l <= checksum_l; + checksum_ll <= checksum_ll; + checksum_lll <= checksum_lll; + checksum_r <= checksum_r; + checksum_rr <= checksum_rr; + checksum_rrr <= checksum_rrr; + end if; + end if; +end process CS_PROC; +checksum(7 downto 0) <= not (checksum_rrr(7 downto 0) + checksum_lll(15 downto 8)); +checksum(15 downto 8) <= not (checksum_lll(7 downto 0) + checksum_rrr(15 downto 8)); + +TC_DATA_PROC : process(CLK) +begin + if rising_edge(CLK) then + tc_data(8) <= '0'; + + if (dissect_current_state = LOAD_FRAME) then + if (data_ctr < 10) then -- headers + for i in 0 to 7 loop + tc_data(i) <= saved_headers((data_ctr - 2) * 8 + i); + end loop; + else -- data + for i in 0 to 7 loop + tc_data(i) <= saved_data((data_ctr - 8 - 2) * 8 + i); + end loop; + + -- mark the last byte + if (data_ctr = data_length + 1) then + tc_data(8) <= '1'; + end if; + end if; + else + tc_data(7 downto 0) <= (others => '0'); + end if; + + TC_DATA_OUT <= tc_data; + + end if; +end process TC_DATA_PROC; + +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then + PS_RESPONSE_READY_OUT <= '1'; + else + PS_RESPONSE_READY_OUT <= '0'; + end if; + + if (dissect_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; + +TC_FRAME_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16)); +TC_FRAME_TYPE_OUT <= x"0008"; +TC_DEST_UDP_OUT <= x"0000"; -- not used +TC_SRC_MAC_OUT <= MY_MAC_IN; +TC_SRC_IP_OUT <= MY_IP_IN; +TC_SRC_UDP_OUT <= x"0000"; -- not used +TC_IP_PROTOCOL_OUT <= X"01"; -- ICMP +TC_IDENT_OUT <= x"2" & sent_frames(11 downto 0); + +ADDR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = READ_FRAME) then + TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; + TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; + end if; + end if; +end process ADDR_PROC; + +-- statistics +-- +--REC_FRAMES_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- rec_frames <= (others => '0'); +-- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then +-- rec_frames <= rec_frames + x"1"; +-- end if; +-- end if; +--end process REC_FRAMES_PROC; +-- +-- needed for identification +SENT_FRAMES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + sent_frames <= (others => '0'); + elsif (dissect_current_state = CLEANUP) then + sent_frames <= sent_frames + x"1"; + end if; + end if; +end process SENT_FRAMES_PROC; +-- +--RECEIVED_FRAMES_OUT <= rec_frames; +--SENT_FRAMES_OUT <= sent_frames; +--RECEIVED_FRAMES_OUT <= rec_frames; +--SENT_FRAMES_OUT <= sent_frames; +-- +--STATS_MACHINE_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- stats_current_state <= IDLE; +-- else +-- stats_current_state <= stats_next_state; +-- end if; +-- end if; +--end process STATS_MACHINE_PROC; +-- +--STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, STAT_DATA_ACK_IN, PS_DATA_IN, dissect_current_state) +--begin +-- +-- case (stats_current_state) is +-- +-- when IDLE => +-- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then +-- stats_next_state <= LOAD_SENT; +-- else +-- stats_next_state <= IDLE; +-- end if; +-- +-- when LOAD_SENT => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= LOAD_RECEIVED; +-- else +-- stats_next_state <= LOAD_SENT; +-- end if; +-- +-- when LOAD_RECEIVED => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= CLEANUP; +-- else +-- stats_next_state <= LOAD_RECEIVED; +-- end if; +-- +-- when CLEANUP => +-- stats_next_state <= IDLE; +-- +-- end case; +-- +--end process STATS_MACHINE; +-- +--SELECTOR : process(CLK) +--begin +-- if rising_edge(CLK) then +-- case(stats_current_state) is +-- +-- when LOAD_SENT => +-- stat_data_temp <= x"0401" & sent_frames; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); +-- +-- when LOAD_RECEIVED => +-- stat_data_temp <= x"0402" & rec_frames; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); +-- +-- when others => +-- stat_data_temp <= (others => '0'); +-- STAT_ADDR_OUT <= (others => '0'); +-- +-- end case; +-- end if; +--end process SELECTOR; +-- +--STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); +--STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); +--STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); +--STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); +-- +--STAT_SYNC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then +-- STAT_DATA_RDY_OUT <= '1'; +-- else +-- STAT_DATA_RDY_OUT <= '0'; +-- end if; +-- end if; +--end process STAT_SYNC; +--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; + +-- **** debug +--DEBUG_OUT(3 downto 0) <= state; +--DEBUG_OUT(4) <= '0'; +--DEBUG_OUT(7 downto 5) <= "000"; +--DEBUG_OUT(8) <= '0'; +--DEBUG_OUT(11 downto 9) <= "000"; +--DEBUG_OUT(31 downto 12) <= (others => '0'); +-- **** + +end trb_net16_gbe_response_constructor_Ping; + + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_PseudoPing.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_PseudoPing.vhd new file mode 100644 index 0000000..748a651 --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_PseudoPing.vhd @@ -0,0 +1,389 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- Response Constructor which responds to Ping messages +-- + +entity trb_net16_gbe_response_constructor_PseudoPing is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_response_constructor_PseudoPing; + + +architecture trb_net16_gbe_response_constructor_PseudoPing of trb_net16_gbe_response_constructor_PseudoPing is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_response_constructor_Ping : architecture is "GBE_MAIN_group"; + +attribute syn_encoding : string; + +type dissect_states is (IDLE, READ_FRAME, GENERATE_DATA, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP); +signal dissect_current_state, dissect_next_state : dissect_states; +attribute syn_encoding of dissect_current_state: signal is "safe,gray"; + +type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP); +signal stats_current_state, stats_next_state : stats_states; +attribute syn_encoding of stats_current_state : signal is "safe,gray"; + +signal rec_frames : std_logic_vector(15 downto 0); +signal sent_frames : std_logic_vector(15 downto 0); + +signal saved_data : std_logic_vector(447 downto 0); +signal saved_headers : std_logic_vector(63 downto 0); + +signal data_ctr : integer range 1 to 1500; +signal data_length : integer range 1 to 1500; +signal tc_data : std_logic_vector(8 downto 0); + +signal checksum : std_logic_vector(15 downto 0); + +signal checksum_l, checksum_r : std_logic_vector(19 downto 0); +signal checksum_ll, checksum_rr : std_logic_vector(15 downto 0); +signal checksum_lll, checksum_rrr : std_logic_vector(15 downto 0); + +signal fifo_wr_en, fifo_rd_en : std_logic; +signal fifo_q : std_logic_vector(7 downto 0); + + +signal stat_data_temp : std_logic_vector(31 downto 0); + +signal tc_wr : std_logic; + +signal data_reg : std_logic_vector(511 downto 0); +signal fifo_data : std_logic_vector(7 downto 0); +signal gen_ctr : std_logic_vector(15 downto 0); +signal size_left : std_logic_vector(15 downto 0); + +begin + +--DISSECT_MACHINE_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- dissect_current_state <= IDLE; +-- else +-- dissect_current_state <= dissect_next_state; +-- end if; +-- end if; +--end process DISSECT_MACHINE_PROC; + +DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length, gen_ctr, size_left, PS_SELECTED_IN) +begin + case dissect_current_state is + + when IDLE => + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + dissect_next_state <= READ_FRAME; + else + dissect_next_state <= IDLE; + end if; + + when READ_FRAME => + if (PS_DATA_IN(8) = '1') then + dissect_next_state <= GENERATE_DATA; + else + dissect_next_state <= READ_FRAME; + end if; + + when GENERATE_DATA => + if (gen_ctr = x"07ff") then + dissect_next_state <= WAIT_FOR_LOAD; + else + dissect_next_state <= GENERATE_DATA; + end if; + + when WAIT_FOR_LOAD => + if (PS_SELECTED_IN = '1') then + dissect_next_state <= LOAD_FRAME; + else + dissect_next_state <= WAIT_FOR_LOAD; + end if; + + when LOAD_FRAME => + if (size_left = x"0000") then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= LOAD_FRAME; + end if; + + when CLEANUP => + dissect_next_state <= IDLE; + + end case; +end process DISSECT_MACHINE; + +fifo : fifo_2048x8 + PORT map( + Reset => RESET, + RPReset => RESET, + WrClock => CLK, + RdClock => CLK, + Data => fifo_data, + WrEn => fifo_wr_en, + RdEn => fifo_rd_en, --TC_RD_EN_IN, + Q => fifo_q, + Full => open, + Empty => open + ); + +fifo_rd_en <= '1' when TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' else '0'; +fifo_wr_en <= '1' when dissect_current_state = GENERATE_DATA else '0'; +fifo_data <= gen_ctr(7 downto 0); + +process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = IDLE or dissect_current_state = CLEANUP) then + gen_ctr <= (others => '0'); + elsif (dissect_current_state = GENERATE_DATA) then + gen_ctr <= gen_ctr + x"1"; + else + gen_ctr <= gen_ctr; + end if; + end if; +end process; + + +TC_DATA_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = LOAD_FRAME and size_left = x"0000") then + tc_data(8) <= '1'; + else + tc_data(8) <= '0'; + end if; + + tc_data(7 downto 0) <= fifo_q; + end if; +end process TC_DATA_PROC; + +TC_DATA_OUT <= tc_data; + +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then + PS_RESPONSE_READY_OUT <= '1'; + else + PS_RESPONSE_READY_OUT <= '0'; + end if; + + if (dissect_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; + +process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = GENERATE_DATA) then + size_left <= x"0500"; + elsif (dissect_current_state = LOAD_FRAME) then + size_left <= size_left - x"1"; + else + size_left <= size_left; + end if; + end if; +end process; + +TC_FRAME_SIZE_OUT <= x"0500"; + +TC_FRAME_TYPE_OUT <= x"0008"; +TC_DEST_UDP_OUT <= x"c350"; -- not used +TC_SRC_MAC_OUT <= g_MY_MAC; +TC_SRC_IP_OUT <= g_MY_IP; +TC_SRC_UDP_OUT <= x"c350"; -- not used +TC_IP_PROTOCOL_OUT <= X"11"; -- ICMP +TC_IDENT_OUT <= x"2" & sent_frames(11 downto 0); + +ADDR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = READ_FRAME) then + TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; + TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; + end if; + end if; +end process ADDR_PROC; + +-- statistics +-- +--REC_FRAMES_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- rec_frames <= (others => '0'); +-- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then +-- rec_frames <= rec_frames + x"1"; +-- end if; +-- end if; +--end process REC_FRAMES_PROC; +-- +-- needed for identification +SENT_FRAMES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + sent_frames <= (others => '0'); + elsif (dissect_current_state = WAIT_FOR_LOAD and PS_SELECTED_IN = '1') then + sent_frames <= sent_frames + x"1"; + end if; + end if; +end process SENT_FRAMES_PROC; +-- +--RECEIVED_FRAMES_OUT <= rec_frames; +--SENT_FRAMES_OUT <= sent_frames; +--RECEIVED_FRAMES_OUT <= rec_frames; +--SENT_FRAMES_OUT <= sent_frames; +-- +--STATS_MACHINE_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- stats_current_state <= IDLE; +-- else +-- stats_current_state <= stats_next_state; +-- end if; +-- end if; +--end process STATS_MACHINE_PROC; +-- +--STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, STAT_DATA_ACK_IN, PS_DATA_IN, dissect_current_state) +--begin +-- +-- case (stats_current_state) is +-- +-- when IDLE => +-- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then +-- stats_next_state <= LOAD_SENT; +-- else +-- stats_next_state <= IDLE; +-- end if; +-- +-- when LOAD_SENT => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= LOAD_RECEIVED; +-- else +-- stats_next_state <= LOAD_SENT; +-- end if; +-- +-- when LOAD_RECEIVED => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= CLEANUP; +-- else +-- stats_next_state <= LOAD_RECEIVED; +-- end if; +-- +-- when CLEANUP => +-- stats_next_state <= IDLE; +-- +-- end case; +-- +--end process STATS_MACHINE; +-- +--SELECTOR : process(CLK) +--begin +-- if rising_edge(CLK) then +-- case(stats_current_state) is +-- +-- when LOAD_SENT => +-- stat_data_temp <= x"0401" & sent_frames; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); +-- +-- when LOAD_RECEIVED => +-- stat_data_temp <= x"0402" & rec_frames; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); +-- +-- when others => +-- stat_data_temp <= (others => '0'); +-- STAT_ADDR_OUT <= (others => '0'); +-- +-- end case; +-- end if; +--end process SELECTOR; +-- +--STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); +--STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); +--STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); +--STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); +-- +--STAT_SYNC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then +-- STAT_DATA_RDY_OUT <= '1'; +-- else +-- STAT_DATA_RDY_OUT <= '0'; +-- end if; +-- end if; +--end process STAT_SYNC; +--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; + +-- **** debug +--DEBUG_OUT(3 downto 0) <= state; +--DEBUG_OUT(4) <= '0'; +--DEBUG_OUT(7 downto 5) <= "000"; +--DEBUG_OUT(8) <= '0'; +--DEBUG_OUT(11 downto 9) <= "000"; +--DEBUG_OUT(31 downto 12) <= (others => '0'); +-- **** + +end trb_net16_gbe_response_constructor_PseudoPing; + + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd new file mode 100644 index 0000000..5f6f95a --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd @@ -0,0 +1,845 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + + +entity trb_net16_gbe_response_constructor_SCTRL is +generic ( STAT_ADDRESS_BASE : integer := 0; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1 +); + port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + + -- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(63 downto 0); + -- END OF INTERFACE + + -- protocol specific ports + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + MAKE_RESET_OUT : out std_logic; + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + -- end of protocol specific ports + + MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0); + + DATA_HIST_OUT : out hist_array + ); +end entity trb_net16_gbe_response_constructor_SCTRL; + +architecture RTL of trb_net16_gbe_response_constructor_SCTRL is + +attribute syn_encoding : string; + +--type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP); +type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP); +--type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_A_WORD, WAIT_ONE, WAIT_TWO, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP); +--type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP); +signal dissect_current_state, dissect_next_state : dissect_states; +attribute syn_encoding of dissect_current_state: signal is "onehot"; + +type stats_states is (IDLE, LOAD_RECEIVED, LOAD_REPLY, CLEANUP); +signal stats_current_state, stats_next_state : stats_states; +attribute syn_encoding of stats_current_state : signal is "onehot"; + +signal saved_target_ip : std_logic_vector(31 downto 0); +signal data_ctr : integer range 0 to 30; + + +signal stat_data_temp : std_logic_vector(31 downto 0); +signal rec_frames : std_logic_vector(15 downto 0); + +signal rx_fifo_q : std_logic_vector(17 downto 0); +signal rx_fifo_qq : std_logic_vector(17 downto 0); +signal rx_fifo_wr, rx_fifo_rd : std_logic; +signal tx_eod, rx_eod : std_logic; + +signal tx_fifo_q : std_logic_vector(8 downto 0); +signal tx_fifo_wr, tx_fifo_rd : std_logic; +signal tx_fifo_reset : std_logic; +signal gsc_reply_read : std_logic; +signal gsc_init_dataready : std_logic; +signal gsc_init_dataready_q : std_logic; + +signal tx_data_ctr : std_logic_vector(15 downto 0); +signal tx_loaded_ctr : std_logic_vector(15 downto 0); +signal tx_frame_loaded : std_logic_vector(15 downto 0); + +signal packet_num : std_logic_vector(2 downto 0); + +signal init_ctr, reply_ctr : std_logic_vector(15 downto 0); +signal rx_empty, tx_empty : std_logic; + +signal rx_full, tx_full : std_logic; + +signal size_left : std_logic_vector(15 downto 0); + +signal reset_detected : std_logic := '0'; +signal make_reset : std_logic := '0'; + + +signal fifo_rd_q : std_logic; + +signal too_much_data : std_logic; + +signal rx_fifo_data : std_logic_vector(8 downto 0); +signal tx_fifo_data : std_logic_vector(17 downto 0); + +signal tc_wr : std_logic; +signal state : std_logic_vector(3 downto 0); +signal saved_hdr_1 : std_logic_vector(7 downto 0) := x"ab"; +signal saved_hdr_2 : std_logic_vector(7 downto 0) := x"cd"; +signal saved_hdr_ctr : std_logic_vector(3 downto 0); + +signal mon_rec_frames, mon_rec_bytes, mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0); + +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_keep of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true; +attribute syn_preserve of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true; + +signal hist_inst : hist_array; +signal reset_all_hist : std_logic_vector(31 downto 0); + +begin + +MAKE_RESET_OUT <= make_reset; + +receive_fifo : fifo_2048x8x16 + PORT map( + Reset => RESET, + RPReset => RESET, + WrClock => CLK, + RdClock => CLK, + Data => rx_fifo_data, + WrEn => rx_fifo_wr, + RdEn => rx_fifo_rd, + Q => rx_fifo_q, + Full => rx_full, + Empty => rx_empty + ); + +--TODO: change to synchronous +rx_fifo_rd <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or + (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or + (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') + else '0'; -- preload first word + +RX_FIFO_WR_SYNC : process(CLK) +begin + if rising_edge(CLK) then + + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and (saved_hdr_ctr = "0100" or saved_hdr_ctr = "1000")) then + rx_fifo_wr <= '1'; + else + rx_fifo_wr <= '0'; + end if; + + rx_fifo_data <= PS_DATA_IN; + end if; +end process RX_FIFO_WR_SYNC; + +SAVED_HDR_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = IDLE and PS_WR_EN_IN = '0' and PS_ACTIVATE_IN = '0') then + saved_hdr_ctr <= "0001"; + elsif (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr /= "1000") then + saved_hdr_ctr(3 downto 0) <= saved_hdr_ctr(2 downto 0) & '0'; + else + saved_hdr_ctr <= saved_hdr_ctr; + end if; + end if; +end process SAVED_HDR_CTR_PROC; + +SAVED_HDR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + if (saved_hdr_ctr = "0001") then + saved_hdr_1 <= PS_DATA_IN(7 downto 0); + saved_hdr_2 <= saved_hdr_2; + elsif (saved_hdr_ctr = "0010") then + saved_hdr_2 <= PS_DATA_IN(7 downto 0); + saved_hdr_1 <= saved_hdr_1; + else + saved_hdr_1 <= saved_hdr_1; + saved_hdr_2 <= saved_hdr_2; + end if; + else + saved_hdr_1 <= saved_hdr_1; + saved_hdr_2 <= saved_hdr_2; + end if; + end if; +end process SAVED_HDR_PROC; + +--RX_FIFO_RD_SYNC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- +-- if (dissect_current_state = LOAD_A_WORD) then +-- rx_fifo_rd <= '1'; +-- else +-- rx_fifo_rd <= '0'; +-- end if; +-- +---- if (dissect_current_state = WAIT_ONE) then +---- gsc_init_dataready <= '1'; +---- elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '0') then +---- gsc_init_dataready <= '1'; +---- else +---- gsc_init_dataready <= '0'; +---- end if; +-- +---- if (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then -- preload the first byte +---- rx_fifo_rd <= '1'; +---- elsif (dissect_current_state = LOAD_TO_HUB) then +---- rx_fifo_rd <= '1'; +---- elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') then +---- rx_fifo_rd <= '1'; +---- else +---- rx_fifo_rd <= '0'; +---- end if; +---- +---- if (dissect_current_state = WAIT_FOR_HUB) then +---- gsc_init_dataready <= '1'; +---- elsif (dissect_current_state = LOAD_TO_HUB and GSC_INIT_READ_IN = '1') then +---- gsc_init_dataready <= '1'; +---- else +---- gsc_init_dataready <= '0'; +---- end if; +---- +---- if (dissect_current_state = WAIT_FOR_HUB) then +---- packet_num <= "100"; +---- elsif (dissect_current_state = LOAD_TO_HUB) then +---- if (gsc_init_dataready = '1' and packet_num = "100") then +---- packet_num <= "000"; +---- elsif (gsc_init_dataready = '1' and packet_num /= "100") then +---- packet_num <= packet_num + "1"; +---- else +---- packet_num <= packet_num; +---- end if; +---- else +---- packet_num <= packet_num; +---- end if; +-- +-- if (dissect_current_state = READ_FRAME) then +-- packet_num <= "011"; +-- elsif (dissect_current_state = LOAD_A_WORD) then +-- if (packet_num = "100") then +-- packet_num <= "000"; +-- else +-- packet_num <= packet_num + "1"; +-- end if; +-- else +-- packet_num <= packet_num; +-- end if; +-- +-- GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9); +-- GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0); +-- +-- --GSC_INIT_DATAREADY_OUT <= gsc_init_dataready; +-- +---- GSC_INIT_PACKET_NUM_OUT <= packet_num; +-- +-- end if; +--end process RX_FIFO_RD_SYNC; +-- +--GSC_INIT_DATAREADY_OUT <= '1' when dissect_current_state = WAIT_FOR_HUB else '0'; + +----TODO: add a register +GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9); +GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0); + +------ TODO: change it to synchronous +GSC_INIT_PACKET_NUM_OUT <= packet_num; +GSC_INIT_DATAREADY_OUT <= gsc_init_dataready; +gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or + (dissect_current_state = WAIT_FOR_HUB) else '0'; + +PACKET_NUM_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = IDLE) then + packet_num <= "100"; + elsif (GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100") then + packet_num <= "000"; + elsif (rx_fifo_rd = '1' and packet_num /= "100") then + packet_num <= packet_num + "1"; + end if; + end if; +end process PACKET_NUM_PROC; + +tf_4k_gen : if SLOWCTRL_BUFFER_SIZE = 1 generate + transmit_fifo : fifo_4kx18x9 + PORT map( + Reset => tx_fifo_reset, + RPReset => tx_fifo_reset, + WrClock => CLK, + RdClock => CLK, + Data => tx_fifo_data, + WrEn => tx_fifo_wr, + RdEn => tx_fifo_rd, + Q => tx_fifo_q, + Full => tx_full, + Empty => tx_empty + ); +end generate tf_4k_gen; + +tf_65k_gen : if SLOWCTRL_BUFFER_SIZE = 2 generate + transmit_fifo : fifo_65536x18x9 + PORT map( + Reset => tx_fifo_reset, + RPReset => tx_fifo_reset, + WrClock => CLK, + RdClock => CLK, + Data => tx_fifo_data, + WrEn => tx_fifo_wr, + RdEn => tx_fifo_rd, + Q => tx_fifo_q, + Full => tx_full, + Empty => tx_empty + ); +end generate tf_65k_gen; + +TX_FIFO_WR_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') then + tx_fifo_wr <= '1'; + elsif (saved_hdr_ctr = "0010") then + tx_fifo_wr <= '1'; + else + tx_fifo_wr <= '0'; + end if; + + if (saved_hdr_ctr = "010") then + tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02"; + else + tx_fifo_data(7 downto 0) <= GSC_REPLY_DATA_IN(15 downto 8); + tx_fifo_data(8) <= '0'; + tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0); + tx_fifo_data(17) <= '0'; + end if; + end if; +end process TX_FIFO_WR_SYNC; + +--TX_FIFO_RD_SYNC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and tx_frame_loaded /= g_MAX_FRAME_SIZE) then +-- tx_fifo_rd <= '1'; +-- else +-- tx_fifo_rd <= '0'; +-- end if; +-- end if; +--end process TX_FIFO_RD_SYNC; +tx_fifo_rd <= '1' when TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' else '0'; + +TX_FIFO_SYNC_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (too_much_data = '1' and dissect_current_state = CLEANUP) then + tx_fifo_reset <= '1'; + else + tx_fifo_reset <= '0'; + end if; + end if; +end process TX_FIFO_SYNC_PROC; + +TC_DATA_PROC : process(CLK) +begin + if rising_edge(CLK) then + + TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0); + + --if (tx_loaded_ctr = tx_data_ctr + x"1" or tx_frame_loaded = g_MAX_FRAME_SIZE - x"1") then + if (tx_loaded_ctr = tx_data_ctr) then + TC_DATA_OUT(8) <= '1'; + else + TC_DATA_OUT(8) <= '0'; + end if; + end if; +end process TC_DATA_PROC; + +GSC_REPLY_READ_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE) then + gsc_reply_read <= '1'; + else + gsc_reply_read <= '0'; + end if; + end if; +end process GSC_REPLY_READ_PROC; +GSC_REPLY_READ_OUT <= gsc_reply_read; + +-- counter of data received from TRBNet hub +TX_DATA_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = IDLE) then + tx_data_ctr <= (others => '0'); + elsif (tx_fifo_wr = '1') then + tx_data_ctr <= tx_data_ctr + x"2"; + end if; + end if; +end process TX_DATA_CTR_PROC; + +TOO_MUCH_DATA_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = IDLE) then + too_much_data <= '0'; + elsif (dissect_current_state = SAVE_RESPONSE) and (tx_data_ctr = CFG_MAX_REPLY_SIZE_IN(15 downto 0)) then + too_much_data <= '1'; + else + too_much_data <= too_much_data; + end if; + end if; +end process TOO_MUCH_DATA_PROC; + +-- total counter of data transported to frame constructor +TX_LOADED_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = IDLE) then + tx_loaded_ctr <= x"0000"; + elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then + tx_loaded_ctr <= tx_loaded_ctr + x"1"; + else + tx_loaded_ctr <= tx_loaded_ctr; + end if; + end if; +end process TX_LOADED_CTR_PROC; + +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (too_much_data = '0') then + if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then + PS_RESPONSE_READY_OUT <= '1'; + else + PS_RESPONSE_READY_OUT <= '0'; + end if; + end if; + + if (dissect_current_state = IDLE or dissect_current_state = WAIT_FOR_RESPONSE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; + +TC_FRAME_TYPE_OUT <= x"0008"; +TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; +TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; +TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8); +TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0); +TC_SRC_MAC_OUT <= MY_MAC_IN; +TC_SRC_IP_OUT <= MY_IP_IN; +TC_SRC_UDP_OUT <= x"9065"; --x"a861"; +TC_IP_PROTOCOL_OUT <= x"11"; +TC_IDENT_OUT <= x"3" & reply_ctr(11 downto 0); + +TC_FRAME_SIZE_OUT <= tx_data_ctr; + +DISSECT_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + dissect_current_state <= IDLE; + elsif rising_edge(CLK) then +-- if (RESET = '1') then +-- if (g_SIMULATE = 0) then +-- dissect_current_state <= IDLE; +-- else +-- dissect_current_state <= WAIT_FOR_RESPONSE; +-- end if; +-- else + dissect_current_state <= dissect_next_state; +-- end if; + end if; +end process DISSECT_MACHINE_PROC; + +DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_data_ctr, rx_fifo_q, GSC_BUSY_IN) +begin + case dissect_current_state is + + when IDLE => + state <= x"0"; + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + dissect_next_state <= READ_FRAME; + else + dissect_next_state <= IDLE; + end if; + + when READ_FRAME => + state <= x"1"; + if (PS_DATA_IN(8) = '1') then + dissect_next_state <= WAIT_FOR_HUB; + else + dissect_next_state <= READ_FRAME; + end if; + + when WAIT_FOR_HUB => + state <= x"2"; + if (GSC_INIT_READ_IN = '1') then + dissect_next_state <= LOAD_TO_HUB; + else + dissect_next_state <= WAIT_FOR_HUB; + end if; + + when LOAD_TO_HUB => + state <= x"3"; + if (rx_fifo_q(17) = '1') then + if (reset_detected = '1') then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= WAIT_FOR_RESPONSE; + end if; + else + dissect_next_state <= LOAD_TO_HUB; + end if; + + when WAIT_FOR_RESPONSE => + state <= x"4"; + if (GSC_REPLY_DATAREADY_IN = '1') then + dissect_next_state <= SAVE_RESPONSE; + else + dissect_next_state <= WAIT_FOR_RESPONSE; + end if; + + when SAVE_RESPONSE => + state <= x"5"; + if (GSC_REPLY_DATAREADY_IN = '0' and GSC_BUSY_IN = '0') then + if (too_much_data = '0') then + dissect_next_state <= WAIT_FOR_LOAD; + else + dissect_next_state <= CLEANUP; + end if; + else + dissect_next_state <= SAVE_RESPONSE; + end if; + + when WAIT_FOR_LOAD => + state <= x"6"; + if (PS_SELECTED_IN = '1') then + dissect_next_state <= LOAD_FRAME; + else + dissect_next_state <= WAIT_FOR_LOAD; + end if; + + when LOAD_FRAME => + state <= x"7"; + if (tx_loaded_ctr = tx_data_ctr) then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= LOAD_FRAME; + end if; + + when CLEANUP => + state <= x"8"; + dissect_next_state <= IDLE; + + end case; +end process DISSECT_MACHINE; + +-- reset request packet detection + RESET_DETECTED_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (dissect_current_state = IDLE) then + reset_detected <= '0'; + elsif (PS_DATA_IN(7 downto 0) = x"80" and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr = "0100") then + reset_detected <= '1'; + else + reset_detected <= reset_detected; + end if; + end if; + end process RESET_DETECTED_PROC; + + MAKE_RESET_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (dissect_current_state = IDLE) then + make_reset <= '0'; + elsif (dissect_current_state = CLEANUP and reset_detected = '1') then + make_reset <= '1'; + else + make_reset <= make_reset; + end if; + end if; + end process MAKE_RESET_PROC; + + +-- monitoring + +hist_ctrs_gen : for i in 0 to 31 generate + + process(CLK) + begin + if rising_edge(CLK) then + if (RESET = '1') then + reset_all_hist(i) <= '1'; + elsif (hist_inst(i) = x"ffff_ffff") then + reset_all_hist(i) <= '1'; + else + reset_all_hist(i) <= '0'; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if (reset_all_hist /= x"0000_0000") then + hist_inst(i) <= (others => '0'); + elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr and i = to_integer(unsigned(tx_data_ctr(15 downto 11)))) then + hist_inst(i) <= hist_inst(i) + x"1"; + else + hist_inst(i) <= hist_inst(i); + end if; + end if; + end process; + +end generate hist_ctrs_gen; + +DATA_HIST_OUT <= hist_inst; + + +process(CLK) +begin + if rising_edge(CLK) then + DEBUG_OUT(0) <= rx_full; + DEBUG_OUT(1) <= rx_empty; + DEBUG_OUT(2) <= tx_full; + DEBUG_OUT(3) <= tx_empty; + DEBUG_OUT(7 downto 4) <= state; + end if; +end process; + +DEBUG_OUT(63 downto 8) <= (others => '0'); + +process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + mon_rec_frames <= (others => '0'); + elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then + mon_rec_frames <= mon_rec_frames + x"1"; + else + mon_rec_frames <= mon_rec_frames; + end if; + end if; +end process; +MONITOR_SELECT_REC_OUT <= mon_rec_frames; + +process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + mon_rec_bytes <= (others => '0'); + elsif (rx_fifo_wr = '1') then + mon_rec_bytes <= mon_rec_bytes + x"1"; + else + mon_rec_bytes <= mon_rec_bytes; + end if; + end if; +end process; +MONITOR_SELECT_REC_BYTES_OUT <= mon_rec_bytes; + +process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + mon_sent_frames <= (others => '0'); + elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then + mon_sent_frames <= mon_sent_frames + x"1"; + else + mon_sent_frames <= mon_sent_frames; + end if; + end if; +end process; +MONITOR_SELECT_SENT_OUT <= mon_sent_frames; + +process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + mon_sent_bytes <= (others => '0'); + elsif (tx_fifo_rd = '1') then + mon_sent_bytes <= mon_sent_bytes + x"1"; + else + mon_sent_bytes <= mon_sent_bytes; + end if; + end if; +end process; +MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes; + +-- statistics +--REC_FRAMES_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- rec_frames <= (others => '0'); +-- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then +-- rec_frames <= rec_frames + x"1"; +-- end if; +-- end if; +--end process REC_FRAMES_PROC; +-- +-- needed for identification +REPLY_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + reply_ctr <= (others => '0'); + elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then + reply_ctr <= reply_ctr + x"1"; + end if; + end if; +end process REPLY_CTR_PROC; +-- +-- +--STATS_MACHINE_PROC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (RESET = '1') then +-- stats_current_state <= IDLE; +-- else +-- stats_current_state <= stats_next_state; +-- end if; +-- end if; +--end process STATS_MACHINE_PROC; +-- +--STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state, tx_loaded_ctr, tx_data_ctr) +--begin +-- +-- case (stats_current_state) is +-- +-- when IDLE => +-- if ((dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr)) then +-- stats_next_state <= LOAD_RECEIVED; +-- else +-- stats_next_state <= IDLE; +-- end if; +-- +-- when LOAD_RECEIVED => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= LOAD_REPLY; +-- else +-- stats_next_state <= LOAD_RECEIVED; +-- end if; +-- +-- when LOAD_REPLY => +-- if (STAT_DATA_ACK_IN = '1') then +-- stats_next_state <= CLEANUP; +-- else +-- stats_next_state <= LOAD_REPLY; +-- end if; +-- +-- when CLEANUP => +-- stats_next_state <= IDLE; +-- +-- end case; +-- +--end process STATS_MACHINE; +-- +--SELECTOR : process(CLK) +--begin +-- if rising_edge(CLK) then +-- case(stats_current_state) is +-- +-- when LOAD_RECEIVED => +-- stat_data_temp <= x"0502" & rec_frames; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); +-- +-- when LOAD_REPLY => +-- stat_data_temp <= x"0503" & reply_ctr; +-- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); +-- +-- when others => +-- stat_data_temp <= (others => '0'); +-- STAT_ADDR_OUT <= (others => '0'); +-- +-- end case; +-- end if; +--end process SELECTOR; +-- +--STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); +--STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); +--STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); +--STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); +-- +--STAT_SYNC : process(CLK) +--begin +-- if rising_edge(CLK) then +-- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then +-- STAT_DATA_RDY_OUT <= '1'; +-- else +-- STAT_DATA_RDY_OUT <= '0'; +-- end if; +-- end if; +--end process STAT_SYNC; +----STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; +-- +---- end of statistics + + +end architecture RTL; diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_Stat.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Stat.vhd new file mode 100644 index 0000000..5453f5a --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Stat.vhd @@ -0,0 +1,333 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:10:12 11/18/2011 +-- Design Name: +-- Module Name: trb_net16_gbe_response_constructor_Stat - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +entity trb_net16_gbe_response_constructor_Stat is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + + TC_BUSY_IN : in std_logic; + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + + STAT_DATA_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0); + STAT_ADDR_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0); + STAT_DATA_RDY_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0); + STAT_DATA_ACK_OUT : out std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0); + +-- debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_response_constructor_Stat; + +architecture Behavioral of trb_net16_gbe_response_constructor_Stat is + +attribute syn_encoding : string; + +type construct_states is (IDLE, WAIT_FOR_LOAD, LOAD_DATA, TERMINATION, CLEANUP); +signal construct_current_state, construct_next_state : construct_states; +attribute syn_encoding of construct_current_state: signal is "safe,gray"; + +signal timer : unsigned(28 downto 0); +signal state : std_logic_vector(3 downto 0); +signal load_ctr : integer range 0 to 255; +signal tc_data : std_logic_vector(8 downto 0); +signal tc_data_t : std_logic_vector(7 downto 0); +signal timer_lock : std_logic; + +signal mem_din : std_logic_vector(31 downto 0); +signal mem_dout, mem_wr_addr : std_logic_vector(7 downto 0); +signal mem_rd_addr : std_logic_vector(9 downto 0); +signal mem_wr_en : std_logic; +signal selected : std_logic_vector(c_MAX_PROTOCOLS downto 0); + +signal pause : integer range 0 to 28; + +signal stat_data_temp : std_logic_vector(31 downto 0); + +begin +--pause <= 10 when g_SIMULATE = 1 else 28; +pause <= 28; + + +mem : statts_mem + PORT map( + WrClock => CLK, + Reset => RESET, + WrClockEn => '1', + WE => mem_wr_en, + WrAddress => mem_wr_addr, + Data => mem_din, + RdClock => CLK, + RdAddress => mem_rd_addr, + Q => mem_dout, + RdClockEn => '1' + ); + +mem_wr_en <= or_all(selected); +STAT_DATA_ACK_OUT <= selected; + +SELECTOR_PROC : process(CLK) + variable found : boolean := false; +begin + if rising_edge(CLK) then + + selected <= (others => '0'); + + if (RESET = '1') then + mem_wr_addr <= (others => '0'); + mem_din <= (others => '0'); + found := false; + else + if (or_all(STAT_DATA_RDY_IN) = '1') then + for i in 0 to c_MAX_PROTOCOLS loop + if (STAT_DATA_RDY_IN(i) = '1') then + mem_wr_addr <= STAT_ADDR_IN((i + 1) * 8 - 1 downto i * 8); + mem_din <= STAT_DATA_IN((i + 1) * 32 - 1 downto i * 32); + selected(i) <= '1'; + found := true; + elsif (i = c_MAX_PROTOCOLS) and (STAT_DATA_RDY_IN(i) = '0') and (found = false) then + found := false; + end if; + end loop; + else + mem_wr_addr <= (others => '0'); + mem_din <= (others => '0'); + found := false; + end if; + end if; + + end if; +end process SELECTOR_PROC; + + + + + +TIMER_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + timer <= (others => '0'); + timer_lock <= '0'; + elsif (timer(pause) = '0') then + timer_lock <= '0'; + timer <= timer + 1; + elsif (timer(pause) = '1') then + timer_lock <= '1'; + timer <= timer + 1; + else + timer <= timer + 1; + end if; + end if; +end process TIMER_PROC; + +-- **** MESSAGES CONSTRUCTING PART + +CONSTRUCT_MACHINE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + construct_current_state <= IDLE; + else + construct_current_state <= construct_next_state; + end if; + end if; +end process CONSTRUCT_MACHINE_PROC; + +CONSTRUCT_MACHINE : process(construct_current_state, timer_lock, TC_BUSY_IN, PS_SELECTED_IN, timer, load_ctr, pause) +begin + case construct_current_state is + + when IDLE => + state <= x"1"; + if (timer(pause) = '1' and timer_lock = '0') then + construct_next_state <= WAIT_FOR_LOAD; + else + construct_next_state <= IDLE; + end if; + + when WAIT_FOR_LOAD => + state <= x"4"; + if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then + construct_next_state <= LOAD_DATA; + else + construct_next_state <= WAIT_FOR_LOAD; + end if; + + when LOAD_DATA => + state <= x"2"; + if (load_ctr = 255) then + construct_next_state <= TERMINATION; + else + construct_next_state <= LOAD_DATA; + end if; + + when TERMINATION => + state <= x"e"; + construct_next_state <= CLEANUP; + + when CLEANUP => + state <= x"9"; + construct_next_state <= IDLE; + + end case; +end process CONSTRUCT_MACHINE; + +LOAD_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (construct_current_state = IDLE) then + load_ctr <= 1; + elsif (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') then + load_ctr <= load_ctr + 1; + end if; + end if; +end process LOAD_CTR_PROC; + +mem_rd_addr <= std_logic_vector(to_unsigned(load_ctr, 10)); + +TC_DATA_PROC : process(construct_current_state, tc_data_t) +begin + + tc_data(8) <= '0'; + + case (construct_current_state) is + + when LOAD_DATA => + for i in 0 to 7 loop + tc_data(i) <= mem_dout(i); + end loop; + + when TERMINATION => + tc_data(7 downto 0) <= x"ff"; + tc_data(8) <= '1'; + + when others => tc_data(7 downto 0) <= x"00"; + + end case; + +end process; + +TC_DATA_SYNC : process(CLK) +begin + if rising_edge(CLK) then + TC_DATA_OUT <= tc_data; + end if; +end process TC_DATA_SYNC; + + +--PS_BUSY_OUT <= '0' when (construct_current_state = IDLE) else '1'; +--PS_RESPONSE_READY_OUT <= '0' when (construct_current_state = IDLE) else '1'; + +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (construct_current_state = IDLE) then + PS_RESPONSE_READY_OUT <= '0'; + else + PS_RESPONSE_READY_OUT <= '1'; + end if; + + if (construct_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; + +TC_FRAME_SIZE_OUT <= x"0100"; +TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip + +TC_DEST_MAC_OUT <= x"ffffffffffff"; +TC_DEST_IP_OUT <= x"ff" & g_MY_IP(23 downto 0); --x"ff00a8c0"; +TC_DEST_UDP_OUT <= x"51c3"; +TC_SRC_MAC_OUT <= g_MY_MAC; +TC_SRC_IP_OUT <= g_MY_IP; +TC_SRC_UDP_OUT <= x"51c3"; +TC_IP_PROTOCOL_OUT <= x"11"; -- udp + +TC_IP_SIZE_OUT <= x"0100"; +TC_UDP_SIZE_OUT <= x"0100"; +TC_FLAGS_OFFSET_OUT <= (others => '0'); + +-- **** debug +DEBUG_OUT(3 downto 0) <= state; +DEBUG_OUT(4) <= '0'; +DEBUG_OUT(7 downto 5) <= "000"; +DEBUG_OUT(8) <= '0'; +DEBUG_OUT(11 downto 9) <= "000"; +DEBUG_OUT(31 downto 12) <= (others => '0'); +-- **** + +end Behavioral; + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_Test.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Test.vhd new file mode 100644 index 0000000..cf8005d --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Test.vhd @@ -0,0 +1,235 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; + +--******** +-- Response Constructor which forwards received frame back ceating a loopback +-- + +entity trb_net16_gbe_response_constructor_Test is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + TC_BUSY_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_response_constructor_Test; + + +architecture trb_net16_gbe_response_constructor_Test of trb_net16_gbe_response_constructor_Test is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_response_constructor_Test: architecture is "GBE_MAIN_group"; + +attribute syn_encoding : string; + +type dissect_states is (IDLE, SAVE, WAIT_FOR_LOAD, LOAD, CLEANUP); +signal dissect_current_state, dissect_next_state : dissect_states; +attribute syn_encoding of dissect_current_state: signal is "safe,gray"; + +signal ff_wr_en : std_logic; +signal ff_rd_en : std_logic; +signal resp_bytes_ctr : std_logic_vector(15 downto 0); +signal ff_empty : std_logic; +signal ff_full : std_logic; +signal ff_q : std_logic_vector(8 downto 0); +signal ff_rd_lock : std_logic; + +signal state : std_logic_vector(3 downto 0); +signal rec_frames : std_logic_vector(15 downto 0); +signal sent_frames : std_logic_vector(15 downto 0); + +begin + +DISSECT_MACHINE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + dissect_current_state <= IDLE; + else + dissect_current_state <= dissect_next_state; + end if; + end if; +end process DISSECT_MACHINE_PROC; + +DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, ff_q, ff_rd_lock, TC_BUSY_IN) +begin + case dissect_current_state is + + when IDLE => + state <= x"1"; + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + dissect_next_state <= SAVE; + else + dissect_next_state <= IDLE; + end if; + + when SAVE => + state <= x"2"; + if (PS_DATA_IN(8) = '1') then + dissect_next_state <= WAIT_FOR_LOAD; + else + dissect_next_state <= SAVE; + end if; + + when WAIT_FOR_LOAD => + state <= x"3"; + if (TC_BUSY_IN = '0') then + dissect_next_state <= LOAD; + else + dissect_next_state <= WAIT_FOR_LOAD; + end if; + + when LOAD => + state <= x"4"; + if (ff_q(8) = '1') and (ff_rd_lock = '0') then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= LOAD; + end if; + + when CLEANUP => + state <= x"5"; + dissect_next_state <= IDLE; + + end case; +end process DISSECT_MACHINE; + +PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; + +ff_wr_en <= '1' when (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') else '0'; + +FF_RD_LOCK_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + ff_rd_lock <= '1'; + elsif (dissect_current_state = LOAD and ff_rd_en = '1') then + ff_rd_lock <= '0'; + else + ff_rd_lock <= '1'; + end if; + end if; +end process FF_RD_LOCK_PROC; + +-- TODO: put a smaller fifo here +FRAME_FIFO: fifo_4096x9 +port map( + Data => PS_DATA_IN, + WrClock => CLK, + RdClock => CLK, + WrEn => ff_wr_en, + RdEn => ff_rd_en, + Reset => RESET, + RPReset => RESET, + Q => ff_q, + Empty => ff_empty, + Full => ff_full +); + +ff_rd_en <= '1' when (TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') else '0'; + +TC_DATA_OUT <= ff_q; + +PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) else '0'; + +TC_FRAME_SIZE_OUT <= resp_bytes_ctr + x"1"; + +TC_FRAME_TYPE_OUT <= x"aa08"; +TC_DEST_MAC_OUT <= x"9a680f201300"; +TC_DEST_IP_OUT <= x"0100a8c0"; +TC_DEST_UDP_OUT <= x"51c3"; +TC_SRC_MAC_OUT <= x"efbeefbe0000"; +TC_SRC_IP_OUT <= x"0b00a8c0"; +TC_SRC_UDP_OUT <= x"51c3"; +TC_IP_PROTOCOL_OUT <= x"11"; + +RESP_BYTES_CTR_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (dissect_current_state = IDLE) then + resp_bytes_ctr <= (others => '0'); + elsif (dissect_current_state = SAVE) then + resp_bytes_ctr <= resp_bytes_ctr + x"1"; + end if; + end if; +end process RESP_BYTES_CTR_PROC; + +REC_FRAMES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + rec_frames <= (others => '0'); + elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + rec_frames <= rec_frames + x"1"; + end if; + end if; +end process REC_FRAMES_PROC; + +SENT_FRAMES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + sent_frames <= (others => '0'); + elsif (dissect_current_state = WAIT_FOR_LOAD and TC_BUSY_IN = '0') then + sent_frames <= sent_frames + x"1"; + end if; + end if; +end process SENT_FRAMES_PROC; + +RECEIVED_FRAMES_OUT <= rec_frames; +SENT_FRAMES_OUT <= sent_frames; + +-- **** debug +DEBUG_OUT(3 downto 0) <= state; +DEBUG_OUT(4) <= ff_empty; +DEBUG_OUT(7 downto 5) <= "000"; +DEBUG_OUT(8) <= ff_full; +DEBUG_OUT(11 downto 9) <= "000"; +DEBUG_OUT(31 downto 12) <= (others => '0'); +-- **** + +end trb_net16_gbe_response_constructor_Test; + + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_Test1.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Test1.vhd new file mode 100644 index 0000000..8a1b618 --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Test1.vhd @@ -0,0 +1,160 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; + +--******** +-- Response Constructor which recevies data and does nothing except counting incoming packets +-- + +entity trb_net16_gbe_response_constructor_Test1 is +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + + TC_BUSY_IN : in std_logic; + + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_response_constructor_Test1; + + +architecture trb_net16_gbe_response_constructor_Test1 of trb_net16_gbe_response_constructor_Test1 is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_response_constructor_Forward : architecture is "GBE_MAIN_group"; + +attribute syn_encoding : string; + +type dissect_states is (IDLE, SAVE, CLEANUP); +signal dissect_current_state, dissect_next_state : dissect_states; +attribute syn_encoding of dissect_current_state: signal is "safe,gray"; + +signal ff_wr_en : std_logic; +signal ff_rd_en : std_logic; +signal resp_bytes_ctr : std_logic_vector(15 downto 0); +signal ff_empty : std_logic; +signal ff_full : std_logic; +signal ff_q : std_logic_vector(8 downto 0); +signal ff_rd_lock : std_logic; + +signal state : std_logic_vector(3 downto 0); +signal rec_frames : std_logic_vector(15 downto 0); +signal sent_frames : std_logic_vector(15 downto 0); + +begin + +DISSECT_MACHINE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + dissect_current_state <= IDLE; + else + dissect_current_state <= dissect_next_state; + end if; + end if; +end process DISSECT_MACHINE_PROC; + +DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN) +begin + case dissect_current_state is + + when IDLE => + state <= x"1"; + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + dissect_next_state <= SAVE; + else + dissect_next_state <= IDLE; + end if; + + when SAVE => + state <= x"2"; + if (PS_DATA_IN(8) = '1') then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= SAVE; + end if; + + when CLEANUP => + state <= x"5"; + dissect_next_state <= IDLE; + + end case; +end process DISSECT_MACHINE; + +PS_BUSY_OUT <= '0'; + +TC_DATA_OUT <= (others => '0'); + +PS_RESPONSE_READY_OUT <= '0'; + +TC_FRAME_SIZE_OUT <= (others => '0'); + +TC_FRAME_TYPE_OUT <= x"0008"; +TC_DEST_MAC_OUT <= x"9a680f201300"; +TC_DEST_IP_OUT <= x"0100a8c0"; +TC_DEST_UDP_OUT <= x"50c3"; +TC_SRC_MAC_OUT <= x"efbeefbe0000"; +TC_SRC_IP_OUT <= x"0b00a8c0"; +TC_SRC_UDP_OUT <= x"50c3"; +TC_IP_PROTOCOL_OUT <= x"11"; + +REC_FRAMES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + rec_frames <= (others => '0'); + elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + rec_frames <= rec_frames + x"1"; + end if; + end if; +end process REC_FRAMES_PROC; + +RECEIVED_FRAMES_OUT <= rec_frames; +SENT_FRAMES_OUT <= (others => '0'); + +-- **** debug +DEBUG_OUT(31 downto 0) <= (others => '0'); +-- **** + +end trb_net16_gbe_response_constructor_Test1; + + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_Trash.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Trash.vhd new file mode 100644 index 0000000..4845606 --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Trash.vhd @@ -0,0 +1,163 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; + +--******** +-- gets all the data which is not supposed to be received by other protocols +-- simply clears the fifo from garbage + +entity trb_net16_gbe_response_constructor_Trash is +generic ( STAT_ADDRESS_BASE : integer := 0 +); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_SIZE_LEFT_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + TC_BUSY_IN : in std_logic; + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); + SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); +-- END OF INTERFACE + +-- debug + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end trb_net16_gbe_response_constructor_Trash; + + +architecture trb_net16_gbe_response_constructor_Trash of trb_net16_gbe_response_constructor_Trash is + +--attribute HGROUP : string; +--attribute HGROUP of trb_net16_gbe_response_constructor_Trash : architecture is "GBE_MAIN_group"; + +attribute syn_encoding : string; + +type dissect_states is (IDLE, SAVE, CLEANUP); +signal dissect_current_state, dissect_next_state : dissect_states; +attribute syn_encoding of dissect_current_state: signal is "safe,gray"; + +signal state : std_logic_vector(3 downto 0); +signal rec_frames : std_logic_vector(15 downto 0); +signal sent_frames : std_logic_vector(15 downto 0); + +begin + +DISSECT_MACHINE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + dissect_current_state <= IDLE; + else + dissect_current_state <= dissect_next_state; + end if; + end if; +end process DISSECT_MACHINE_PROC; + +DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN) +begin + case dissect_current_state is + + when IDLE => + state <= x"1"; + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + dissect_next_state <= SAVE; + else + dissect_next_state <= IDLE; + end if; + + when SAVE => + state <= x"2"; + if (PS_DATA_IN(8) = '1') then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= SAVE; + end if; + + when CLEANUP => + state <= x"5"; + dissect_next_state <= IDLE; + + end case; +end process DISSECT_MACHINE; + +PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; + +TC_DATA_OUT <= '0' & x"ab"; + +PS_RESPONSE_READY_OUT <= '0'; + +TC_FRAME_SIZE_OUT <= (others => '0'); + +TC_FRAME_TYPE_OUT <= (others => '0'); +TC_DEST_MAC_OUT <= (others => '0'); +TC_DEST_IP_OUT <= (others => '0'); +TC_DEST_UDP_OUT <= (others => '0'); +TC_SRC_MAC_OUT <= (others => '0'); +TC_SRC_IP_OUT <= (others => '0'); +TC_SRC_UDP_OUT <= (others => '0'); +TC_IP_PROTOCOL_OUT <= (others => '0'); + +REC_FRAMES_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + rec_frames <= (others => '0'); + elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + rec_frames <= rec_frames + x"1"; + end if; + end if; +end process REC_FRAMES_PROC; + +RECEIVED_FRAMES_OUT <= rec_frames; +SENT_FRAMES_OUT <= (others => '0'); + +-- **** debug +DEBUG_OUT(3 downto 0) <= state; +DEBUG_OUT(31 downto 4) <= (others => '0'); +-- **** + +end trb_net16_gbe_response_constructor_Trash; + + diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd new file mode 100644 index 0000000..d70d2a9 --- /dev/null +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd @@ -0,0 +1,617 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +entity trb_net16_gbe_response_constructor_TrbNetData is +generic ( + RX_PATH_ENABLE : integer range 0 to 1 := 1; + DO_SIMULATION : integer range 0 to 1 := 0; + READOUT_BUFFER_SIZE : integer range 1 to 4 := 1 + ); +port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + +-- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_ADDR_OUT : out std_logic_vector(7 downto 0); + STAT_DATA_RDY_OUT : out std_logic; + STAT_DATA_ACK_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(63 downto 0); +-- END OF INTERFACE + + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + -- ip configurator + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + + MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(31 downto 0); + MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(31 downto 0); + + DATA_HIST_OUT : out hist_array +); +end trb_net16_gbe_response_constructor_TrbNetData; + + +architecture trb_net16_gbe_response_constructor_TrbNetData of trb_net16_gbe_response_constructor_TrbNetData is + +attribute syn_encoding : string; + +signal ip_cfg_start : std_logic; +signal ip_cfg_bank : std_logic_vector(3 downto 0); +signal ip_cfg_done : std_logic; +signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); +signal ip_cfg_mem_data : std_logic_vector(31 downto 0); +signal ip_cfg_mem_clk : std_logic; + +signal ic_dest_mac, ic_dest_mac_shift : std_logic_vector(47 downto 0); +signal ic_dest_ip, ic_dest_ip_shift : std_logic_vector(31 downto 0); +signal ic_dest_udp, ic_dest_udp_shift : std_logic_vector(15 downto 0); +signal ic_src_mac, ic_src_mac_shift : std_logic_vector(47 downto 0); +signal ic_src_ip, ic_src_ip_shift : std_logic_vector(31 downto 0); +signal ic_src_udp, ic_src_udp_shift : std_logic_vector(15 downto 0); + +signal pc_wr_en : std_logic; +signal pc_data : std_logic_vector(7 downto 0); +signal pc_eoq : std_logic; +signal pc_sos : std_logic; +signal pc_ready : std_logic; +signal pc_sub_size : std_logic_vector(31 downto 0); +signal pc_trig_nr : std_logic_vector(31 downto 0); +signal pc_eos : std_logic; + +signal tc_rd_en : std_logic; +signal tc_data : std_logic_vector(8 downto 0); +signal tc_size : std_logic_vector(15 downto 0); +signal tc_sod : std_logic; +signal pc_trig_type, pc_trig_type_shift : std_logic_vector(3 downto 0); + +type dissect_states is (IDLE, WAIT_FOR_LOAD, LOAD, CLEANUP); +signal dissect_current_state, dissect_next_state : dissect_states; +attribute syn_encoding of dissect_current_state : signal is "onehot"; + +signal event_bytes : std_logic_vector(15 downto 0); +signal loaded_bytes : std_logic_vector(15 downto 0); +signal sent_packets : std_logic_vector(15 downto 0); + +signal mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0); +signal ipu_dbg : std_logic_vector(383 downto 0); +signal constr_dbg : std_logic_vector(63 downto 0); + +signal hist_inst : hist_array; +signal tc_sod_flag : std_logic; +signal reset_all_hist : std_logic_vector(31 downto 0); +signal ipu_monitor : std_logic_vector(223 downto 0); + +-- JUST FOR DEBUGING PURPOSE +type sim_check_states is (IDLE, SAVE_HDR, GO_OVER_DATA, SAVE_TLR, GET_ONE_MORE, GET_SECOND_MORE, CLEANUP); +signal sim_check_current, sim_check_next : sim_check_states; + +signal hdr, tlr : std_logic_vector(255 downto 0); + + + +begin + + +sim_check_gen : if DO_SIMULATION = 1 generate + + process(RESET, CLK) + begin + if RESET = '1' then + sim_check_current <= IDLE; + elsif rising_edge(CLK) then + sim_check_current <= sim_check_next; + end if; + end process; + + process(sim_check_current, tc_sod, loaded_bytes, tc_size, hdr, tlr, event_bytes) + begin + case (sim_check_current) is + + when IDLE => + if (tc_sod = '1') then + sim_check_next <= SAVE_HDR; + else + sim_check_next <= IDLE; + end if; + + when SAVE_HDR => + if (loaded_bytes = x"001f" + x"0002") then + sim_check_next <= GO_OVER_DATA; + else + sim_check_next <= SAVE_HDR; + end if; + + when GO_OVER_DATA => + if (loaded_bytes = tc_size + x"0001") then + sim_check_next <= SAVE_TLR; + else + sim_check_next <= GO_OVER_DATA; + end if; + + when SAVE_TLR => + if (loaded_bytes = event_bytes) then + sim_check_next <= GET_ONE_MORE; + else + sim_check_next <= SAVE_TLR; + end if; + + when GET_ONE_MORE => + sim_check_next <= GET_SECOND_MORE; + + when GET_SECOND_MORE => + sim_check_next <= CLEANUP; + + when CLEANUP => + + --assert (hdr = tlr) report "--------- >>>> Header Trailer mismatch" severity failure; + + sim_check_next <= IDLE; + + end case; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if (sim_check_current = SAVE_HDR and loaded_bytes > x"0001") then + hdr((to_integer(unsigned(loaded_bytes - x"0002") * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - x"0002")) * 8)) <= tc_data(7 downto 0); + else + hdr <= hdr; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if (sim_check_current = SAVE_TLR) then + tlr((to_integer(unsigned(loaded_bytes - tc_size - 2) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 2)) * 8)) <= tc_data(7 downto 0); + elsif (sim_check_current = GET_ONE_MORE) then + tlr((to_integer(unsigned(loaded_bytes - tc_size - 1) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 1)) * 8)) <= tc_data(7 downto 0); + elsif (sim_check_current = GET_ONE_MORE) then + tlr((to_integer(unsigned(loaded_bytes - tc_size) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size)) * 8)) <= tc_data(7 downto 0); + else + tlr <= tlr; + end if; + end if; + end process; + + +end generate sim_check_gen; + + + + +THE_IP_CONFIGURATOR: ip_configurator +port map( + CLK => CLK, + RESET => RESET, + -- configuration interface + START_CONFIG_IN => ip_cfg_start, + BANK_SELECT_IN => ip_cfg_bank, + CONFIG_DONE_OUT => ip_cfg_done, + MEM_ADDR_OUT => ip_cfg_mem_addr, + MEM_DATA_IN => ip_cfg_mem_data, + MEM_CLK_OUT => ip_cfg_mem_clk, + -- information for IP cores + DEST_MAC_OUT => ic_dest_mac, + DEST_IP_OUT => ic_dest_ip, + DEST_UDP_OUT => ic_dest_udp, + SRC_MAC_OUT => ic_src_mac, + SRC_IP_OUT => ic_src_ip, + SRC_UDP_OUT => ic_src_udp, + MTU_OUT => open, + -- Debug + DEBUG_OUT => open +); + +MB_IP_CONFIG: slv_mac_memory +port map( + CLK => CLK, + RESET => RESET, + BUSY_IN => '0', + -- Slave bus + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + -- I/O to the backend + MEM_CLK_IN => ip_cfg_mem_clk, + MEM_ADDR_IN => ip_cfg_mem_addr, + MEM_DATA_OUT => ip_cfg_mem_data, + -- Status lines + STAT => open +); + +THE_IPU_INTERFACE: entity work.trb_net16_gbe_ipu_interface +generic map ( + DO_SIMULATION => DO_SIMULATION +) +port map( + CLK_IPU => CLK, + CLK_GBE => CLK, + RESET => RESET, + --Event information coming from CTS + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + -- Data from Frontends + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + -- slow control interface + START_CONFIG_OUT => ip_cfg_start, + BANK_SELECT_OUT => ip_cfg_bank, + CONFIG_DONE_IN => ip_cfg_done, + DATA_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, + DATA_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, + MULT_EVT_ENABLE_IN => CFG_MULT_ENABLE_IN, + MAX_SUBEVENT_SIZE_IN => CFG_MAX_SUB_IN, + MAX_QUEUE_SIZE_IN => CFG_MAX_QUEUE_IN, + MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, + MAX_SINGLE_SUB_SIZE_IN => CFG_MAX_SINGLE_SUB_IN, + READOUT_CTR_IN => CFG_READOUT_CTR_IN, + READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, + -- PacketConstructor interface + PC_WR_EN_OUT => pc_wr_en, + PC_DATA_OUT => pc_data, + PC_READY_IN => pc_ready, + PC_SOS_OUT => pc_sos, + PC_EOS_OUT => pc_eos, + PC_EOQ_OUT => pc_eoq, + PC_SUB_SIZE_OUT => pc_sub_size, + PC_TRIG_NR_OUT => pc_trig_nr, + PC_TRIGGER_TYPE_OUT => pc_trig_type, + MONITOR_OUT => ipu_monitor, + DEBUG_OUT => ipu_dbg +); + +MONITOR_SELECT_DROP_OUT_OUT <= ipu_monitor(31 downto 0); + +PACKET_CONSTRUCTOR : entity work.trb_net16_gbe_event_constr +generic map( + READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, + DO_SIMULATION => DO_SIMULATION +) +port map( + CLK => CLK, + RESET => RESET, + PC_WR_EN_IN => pc_wr_en, + PC_DATA_IN => pc_data, + PC_READY_OUT => pc_ready, + PC_START_OF_SUB_IN => pc_sos, + PC_END_OF_SUB_IN => pc_eos, + PC_END_OF_QUEUE_IN => pc_eoq, + PC_SUB_SIZE_IN => pc_sub_size, + PC_DECODING_IN => CFG_SUBEVENT_DEC_IN, + PC_EVENT_ID_IN => CFG_SUBEVENT_ID_IN, + PC_TRIG_NR_IN => pc_trig_nr, + PC_TRIGGER_TYPE_IN => pc_trig_type_shift, + PC_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, + PC_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, + TC_RD_EN_IN => tc_rd_en, + TC_DATA_OUT => tc_data, + TC_EVENT_SIZE_OUT => tc_size, + TC_SOD_OUT => tc_sod, + DEBUG_OUT => constr_dbg +); + +tc_rd_en <= '1' when PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' else '0'; + +DISSECT_MACHINE_PROC : process(RESET, CLK) +begin + if RESET = '1' then + dissect_current_state <= IDLE; + elsif rising_edge(CLK) then + dissect_current_state <= dissect_next_state; + end if; +end process DISSECT_MACHINE_PROC; + +DISSECT_MACHINE : process(dissect_current_state, tc_sod, event_bytes, loaded_bytes, PS_SELECTED_IN) +begin + case dissect_current_state is + + when IDLE => + if (tc_sod = '1') then + dissect_next_state <= WAIT_FOR_LOAD; + else + dissect_next_state <= IDLE; + end if; + + when WAIT_FOR_LOAD => + if (PS_SELECTED_IN = '1') then + dissect_next_state <= LOAD; + else + dissect_next_state <= WAIT_FOR_LOAD; + end if; + + when LOAD => + if (event_bytes = loaded_bytes) then + dissect_next_state <= CLEANUP; + else + dissect_next_state <= LOAD; + end if; + + when CLEANUP => + dissect_next_state <= IDLE; + + end case; +end process DISSECT_MACHINE; + +PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; +PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) or (dissect_current_state = WAIT_FOR_LOAD) else '0'; + +TC_DATA_OUT <= tc_data; + +EVENT_BYTES_PROC : process (clk) is +begin + if rising_edge(clk) then + if dissect_current_state = IDLE and tc_sod = '1' then + event_bytes <= tc_size + x"20"; -- adding termination bytes + else + event_bytes <= event_bytes; + end if; + end if; +end process EVENT_BYTES_PROC; + +LOADED_BYTES_PROC : process (clk) is +begin + if rising_edge(clk) then + if (dissect_current_state = IDLE) then + loaded_bytes <= (others => '0'); + elsif (dissect_current_state = LOAD and TC_RD_EN_IN = '1') then + loaded_bytes <= loaded_bytes + x"1"; + else + loaded_bytes <= loaded_bytes; + end if; + end if; +end process LOADED_BYTES_PROC; + +TC_FRAME_SIZE_OUT <= event_bytes; +TC_FRAME_TYPE_OUT <= x"0008"; + +TC_DEST_MAC_OUT <= ic_dest_mac_shift; --x"c4e870211b00"; --ic_dest_mac; +TC_DEST_IP_OUT <= ic_dest_ip_shift; --x"0300a8c0"; --ic_dest_ip; +TC_DEST_UDP_OUT <= ic_dest_udp_shift; --x"c35c"; --ic_dest_udp; + +--TC_DEST_MAC_OUT <= x"87883c290c00"; --ic_dest_mac; +--TC_DEST_IP_OUT <= x"0188a8c0"; --ic_dest_ip; +--TC_DEST_UDP_OUT <= x"c35b"; --ic_dest_udp; + +process(CLK) +begin + if rising_edge(CLK) then + if (ip_cfg_start = '1') then + ic_dest_mac_shift <= ic_dest_mac; + ic_dest_ip_shift <= ic_dest_ip; + ic_dest_udp_shift <= ic_dest_udp; + + ic_src_mac_shift <= ic_src_mac; + ic_src_ip_shift <= ic_src_ip; + ic_src_udp_shift <= ic_src_udp; + + pc_trig_type_shift <= pc_trig_type; + else + ic_dest_mac_shift <= ic_dest_mac_shift; + ic_dest_ip_shift <= ic_dest_ip_shift; + ic_dest_udp_shift <= ic_dest_udp_shift; + + ic_src_mac_shift <= ic_src_mac_shift; + ic_src_ip_shift <= ic_src_ip_shift; + ic_src_udp_shift <= ic_src_udp_shift; + + pc_trig_type_shift <= pc_trig_type_shift; + end if; + end if; +end process; + + + +rx_enable_gen : if (RX_PATH_ENABLE = 1) generate + TC_SRC_MAC_OUT <= MY_MAC_IN; + TC_SRC_IP_OUT <= MY_IP_IN; +end generate rx_enable_gen; + +rx_disable_gen : if (RX_PATH_ENABLE = 0) generate + TC_SRC_MAC_OUT <= MY_MAC_IN; + TC_SRC_IP_OUT <= ic_src_ip_shift; +end generate rx_disable_gen; + +TC_SRC_UDP_OUT <= ic_src_udp_shift; +TC_IP_PROTOCOL_OUT <= x"11"; +TC_IDENT_OUT <= x"4" & sent_packets(11 downto 0); + +SENT_PACKETS_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + sent_packets <= (others => '0'); + elsif (dissect_current_state = IDLE and tc_sod = '1') then + sent_packets <= sent_packets + x"1"; + end if; + end if; +end process SENT_PACKETS_PROC; + +-- monitoring + + +process(CLK) +begin + if rising_edge(CLK) then + if (tc_sod = '1' and tc_sod_flag = '0') then + tc_sod_flag <= '1'; + elsif (tc_sod = '0') then + tc_sod_flag <= '0'; + else + tc_sod_flag <= tc_sod_flag; + end if; + end if; +end process; + +hist_ctrs_gen : for i in 0 to 31 generate + + process(CLK) + begin + if rising_edge(CLK) then + if (RESET = '1') then + reset_all_hist(i) <= '1'; + elsif (hist_inst(i) = x"ffff_ffff") then + reset_all_hist(i) <= '1'; + else + reset_all_hist(i) <= '0'; + end if; + end if; + end process; + + HIST_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (RESET = '1') or (reset_all_hist /= x"0000_0000") then + hist_inst(i) <= (others => '0'); + elsif (tc_sod = '1' and tc_sod_flag = '0' and i = to_integer(unsigned(event_bytes(15 downto 11)))) then + hist_inst(i) <= hist_inst(i) + x"1"; + else + hist_inst(i) <= hist_inst(i); + end if; + end if; + end process; +end generate hist_ctrs_gen; + +DATA_HIST_OUT <= hist_inst; + +process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + mon_sent_frames <= (others => '0'); + elsif (dissect_current_state = LOAD and event_bytes = loaded_bytes) then + mon_sent_frames <= mon_sent_frames + x"1"; + else + mon_sent_frames <= mon_sent_frames; + end if; + end if; +end process; +MONITOR_SELECT_SENT_OUT <= mon_sent_frames; + +process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + mon_sent_bytes <= (others => '0'); + elsif (tc_rd_en = '1') then + mon_sent_bytes <= mon_sent_bytes + x"1"; + else + mon_sent_bytes <= mon_sent_bytes; + end if; + end if; +end process; + +MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes; + + +MONITOR_SELECT_REC_BYTES_OUT <= (others => '0'); +MONITOR_SELECT_REC_OUT <= (others => '0'); + +DEBUG_OUT(31 downto 0) <= ipu_dbg(31 downto 0); +DEBUG_OUT(63 downto 32) <= constr_dbg(31 downto 0); + + + +end trb_net16_gbe_response_constructor_TrbNetData; + + diff --git a/gbe_trb/testbenches/aa_full_wrapper_tb.vhd b/gbe_trb/testbenches/aa_full_wrapper_tb.vhd new file mode 100644 index 0000000..e710131 --- /dev/null +++ b/gbe_trb/testbenches/aa_full_wrapper_tb.vhd @@ -0,0 +1,137 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE ieee.math_real.all; +USE ieee.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +ENTITY aa_full_wrapper_tb IS +END aa_full_wrapper_tb; + +ARCHITECTURE behavior OF aa_full_wrapper_tb IS + +signal clk_sys, clk_125, reset, gsr_n, trigger : std_logic := '0'; + +begin + + uut : entity work.gbe_wrapper + generic map( + DO_SIMULATION => 1, + INCLUDE_DEBUG => 0, + USE_INTERNAL_TRBNET_DUMMY => 0, + USE_EXTERNAL_TRBNET_DUMMY => 1, + RX_PATH_ENABLE => 1, + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 0, + FIXED_SIZE => 13750, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY => 200, + NUMBER_OF_GBE_LINKS => 4, + LINKS_ACTIVE => "1111", + LINK_HAS_PING => "1111", + LINK_HAS_ARP => "1111", + LINK_HAS_DHCP => "1111", + LINK_HAS_READOUT => "1000", + LINK_HAS_SLOWCTRL => "1000", + NUMBER_OF_OUTPUT_LINKS => 4 + ) + port map( + CLK_SYS_IN => clk_sys, + CLK_125_IN => clk_125, + RESET => reset, + GSR_N => gsr_n, + SD_RXD_P_IN => (others => '0'), + SD_RXD_N_IN => (others => '0'), + SD_TXD_P_OUT => open, + SD_TXD_N_OUT => open, + SD_PRSNT_N_IN => (others => '0'), + SD_LOS_IN => (others => '0'), + SD_TXDIS_OUT => open, + TRIGGER_IN => trigger, + CTS_NUMBER_IN => (others => '0'), + CTS_CODE_IN => (others => '0'), + CTS_INFORMATION_IN => (others => '0'), + CTS_READOUT_TYPE_IN => (others => '0'), + CTS_START_READOUT_IN => '0', + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => open, + CTS_READ_IN => '0', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => open, + FEE_DATA_IN => (others => '0'), + FEE_DATAREADY_IN => '0', + FEE_READ_OUT => open, + FEE_STATUS_BITS_IN => (others => '0'), + FEE_BUSY_IN => '0', + MC_UNIQUE_ID_IN => (others => '0'), + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => open, + GSC_INIT_DATA_OUT => open, + GSC_INIT_PACKET_NUM_OUT => open, + GSC_INIT_READ_IN => '1', + GSC_REPLY_DATAREADY_IN => '1', + GSC_REPLY_DATA_IN => x"abcd", + GSC_REPLY_PACKET_NUM_IN => "111", + GSC_REPLY_READ_OUT => open, + GSC_BUSY_IN => '0', + SLV_ADDR_IN => (others => '0'), + SLV_READ_IN => '0', + SLV_WRITE_IN => '0', + SLV_BUSY_OUT => open, + SLV_ACK_OUT => open, + SLV_DATA_IN => (others => '0'), + SLV_DATA_OUT => open, + BUS_ADDR_IN => (others => '0'), + BUS_DATA_IN => (others => '0'), + BUS_DATA_OUT => open, + BUS_WRITE_EN_IN => '0', + BUS_READ_EN_IN => '0', + BUS_ACK_OUT => open, + MAKE_RESET_OUT => open, + DEBUG_OUT => open + ); + + process + begin + clk_sys <= '1'; wait for 5 ns; + clk_sys <= '0'; wait for 5 ns; + end process; + + process + begin + clk_125 <= '1'; wait for 4 ns; + clk_125 <= '0'; wait for 4 ns; + end process; + + process + begin + reset <= '1'; + gsr_n <= '0'; + wait for 100 ns; + reset <= '0'; + gsr_n <= '1'; + wait for 20 us; + + + for i in 0 to 10000 loop + trigger <= '1'; + wait for 100 ns; + trigger <= '0'; + wait for 10 us; + end loop; + + wait; + end process; + + +end; \ No newline at end of file diff --git a/gbe_trb/testbenches/aa_ipu_dummy_tb.vhd b/gbe_trb/testbenches/aa_ipu_dummy_tb.vhd new file mode 100644 index 0000000..b755ee5 --- /dev/null +++ b/gbe_trb/testbenches/aa_ipu_dummy_tb.vhd @@ -0,0 +1,271 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE ieee.math_real.all; +USE ieee.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +ENTITY aa_ipu_dummy_tb IS +END aa_ipu_dummy_tb; + +ARCHITECTURE behavior OF aa_ipu_dummy_tb IS + + +signal clk, reset,RX_MAC_CLK : std_logic; + +SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); +SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); +SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); +SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); +SIGNAL CTS_START_READOUT_IN : std_logic; +SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); +SIGNAL CTS_DATAREADY_OUT : std_logic; +SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; +SIGNAL CTS_READ_IN : std_logic; +SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); +SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); +SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); +SIGNAL FEE_DATAREADY_IN : std_logic; +SIGNAL FEE_READ_OUT : std_logic; +SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0) := x"0000_0000"; +SIGNAL FEE_BUSY_IN : std_logic; + +signal gsr : std_logic; + +signal MAC_RX_EOF_IN, MAC_RX_EN_IN : std_logic; +signal MAC_RXD_IN : std_logic_vector(7 downto 0); + +signal gbe_ready : std_logic; +signal trigger : std_logic; +signal MLT_CTS_NUMBER_OUT : std_logic_vector(16 * 1 - 1 downto 0); +signal MLT_CTS_CODE_OUT : std_logic_vector(8 * 1 - 1 downto 0); +signal MLT_CTS_READOUT_TYPE_OUT : std_logic_vector(4 * 1 - 1 downto 0); +signal MLT_CTS_READOUT_FINISHED_IN : std_logic_vector(1 - 1 downto 0); +signal MLT_CTS_INFORMATION_OUT : std_logic_vector(8 * 1 - 1 downto 0); +signal MLT_CTS_START_READOUT_OUT : std_logic_vector(1 - 1 downto 0); +signal MLT_CTS_DATA_IN : std_logic_vector(32 * 1 - 1 downto 0); +signal MLT_CTS_DATAREADY_IN : std_logic_vector(1 - 1 downto 0); +signal MLT_CTS_READ_OUT : std_logic_vector(1 - 1 downto 0); +signal MLT_CTS_LENGTH_IN : std_logic_vector(16 * 1 - 1 downto 0); +signal MLT_CTS_ERROR_PATTERN_IN : std_logic_vector(32 * 1 - 1 downto 0); +signal MLT_FEE_DATA_OUT : std_logic_vector(16 * 1 - 1 downto 0); +signal MLT_FEE_DATAREADY_OUT : std_logic_vector(1 - 1 downto 0); +signal MLT_FEE_READ_IN : std_logic_vector(1 - 1 downto 0); +signal MLT_FEE_STATUS_BITS_OUT : std_logic_vector(32 * 1 - 1 downto 0); +signal MLT_FEE_BUSY_OUT : std_logic_vector(1 - 1 downto 0); + +begin + + gsr <= not reset; + + + dummy_inst : entity work.gbe_ipu_dummy + generic map(DO_SIMULATION => 1, + FIXED_SIZE_MODE => 1, + FIXED_SIZE => 20, + INCREMENTAL_MODE => 0, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY_MODE => 1, + FIXED_DELAY => 50) + port map(clk => CLK, + rst => RESET, + GBE_READY_IN => gbe_ready, + + CFG_EVENT_SIZE_IN => x"0000", + CFG_TRIGGERED_MODE_IN => '0', + TRIGGER_IN => trigger, + + CTS_NUMBER_OUT => CTS_NUMBER_IN, + CTS_CODE_OUT => CTS_CODE_IN, + CTS_INFORMATION_OUT => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_OUT => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_OUT => CTS_START_READOUT_IN, + CTS_DATA_IN => CTS_DATA_OUT, + CTS_DATAREADY_IN => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_IN => CTS_READOUT_FINISHED_OUT, + CTS_READ_OUT => CTS_READ_IN, + CTS_LENGTH_IN => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_IN => CTS_ERROR_PATTERN_OUT, + FEE_DATA_OUT => FEE_DATA_IN, + FEE_DATAREADY_OUT => FEE_DATAREADY_IN, + FEE_READ_IN => FEE_READ_OUT, + FEE_STATUS_BITS_OUT => FEE_STATUS_BITS_IN, + FEE_BUSY_OUT => FEE_BUSY_IN + ); + + dummy_mult : entity work.gbe_ipu_multiplexer + generic map( + DO_SIMULATION => 1, + INCLUDE_DEBUG => 1, + LINK_HAS_READOUT => "0001", + NUMBER_OF_GBE_LINKS => 1 + ) + port map( + CLK_SYS_IN => CLK, + RESET => RESET, + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + MLT_CTS_NUMBER_OUT => MLT_CTS_NUMBER_OUT, + MLT_CTS_CODE_OUT => MLT_CTS_CODE_OUT, + MLT_CTS_INFORMATION_OUT => MLT_CTS_INFORMATION_OUT, + MLT_CTS_READOUT_TYPE_OUT => MLT_CTS_READOUT_TYPE_OUT, + MLT_CTS_START_READOUT_OUT => MLT_CTS_START_READOUT_OUT, + MLT_CTS_DATA_IN => MLT_CTS_DATA_IN, + MLT_CTS_DATAREADY_IN => MLT_CTS_DATAREADY_IN, + MLT_CTS_READOUT_FINISHED_IN => MLT_CTS_READOUT_FINISHED_IN, + MLT_CTS_READ_OUT => MLT_CTS_READ_OUT, + MLT_CTS_LENGTH_IN => MLT_CTS_LENGTH_IN, + MLT_CTS_ERROR_PATTERN_IN => MLT_CTS_ERROR_PATTERN_IN, + MLT_FEE_DATA_OUT => MLT_FEE_DATA_OUT, + MLT_FEE_DATAREADY_OUT => MLT_FEE_DATAREADY_OUT, + MLT_FEE_READ_IN => MLT_FEE_READ_IN, + MLT_FEE_STATUS_BITS_OUT => MLT_FEE_STATUS_BITS_OUT, + MLT_FEE_BUSY_OUT => MLT_FEE_BUSY_OUT, + DEBUG_OUT => open + ); + + dummy_trbnet : entity work.trb_net16_gbe_response_constructor_TrbNetData + generic map( + RX_PATH_ENABLE => 1, + DO_SIMULATION => 1, + READOUT_BUFFER_SIZE => 4 + ) + port map( + CLK => CLK, + RESET => RESET, + MY_MAC_IN => x"001122334455", + MY_IP_IN => x"00112233", + PS_DATA_IN => (others => '0'), + PS_WR_EN_IN => '0', + PS_ACTIVATE_IN => '0', + PS_RESPONSE_READY_OUT => open, + PS_BUSY_OUT => open, + PS_SELECTED_IN => '0', + PS_SRC_MAC_ADDRESS_IN => (others => '0'), + PS_DEST_MAC_ADDRESS_IN => (others => '0'), + PS_SRC_IP_ADDRESS_IN => (others => '0'), + PS_DEST_IP_ADDRESS_IN => (others => '0'), + PS_SRC_UDP_PORT_IN => (others => '0'), + PS_DEST_UDP_PORT_IN => (others => '0'), + TC_RD_EN_IN => '0', + TC_DATA_OUT => open, + TC_FRAME_SIZE_OUT => open, + TC_FRAME_TYPE_OUT => open, + TC_IP_PROTOCOL_OUT => open, + TC_DEST_MAC_OUT => open, + TC_DEST_IP_OUT => open, + TC_DEST_UDP_OUT => open, + TC_SRC_MAC_OUT => open, + TC_SRC_IP_OUT => open, + TC_SRC_UDP_OUT => open, + TC_IDENT_OUT => open, + STAT_DATA_OUT => open, + STAT_ADDR_OUT => open, + STAT_DATA_RDY_OUT => open, + STAT_DATA_ACK_IN => '0', + DEBUG_OUT => open, + CTS_NUMBER_IN => MLT_CTS_NUMBER_OUT, + CTS_CODE_IN => MLT_CTS_CODE_OUT, + CTS_INFORMATION_IN => MLT_CTS_INFORMATION_OUT, + CTS_READOUT_TYPE_IN => MLT_CTS_READOUT_TYPE_OUT, + CTS_START_READOUT_IN => MLT_CTS_START_READOUT_OUT(0), + CTS_DATA_OUT => MLT_CTS_DATA_IN, + CTS_DATAREADY_OUT => MLT_CTS_DATAREADY_IN(0), + CTS_READOUT_FINISHED_OUT => MLT_CTS_READOUT_FINISHED_IN(0), + CTS_READ_IN => MLT_CTS_READ_OUT(0), + CTS_LENGTH_OUT => MLT_CTS_LENGTH_IN, + CTS_ERROR_PATTERN_OUT => MLT_CTS_ERROR_PATTERN_IN, + FEE_DATA_IN => MLT_FEE_DATA_OUT, + FEE_DATAREADY_IN => MLT_FEE_DATAREADY_OUT(0), + FEE_READ_OUT => MLT_FEE_READ_IN(0), + FEE_STATUS_BITS_IN => MLT_FEE_STATUS_BITS_OUT, + FEE_BUSY_IN => MLT_FEE_BUSY_OUT(0), + SLV_ADDR_IN => (others => '0'), + SLV_READ_IN => '0', + SLV_WRITE_IN => '0', + SLV_BUSY_OUT => open, + SLV_ACK_OUT => open, + SLV_DATA_IN => (others =>'0'), + SLV_DATA_OUT => open, + CFG_GBE_ENABLE_IN => '1', + CFG_IPU_ENABLE_IN => '1', + CFG_MULT_ENABLE_IN => '0', + CFG_SUBEVENT_ID_IN => (others => '0'), + CFG_SUBEVENT_DEC_IN => (others => '0'), + CFG_QUEUE_DEC_IN => (others => '0'), + CFG_READOUT_CTR_IN => (others => '0'), + CFG_READOUT_CTR_VALID_IN => '0', + CFG_INSERT_TTYPE_IN => '0', + CFG_MAX_SUB_IN => x"fff0", + CFG_MAX_QUEUE_IN => x"fff0", + CFG_MAX_SUBS_IN_QUEUE_IN => x"fff0", + CFG_MAX_SINGLE_SUB_IN => x"fff0", + MONITOR_SELECT_REC_OUT => open, + MONITOR_SELECT_REC_BYTES_OUT => open, + MONITOR_SELECT_SENT_BYTES_OUT => open, + MONITOR_SELECT_SENT_OUT => open, + MONITOR_SELECT_DROP_IN_OUT => open, + MONITOR_SELECT_DROP_OUT_OUT => open, + DATA_HIST_OUT => open + ); + +-- 100 MHz system clock +CLOCK_GEN_PROC: process +begin + CLK <= '1'; wait for 5.0 ns; + CLK <= '0'; wait for 5.0 ns; +end process CLOCK_GEN_PROC; + + +testbench_proc : process +begin + reset <= '1'; + + trigger <= '0'; + gbe_ready <= '1'; + + --FEE_READ_OUT <= '1'; + + wait for 100 ns; + reset <= '0'; + + wait for 1 us; + + trigger <= '1'; + wait for 100 ns; + trigger <= '0'; + + + wait for 500 ns; + wait until rising_edge(CLK); + --FEE_READ_OUT <= '0'; + wait until rising_edge(CLK); + --FEE_READ_OUT <= '1'; + + wait; + +end process testbench_proc; + +end; \ No newline at end of file diff --git a/gbe_trb/testbenches/aa_wrapper_tb.vhd b/gbe_trb/testbenches/aa_wrapper_tb.vhd new file mode 100644 index 0000000..67ce29e --- /dev/null +++ b/gbe_trb/testbenches/aa_wrapper_tb.vhd @@ -0,0 +1,1339 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE ieee.math_real.all; +USE ieee.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +ENTITY aa_wrapper_tb IS + generic(NUMBER_OF_OUTPUT_LINKS : integer range 0 to 4 := 2); +END aa_wrapper_tb; + +ARCHITECTURE behavior OF aa_wrapper_tb IS + + component gbe_ipu_dummy is + generic (DO_SIMULATION : integer range 0 to 1 := 0); + port ( + clk : in std_logic; + rst : in std_logic; + GBE_READY_IN : in std_logic; + + CFG_EVENT_SIZE_IN : in std_logic_vector(15 downto 0); + CFG_TRIGGERED_MODE_IN : in std_logic; + TRIGGER_IN : in std_logic; + + CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); + CTS_CODE_OUT : out std_logic_vector (7 downto 0); + CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + CTS_START_READOUT_OUT : out std_logic; + CTS_DATA_IN : in std_logic_vector (31 downto 0); + CTS_DATAREADY_IN : in std_logic; + CTS_READOUT_FINISHED_IN : in std_logic; + CTS_READ_OUT : out std_logic; + CTS_LENGTH_IN : in std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_OUT : out std_logic_vector (15 downto 0); + FEE_DATAREADY_OUT : out std_logic; + FEE_READ_IN : in std_logic; + FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + FEE_BUSY_OUT : out std_logic + ); +end component; + +signal clk, reset,RX_MAC_CLK : std_logic; + +SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); +SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); +SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); +SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); +SIGNAL CTS_START_READOUT_IN : std_logic; +SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); +SIGNAL CTS_DATAREADY_OUT : std_logic; +SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; +SIGNAL CTS_READ_IN : std_logic; +SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); +SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); +SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); +SIGNAL FEE_DATAREADY_IN : std_logic; +SIGNAL FEE_READ_OUT : std_logic; +SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0) := x"0000_0000"; +SIGNAL FEE_BUSY_IN : std_logic; + + +signal mac_tx_done, mac_fifoeof : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal gsr : std_logic; + +signal MAC_RX_EOF_IN, MAC_RX_EN_IN : std_logic; +signal MAC_RXD_IN : std_logic_vector(7 downto 0); +signal mac_read : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mac_fifoavail : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal master_mac : std_logic_vector(47 downto 0); + +signal mlt_cts_number : std_logic_vector (16 * NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_code : std_logic_vector (8 * NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_information : std_logic_vector (8 * NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_readout_type : std_logic_vector (4 * NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_start_readout : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_data : std_logic_vector (32 * NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_dataready : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_readout_finished : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_read : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_length : std_logic_vector (16 * NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_cts_error_pattern : std_logic_vector (32 * NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_fee_data : std_logic_vector (16 * NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_fee_dataready : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_fee_read : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_fee_status : std_logic_vector (32 * NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal mlt_fee_busy : std_logic_vector(NUMBER_OF_OUTPUT_LINKS - 1 downto 0); +signal gbe_ready : std_logic; +signal trigger : std_logic; + +begin + + gsr <= not reset; + + + gbe_inst1 : entity work.gbe_logic_wrapper + generic map( + DO_SIMULATION => 1, + INCLUDE_DEBUG => 1, + USE_INTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + + INCLUDE_READOUT => '1', + INCLUDE_SLOWCTRL => '1', + INCLUDE_DHCP => '1', + INCLUDE_ARP => '1', + INCLUDE_PING => '1', + + FRAME_BUFFER_SIZE => 1, + READOUT_BUFFER_SIZE => 2, + SLOWCTRL_BUFFER_SIZE => 2, + + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 1, + UP_DOWN_LIMIT => 200, + FIXED_DELAY => 1 + ) + port map( + CLK_SYS_IN => clk, + CLK_125_IN => RX_MAC_CLK, + CLK_RX_125_IN => RX_MAC_CLK, + RESET => RESET, + GSR_N => gsr, + + MY_MAC_OUT => master_mac, + MY_MAC_IN => x"ffffffffffff", + + MAC_READY_CONF_IN => '1', + MAC_RECONF_OUT => open, + MAC_AN_READY_IN => '1', + MAC_FIFOAVAIL_OUT => mac_fifoavail(0), + MAC_FIFOEOF_OUT => mac_fifoeof(0), + MAC_FIFOEMPTY_OUT => open, + MAC_RX_FIFOFULL_OUT => open, + MAC_TX_DATA_OUT => open, + MAC_TX_READ_IN => mac_read(0), + MAC_TX_DISCRFRM_IN => '0', + MAC_TX_STAT_EN_IN => '0', + MAC_TX_STATS_IN => (others => '0'), + MAC_TX_DONE_IN => mac_tx_done(0), + MAC_RX_FIFO_ERR_IN => '0', + MAC_RX_STATS_IN => (others => '0'), + MAC_RX_DATA_IN => MAC_RXD_IN, + MAC_RX_WRITE_IN => MAC_RX_EN_IN, + MAC_RX_STAT_EN_IN => '0', + MAC_RX_EOF_IN => MAC_RX_EOF_IN, + MAC_RX_ERROR_IN => '0', + + CTS_NUMBER_IN => mlt_cts_number(1 * 16 - 1 downto 0 * 16), + CTS_CODE_IN => mlt_cts_code(1 * 8 - 1 downto 0 * 8), + CTS_INFORMATION_IN => mlt_cts_information(1 * 8 - 1 downto 0 * 8), + CTS_READOUT_TYPE_IN => mlt_cts_readout_type(1 * 4 - 1 downto 0 * 4), + CTS_START_READOUT_IN => mlt_cts_start_readout(0), + CTS_DATA_OUT => mlt_cts_data(1 * 32 - 1 downto 0 * 32), + CTS_DATAREADY_OUT => mlt_cts_dataready(0), + CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0), + CTS_READ_IN => mlt_cts_read(0), + CTS_LENGTH_OUT => mlt_cts_length(1 * 16 - 1 downto 0 * 16), + CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(1 * 32 - 1 downto 0 * 32), + FEE_DATA_IN => mlt_fee_data(1 * 16 - 1 downto 0 * 16), + FEE_DATAREADY_IN => mlt_fee_dataready(0), + FEE_READ_OUT => mlt_fee_read(0), + FEE_STATUS_BITS_IN => mlt_fee_status(1 * 32 - 1 downto 0 * 32), + FEE_BUSY_IN => mlt_fee_busy(0), + + MC_UNIQUE_ID_IN => (others => '0'), + + GSC_CLK_IN => clk, + GSC_INIT_DATAREADY_OUT => open, --GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => open, --GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => open, --GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => '0', --GSC_INIT_READ_IN, + GSC_REPLY_DATAREADY_IN => '0', --GSC_REPLY_DATAREADY_IN, + GSC_REPLY_DATA_IN => (others => '0'), --GSC_REPLY_DATA_IN, + GSC_REPLY_PACKET_NUM_IN => (others => '0'), --GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => open, --GSC_REPLY_READ_OUT, + GSC_BUSY_IN => '0', --GSC_BUSY_IN, + + SLV_ADDR_IN => (others => '0'), --SLV_ADDR_IN, + SLV_READ_IN => '0', --SLV_READ_IN, + SLV_WRITE_IN => '0', --SLV_WRITE_IN, + SLV_BUSY_OUT => open, --SLV_BUSY_OUT, + SLV_ACK_OUT => open, --SLV_ACK_OUT, + SLV_DATA_IN => (others => '0'), --SLV_DATA_IN, + SLV_DATA_OUT => open, --SLV_DATA_OUT, + + CFG_GBE_ENABLE_IN => '1', + CFG_IPU_ENABLE_IN => '0', + CFG_MULT_ENABLE_IN => '0', + CFG_MAX_FRAME_IN => x"0578", + CFG_ALLOW_RX_IN => '1', + CFG_SOFT_RESET_IN => '0', + CFG_SUBEVENT_ID_IN => (others => '0'), + CFG_SUBEVENT_DEC_IN => (others => '0'), + CFG_QUEUE_DEC_IN => (others => '0'), + CFG_READOUT_CTR_IN => (others => '0'), + CFG_READOUT_CTR_VALID_IN => '0', + CFG_INSERT_TTYPE_IN => '0', + CFG_MAX_SUB_IN => x"0578", + CFG_MAX_QUEUE_IN => x"1000", + CFG_MAX_SUBS_IN_QUEUE_IN => x"0002", + CFG_MAX_SINGLE_SUB_IN => x"0578", + CFG_ADDITIONAL_HDR_IN => '0', + CFG_MAX_REPLY_SIZE_IN => x"0000_fa00", + + MAKE_RESET_OUT => open + ); + + gbe_inst2 : entity work.gbe_logic_wrapper + generic map( + DO_SIMULATION => 1, + INCLUDE_DEBUG => 1, + USE_INTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + + INCLUDE_READOUT => '1', + INCLUDE_SLOWCTRL => '0', + INCLUDE_DHCP => '0', + INCLUDE_ARP => '0', + INCLUDE_PING => '0', + + FRAME_BUFFER_SIZE => 1, + READOUT_BUFFER_SIZE => 2, + SLOWCTRL_BUFFER_SIZE => 2, + + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 1, + UP_DOWN_LIMIT => 200, + FIXED_DELAY => 1 + ) + port map( + CLK_SYS_IN => clk, + CLK_125_IN => RX_MAC_CLK, + CLK_RX_125_IN => RX_MAC_CLK, + RESET => RESET, + GSR_N => gsr, + + MY_MAC_OUT => open, + MY_MAC_IN => x"ffffffffffff", + + MAC_READY_CONF_IN => '1', + MAC_RECONF_OUT => open, + MAC_AN_READY_IN => '1', + MAC_FIFOAVAIL_OUT => mac_fifoavail(1), + MAC_FIFOEOF_OUT => mac_fifoeof(1), + MAC_FIFOEMPTY_OUT => open, + MAC_RX_FIFOFULL_OUT => open, + MAC_TX_DATA_OUT => open, + MAC_TX_READ_IN => mac_read(1), + MAC_TX_DISCRFRM_IN => '0', + MAC_TX_STAT_EN_IN => '0', + MAC_TX_STATS_IN => (others => '0'), + MAC_TX_DONE_IN => mac_tx_done(1), + MAC_RX_FIFO_ERR_IN => '0', + MAC_RX_STATS_IN => (others => '0'), + MAC_RX_DATA_IN => MAC_RXD_IN, + MAC_RX_WRITE_IN => MAC_RX_EN_IN, + MAC_RX_STAT_EN_IN => '0', + MAC_RX_EOF_IN => MAC_RX_EOF_IN, + MAC_RX_ERROR_IN => '0', + + CTS_NUMBER_IN => mlt_cts_number(2 * 16 - 1 downto 1 * 16), + CTS_CODE_IN => mlt_cts_code(2 * 8 - 1 downto 1 * 8), + CTS_INFORMATION_IN => mlt_cts_information(2 * 8 - 1 downto 1 * 8), + CTS_READOUT_TYPE_IN => mlt_cts_readout_type(2 * 4 - 1 downto 1 * 4), + CTS_START_READOUT_IN => mlt_cts_start_readout(1), + CTS_DATA_OUT => mlt_cts_data(2 * 32 - 1 downto 1 * 32), + CTS_DATAREADY_OUT => mlt_cts_dataready(1), + CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(1), + CTS_READ_IN => mlt_cts_read(1), + CTS_LENGTH_OUT => mlt_cts_length(2 * 16 - 1 downto 1 * 16), + CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(2 * 32 - 1 downto 1 * 32), + FEE_DATA_IN => mlt_fee_data(2 * 16 - 1 downto 1 * 16), + FEE_DATAREADY_IN => mlt_fee_dataready(1), + FEE_READ_OUT => mlt_fee_read(1), + FEE_STATUS_BITS_IN => mlt_fee_status(2 * 32 - 1 downto 1 * 32), + FEE_BUSY_IN => mlt_fee_busy(1), + + MC_UNIQUE_ID_IN => (others => '0'), + + GSC_CLK_IN => clk, + GSC_INIT_DATAREADY_OUT => open, --GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => open, --GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => open, --GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => '0', --GSC_INIT_READ_IN, + GSC_REPLY_DATAREADY_IN => '0', --GSC_REPLY_DATAREADY_IN, + GSC_REPLY_DATA_IN => (others => '0'), --GSC_REPLY_DATA_IN, + GSC_REPLY_PACKET_NUM_IN => (others => '0'), --GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => open, --GSC_REPLY_READ_OUT, + GSC_BUSY_IN => '0', --GSC_BUSY_IN, + + SLV_ADDR_IN => (others => '0'), --SLV_ADDR_IN, + SLV_READ_IN => '0', --SLV_READ_IN, + SLV_WRITE_IN => '0', --SLV_WRITE_IN, + SLV_BUSY_OUT => open, --SLV_BUSY_OUT, + SLV_ACK_OUT => open, --SLV_ACK_OUT, + SLV_DATA_IN => (others => '0'), --SLV_DATA_IN, + SLV_DATA_OUT => open, --SLV_DATA_OUT, + + CFG_GBE_ENABLE_IN => '1', + CFG_IPU_ENABLE_IN => '0', + CFG_MULT_ENABLE_IN => '0', + CFG_MAX_FRAME_IN => x"0578", + CFG_ALLOW_RX_IN => '1', + CFG_SOFT_RESET_IN => '0', + CFG_SUBEVENT_ID_IN => (others => '0'), + CFG_SUBEVENT_DEC_IN => (others => '0'), + CFG_QUEUE_DEC_IN => (others => '0'), + CFG_READOUT_CTR_IN => (others => '0'), + CFG_READOUT_CTR_VALID_IN => '0', + CFG_INSERT_TTYPE_IN => '0', + CFG_MAX_SUB_IN => x"0578", + CFG_MAX_QUEUE_IN => x"1000", + CFG_MAX_SUBS_IN_QUEUE_IN => x"0002", + CFG_MAX_SINGLE_SUB_IN => x"0578", + CFG_ADDITIONAL_HDR_IN => '0', + CFG_MAX_REPLY_SIZE_IN => x"0000_fa00", + + MAKE_RESET_OUT => open + ); +-- +-- gbe_inst3 : entity work.gbe_logic_wrapper +-- generic map( +-- DO_SIMULATION => 1, +-- INCLUDE_DEBUG => 1, +-- USE_INTERNAL_TRBNET_DUMMY => 0, +-- RX_PATH_ENABLE => 1, +-- +-- INCLUDE_READOUT => '1', +-- INCLUDE_SLOWCTRL => '0', +-- INCLUDE_DHCP => '1', +-- INCLUDE_ARP => '1', +-- INCLUDE_PING => '1', +-- +-- FRAME_BUFFER_SIZE => 1, +-- READOUT_BUFFER_SIZE => 2, +-- SLOWCTRL_BUFFER_SIZE => 2, +-- +-- FIXED_SIZE_MODE => 1, +-- INCREMENTAL_MODE => 1, +-- FIXED_SIZE => 100, +-- FIXED_DELAY_MODE => 1, +-- UP_DOWN_MODE => 1, +-- UP_DOWN_LIMIT => 200, +-- FIXED_DELAY => 1 +-- ) +-- port map( +-- CLK_SYS_IN => clk, +-- CLK_125_IN => RX_MAC_CLK, +-- CLK_RX_125_IN => RX_MAC_CLK, +-- RESET => RESET, +-- GSR_N => gsr, +-- +-- MY_MAC_OUT => open, +-- MY_MAC_IN => x"ffffffffffff", +-- +-- MAC_READY_CONF_IN => '1', +-- MAC_RECONF_OUT => open, +-- MAC_AN_READY_IN => '1', +-- MAC_FIFOAVAIL_OUT => mac_fifoavail(2), +-- MAC_FIFOEOF_OUT => mac_fifoeof(2), +-- MAC_FIFOEMPTY_OUT => open, +-- MAC_RX_FIFOFULL_OUT => open, +-- MAC_TX_DATA_OUT => open, +-- MAC_TX_READ_IN => mac_read(2), +-- MAC_TX_DISCRFRM_IN => '0', +-- MAC_TX_STAT_EN_IN => '0', +-- MAC_TX_STATS_IN => (others => '0'), +-- MAC_TX_DONE_IN => mac_tx_done(2), +-- MAC_RX_FIFO_ERR_IN => '0', +-- MAC_RX_STATS_IN => (others => '0'), +-- MAC_RX_DATA_IN => MAC_RXD_IN, +-- MAC_RX_WRITE_IN => MAC_RX_EN_IN, +-- MAC_RX_STAT_EN_IN => '0', +-- MAC_RX_EOF_IN => MAC_RX_EOF_IN, +-- MAC_RX_ERROR_IN => '0', +-- +-- CTS_NUMBER_IN => mlt_cts_number(3 * 16 - 1 downto 2 * 16), +-- CTS_CODE_IN => mlt_cts_code(3 * 8 - 1 downto 2 * 8), +-- CTS_INFORMATION_IN => mlt_cts_information(3 * 8 - 1 downto 2 * 8), +-- CTS_READOUT_TYPE_IN => mlt_cts_readout_type(3 * 4 - 1 downto 2 * 4), +-- CTS_START_READOUT_IN => mlt_cts_start_readout(2), +-- CTS_DATA_OUT => mlt_cts_data(3 * 32 - 1 downto 2 * 32), +-- CTS_DATAREADY_OUT => mlt_cts_dataready(2), +-- CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(2), +-- CTS_READ_IN => mlt_cts_read(2), +-- CTS_LENGTH_OUT => mlt_cts_length(3 * 16 - 1 downto 2 * 16), +-- CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(3 * 32 - 1 downto 2 * 32), +-- FEE_DATA_IN => mlt_fee_data(3 * 16 - 1 downto 2 * 16), +-- FEE_DATAREADY_IN => mlt_fee_dataready(2), +-- FEE_READ_OUT => mlt_fee_read(2), +-- FEE_STATUS_BITS_IN => mlt_fee_status(3 * 32 - 1 downto 2 * 32), +-- FEE_BUSY_IN => mlt_fee_busy(2), +-- +-- MC_UNIQUE_ID_IN => (others => '0'), +-- +-- GSC_CLK_IN => clk, +-- GSC_INIT_DATAREADY_OUT => open, --GSC_INIT_DATAREADY_OUT, +-- GSC_INIT_DATA_OUT => open, --GSC_INIT_DATA_OUT, +-- GSC_INIT_PACKET_NUM_OUT => open, --GSC_INIT_PACKET_NUM_OUT, +-- GSC_INIT_READ_IN => '0', --GSC_INIT_READ_IN, +-- GSC_REPLY_DATAREADY_IN => '0', --GSC_REPLY_DATAREADY_IN, +-- GSC_REPLY_DATA_IN => (others => '0'), --GSC_REPLY_DATA_IN, +-- GSC_REPLY_PACKET_NUM_IN => (others => '0'), --GSC_REPLY_PACKET_NUM_IN, +-- GSC_REPLY_READ_OUT => open, --GSC_REPLY_READ_OUT, +-- GSC_BUSY_IN => '0', --GSC_BUSY_IN, +-- +-- SLV_ADDR_IN => (others => '0'), --SLV_ADDR_IN, +-- SLV_READ_IN => '0', --SLV_READ_IN, +-- SLV_WRITE_IN => '0', --SLV_WRITE_IN, +-- SLV_BUSY_OUT => open, --SLV_BUSY_OUT, +-- SLV_ACK_OUT => open, --SLV_ACK_OUT, +-- SLV_DATA_IN => (others => '0'), --SLV_DATA_IN, +-- SLV_DATA_OUT => open, --SLV_DATA_OUT, +-- +-- CFG_GBE_ENABLE_IN => '1', +-- CFG_IPU_ENABLE_IN => '0', +-- CFG_MULT_ENABLE_IN => '0', +-- CFG_MAX_FRAME_IN => x"0578", +-- CFG_ALLOW_RX_IN => '1', +-- CFG_SOFT_RESET_IN => '0', +-- CFG_SUBEVENT_ID_IN => (others => '0'), +-- CFG_SUBEVENT_DEC_IN => (others => '0'), +-- CFG_QUEUE_DEC_IN => (others => '0'), +-- CFG_READOUT_CTR_IN => (others => '0'), +-- CFG_READOUT_CTR_VALID_IN => '0', +-- CFG_INSERT_TTYPE_IN => '0', +-- CFG_MAX_SUB_IN => x"0578", +-- CFG_MAX_QUEUE_IN => x"1000", +-- CFG_MAX_SUBS_IN_QUEUE_IN => x"0002", +-- CFG_MAX_SINGLE_SUB_IN => x"0578", +-- CFG_ADDITIONAL_HDR_IN => '0', +-- CFG_MAX_REPLY_SIZE_IN => x"0000_fa00", +-- +-- MAKE_RESET_OUT => open +-- ); + + ipu_mult : entity work.gbe_ipu_multiplexer + generic map( + DO_SIMULATION => 1, + INCLUDE_DEBUG => 1, + NUMBER_OF_OUTPUT_LINKS => 2 + ) + port map( + CLK_SYS_IN => CLK, + RESET => RESET, + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + + MLT_CTS_NUMBER_OUT => mlt_cts_number, + MLT_CTS_CODE_OUT => mlt_cts_code, + MLT_CTS_INFORMATION_OUT => mlt_cts_information, + MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type, + MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout, + MLT_CTS_DATA_IN => mlt_cts_data, + MLT_CTS_DATAREADY_IN => mlt_cts_dataready, + MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished, + MLT_CTS_READ_OUT => mlt_cts_read, + MLT_CTS_LENGTH_IN => mlt_cts_length, + MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern, + MLT_FEE_DATA_OUT => mlt_fee_data, + MLT_FEE_DATAREADY_OUT => mlt_fee_dataready, + MLT_FEE_READ_IN => mlt_fee_read, + MLT_FEE_STATUS_BITS_OUT => mlt_fee_status, + MLT_FEE_BUSY_OUT => mlt_fee_busy, + + DEBUG_OUT => open + ); + + dummy_inst : entity work.gbe_ipu_dummy + generic map(DO_SIMULATION => 1, + FIXED_SIZE_MODE => 1, + FIXED_SIZE => 100, + INCREMENTAL_MODE => 0, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY_MODE => 1, + FIXED_DELAY => 50) + port map(clk => CLK, + rst => RESET, + GBE_READY_IN => gbe_ready, + + CFG_EVENT_SIZE_IN => x"0100", + CFG_TRIGGERED_MODE_IN => '1', + TRIGGER_IN => trigger, + + CTS_NUMBER_OUT => CTS_NUMBER_IN, + CTS_CODE_OUT => CTS_CODE_IN, + CTS_INFORMATION_OUT => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_OUT => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_OUT => CTS_START_READOUT_IN, + CTS_DATA_IN => CTS_DATA_OUT, + CTS_DATAREADY_IN => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_IN => CTS_READOUT_FINISHED_OUT, + CTS_READ_OUT => CTS_READ_IN, + CTS_LENGTH_IN => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_IN => CTS_ERROR_PATTERN_OUT, + FEE_DATA_OUT => FEE_DATA_IN, + FEE_DATAREADY_OUT => FEE_DATAREADY_IN, + FEE_READ_IN => FEE_READ_OUT, + FEE_STATUS_BITS_OUT => FEE_STATUS_BITS_IN, + FEE_BUSY_OUT => FEE_BUSY_IN + ); + +-- 125 MHz MAC clock +CLOCK2_GEN_PROC: process +begin + RX_MAC_CLK <= '1'; wait for 3.0 ns; + RX_MAC_CLK <= '0'; wait for 4.0 ns; +end process CLOCK2_GEN_PROC; + +-- 100 MHz system clock +CLOCK_GEN_PROC: process +begin + CLK <= '1'; wait for 5.0 ns; + CLK <= '0'; wait for 5.0 ns; +end process CLOCK_GEN_PROC; + + +process +begin + mac_tx_done(0) <= '0'; + wait until rising_edge(mac_fifoeof(0)); + wait until rising_edge(rx_mac_clk); + mac_tx_done(0) <= '1'; + wait until rising_edge(rx_mac_clk); +end process; + +process +begin + mac_tx_done(1) <= '0'; + wait until rising_edge(mac_fifoeof(1)); + wait until rising_edge(rx_mac_clk); + mac_tx_done(1) <= '1'; + wait until rising_edge(rx_mac_clk); +end process; + +-- process +-- begin +-- mac_tx_done(1) <= '0'; +-- wait until rising_edge(mac_fifoeof(2)); +-- wait until rising_edge(rx_mac_clk); +-- mac_tx_done(1) <= '1'; +-- wait until rising_edge(rx_mac_clk); +-- end process; + +process(rx_mac_clk) +begin + if rising_edge(rx_mac_clk) then + mac_read(0) <= mac_fifoavail(0); + mac_read(1) <= mac_fifoavail(1); + --mac_read(2) <= mac_fifoavail(2); + end if; +end process; + + +testbench_proc : process +begin + reset <= '1'; + + trigger <= '0'; + gbe_ready <= '0'; + MAC_RX_EN_IN <= '0'; + MAC_RXD_IN <= x"00"; + MAC_RX_EOF_IN <= '0'; + + wait for 100 ns; + reset <= '0'; + + wait for 5 us; + +-- FIRST FRAME UDP - DHCP Offer + wait until rising_edge(RX_MAC_CLK); + MAC_RX_EN_IN <= '1'; +-- dest mac + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); +-- src mac + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"aa"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"bb"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"cc"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"dd"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ee"; + wait until rising_edge(RX_MAC_CLK); +-- frame type + MAC_RXD_IN <= x"08"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); +-- ip headers + MAC_RXD_IN <= x"45"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"10"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"01"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"5a"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"49"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"11"; -- udp + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"cc"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"cc"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"c0"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"a8"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"01"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"c0"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"a8"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"02"; +-- udp headers + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"43"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"44"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"02"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"2c"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"aa"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"bb"; +-- dhcp data + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"02"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"01"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"06"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; --transcation id + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff";--transcation id + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"fa";--transcation id + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ce";--transcation id + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"c0"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"a8"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"10"; + + for i in 0 to 219 loop + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + end loop; + + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"35"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"01"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"02"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RX_EOF_IN <= '1'; + + wait until rising_edge(RX_MAC_CLK); + MAC_RX_EN_IN <='0'; + MAC_RX_EOF_IN <= '0'; + + wait for 6 us; + + wait until rising_edge(RX_MAC_CLK); + MAC_RX_EN_IN <= '1'; +-- dest mac + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); +-- src mac + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"aa"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"bb"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"cc"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"dd"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ee"; + wait until rising_edge(RX_MAC_CLK); +-- frame type + MAC_RXD_IN <= x"08"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); +-- ip headers + MAC_RXD_IN <= x"45"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"10"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"01"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"5a"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"49"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"11"; -- udp + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"cc"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"cc"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"c0"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"a8"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"01"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"c0"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"a8"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"02"; +-- udp headers + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"43"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"44"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"02"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"2c"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"aa"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"bb"; +-- dhcp data + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"02"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"01"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"06"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ff"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"fa"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"ce"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"c0"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"a8"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"10"; + + for i in 0 to 219 loop + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + end loop; + + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"35"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"01"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"05"; + wait until rising_edge(RX_MAC_CLK); + MAC_RXD_IN <= x"00"; + wait until rising_edge(RX_MAC_CLK); + MAC_RX_EOF_IN <= '1'; + + wait until rising_edge(RX_MAC_CLK); + MAC_RX_EN_IN <='0'; + MAC_RX_EOF_IN <= '0'; + + + wait for 5 us; + + + + +-- +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RX_EN_IN <= '1'; +---- dest mac +-- MAC_RXD_IN <= x"02"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"be"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +---- src mac +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"aa"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"bb"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"cc"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"dd"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"ee"; +-- wait until rising_edge(RX_MAC_CLK); +---- frame type +-- MAC_RXD_IN <= x"08"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +---- ip headers +-- MAC_RXD_IN <= x"45"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"10"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"5a"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"49"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"ff"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"cc"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"cc"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"c0"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"a8"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"c0"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"a8"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"02"; +---- ping headers +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"08"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"47"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"d3"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"3c"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +---- ping data +-- MAC_RXD_IN <= x"8c"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"da"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"e7"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"4d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"36"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"c4"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"08"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"09"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0a"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0b"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0c"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0e"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0f"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RX_EOF_IN <= '1'; +-- MAC_RXD_IN <= x"aa"; +-- +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RX_EN_IN <='0'; +-- MAC_RX_EOF_IN <= '0'; +-- +-- +-- wait for 15 us; +-- +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RX_EN_IN <= '1'; +---- dest mac +-- MAC_RXD_IN <= x"02"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"be"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +---- src mac +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"aa"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"bb"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"cc"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"dd"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"ee"; +-- wait until rising_edge(RX_MAC_CLK); +---- frame type +-- MAC_RXD_IN <= x"08"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +---- ip headers +-- MAC_RXD_IN <= x"45"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"10"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"5a"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"49"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"ff"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"cc"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"cc"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"c0"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"a8"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"c0"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"a8"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"02"; +---- ping headers +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"08"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"47"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"d3"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"3c"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +---- ping data +-- MAC_RXD_IN <= x"8c"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"da"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"e7"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"4d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"36"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"c4"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"08"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"09"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0a"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0b"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0c"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0e"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0f"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RX_EOF_IN <= '1'; +-- MAC_RXD_IN <= x"aa"; +-- +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RX_EN_IN <='0'; +-- MAC_RX_EOF_IN <= '0'; + + wait for 2 us; + + gbe_ready <= '1'; + + wait for 1 us; + + trigger <= '1'; + +-- for i in 0 to 100000 loop +-- wait until rising_edge(CLK); +-- trigger <= '1'; +-- wait until rising_edge(CLK); +-- wait until rising_edge(CLK); +-- trigger <= '0'; +-- +-- --wait for 17 us; +-- end loop; + + +-- for i in 0 to 100 loop +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RX_EN_IN <= '1'; +-- -- dest mac +-- MAC_RXD_IN <= x"02"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"be"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- -- src mac +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"aa"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"bb"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"cc"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"dd"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"ee"; +-- wait until rising_edge(RX_MAC_CLK); +-- -- frame type +-- MAC_RXD_IN <= x"08"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- -- ip headers +-- MAC_RXD_IN <= x"45"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"10"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"5a"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"49"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"ff"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"cc"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"cc"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"c0"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"a8"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"c0"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"a8"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"02"; +-- -- ping headers +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"08"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"47"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"d3"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"3c"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"01"; +-- wait until rising_edge(RX_MAC_CLK); +-- -- ping data +-- MAC_RXD_IN <= x"8c"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"da"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"e7"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"4d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"36"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"c4"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"00"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"08"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"09"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0a"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0b"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0c"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0d"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0e"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RXD_IN <= x"0f"; +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RX_EOF_IN <= '1'; +-- MAC_RXD_IN <= x"aa"; +-- +-- wait until rising_edge(RX_MAC_CLK); +-- MAC_RX_EN_IN <='0'; +-- MAC_RX_EOF_IN <= '0'; +-- +-- wait for 50 us; +-- +-- end loop; + + wait; + +end process testbench_proc; + +end; \ No newline at end of file