From: hadaq Date: Thu, 28 May 2009 11:26:46 +0000 (+0000) Subject: attilio:only calibration enabled, all channels are calibrated X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=fe646b531330ebab622b797e6d401f79acca4a5a;p=mdcoep.git attilio:only calibration enabled, all channels are calibrated --- diff --git a/compile_gsi.pl b/compile_gsi.pl index a6c322f..a993f77 100755 --- a/compile_gsi.pl +++ b/compile_gsi.pl @@ -32,8 +32,8 @@ my $PACKAGE="FPBGA256"; my $SPEEDGRADE="5"; #create full lpf file -system("cp ../trbnet/pinout/mdc_oep3.lpf workdir/mdc_oepb.lpf"); -system("cat constraints.lpf >> workdir/mdc_oepb.lpf"); +#system("cp ../trbnet/pinout/mdc_oep3.lpf workdir/mdc_oepb.lpf"); +#system("cat constraints.lpf >> workdir/mdc_oepb.lpf"); #generate timestamp my $t=time; diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index cb8674f..28c4cf9 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -121,13 +121,14 @@ architecture mdc_oepb_arch of mdc_oepb is signal reg_REGIO_ADDR : std_logic_vector(15 downto 0); signal reg_REGIO_READ : std_logic; signal last_reg_REGIO_READ : std_logic; + signal very_last_reg_REGIO_READ : std_logic; signal reg_REGIO_WRITE : std_logic; - signal thresh_mem_data : std_logic_vector(7 downto 0); - signal thresh_mem_data_out : std_logic_vector(7 downto 0); + signal thresh_mem_data : std_logic_vector(15 downto 0); + signal thresh_mem_data_out : std_logic_vector(15 downto 0); signal thresh_mem_write: std_logic; signal thresh_mem_read : std_logic; - signal thresh_mem_addr : std_logic_vector(6 downto 0); + signal thresh_mem_addr : std_logic_vector(8 downto 0); signal token_to_mux_out_i : std_logic; signal init_all_buses_i : std_logic_vector(3 downto 0); @@ -142,7 +143,9 @@ architecture mdc_oepb_arch of mdc_oepb is signal debug_trigger_distributor_i : std_logic_vector(31 downto 0); signal last_LVL1_TRG_RECEIVED_OUT : std_logic; signal pseudo_timing_trigger : std_logic; - + signal cal_trigger_register_in_i : std_logic_vector(15 downto 0); + signal direction_data_line_in_i : std_logic_vector(3 downto 0); + begin --------------------------------------------------------------------- -- PLL: 100 MHz @@ -154,8 +157,6 @@ begin LOCK => pll_locked ); - - -- reset <= c_reset or not pll25_lock; --------------------------------------------------------------------- -- Reset process @@ -235,6 +236,7 @@ begin REGIO_COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT, REGIO_REGISTERS_IN => REGIO_REGISTERS_IN, REGIO_REGISTERS_OUT => REGIO_REGISTERS_OUT, + --following ports only used when using internal data port REGIO_ADDR_OUT => REGIO_ADDR_OUT, REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, @@ -327,16 +329,17 @@ begin -- F000 - F00F Test readout addresses (15-0) - THE_REG_DAT_ADDR : process(CLK_100) begin if rising_edge(CLK_100) then - if REGIO_READ_ENABLE_OUT = '1' or REGIO_WRITE_ENABLE_OUT = '1' then + if (REGIO_READ_ENABLE_OUT = '1' or REGIO_WRITE_ENABLE_OUT = '1') then reg_REGIO_ADDR <= REGIO_ADDR_OUT; end if; reg_REGIO_READ <= REGIO_READ_ENABLE_OUT; reg_REGIO_WRITE <= REGIO_WRITE_ENABLE_OUT; + last_reg_REGIO_READ <= reg_REGIO_READ; + very_last_reg_REGIO_READ <= last_reg_REGIO_READ; end if; end process; @@ -349,27 +352,28 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) REGIO_DATAREADY_IN <= '0'; REGIO_DATA_IN <= (others => '0'); REGIO_UNKNOWN_ADDR_IN <= '0'; - +--adc adc_read <= '0'; adc_write <= '0'; adc_data_in <= REGIO_DATA_OUT; adc_addr <= REGIO_ADDR_OUT(5 downto 0); adc_timeout <= REGIO_TIMEOUT_OUT; - thresh_mem_data <= REGIO_DATA_OUT(7 downto 0); - thresh_mem_addr <= REGIO_ADDR_OUT(6 downto 0); +--configuration memory + thresh_mem_data <= REGIO_DATA_OUT(15 downto 0); + thresh_mem_addr <= REGIO_ADDR_OUT(8 downto 0);--(6 downto 0); thresh_mem_write <= '0'; thresh_mem_read <= '0'; - + if reg_REGIO_ADDR(15 downto 7) = x"A0"&'0' then - thresh_mem_write <= reg_REGIO_WRITE; + thresh_mem_write <= REGIO_WRITE_ENABLE_OUT;--reg_REGIO_WRITE; thresh_mem_read <= reg_REGIO_READ; - REGIO_DATA_IN(7 downto 0) <= thresh_mem_data_out; - REGIO_DATA_IN(31 downto 8) <= (others => '0'); + REGIO_DATA_IN(15 downto 0) <= thresh_mem_data_out; + REGIO_DATA_IN(31 downto 16)<= (others => '0'); REGIO_UNKNOWN_ADDR_IN <= '0'; REGIO_NO_MORE_DATA_IN <= '0'; REGIO_WRITE_ACK_IN <= reg_REGIO_WRITE; - REGIO_DATAREADY_IN <= last_reg_REGIO_READ; + REGIO_DATAREADY_IN <= very_last_reg_REGIO_READ; elsif reg_REGIO_ADDR(15 downto 8) = x"80" then REGIO_DATA_IN <= adc_data_out; @@ -389,20 +393,20 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) --------------------------------------------------------------------- -- Threshold memory --------------------------------------------------------------------- - THE_THRESH_MEM : ram_dp - generic map( - depth => 7, - width => 8 - ) - port map( - CLK => CLK_100, - wr1 => thresh_mem_write, - a1 => thresh_mem_addr, - dout1 => thresh_mem_data_out, - din1 => thresh_mem_data, - a2 => (others => '0'), - dout2 => open - ); +-- THE_THRESH_MEM : ram_dp +-- generic map( +-- depth => 7, +-- width => 8 +-- ) +-- port map( +-- CLK => CLK_100, +-- wr1 => thresh_mem_write, +-- a1 => thresh_mem_addr, +-- dout1 => thresh_mem_data_out, +-- din1 => thresh_mem_data, +-- a2 => (others => '0'), +-- dout2 => open +-- ); --------------------------------------------------------------------- -- ADC @@ -476,6 +480,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) if rising_edge(CLK_100) then last_LVL1_TRG_RECEIVED_OUT <= REGIO_REGISTERS_OUT(0); pseudo_timing_trigger <= REGIO_REGISTERS_OUT(0) and not last_LVL1_TRG_RECEIVED_OUT; + cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(7 downto 4); end if; end process; @@ -490,7 +495,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) INIT_ALL_BUSES_OUT => init_all_buses_i, ROC1_WRITTEN_IN => roc1_written_i, TOKEN_TO_TRB_OUT => open,--LVL1_TRG_RELEASE_IN, - CAL_TRIGGER_REGISTER_IN => (others => '0'), + CAL_TRIGGER_REGISTER_IN => cal_trigger_register_in_i, DEBUG_REGISTER_OUT => debug_trigger_distributor_i, LED_CNT_1_OUT => D(4), LED_CNT_2_OUT => D(3), @@ -501,7 +506,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) --------------------------------------------------------------------- -- FEE Readout --------------------------------------------------------------------- - THE_MDC_OEP_READOUT : mdc_addon_daq_bus_0 + THE_MDC_OEP_READOUT : mdc_addon_daq_bus_0 --generic map (bus_number => bus_number) port map ( CLK => CLK_100, @@ -535,7 +540,8 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) D => open, A_RDO_OUT => open, ROC1_WRITTEN_OUT => roc1_written_i, - BUS_NUMBER_IN => x"1", + -- BUS_NUMBER_IN => x"1", + DIRECTION_DATA_LINE_IN => direction_data_line_in_i, BUS_CHAIN_IN => x"1", ACKNOWLEDGE_TRB_INTERFACE_IN => x"1", @@ -544,11 +550,11 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) READ_FIFO_IN => '0', DEBUG_REGISTER_TRB_INTERFACE => (others => '0'), - RAM_ADDRESS_IN => (others => '0'), - RAM_DATA_IN => (others => '0'), - RAM_DATA_OUT => open, + RAM_ADDRESS_IN => thresh_mem_addr,-- (others => '0'), --8 to 0 + RAM_DATA_IN => thresh_mem_data, --15 to 0 + RAM_DATA_OUT => thresh_mem_data_out, RAM_READ_ENABLE_IN => '0', - RAM_WRITE_ENABLE_IN => '0', + RAM_WRITE_ENABLE_IN => thresh_mem_write, A_ADD_CONFIGURATION_OUT => a_add_configuration_i, A_DST_CONFIGURATION_OUT => a_dst_configuration_i, @@ -594,28 +600,22 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) ------------------------------------------------------------------------------- -- DATA MULTIPLEXER for INOUT DST, AOD,TAD ------------------------------------------------------------------------------- - process(debug_trigger_distributor_i(3 downto 0),TAD,TAOD, TDST, + process(TAD,TAOD, TDST,direction_data_line_in_i, a_add_configuration_i, a_aod_configuration_i,a_dst_configuration_i) begin - --DATA TACKING - if (debug_trigger_distributor_i(3 downto 0) = x"1" or - debug_trigger_distributor_i(3 downto 0) = x"2" or - debug_trigger_distributor_i(3 downto 0) = x"3" or - debug_trigger_distributor_i(3 downto 0) = x"4") then +--DATA TACKING + if direction_data_line_in_i = x"1" then a_add_data_i <= TAD; a_aod_data_i <= TAOD; a_dst_data_i <= TDST; TAOD <= 'Z'; TDST <= 'Z'; TAD <= (others => 'Z'); --- D(1) <= '0'; --- D(2) <= '1'; - elsif(debug_trigger_distributor_i(3 downto 0) = x"5" or - debug_trigger_distributor_i(3 downto 0) = x"6" or - debug_trigger_distributor_i(3 downto 0) = x"7") then - --CONFIGURATION +--CONFIGURATION or CALIBRATION + elsif(direction_data_line_in_i = x"D") then + TAOD <= a_aod_configuration_i; TDST <= a_dst_configuration_i; TAD <= a_add_configuration_i; @@ -623,10 +623,8 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) a_add_data_i <= (others => '0'); a_aod_data_i <= '0'; a_dst_data_i <= '0'; --- D(1) <= '1'; --- D(2) <= '1'; - else + else --DATA TACKING a_add_data_i <= TAD; a_aod_data_i <= TAOD; @@ -634,21 +632,9 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) TAOD <= 'Z'; TDST <= 'Z'; TAD <= (others => 'Z'); --- D(1) <= '0'; --- D(2) <= '0'; end if; end process; ---------------------------------------------------------------------- --- Outputs to Logic Analyzer ---------------------------------------------------------------------- --- TAD(7 downto 0) <= med_dataready_in & MED_PACKET_NUM_IN & med_data_in(3 downto 0); --- TAD(7 downto 0) <= MED_STAT_DEBUG(48 downto 41); --- TAD(8) <= CLK; --- LB(7 downto 0) <= MED_STAT_DEBUG(40) & MED_STAT_DEBUG(38 downto 32); - - - --------------------------------------------------------------------- -- LED --------------------------------------------------------------------- @@ -657,8 +643,6 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) -- D(3) <= not MED_STAT_DEBUG(7); -- D(4) <= not MED_STAT_DEBUG(8); - - --------------------------------------------------------------------- -- List of debugging signals ---------------------------------------------------------------------