From: Cahit Date: Mon, 20 Oct 2014 14:13:50 +0000 (+0200) Subject: tdc release 2.0.xx X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=feb6804b0d5815c99df6b21141d93690de30f247;p=trb3.git tdc release 2.0.xx --- diff --git a/tdc_releases/ReleaseNotes.txt b/tdc_releases/ReleaseNotes.txt index 7bc5631..87c847e 100644 --- a/tdc_releases/ReleaseNotes.txt +++ b/tdc_releases/ReleaseNotes.txt @@ -1,9 +1,13 @@ Version Release Date Release Notes ------------------------------------------------------------------------------------- -tdc_v2.0 15.11.2012 Double edge detection for longer than 20 ns is +tdc_v2.0 25.08.2014 Double edge detection for longer than 20 ns is implemented. (Not stable-will be fixed in future releases.) +tdc_v1.7.3 15.08.2014 Dead time in the encoder is increased 5ns for + easier placement. + Hit scaler register size is increased to 31 bits. + tdc_v1.7.1 29.07.2014 Feature Bit support. Tidy up the entities. diff --git a/tdc_releases/tdc_v2.0/Adder_304.ngo b/tdc_releases/tdc_v2.0/Adder_304.ngo new file mode 100644 index 0000000..e7a70ba Binary files /dev/null and b/tdc_releases/tdc_v2.0/Adder_304.ngo differ diff --git a/tdc_releases/tdc_v2.0/BusHandler.vhd b/tdc_releases/tdc_v2.0/BusHandler.vhd index d340fb7..932cfe8 100644 --- a/tdc_releases/tdc_v2.0/BusHandler.vhd +++ b/tdc_releases/tdc_v2.0/BusHandler.vhd @@ -30,9 +30,16 @@ architecture Behavioral of BusHandler is signal data_out_reg : std_logic_vector(31 downto 0); signal data_ready_reg : std_logic; signal unknown_addr_reg : std_logic; - + signal read_en_i : std_logic; + signal write_en_i : std_logic; + signal addr_i : std_logic_vector(6 downto 0); + begin + read_en_i <= READ_EN_IN when rising_edge(CLK); + write_en_i <= WRITE_EN_IN when rising_edge(CLK); + addr_i <= ADDR_IN when rising_edge(CLK); + READ_WRITE_RESPONSE : process (CLK, RESET) begin if rising_edge(CLK) then @@ -40,17 +47,17 @@ begin data_out_reg <= (others => '0'); data_ready_reg <= '0'; unknown_addr_reg <= '0'; - elsif READ_EN_IN = '1' then - if to_integer(unsigned(ADDR_IN)) > BUS_LENGTH then -- if bigger than 64 + elsif read_en_i = '1' then + if to_integer(unsigned(addr_i)) > BUS_LENGTH then -- if bigger than 64 data_out_reg <= (others => '0'); data_ready_reg <= '0'; unknown_addr_reg <= '1'; else - data_out_reg <= DATA_IN(to_integer(unsigned(ADDR_IN))); + data_out_reg <= DATA_IN(to_integer(unsigned(addr_i))); data_ready_reg <= '1'; unknown_addr_reg <= '0'; end if; - elsif WRITE_EN_IN = '1' then + elsif write_en_i = '1' then data_out_reg <= (others => '0'); data_ready_reg <= '0'; unknown_addr_reg <= '1'; diff --git a/tdc_releases/tdc_v2.0/Channel.vhd b/tdc_releases/tdc_v2.0/Channel.vhd index ade41c9..b47796b 100644 --- a/tdc_releases/tdc_v2.0/Channel.vhd +++ b/tdc_releases/tdc_v2.0/Channel.vhd @@ -6,38 +6,50 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; -use work.version.all; +use work.tdc_components.all; +use work.config.all; entity Channel is generic ( - CHANNEL_ID : integer range 1 to 64); + CHANNEL_ID : integer range 0 to 64; + DEBUG : integer range 0 to 1; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); port ( - RESET_200 : in std_logic; - RESET_100 : in std_logic; - RESET_COUNTERS : in std_logic; - CLK_200 : in std_logic; - CLK_100 : in std_logic; + RESET_200 : in std_logic; + RESET_100 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_200 : in std_logic; + CLK_100 : in std_logic; -- - HIT_IN : in std_logic; - SCALER_IN : in std_logic; - READ_EN_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_FULL_OUT : out std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - TRIGGER_WINDOW_END_IN : in std_logic; - DATA_FINISHED_IN : in std_logic; - RUN_MODE : in std_logic; + HIT_IN : in std_logic; + HIT_EDGE_IN : in std_logic; + TRIGGER_WIN_END_TDC : in std_logic; + TRIGGER_WIN_END_RDO : in std_logic; + READ_EN_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_DATA_VALID_OUT : out std_logic; + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_EMPTY_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); -- - LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); - HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); - ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); - FIFO_WR_NUMBER : out std_logic_vector(23 downto 0); + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; -- - Channel_DEBUG : out std_logic_vector(31 downto 0) + EPOCH_WRITE_EN_IN : in std_logic; + LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); + HIT_DETECT_NUMBER : out std_logic_vector(30 downto 0); + ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); + ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); + FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0); +-- + Channel_200_DEBUG : out std_logic_vector(31 downto 0); + Channel_DEBUG : out std_logic_vector(31 downto 0) ); end Channel; @@ -47,75 +59,172 @@ architecture Channel of Channel is -- Signal Declarations ------------------------------------------------------------------------------- - -- reset - signal reset_counters_200 : std_logic; + -- time stamp + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + signal epoch_cntr_reg : std_logic_vector(27 downto 0); + signal trig_win_end_tdc_i : std_logic; + signal trig_win_end_rdo_i : std_logic; - -- hit signals - signal hit_in_i : std_logic; - signal hit_reg : std_logic; - signal hit_buf : std_logic; + -- from channel + signal ch_data_i : std_logic_vector(35 downto 0); + signal ch_data_valid_i : std_logic; - -- time stamp - signal coarse_cntr_reg : std_logic_vector(10 downto 0); + -- from buffer + signal buf_data_i : std_logic_vector(35 downto 0); + signal buf_data_valid_i : std_logic; + signal buf_empty_i : std_logic; + signal buf_empty_reg : std_logic; + signal buf_full_i : std_logic; + signal buf_almost_full_i : std_logic; + + -- fron readout + signal rd_en_reg : std_logic; -- debug - signal sync_q : std_logic_vector(2 downto 0); - signal hit_pulse : std_logic; - signal fifo_wr_en_i : std_logic; - signal fifo_wr_en_reg : std_logic; - signal encoder_start_i : std_logic; - signal encoder_start_reg : std_logic; - signal lost_hit_cntr : unsigned(23 downto 0); - signal hit_detect_cntr : unsigned(23 downto 0); - signal encoder_start_cntr : unsigned(23 downto 0); - signal fifo_wr_cntr : unsigned(23 downto 0); + signal sync_q : std_logic_vector(2 downto 0); + signal hit_pulse_100 : std_logic; + signal encoder_finished_i : std_logic; + signal encoder_finished_100 : std_logic; + signal encoder_start_i : std_logic; + signal encoder_start_100 : std_logic; + signal fifo_write_i : std_logic; + signal fifo_write_100 : std_logic; + signal lost_hit_cntr : unsigned(23 downto 0); + signal hit_detect_cntr : unsigned(30 downto 0); + signal encoder_start_cntr : unsigned(23 downto 0); + signal encoder_finished_cntr : unsigned(23 downto 0); + signal fifo_write_cntr : unsigned(23 downto 0); + signal channel_200_debug_i : std_logic_vector(31 downto 0); + signal ch_buffer_counter : unsigned(15 downto 0) := (others => '0'); + signal ch_buffer_out_counter : unsigned(15 downto 0) := (others => '0'); + signal ch_buffer_valid_counter : unsigned(15 downto 0) := (others => '0'); -- other - signal trg_win_end_i : std_logic; - signal data_finished_i : std_logic; - signal run_mode_i : std_logic; ------------------------------------------------------------------------------- - attribute syn_keep : boolean; - attribute syn_keep of hit_buf : signal is true; - attribute syn_preserve : boolean; - attribute syn_preserve of coarse_cntr_reg : signal is true; + attribute syn_keep : boolean; + attribute syn_keep of trig_win_end_tdc_i : signal is true; + attribute syn_keep of trig_win_end_rdo_i : signal is true; + attribute syn_keep of epoch_cntr_reg : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of coarse_cntr_reg : signal is true; + attribute syn_preserve of trig_win_end_tdc_i : signal is true; + attribute syn_preserve of epoch_cntr_reg : signal is true; + attribute nomerge : string; + attribute nomerge of trig_win_end_tdc_i : signal is "true"; + attribute nomerge of trig_win_end_rdo_i : signal is "true"; + attribute nomerge of epoch_cntr_reg : signal is "true"; ------------------------------------------------------------------------------- begin - --hit_in_i <= HIT_IN; - --hit_buf <= not hit_in_i; - - Channel_200_1 : Channel_200 + Channel200 : Channel_200 generic map ( - CHANNEL_ID => CHANNEL_ID) + CHANNEL_ID => CHANNEL_ID, + DEBUG => DEBUG, + SIMULATION => SIMULATION, + REFERENCE => REFERENCE) port map ( CLK_200 => CLK_200, RESET_200 => RESET_200, CLK_100 => CLK_100, RESET_100 => RESET_100, - HIT_IN => HIT_IN, --hit_buf, - EPOCH_COUNTER_IN => EPOCH_COUNTER_IN, - TRIGGER_WINDOW_END_IN => trg_win_end_i, - DATA_FINISHED_IN => data_finished_i, - RUN_MODE => run_mode_i, + HIT_IN => HIT_IN, + HIT_EDGE_IN => HIT_EDGE_IN, + TRIGGER_WIN_END_TDC => trig_win_end_tdc_i, + TRIGGER_WIN_END_RDO => trig_win_end_rdo_i, + EPOCH_COUNTER_IN => epoch_cntr_reg, COARSE_COUNTER_IN => coarse_cntr_reg, READ_EN_IN => READ_EN_IN, - FIFO_DATA_OUT => FIFO_DATA_OUT, - FIFO_EMPTY_OUT => FIFO_EMPTY_OUT, - FIFO_FULL_OUT => FIFO_FULL_OUT, - FIFO_ALMOST_FULL_OUT => FIFO_ALMOST_FULL_OUT, - FIFO_WR_OUT => fifo_wr_en_i, - ENCODER_START_OUT => encoder_start_i); - - trg_win_end_i <= TRIGGER_WINDOW_END_IN when rising_edge(CLK_200); - data_finished_i <= DATA_FINISHED_IN when rising_edge(CLK_100); - run_mode_i <= RUN_MODE when rising_edge(CLK_100); - encoder_start_reg <= encoder_start_i when rising_edge(CLK_200); - fifo_wr_en_reg <= fifo_wr_en_i when rising_edge(CLK_200); + FIFO_DATA_OUT => ch_data_i, + FIFO_DATA_VALID_OUT => ch_data_valid_i, + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + EPOCH_WRITE_EN_IN => EPOCH_WRITE_EN_IN, + ENCODER_START_OUT => encoder_start_i, + ENCODER_FINISHED_OUT => encoder_finished_i, + FIFO_WRITE_OUT => fifo_write_i, + CHANNEL_200_DEBUG => channel_200_debug_i); + + Buffer_128 : if RING_BUFFER_SIZE = 3 generate + The_Buffer : FIFO_36x128_OutReg + port map ( + Data => ch_data_i, + Clock => CLK_100, + WrEn => ch_data_valid_i, + RdEn => READ_EN_IN, + Reset => RESET_100, + Q => buf_data_i, + Empty => buf_empty_i, + Full => buf_full_i); + end generate Buffer_128; + + Buffer_64 : if RING_BUFFER_SIZE = 1 generate + The_Buffer : FIFO_36x64_OutReg + port map ( + Data => ch_data_i, + Clock => CLK_100, + WrEn => ch_data_valid_i, + RdEn => READ_EN_IN, + Reset => RESET_100, + Q => buf_data_i, + Empty => buf_empty_i, + Full => buf_full_i); + end generate Buffer_64; + + Buffer_32 : if RING_BUFFER_SIZE = 0 generate + The_Buffer : FIFO_36x32_OutReg + port map ( + Data => ch_data_i, + Clock => CLK_100, + WrEn => ch_data_valid_i, + RdEn => READ_EN_IN, + Reset => RESET_100, + Q => buf_data_i, + Empty => buf_empty_i, + Full => buf_full_i); + end generate Buffer_32; + + FIFO_DATA_OUT <= buf_data_i; + FIFO_DATA_VALID_OUT <= buf_data_valid_i; + FIFO_EMPTY_OUT <= buf_empty_i; + FIFO_ALMOST_EMPTY_OUT <= '0'; + trig_win_end_tdc_i <= TRIGGER_WIN_END_TDC; + trig_win_end_rdo_i <= TRIGGER_WIN_END_RDO; + rd_en_reg <= READ_EN_IN when rising_edge(CLK_100); + buf_empty_reg <= buf_empty_i when rising_edge(CLK_100); + buf_data_valid_i <= rd_en_reg and not buf_empty_reg when rising_edge(CLK_100); + + pulse_sync_encoder_start : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => encoder_start_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => encoder_start_100); + + pulse_sync_encoder_finished : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => encoder_finished_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => encoder_finished_100); + + pulse_sync_fifo_write : pulse_sync + port map ( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_200, + PULSE_A_IN => fifo_write_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_100, + PULSE_B_OUT => fifo_write_100); CoarseCounter : ShiftRegisterSISO generic map ( @@ -123,93 +232,126 @@ begin WIDTH => 11) port map ( CLK => CLK_200, - RESET => RESET_200, D_IN => COARSE_COUNTER_IN, D_OUT => coarse_cntr_reg); + epoch_cntr_reg <= EPOCH_COUNTER_IN when rising_edge(CLK_200); + ------------------------------------------------------------------------------- -- DEBUG Counters ------------------------------------------------------------------------------- - reset_counters_200 <= RESET_COUNTERS when rising_edge(CLK_200); - --purpose: Hit Signal Synchroniser - sync_q(0) <= SCALER_IN when rising_edge(CLK_200); - sync_q(1) <= sync_q(0) when rising_edge(CLK_200); - sync_q(2) <= sync_q(1) when rising_edge(CLK_200); + sync_q(0) <= HIT_IN when rising_edge(CLK_100); + sync_q(1) <= sync_q(0) when rising_edge(CLK_100); + sync_q(2) <= sync_q(1) when rising_edge(CLK_100); - edge_to_pulse_1 : edge_to_pulse + risingEdgeDetect_1 : risingEdgeDetect port map ( - clock => CLK_200, - en_clk => '1', - signal_in => sync_q(2), - pulse => hit_pulse); - - --purpose: Counts the detected but unwritten hits - Lost_Hit_Counter : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' or reset_counters_200 = '1' then - lost_hit_cntr <= (others => '0'); - elsif hit_pulse = '1' then - lost_hit_cntr <= lost_hit_cntr + to_unsigned(1, 1); - elsif fifo_wr_en_reg = '1' then - lost_hit_cntr <= lost_hit_cntr - to_unsigned(1, 1); - end if; - end if; - end process Lost_Hit_Counter; - - LOST_HIT_NUMBER <= std_logic_vector(lost_hit_cntr) when rising_edge(CLK_100); + CLK => CLK_100, + SIGNAL_IN => sync_q(2), + PULSE_OUT => hit_pulse_100); --purpose: Counts the detected hits - Hit_Detect_Counter : process (CLK_200, RESET_200, hit_pulse) + Hit_Detect_Counter : process (CLK_100) begin - if rising_edge(CLK_200) then - if RESET_200 = '1' or reset_counters_200 = '1' then + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then hit_detect_cntr <= (others => '0'); - elsif hit_pulse = '1' then - hit_detect_cntr <= hit_detect_cntr + to_unsigned(1, 1); + elsif hit_pulse_100 = '1' then + hit_detect_cntr <= hit_detect_cntr + to_unsigned(1, 31); end if; end if; end process Hit_Detect_Counter; HIT_DETECT_NUMBER <= std_logic_vector(hit_detect_cntr) when rising_edge(CLK_100); - --purpose: Counts the encoder start times - Encoder_Start_Counter : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' or reset_counters_200 = '1' then - encoder_start_cntr <= (others => '0'); - elsif encoder_start_reg = '1' then - encoder_start_cntr <= encoder_start_cntr + to_unsigned(1, 1); + gen_DEBUG : if DEBUG = c_YES generate + --purpose: Counts the detected but unwritten hits + Lost_Hit_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + lost_hit_cntr <= (others => '0'); + elsif hit_pulse_100 = '1' then + lost_hit_cntr <= lost_hit_cntr + to_unsigned(1, 24); + elsif fifo_write_100 = '1' then + lost_hit_cntr <= lost_hit_cntr - to_unsigned(1, 24); + end if; end if; - end if; - end process Encoder_Start_Counter; + end process Lost_Hit_Counter; - ENCODER_START_NUMBER <= std_logic_vector(encoder_start_cntr) when rising_edge(CLK_100); + LOST_HIT_NUMBER <= std_logic_vector(lost_hit_cntr) when rising_edge(CLK_100); - --purpose: Counts the written hits - FIFO_WR_Counter : process (CLK_200) - begin - if rising_edge(CLK_200) then - if RESET_200 = '1' or reset_counters_200 = '1' then - fifo_wr_cntr <= (others => '0'); - elsif fifo_wr_en_reg = '1' then - fifo_wr_cntr <= fifo_wr_cntr + to_unsigned(1, 1); + --purpose: Counts the encoder start times + Encoder_Start_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + ch_buffer_counter <= (others => '0'); + elsif ch_data_valid_i = '1' then + if ch_data_i(35 downto 31) = "00011" then -- it is a data word + ch_buffer_counter <= ch_buffer_counter + to_unsigned(1, 16); + end if; + end if; + --elsif encoder_start_100 = '1' then + -- encoder_start_cntr <= encoder_start_cntr + to_unsigned(1, 16); + --end if; end if; - end if; - end process FIFO_WR_Counter; + end process Encoder_Start_Counter; + + --ENCODER_START_NUMBER <= std_logic_vector(encoder_start_cntr) when rising_edge(CLK_100); + ENCODER_START_NUMBER(15 downto 0) <= std_logic_vector(ch_buffer_counter) when rising_edge(CLK_100); + + --purpose: Counts the encoder finished signals + ENCODER_FINISHED_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + ch_buffer_out_counter <= (others => '0'); + elsif buf_data_i(35 downto 31) = "00011" then + ch_buffer_out_counter <= ch_buffer_out_counter + to_unsigned(1, 16); + end if; + end if; + end process ENCODER_FINISHED_Counter; + + --ENCODER_FINISHED_NUMBER <= std_logic_vector(encoder_finished_cntr) when rising_edge(CLK_100); + ENCODER_FINISHED_NUMBER(15 downto 0) <= std_logic_vector(ch_buffer_out_counter) when rising_edge(CLK_100); + + --purpose: Counts the written hits + FIFO_WRITE_Counter : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + ch_buffer_valid_counter <= (others => '0'); + elsif buf_data_valid_i = '1' then + if buf_data_i(35 downto 31) = "00011" then + ch_buffer_valid_counter <= ch_buffer_valid_counter + to_unsigned(1, 16); + end if; + end if; + end if; + end process FIFO_WRITE_Counter; + + --FIFO_WRITE_NUMBER <= std_logic_vector(fifo_write_cntr) when rising_edge(CLK_100); + FIFO_WRITE_NUMBER(15 downto 0) <= std_logic_vector(ch_buffer_valid_counter) when rising_edge(CLK_100); + end generate gen_DEBUG; + +------------------------------------------------------------------------------- +-- DEBUG +------------------------------------------------------------------------------- + Channel_DEBUG(7 downto 0) <= buf_data_i(35 downto 28); + Channel_DEBUG(8) <= buf_data_valid_i; + Channel_DEBUG(9) <= READ_EN_IN; - FIFO_WR_NUMBER <= std_logic_vector(fifo_wr_cntr) when rising_edge(CLK_100); - --Channel_DEBUG(0) <= HIT_IN; + Channel_200_DEBUG <= channel_200_debug_i; + --Channel_DEBUG(0) <= fifo_write_100 when rising_edge(CLK_100); --Channel_DEBUG(1) <= result_2_reg; --Channel_DEBUG(2) <= hit_detect_i; --Channel_DEBUG(3) <= hit_detect_reg; --Channel_DEBUG(4) <= '0'; --Channel_DEBUG(5) <= ff_array_en_i; --Channel_DEBUG(6) <= encoder_start_i; - --Channel_DEBUG(7) <= fifo_wr_i; + --Channel_DEBUG(7) <= encoder_finished_i; --Channel_DEBUG(15 downto 8) <= result_i(7 downto 0); --Channel_DEBUG(31 downto 16) <= (others => '0'); diff --git a/tdc_releases/tdc_v2.0/Channel_200.vhd b/tdc_releases/tdc_v2.0/Channel_200.vhd index fd4c5b8..43990eb 100644 --- a/tdc_releases/tdc_v2.0/Channel_200.vhd +++ b/tdc_releases/tdc_v2.0/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2012-11-26 +-- Last update: 2014-08-28 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -18,11 +18,16 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; -use work.version.all; +use work.tdc_components.all; +use work.config.all; entity Channel_200 is + generic ( - CHANNEL_ID : integer range 1 to 64); + CHANNEL_ID : integer range 0 to 64; + DEBUG : integer range 0 to 1; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); port ( CLK_200 : in std_logic; -- 200 MHz clk RESET_200 : in std_logic; -- reset sync with 200Mhz clk @@ -30,20 +35,26 @@ entity Channel_200 is RESET_100 : in std_logic; -- reset sync with 100Mhz clk -- HIT_IN : in std_logic; -- hit in + HIT_EDGE_IN : in std_logic; -- hit edge in + TRIGGER_WIN_END_TDC : in std_logic; -- trigger window end strobe + TRIGGER_WIN_END_RDO : in std_logic; -- trigger window end strobe EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); -- system coarse counter - TRIGGER_WINDOW_END_IN : in std_logic; - DATA_FINISHED_IN : in std_logic; - RUN_MODE : in std_logic; COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); READ_EN_IN : in std_logic; -- read en signal - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); -- fifo data out - FIFO_EMPTY_OUT : out std_logic; -- fifo empty signal - FIFO_FULL_OUT : out std_logic; -- fifo full signal - FIFO_ALMOST_FULL_OUT : out std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); -- fifo data out + FIFO_DATA_VALID_OUT : out std_logic; -- fifo data valid signal -- - FIFO_WR_OUT : out std_logic; - ENCODER_START_OUT : out std_logic); - + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; +-- + EPOCH_WRITE_EN_IN : in std_logic; + ENCODER_START_OUT : out std_logic; + ENCODER_FINISHED_OUT : out std_logic; + FIFO_WRITE_OUT : out std_logic; + CHANNEL_200_DEBUG : out std_logic_vector(31 downto 0) + ); end Channel_200; @@ -55,110 +66,124 @@ architecture Channel_200 of Channel_200 is signal result_i : std_logic_vector(303 downto 0); signal ff_array_en_i : std_logic; - -- edge detection - signal hit_reg : std_logic_vector(9 downto 0); - signal hit_in_i : std_logic; - -- hit detection - signal result_2_reg : std_logic; - signal hit_detect_i : std_logic; + signal result_2_reg : std_logic := '0'; + signal hit_detect_i : std_logic := '0'; signal hit_detect_reg : std_logic; signal hit_detect_2reg : std_logic; + signal edge_type_i : std_logic; -- time stamp - signal time_stamp_i : std_logic_vector(10 downto 0); - signal time_stamp_r : std_logic_vector(10 downto 0); - signal time_stamp_f : std_logic_vector(10 downto 0); - signal coarse_cntr_reg : std_logic_vector(10 downto 0); + signal time_stamp_i : std_logic_vector(10 downto 0); + signal time_stamp_reg : std_logic_vector(10 downto 0); + signal time_stamp_2reg : std_logic_vector(10 downto 0); + signal time_stamp_3reg : std_logic_vector(10 downto 0); + signal time_stamp_4reg : std_logic_vector(10 downto 0); + signal time_stamp_5reg : std_logic_vector(10 downto 0); + signal time_stamp_6reg : std_logic_vector(10 downto 0); + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + signal coarse_cntr_overflow : std_logic; + signal coarse_cntr_overflow_reg : std_logic; + signal coarse_cntr_overflow_2reg : std_logic; + signal coarse_cntr_overflow_3reg : std_logic; + signal coarse_cntr_overflow_4reg : std_logic; + signal coarse_cntr_overflow_5reg : std_logic; + signal coarse_cntr_overflow_6reg : std_logic; + signal coarse_cntr_overflow_7reg : std_logic; -- encoder signal encoder_start_i : std_logic; signal encoder_finished_i : std_logic; signal encoder_data_out_i : std_logic_vector(9 downto 0); - signal fine_time_r : std_logic_vector(9 downto 0); - signal fine_time_f : std_logic_vector(9 downto 0); signal encoder_debug_i : std_logic_vector(31 downto 0); - ---- coarse counter overflow - --signal coarse_cntr_overflow_release : std_logic; - --signal coarse_cntr_overflow_flag : std_logic; - -- epoch counter - signal epoch_cntr : std_logic_vector(27 downto 0); - signal epoch_marker_r : std_logic_vector(27 downto 0); - signal epoch_marker_f : std_logic_vector(27 downto 0); - signal epoch_word_first : std_logic_vector(31 downto 0); - signal epoch_cntr_up : std_logic; - signal epoch_capture_time : std_logic_vector(10 downto 0); - - -- fifo - signal fifo_data_out_i : std_logic_vector(31 downto 0); - signal fifo_data_in_i : std_logic_vector(31 downto 0); - signal fifo_empty_i : std_logic; - signal fifo_full_i : std_logic; - signal fifo_was_full_i : std_logic; - signal fifo_almost_full_i : std_logic; - signal fifo_wr_en_i : std_logic; - signal fifo_rd_en_i : std_logic; - - -- fsm - type FSM is (IDLE, WAIT_FOR_FALLING_EDGE, WRITE_DATA_R, WRITE_EPOCH_F, WRITE_DATA_F); - signal FSM_CURRENT, FSM_NEXT : FSM; - signal fifo_wr_en_fsm : std_logic; - signal fifo_data_in_fsm : std_logic_vector(31 downto 0); - signal fsm_debug_fsm : std_logic_vector(3 downto 0); - signal fsm_debug_i : std_logic_vector(3 downto 0); - - -- other - signal read_en_reg : std_logic; - signal read_en_2reg : std_logic; - signal first_read_i : std_logic; - signal trg_win_end_i : std_logic; - - attribute syn_keep : boolean; - attribute syn_keep of ff_array_en_i : signal is true; - attribute syn_keep of trg_win_end_i : signal is true; - attribute syn_keep of encoder_start_i : signal is true; - attribute syn_keep of hit_in_i : signal is true; - attribute NOMERGE : string; - attribute NOMERGE of hit_in_i : signal is "true"; - attribute syn_preserve : boolean; - attribute syn_preserve of trg_win_end_i : signal is true; + signal epoch_cntr : std_logic_vector(27 downto 0) := (others => '0'); + signal epoch_cntr_reg : std_logic_vector(27 downto 0) := (others => '0'); + signal epoch_cntr_updated : std_logic := '0'; + signal epoch_value : std_logic_vector(35 downto 0); + + -- ring bugger + signal ringBuffer_data_out_i : std_logic_vector(35 downto 0); + signal ringBuffer_data_in_i : std_logic_vector(35 downto 0); + signal ringBuffer_empty_i : std_logic; + signal ringBuffer_full_i : std_logic; + signal ringBuffer_almost_full_sync : std_logic; + signal ringBuffer_almost_full_i : std_logic := '0'; + signal ringBuffer_almost_full_flag : std_logic := '0'; + signal ringBuffer_wr_en_i : std_logic; + signal ringBuffer_rd_en_i : std_logic; + signal ringBuffer_rd_data_i : std_logic; + signal fifo_data_i : std_logic_vector(35 downto 0); + signal fifo_data_valid_i : std_logic; + + -- fsm + type FSM_WR is (WRITE_EPOCH, WRITE_DATA, WRITE_STOP_A, WRITE_STOP_B, WRITE_STOP_C, WRITE_STOP_D, WAIT_FOR_HIT, + WAIT_FOR_VALIDITY, EXCEPTION); + signal FSM_WR_CURRENT : FSM_WR := WRITE_EPOCH; + signal FSM_WR_NEXT : FSM_WR; + signal write_epoch_fsm : std_logic; + signal write_epoch_i : std_logic := '0'; + signal write_data_fsm : std_logic; + signal write_data_i : std_logic := '0'; + signal write_stop_a_fsm : std_logic; + signal write_stop_a_i : std_logic := '0'; + signal write_stop_b_fsm : std_logic; + signal write_stop_b_i : std_logic := '0'; + signal write_data_flag_fsm : std_logic; + signal write_data_flag_i : std_logic := '0'; + signal trig_win_end_tdc_flag_fsm : std_logic; + signal trig_win_end_tdc_flag_i : std_logic := '0'; + signal fsm_wr_debug_fsm : std_logic_vector(3 downto 0); + signal fsm_wr_debug_i : std_logic_vector(3 downto 0); + + type FSM_RD is (IDLE, FLUSH_A, FLUSH_B, FLUSH_C, FLUSH_D, READOUT_EPOCH, READOUT_DATA_A, READOUT_DATA_B, READOUT_DATA_C); + signal FSM_RD_STATE : FSM_RD; + signal trigger_win_end_rdo_flag_i : std_logic := '0'; + signal fsm_rd_debug_i : std_logic_vector(3 downto 0); + + ----------------------------------------------------------------------------- + -- debug + signal data_cnt_total : integer range 0 to 2147483647 := 0; + signal data_cnt_event : integer range 0 to 255 := 0; + signal epoch_cnt_total : integer range 0 to 65535 := 0; + signal epoch_cnt_event : integer range 0 to 127 := 0; + ----------------------------------------------------------------------------- + + attribute syn_keep : boolean; + attribute syn_keep of ff_array_en_i : signal is true; - begin -- Channel_200 - trg_win_end_i <= TRIGGER_WINDOW_END_IN when rising_edge(CLK_200); - - hit_reg(9) <= HIT_IN when rising_edge(CLK_200); - GenHitRegArray : for i in 8 downto 0 generate - hit_reg(i) <= hit_reg(i+1) when rising_edge(CLK_200); - end generate GenHitRegArray; - - -- purpose: Toggle between the edges of the hit signal - ToggleHitEdge : process (hit_reg, HIT_IN) - begin -- process ToggleHitEdge - if hit_reg(7) = '0' then - hit_in_i <= HIT_IN; - else - hit_in_i <= not HIT_IN; - end if; - end process ToggleHitEdge; - - --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition - FC : Adder_304 - port map ( - CLK => CLK_200, - RESET => RESET_200, - DataA => data_a_i, - DataB => data_b_i, - ClkEn => ff_array_en_i, - Result => result_i); - - data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; - data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & hit_in_i & x"000000" & "00" & not(hit_in_i); + SimAdderYes : if SIMULATION = c_YES generate + --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition + FC : Adder_304 + port map ( + CLK => CLK_200, + RESET => RESET_200, + DataA => data_a_i, + DataB => data_b_i, + ClkEn => ff_array_en_i, + Result => result_i); + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000FFFFFFF"&x"7FFFFFF"; + data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000"& HIT_IN & x"000000"&"00" & not(HIT_IN); + end generate SimAdderYes; + SimAdderNo : if SIMULATION = c_NO generate + --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition + FC : Adder_304 + port map ( + CLK => CLK_200, + RESET => RESET_200, + DataA => data_a_i, + DataB => data_b_i, + ClkEn => ff_array_en_i, + Result => result_i); + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"&x"7FFFFFF"; + data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000"& HIT_IN & x"000000"&"00" & not(HIT_IN); + end generate SimAdderNo; + + ff_array_en_i <= not(hit_detect_i or hit_detect_reg or hit_detect_2reg); - ff_array_en_i <= not(hit_detect_i or hit_detect_reg or hit_detect_2reg); result_2_reg <= result_i(2) when rising_edge(CLK_200); hit_detect_i <= (not result_2_reg) and result_i(2); -- detects the hit by -- comparing the @@ -168,33 +193,77 @@ begin -- Channel_200 hit_detect_2reg <= hit_detect_reg when rising_edge(CLK_200); coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200); encoder_start_i <= hit_detect_reg; +-- encoder_start_i <= hit_detect_2reg; ENCODER_START_OUT <= encoder_start_i; - TimeStampCapture : process (CLK_200) - begin + EdgeTypeCapture: process (CLK_200) is + begin -- process EdgeTypeCapture if rising_edge(CLK_200) then - if RESET_200 = '1' then - time_stamp_i <= (others => '0'); - elsif hit_detect_reg = '1' then - time_stamp_i <= coarse_cntr_reg; + if encoder_start_i = '1' then + edge_type_i <= HIT_EDGE_IN; end if; end if; - end process TimeStampCapture; + end process EdgeTypeCapture; - epoch_capture_time <= "00000000111"; - - EpochCounterCapture : process (CLK_200) + TimeStampCapture : process (CLK_200) begin if rising_edge(CLK_200) then - if RESET_200 = '1' then - epoch_cntr <= (others => '0'); - epoch_cntr_up <= '0'; - elsif coarse_cntr_reg = epoch_capture_time then - epoch_cntr <= EPOCH_COUNTER_IN; - epoch_cntr_up <= '1'; + if hit_detect_reg = '1' then + time_stamp_i <= coarse_cntr_reg; end if; + time_stamp_reg <= time_stamp_i; + time_stamp_2reg <= time_stamp_reg; + time_stamp_3reg <= time_stamp_2reg; + time_stamp_4reg <= time_stamp_3reg; + time_stamp_5reg <= time_stamp_4reg; + time_stamp_6reg <= time_stamp_5reg; end if; - end process EpochCounterCapture; + end process TimeStampCapture; + + CoarseCounterOverflow : entity work.fallingEdgeDetect + port map ( + CLK => CLK_200, + SIGNAL_IN => coarse_cntr_reg(10), + PULSE_OUT => coarse_cntr_overflow); + + coarse_cntr_overflow_reg <= coarse_cntr_overflow when rising_edge(CLK_200); + coarse_cntr_overflow_2reg <= coarse_cntr_overflow_reg when rising_edge(CLK_200); + coarse_cntr_overflow_3reg <= coarse_cntr_overflow_2reg when rising_edge(CLK_200); + coarse_cntr_overflow_4reg <= coarse_cntr_overflow_3reg when rising_edge(CLK_200); + coarse_cntr_overflow_5reg <= coarse_cntr_overflow_4reg when rising_edge(CLK_200); + coarse_cntr_overflow_6reg <= coarse_cntr_overflow_5reg when rising_edge(CLK_200); + coarse_cntr_overflow_7reg <= coarse_cntr_overflow_6reg when rising_edge(CLK_200); + + isChannelEpoch : if REFERENCE = c_NO generate + EpochCounterCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if coarse_cntr_overflow_7reg = '1' then + epoch_cntr <= EPOCH_COUNTER_IN; + epoch_cntr_updated <= '1'; + elsif write_epoch_i = '1' then + epoch_cntr_updated <= '0'; + end if; + end if; + end process EpochCounterCapture; + end generate isChannelEpoch; + + isReferenceEpoch : if REFERENCE = c_YES generate + EpochCounterCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if hit_detect_reg = '1' then + epoch_cntr <= EPOCH_COUNTER_IN; + epoch_cntr_reg <= epoch_cntr; + end if; + if hit_detect_2reg = '1' and epoch_cntr /= epoch_cntr_reg then + epoch_cntr_updated <= '1'; + elsif write_epoch_i = '1' then + epoch_cntr_updated <= '0'; + end if; + end if; + end process EpochCounterCapture; + end generate isReferenceEpoch; --purpose: Encoder Encoder : Encoder_304_Bit @@ -207,250 +276,543 @@ begin -- Channel_200 BINARY_CODE_OUT => encoder_data_out_i, ENCODER_DEBUG => encoder_debug_i); - --purpose: registers the data from the encoder and the coarse counter - HitDataRegister : process (CLK_200, RESET_200) + RingBuffer_128 : if RING_BUFFER_SIZE = 3 generate + FIFO : FIFO_DC_36x128_OutReg + port map ( + Data => ringBuffer_data_in_i, + WrClock => CLK_200, + RdClock => CLK_100, + WrEn => ringBuffer_wr_en_i, + RdEn => ringBuffer_rd_en_i, + Reset => RESET_100, + RPReset => RESET_100, + Q => ringBuffer_data_out_i, + Empty => ringBuffer_empty_i, + Full => ringBuffer_full_i, + AlmostFull => ringBuffer_almost_full_i); + end generate RingBuffer_128; + + RingBuffer_64 : if RING_BUFFER_SIZE = 1 generate + FIFO : FIFO_DC_36x64_OutReg + port map ( + Data => ringBuffer_data_in_i, + WrClock => CLK_200, + RdClock => CLK_100, + WrEn => ringBuffer_wr_en_i, + RdEn => ringBuffer_rd_en_i, + Reset => RESET_100, + RPReset => RESET_100, + Q => ringBuffer_data_out_i, + Empty => ringBuffer_empty_i, + Full => ringBuffer_full_i, + AlmostFull => ringBuffer_almost_full_i); + end generate RingBuffer_64; + + RingBuffer_32 : if RING_BUFFER_SIZE = 0 generate + FIFO : FIFO_DC_36x32_OutReg + port map ( + Data => ringBuffer_data_in_i, + WrClock => CLK_200, + RdClock => CLK_100, + WrEn => ringBuffer_wr_en_i, + RdEn => ringBuffer_rd_en_i, + Reset => RESET_100, + RPReset => RESET_100, + Q => ringBuffer_data_out_i, + Empty => ringBuffer_empty_i, + Full => ringBuffer_full_i, + AlmostFull => ringBuffer_almost_full_i); + end generate RingBuffer_32; + + ringBuffer_almost_full_sync <= ringBuffer_almost_full_i when rising_edge(CLK_100); + ringBuffer_rd_en_i <= ringBuffer_rd_data_i or ringBuffer_almost_full_sync when rising_edge(CLK_100); + + FifoAlmostEmptyFlag : process (CLK_100) begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - epoch_marker_f <= (others => '0'); - time_stamp_f <= (others => '0'); - fine_time_f <= (others => '0'); - epoch_marker_r <= (others => '0'); - time_stamp_r <= (others => '0'); - fine_time_r <= (others => '0'); - elsif encoder_finished_i = '1' then --or fifo_wr_en_i = '1' then - epoch_marker_f <= epoch_cntr; - time_stamp_f <= time_stamp_i; - fine_time_f <= encoder_data_out_i; - epoch_marker_r <= epoch_marker_f; - time_stamp_r <= time_stamp_f; - fine_time_r <= fine_time_f; + if rising_edge(CLK_100) then + if RESET_100 = '1' then + ringBuffer_almost_full_flag <= '0'; + elsif FSM_RD_STATE = READOUT_DATA_C then + ringBuffer_almost_full_flag <= '0'; + elsif ringBuffer_almost_full_sync = '1' then + ringBuffer_almost_full_flag <= '1'; end if; end if; - end process HitDataRegister; + end process FifoAlmostEmptyFlag; + - --purpose: FSM controls the write signal to the FIFO according to the edge type - FSM_CLK : process (CLK_200, RESET_200) +------------------------------------------------------------------------------- +-- Write Stage +------------------------------------------------------------------------------- + -- Readout fsm + FSM_CLK : process (CLK_200) begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - FSM_CURRENT <= IDLE; - fifo_data_in_i <= (others => '0'); - fifo_wr_en_i <= '0'; - fsm_debug_i <= (others => '0'); - else - FSM_CURRENT <= FSM_NEXT; - fifo_data_in_i <= fifo_data_in_fsm; - fifo_wr_en_i <= fifo_wr_en_fsm; - fsm_debug_i <= fsm_debug_fsm; - end if; + if RESET_200 = '1' then + FSM_WR_CURRENT <= WRITE_EPOCH; + elsif rising_edge(CLK_200) then + FSM_WR_CURRENT <= FSM_WR_NEXT; + write_epoch_i <= write_epoch_fsm; + write_data_i <= write_data_fsm; + write_stop_a_i <= write_stop_a_fsm; + write_stop_b_i <= write_stop_b_fsm; + write_data_flag_i <= write_data_flag_fsm; + fsm_wr_debug_i <= fsm_wr_debug_fsm; end if; end process FSM_CLK; - FSM_PROC : process (FSM_CURRENT, encoder_finished_i, hit_reg, epoch_marker_r, fine_time_r, time_stamp_r, - epoch_marker_f, fine_time_f, time_stamp_f) - begin - fifo_data_in_fsm <= (others => '0'); - fifo_wr_en_fsm <= '0'; - fsm_debug_fsm <= (others => '0'); - - case (FSM_CURRENT) is - when IDLE => - if encoder_finished_i = '1' then - FSM_NEXT <= WAIT_FOR_FALLING_EDGE; - else - FSM_NEXT <= IDLE; - end if; - fsm_debug_fsm <= x"1"; + isChannel : if REFERENCE = c_NO generate -- if it is a normal channel + FSM_PROC : process (FSM_WR_CURRENT, encoder_finished_i, epoch_cntr_updated, TRIGGER_WIN_END_TDC, + trig_win_end_tdc_flag_i, write_data_flag_i) + begin + + FSM_WR_NEXT <= WRITE_EPOCH; + write_epoch_fsm <= '0'; + write_data_fsm <= '0'; + write_stop_a_fsm <= '0'; + write_stop_b_fsm <= '0'; + write_data_flag_fsm <= write_data_flag_i; + fsm_wr_debug_fsm <= x"0"; + + case (FSM_WR_CURRENT) is + when WRITE_EPOCH => + if encoder_finished_i = '1' or write_data_flag_i = '1' then + write_epoch_fsm <= '1'; + write_data_flag_fsm <= '0'; + FSM_WR_NEXT <= EXCEPTION; + elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + write_epoch_fsm <= '0'; + FSM_WR_NEXT <= WRITE_EPOCH; + end if; + fsm_wr_debug_fsm <= x"1"; -- - when WAIT_FOR_FALLING_EDGE => - if encoder_finished_i = '1' then - FSM_NEXT <= WRITE_DATA_R; - fifo_data_in_fsm(31 downto 29) <= "011"; - fifo_data_in_fsm(28) <= '0'; - fifo_data_in_fsm(27 downto 0) <= epoch_marker_r; - fifo_wr_en_fsm <= '1'; - elsif hit_reg(0) = '0' then - FSM_NEXT <= IDLE; - else - FSM_NEXT <= WAIT_FOR_FALLING_EDGE; - end if; - fsm_debug_fsm <= x"2"; + when WRITE_DATA => + if epoch_cntr_updated = '1' then + write_epoch_fsm <= '1'; + FSM_WR_NEXT <= EXCEPTION; + else + write_data_fsm <= '1'; + if trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + end if; + fsm_wr_debug_fsm <= x"2"; -- - when WRITE_DATA_R => - FSM_NEXT <= WRITE_EPOCH_F; - fifo_data_in_fsm(31) <= '1'; -- data marker - fifo_data_in_fsm(30 downto 29) <= "00"; -- reserved bits - fifo_data_in_fsm(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - fifo_data_in_fsm(21 downto 12) <= fine_time_r; -- fine time from the encoder - fifo_data_in_fsm(11) <= '1'; -- edge_type: rising '1' or falling '0' edge - fifo_data_in_fsm(10 downto 0) <= time_stamp_r; -- hit time stamp - fifo_wr_en_fsm <= '1'; - fsm_debug_fsm <= x"3"; + when EXCEPTION => + write_data_fsm <= '1'; + if trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + fsm_wr_debug_fsm <= x"3"; -- - when WRITE_EPOCH_F => - FSM_NEXT <= WRITE_DATA_F; - fifo_data_in_fsm(31 downto 29) <= "011"; - fifo_data_in_fsm(28) <= '0'; - fifo_data_in_fsm(27 downto 0) <= epoch_marker_f; - fifo_wr_en_fsm <= '1'; - fsm_debug_fsm <= x"2"; + when WAIT_FOR_HIT => + if epoch_cntr_updated = '1' and encoder_finished_i = '0' then + FSM_WR_NEXT <= WRITE_EPOCH; + elsif epoch_cntr_updated = '0' and encoder_finished_i = '1' then + FSM_WR_NEXT <= WRITE_DATA; + elsif epoch_cntr_updated = '1' and encoder_finished_i = '1' then + FSM_WR_NEXT <= WRITE_DATA; + elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + fsm_wr_debug_fsm <= x"4"; -- - when WRITE_DATA_F => - FSM_NEXT <= IDLE; - fifo_data_in_fsm(31) <= '1'; -- data marker - fifo_data_in_fsm(30 downto 29) <= "00"; -- reserved bits - fifo_data_in_fsm(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - fifo_data_in_fsm(21 downto 12) <= fine_time_f; -- fine time from the encoder - fifo_data_in_fsm(11) <= '0'; --edge_type: rising '1' or falling '0' edge - fifo_data_in_fsm(10 downto 0) <= time_stamp_f; -- hit time stamp - fifo_wr_en_fsm <= '1'; - fsm_debug_fsm <= x"3"; + when WRITE_STOP_A => + write_stop_a_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_B; + if encoder_finished_i = '1' then + write_data_flag_fsm <= '1'; + end if; + fsm_wr_debug_fsm <= x"5"; -- - when others => - FSM_NEXT <= IDLE; - end case; - end process FSM_PROC; + when WRITE_STOP_B => + write_stop_a_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_C; + if encoder_finished_i = '1' then + write_data_flag_fsm <= '1'; + end if; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_C => + write_stop_b_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_D; + if encoder_finished_i = '1' then + write_data_flag_fsm <= '1'; + end if; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_D => + write_stop_b_fsm <= '1'; + FSM_WR_NEXT <= WRITE_EPOCH; + if encoder_finished_i = '1' then + write_data_flag_fsm <= '1'; + end if; + fsm_wr_debug_fsm <= x"5"; +-- + when others => + FSM_WR_NEXT <= WRITE_EPOCH; + write_epoch_fsm <= '0'; + write_data_fsm <= '0'; + write_stop_a_fsm <= '0'; + write_stop_b_fsm <= '0'; + fsm_wr_debug_fsm <= x"0"; + end case; + end process FSM_PROC; + end generate isChannel; -- if it is a normal channel + + isReference : if REFERENCE = c_YES generate -- if it is the reference channel + FSM_PROC : process (FSM_WR_CURRENT, encoder_finished_i, epoch_cntr_updated, TRIGGER_WIN_END_TDC, + trig_win_end_tdc_flag_i, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, + MULTI_TMG_TRG_IN, SPIKE_DETECTED_IN) + begin + + FSM_WR_NEXT <= WRITE_EPOCH; + write_epoch_fsm <= '0'; + write_data_fsm <= '0'; + write_stop_a_fsm <= '0'; + write_stop_b_fsm <= '0'; + fsm_wr_debug_fsm <= x"0"; + + case (FSM_WR_CURRENT) is + when WRITE_EPOCH => + if encoder_finished_i = '1' then + FSM_WR_NEXT <= WAIT_FOR_VALIDITY; + elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + write_epoch_fsm <= '0'; + FSM_WR_NEXT <= WRITE_EPOCH; + end if; + fsm_wr_debug_fsm <= x"1"; +-- + when WAIT_FOR_VALIDITY => + if VALID_TIMING_TRG_IN = '1' or VALID_NOTIMING_TRG_IN = '1'then + write_epoch_fsm <= '1'; + FSM_WR_NEXT <= EXCEPTION; + elsif MULTI_TMG_TRG_IN = '1' or SPIKE_DETECTED_IN = '1' then + FSM_WR_NEXT <= WRITE_EPOCH; + else + FSM_WR_NEXT <= WAIT_FOR_VALIDITY; + end if; + fsm_wr_debug_fsm <= x"6"; +-- + when WRITE_DATA => + if epoch_cntr_updated = '1' then + write_epoch_fsm <= '1'; + FSM_WR_NEXT <= EXCEPTION; + else + write_data_fsm <= '1'; + if trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + end if; + fsm_wr_debug_fsm <= x"2"; +-- + when EXCEPTION => + write_data_fsm <= '1'; + if trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + fsm_wr_debug_fsm <= x"3"; +-- + when WAIT_FOR_HIT => + if epoch_cntr_updated = '1' and encoder_finished_i = '0' then + FSM_WR_NEXT <= WRITE_EPOCH; + elsif epoch_cntr_updated = '0' and encoder_finished_i = '1' then + FSM_WR_NEXT <= WRITE_DATA; + elsif epoch_cntr_updated = '1' and encoder_finished_i = '1' then + FSM_WR_NEXT <= WRITE_DATA; + elsif trig_win_end_tdc_flag_i = '1' or TRIGGER_WIN_END_TDC = '1' then + FSM_WR_NEXT <= WRITE_STOP_A; + else + FSM_WR_NEXT <= WAIT_FOR_HIT; + end if; + fsm_wr_debug_fsm <= x"4"; +-- + when WRITE_STOP_A => + write_stop_a_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_B; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_B => + write_stop_a_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_C; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_C => + write_stop_b_fsm <= '1'; + FSM_WR_NEXT <= WRITE_STOP_D; + fsm_wr_debug_fsm <= x"5"; +-- + when WRITE_STOP_D => + write_stop_b_fsm <= '1'; + FSM_WR_NEXT <= WRITE_EPOCH; + fsm_wr_debug_fsm <= x"5"; +-- + when others => + FSM_WR_NEXT <= WRITE_EPOCH; + write_epoch_fsm <= '0'; + write_data_fsm <= '0'; + write_stop_a_fsm <= '0'; + write_stop_b_fsm <= '0'; + fsm_wr_debug_fsm <= x"0"; + end case; + end process FSM_PROC; + end generate isReference; -- if it is the reference channel + + TriggerWindowFlag : process (CLK_200) + begin + if rising_edge(CLK_200) then + if RESET_200 = '1' then + trig_win_end_tdc_flag_i <= '0'; + elsif TRIGGER_WIN_END_TDC = '1' then + trig_win_end_tdc_flag_i <= '1'; + elsif FSM_WR_CURRENT = WRITE_STOP_D then + trig_win_end_tdc_flag_i <= '0'; + end if; + end if; + end process TriggerWindowFlag; - FIFO : FIFO_32x32_OutReg - port map ( - Data => fifo_data_in_i, - WrClock => CLK_200, - RdClock => CLK_100, - WrEn => fifo_wr_en_i, - RdEn => fifo_rd_en_i, - Reset => RESET_100, - RPReset => RESET_200, - Q => fifo_data_out_i, - Empty => fifo_empty_i, - Full => fifo_full_i, - AlmostFull => fifo_almost_full_i); - - fifo_rd_en_i <= READ_EN_IN or fifo_full_i; - - ---- purpose: Sets the Overflow Flag - --CoarseCounterOverflowFlag : process (CLK_200) - --begin - -- if rising_edge(CLK_200) then - -- if RESET_200 = '1' then - -- coarse_cntr_overflow_flag <= '0'; - -- elsif epoch_cntr_up = '1' or trg_win_end_i = '1' then - -- coarse_cntr_overflow_flag <= '1'; - -- elsif coarse_cntr_overflow_release = '1' then - -- coarse_cntr_overflow_flag <= '0'; - -- end if; - -- end if; - --end process CoarseCounterOverflowFlag; - - ---- purpose: Generate Fifo Wr Signal - --FifoWriteSignal : process (CLK_200) - --begin - -- if rising_edge(CLK_200) then - -- if RESET_200 = '1' then - -- fifo_data_in_i <= (others => '0'); - -- coarse_cntr_overflow_release <= '0'; - -- fifo_wr_en_i <= '0'; - -- elsif encoder_finished_i = '1' then - -- --if coarse_cntr_overflow_flag = '0' then - -- -- fifo_data_in_i(31) <= '1'; -- data marker - -- -- fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits - -- -- fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - -- -- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder - -- -- fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - -- ---- fifo_data_in_i(10 downto 0) <= time_stamp_reg; -- hit time stamp - -- -- fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp - -- -- coarse_cntr_overflow_release <= '0'; - -- -- fifo_wr_en_i <= '1'; - -- --else - -- --if and_all(TIME_STAMP_IN(10 downto 3)) = '1' then -- for the hits after 0x7f8 - -- --if and_all(time_stamp_i(10 downto 3)) = '1' then -- for the hits after 0x7f8 - -- -- fifo_data_in_i(31) <= '1'; -- data marker - -- -- fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits - -- -- fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - -- -- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder - -- -- fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - -- -- --fifo_data_in_i(10 downto 0) <= time_stamp_reg; -- hit time stamp - -- -- fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp - -- -- coarse_cntr_overflow_release <= '0'; - -- -- fifo_wr_en_i <= '1'; - -- --else - - -- fifo_data_in_i(31 downto 29) <= "011"; - -- fifo_data_in_i(28) <= '0'; - -- fifo_data_in_i(27 downto 0) <= epoch_cntr; - -- coarse_cntr_overflow_release <= '1'; - -- fifo_wr_en_i <= '1'; - -- --end if; - -- --end if; - -- elsif coarse_cntr_overflow_release = '1' then - -- fifo_data_in_i(31) <= '1'; -- data marker - -- fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits - -- fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - -- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder - -- fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - -- --fifo_data_in_i(10 downto 0) <= time_stamp_reg; -- hit time stamp - -- fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp - -- coarse_cntr_overflow_release <= '0'; - -- fifo_wr_en_i <= '1'; - -- else - -- fifo_data_in_i <= (others => '0'); - -- coarse_cntr_overflow_release <= '0'; - -- fifo_wr_en_i <= '0'; - -- end if; - -- end if; - --end process FifoWriteSignal; - - FIFO_WR_OUT <= fifo_wr_en_i; - - EpochCounterCaptureFirstWord : process (CLK_100, RESET_100) + -- purpose: Generate Fifo Wr Signal + FifoWriteSignal : process (CLK_200) begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - epoch_word_first <= x"60000000"; - elsif DATA_FINISHED_IN = '1' and RUN_MODE = '0' then - epoch_word_first <= x"60000000"; - elsif fifo_data_out_i(31 downto 29) = "011" then - epoch_word_first <= fifo_data_out_i; + if rising_edge(CLK_200) then + if write_epoch_i = '1' and EPOCH_WRITE_EN_IN = '1' then + ringBuffer_data_in_i(35 downto 32) <= x"1"; + ringBuffer_data_in_i(31 downto 29) <= "011"; + ringBuffer_data_in_i(28) <= '0'; + ringBuffer_data_in_i(27 downto 0) <= epoch_cntr; + ringBuffer_wr_en_i <= '1'; + elsif write_data_i = '1' then + ringBuffer_data_in_i(35 downto 32) <= x"1"; + ringBuffer_data_in_i(31) <= '1'; -- data marker + ringBuffer_data_in_i(30 downto 29) <= "00"; -- reserved bits + ringBuffer_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number + ringBuffer_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder + ringBuffer_data_in_i(11) <= edge_type_i; -- rising '1' or falling '0' edge + ringBuffer_data_in_i(10 downto 0) <= time_stamp_6reg; -- hit time stamp + ringBuffer_wr_en_i <= '1'; + elsif write_stop_a_i = '1' then + ringBuffer_data_in_i(35 downto 32) <= x"f"; + ringBuffer_data_in_i(31 downto 0) <= (others => '0'); + ringBuffer_wr_en_i <= '1'; + elsif write_stop_b_i = '1' then + ringBuffer_data_in_i(35 downto 32) <= x"0"; + ringBuffer_data_in_i(31 downto 0) <= (others => '0'); + ringBuffer_wr_en_i <= '1'; + else + ringBuffer_data_in_i(35 downto 32) <= x"e"; + ringBuffer_data_in_i(31 downto 0) <= (others => '0'); + ringBuffer_wr_en_i <= '0'; end if; end if; - end process EpochCounterCaptureFirstWord; + end process FifoWriteSignal; - read_en_reg <= READ_EN_IN when rising_edge(CLK_100); - read_en_2reg <= read_en_reg when rising_edge(CLK_100); - first_read_i <= read_en_reg and not(read_en_2reg) when rising_edge(CLK_100); + FIFO_WRITE_OUT <= ringBuffer_wr_en_i; + ENCODER_FINISHED_OUT <= encoder_finished_i; - FifoWasFull : process (CLK_100, RESET_100) +------------------------------------------------------------------------------- +-- Read Stage +------------------------------------------------------------------------------- + -- Determine the next state synchronously, based on the current state and the + -- input + FSM_DATA_STATE : process (CLK_100) begin - if rising_edge(CLK_100) then + if (rising_edge(CLK_100)) then if RESET_100 = '1' then - fifo_was_full_i <= '0'; - elsif fifo_full_i = '1' then - fifo_was_full_i <= '1'; - elsif fifo_empty_i = '1' then - fifo_was_full_i <= '0'; + FSM_RD_STATE <= IDLE; + else + + case FSM_RD_STATE is + when IDLE => + -- if the data readout is triggered by the end of the trigger window + if TRIGGER_WIN_END_RDO = '1' then + FSM_RD_STATE <= READOUT_DATA_A; + -- if the data readout is triggered by full fifo + elsif ringBuffer_almost_full_flag = '1' then + FSM_RD_STATE <= FLUSH_A; + else + FSM_RD_STATE <= IDLE; + end if; + -- + when FLUSH_A => + FSM_RD_STATE <= FLUSH_D; + -- + when FLUSH_B => + FSM_RD_STATE <= FLUSH_C; + -- + when FLUSH_C => + FSM_RD_STATE <= FLUSH_D; + -- + when FLUSH_D => + -- wait until a readout request and register the last epoch word + if TRIGGER_WIN_END_RDO = '1' or trigger_win_end_rdo_flag_i = '1' then + FSM_RD_STATE <= READOUT_EPOCH; + else + FSM_RD_STATE <= FLUSH_D; + end if; + -- + when READOUT_EPOCH => + -- first epoch word should be readout + FSM_RD_STATE <= READOUT_DATA_A; + -- + when READOUT_DATA_A => + FSM_RD_STATE <= READOUT_DATA_B; + -- + when READOUT_DATA_B => + FSM_RD_STATE <= READOUT_DATA_C; + -- + when READOUT_DATA_C => + -- normal data readout until the end of the readout request + if ringBuffer_data_out_i(35 downto 32) = x"f" then + FSM_RD_STATE <= IDLE; + else + FSM_RD_STATE <= READOUT_DATA_C; + end if; + -- + when others => + FSM_RD_STATE <= IDLE; + end case; end if; end if; - end process FifoWasFull; + end process FSM_DATA_STATE; - RegisterOutputs : process (CLK_100) + -- Determine the output based only on the current state and the input (do not wait for a clock + -- edge). + FSM_DATA_OUTPUT : process (FSM_RD_STATE, TRIGGER_WIN_END_RDO, ringBuffer_data_out_i, epoch_value) begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - FIFO_DATA_OUT <= (others => '1'); - FIFO_EMPTY_OUT <= '0'; - FIFO_FULL_OUT <= '0'; - FIFO_ALMOST_FULL_OUT <= '0'; - else - if first_read_i = '1' and fifo_was_full_i = '1' then - FIFO_DATA_OUT <= epoch_word_first; + trigger_win_end_rdo_flag_i <= trigger_win_end_rdo_flag_i; + epoch_value <= epoch_value; + + case FSM_RD_STATE is + when IDLE => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + ringBuffer_rd_data_i <= '0'; + fsm_rd_debug_i <= x"1"; + when FLUSH_A => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + ringBuffer_rd_data_i <= '0'; + if TRIGGER_WIN_END_RDO = '1' then + trigger_win_end_rdo_flag_i <= '1'; + end if; + fsm_rd_debug_i <= x"2"; + when FLUSH_B => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + ringBuffer_rd_data_i <= '0'; + if TRIGGER_WIN_END_RDO = '1' then + trigger_win_end_rdo_flag_i <= '1'; + end if; + fsm_rd_debug_i <= x"3"; + when FLUSH_C => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + ringBuffer_rd_data_i <= '0'; + if TRIGGER_WIN_END_RDO = '1' then + trigger_win_end_rdo_flag_i <= '1'; + end if; + fsm_rd_debug_i <= x"4"; + when FLUSH_D => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + ringBuffer_rd_data_i <= '0'; + if ringBuffer_data_out_i(31 downto 29) = "011" then + epoch_value <= ringBuffer_data_out_i; + end if; + fsm_rd_debug_i <= x"5"; + when READOUT_EPOCH => + fifo_data_i <= epoch_value; + fifo_data_valid_i <= '1'; + ringBuffer_rd_data_i <= '1'; + fsm_rd_debug_i <= x"6"; + when READOUT_DATA_A => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + ringBuffer_rd_data_i <= '1'; + trigger_win_end_rdo_flag_i <= '0'; + fsm_rd_debug_i <= x"7"; + when READOUT_DATA_B => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + ringBuffer_rd_data_i <= '1'; + fsm_rd_debug_i <= x"8"; + when READOUT_DATA_C => + fifo_data_i <= ringBuffer_data_out_i; + if ringBuffer_data_out_i(35 downto 32) = x"0" then + fifo_data_valid_i <= '0'; else - FIFO_DATA_OUT <= fifo_data_out_i; + fifo_data_valid_i <= '1'; end if; - FIFO_EMPTY_OUT <= fifo_empty_i; - FIFO_FULL_OUT <= fifo_full_i; - FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i; - end if; - end if; - end process RegisterOutputs; + ringBuffer_rd_data_i <= '1'; + fsm_rd_debug_i <= x"9"; + when others => + fifo_data_i <= (others => '0'); + fifo_data_valid_i <= '0'; + ringBuffer_rd_data_i <= '0'; + fsm_rd_debug_i <= x"0"; + end case; + end process FSM_DATA_OUTPUT; + FIFO_DATA_OUT <= fifo_data_i; + FIFO_DATA_VALID_OUT <= fifo_data_valid_i; + +------------------------------------------------------------------------------- +-- DEBUG +------------------------------------------------------------------------------- + --CHANNEL_200_DEBUG(7 downto 0) <= ringBuffer_data_in_i(35 downto 28); + --CHANNEL_200_DEBUG(15 downto 8) <= fifo_data_i(35 downto 28); + --CHANNEL_200_DEBUG(16) <= ringBuffer_wr_en_i; + --CHANNEL_200_DEBUG(17) <= fifo_data_valid_i; + --CHANNEL_200_DEBUG(18) <= ringBuffer_rd_en_i; + --CHANNEL_200_DEBUG(23 downto 19) <= (others => '0'); + CHANNEL_200_DEBUG(23 downto 0) <= (others => '0'); + CHANNEL_200_DEBUG(27 downto 24) <= fsm_rd_debug_i; + CHANNEL_200_DEBUG(31 downto 28) <= fsm_wr_debug_i; + + gen_SIMULATION : if SIMULATION = c_YES generate + -- count data written + data_cntr : process + begin + wait until rising_edge(CLK_100); + if fifo_data_valid_i = '1' and fifo_data_i(31 downto 29) = "100" then + data_cnt_event <= data_cnt_event + 1; + elsif fifo_data_valid_i = '1' and fifo_data_i(31 downto 29) = "011" then + epoch_cnt_event <= epoch_cnt_event + 1; + elsif TRIGGER_WIN_END_RDO = '1' then + data_cnt_event <= 0; + epoch_cnt_event <= 0; + end if; + end process data_cntr; + + process(fifo_data_valid_i) + begin -- process + data_cnt_total <= data_cnt_total + data_cnt_event; + epoch_cnt_total <= epoch_cnt_total + epoch_cnt_event; + end process; + + -- check if data count per event is correct + --CheckEpochCounter : process + --begin + -- wait until falling_edge(fifo_data_valid_i); + -- wait for 1 ns; + -- if data_cnt_event /= 30 then + -- report "wrong number of hits in channel " & integer'image(CHANNEL_ID) severity error; + -- end if; + --end process CheckEpochCounter; + + end generate gen_SIMULATION; + end Channel_200; diff --git a/tdc_releases/tdc_v2.0/Encoder_304_Bit.vhd b/tdc_releases/tdc_v2.0/Encoder_304_Bit.vhd index 9b9a63e..dbdf137 100644 --- a/tdc_releases/tdc_v2.0/Encoder_304_Bit.vhd +++ b/tdc_releases/tdc_v2.0/Encoder_304_Bit.vhd @@ -4,7 +4,7 @@ -- File : Encoder_304_Bit.vhd -- Author : Cahit Ugur -- Created : 2011-11-28 --- Last update: 2012-11-12 +-- Last update: 2014-06-24 ------------------------------------------------------------------------------- -- Description: Encoder for 304 bits ------------------------------------------------------------------------------- @@ -20,9 +20,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; +use work.tdc_components.all; -- synopsys translate_off library ecp3; @@ -31,13 +29,14 @@ use ecp3.components.all; entity Encoder_304_Bit is port ( - RESET : in std_logic; -- system reset - CLK : in std_logic; -- system clock - START_IN : in std_logic; - THERMOCODE_IN : in std_logic_vector(303 downto 0); - FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - ENCODER_DEBUG : out std_logic_vector(31 downto 0) + RESET : in std_logic; -- system reset + CLK : in std_logic; -- system clock + START_IN : in std_logic; + THERMOCODE_IN : in std_logic_vector(303 downto 0); + FINISHED_OUT : out std_logic; + BINARY_CODE_OUT : out std_logic_vector(9 downto 0); + ENCODER_INFO_OUT : out std_logic_vector(1 downto 0); + ENCODER_DEBUG : out std_logic_vector(31 downto 0) ); end Encoder_304_Bit; @@ -57,87 +56,44 @@ architecture behavioral of Encoder_304_Bit is ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- - signal P_lut : std_logic_vector(37 downto 0); - signal P_one : std_logic_vector(37 downto 0); - signal mux_control : std_logic_vector(5 downto 0); - signal mux_control_reg : std_logic_vector(5 downto 0); - signal mux_control_2reg : std_logic_vector(5 downto 0); - signal mux_control_3reg : std_logic_vector(5 downto 0); - signal mux_control_4reg : std_logic_vector(5 downto 0); - signal interval_reg : std_logic_vector(8 downto 0); - signal interval_binary : std_logic_vector(2 downto 0); - signal binary_code_f : std_logic_vector(8 downto 0); - signal binary_code_r : std_logic_vector(8 downto 0); - signal start_reg : std_logic; - signal start_2reg : std_logic; - signal start_3reg : std_logic; - signal rom_done_i : std_logic; -- indicates that the encoding of rising edge is done - signal rom_done_reg : std_logic; -- indicates that the encoding of rising edge is done - signal interval_detected_i : std_logic; - signal address_i : std_logic_vector(9 downto 0); - signal q_reg : std_logic_vector(7 downto 0); - signal q_2reg : std_logic_vector(7 downto 0); --- FSM signals - type FSM is (IDLE, START_CNT_2, START_CNT_3, START_CNT_4); - signal FSM_CURRENT, FSM_NEXT : FSM; - - signal start_cnt_1_fsm : std_logic; - signal start_cnt_2_fsm : std_logic; - signal start_cnt_3_fsm : std_logic; - signal start_cnt_4_fsm : std_logic; - signal start_cnt_1_i : std_logic; - signal start_cnt_2_i : std_logic; - signal start_cnt_3_i : std_logic; - signal start_cnt_4_i : std_logic; + signal P_lut : std_logic_vector(37 downto 0); + signal P_one : std_logic_vector(37 downto 0); + signal mux_control : std_logic_vector(5 downto 0); + signal mux_control_reg : std_logic_vector(5 downto 0); + signal mux_control_2reg : std_logic_vector(5 downto 0); + signal mux_control_3reg : std_logic_vector(5 downto 0); + signal interval_reg : std_logic_vector(8 downto 0); + signal interval_binary : std_logic_vector(2 downto 0); + signal binary_code_f : std_logic_vector(8 downto 0); + signal binary_code_r : std_logic_vector(8 downto 0); + signal start_reg : std_logic; + signal start_2reg : std_logic; + signal address_i : std_logic_vector(9 downto 0); + signal q_reg : std_logic_vector(7 downto 0); + signal info : std_logic_vector(1 downto 0); + signal info_reg : std_logic_vector(1 downto 0); + signal info_2reg : std_logic_vector(1 downto 0); -- - signal proc_cnt_1 : std_logic_vector(3 downto 0); - signal proc_cnt_2 : std_logic_vector(3 downto 0); - signal proc_cnt_3 : std_logic_vector(3 downto 0); - signal proc_cnt_4 : std_logic_vector(3 downto 0); - signal proc_finished_1 : std_logic; - signal proc_finished_2 : std_logic; - signal proc_finished_3 : std_logic; - signal proc_finished_4 : std_logic; - signal conv_finished_i : std_logic; + signal conv_finished_i : std_logic; + signal thermocode_i : std_logic_vector(304 downto 0); + signal start_pipeline : std_logic_vector(6 downto 0) := (others => '0'); attribute syn_keep : boolean; attribute syn_keep of mux_control : signal is true; attribute syn_keep of mux_control_reg : signal is true; attribute syn_keep of mux_control_2reg : signal is true; attribute syn_keep of mux_control_3reg : signal is true; - attribute syn_keep of mux_control_4reg : signal is true; ------------------------------------------------------------------------------- begin - --purpose : Register signals - Register_Signals : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - start_reg <= '0'; - start_2reg <= '0'; - start_3reg <= '0'; - mux_control_reg <= (others => '0'); - mux_control_2reg <= (others => '0'); - mux_control_3reg <= (others => '0'); - mux_control_4reg <= (others => '0'); - q_2reg <= (others => '0'); - rom_done_reg <= '0'; - interval_detected_i <= '0'; - else - start_reg <= START_IN; - start_2reg <= start_reg; - start_3reg <= start_2reg; - mux_control_reg <= mux_control; - mux_control_2reg <= mux_control_reg; - mux_control_3reg <= mux_control_2reg; - mux_control_4reg <= mux_control_3reg; - q_2reg <= q_reg; - rom_done_reg <= rom_done_i; - interval_detected_i <= rom_done_i and rom_done_reg; - end if; - end if; - end process Register_Signals; + + thermocode_i(304 downto 1) <= THERMOCODE_IN; + thermocode_i(0) <= '1'; + start_reg <= START_IN when rising_edge(CLK); + start_2reg <= start_reg when rising_edge(CLK); + mux_control_reg <= mux_control when rising_edge(CLK); + mux_control_2reg <= mux_control_reg when rising_edge(CLK); + mux_control_3reg <= mux_control_2reg when rising_edge(CLK); Interval_Determination_First : LUT4 generic map (INIT => X"15A8") @@ -156,10 +112,10 @@ begin P_one(i) <= P_lut(i) and (not P_lut(i+1)) when rising_edge(CLK); end generate Gen_P_one; - P_one_assign : process (CLK, START_IN, P_lut) + P_one_assign : process (CLK) begin if rising_edge(CLK) then - if RESET = '1' or START_IN = '0' then + if START_IN = '0' then P_one(37) <= '0'; else P_one(37) <= P_lut(37); @@ -167,13 +123,11 @@ begin end if; end process P_one_assign; - Interval_Number_to_Binary : process (CLK, RESET) + Interval_Number_to_Binary : process (CLK) begin -- The interval number with the 0-1 transition is converted from 1-of-N code to binary -- code for the control of the MUX. if rising_edge(CLK) then - if RESET = '1' then - mux_control <= (others => '0'); - elsif START_IN = '1' or start_reg = '1' then + if start_2reg = '1' or start_reg = '1' then mux_control(0) <= P_one(0) or P_one(2) or P_one(4) or P_one(6) or P_one(8) or P_one(10) or P_one(12) or P_one(14) or P_one(16) or P_one(18) or P_one(20) or P_one(22) or P_one(24) or P_one(26) or P_one(28) or P_one(30) or P_one(32) or P_one(34) or @@ -200,299 +154,87 @@ begin end if; end process Interval_Number_to_Binary; - Interval_Selection : process (CLK, RESET) + Interval_Selection : process (CLK) + variable tmp : std_logic_vector(9 downto 1); begin -- The interval with the 0-1 transition is selected. if rising_edge(CLK) then - if RESET = '1' then - interval_reg <= (others => '0'); - else - case mux_control is - when "000001" => interval_reg <= THERMOCODE_IN(7 downto 0) & '1'; - when "000010" => interval_reg <= THERMOCODE_IN(15 downto 7); - when "000011" => interval_reg <= THERMOCODE_IN(23 downto 15); - when "000100" => interval_reg <= THERMOCODE_IN(31 downto 23); - when "000101" => interval_reg <= THERMOCODE_IN(39 downto 31); - when "000110" => interval_reg <= THERMOCODE_IN(47 downto 39); - when "000111" => interval_reg <= THERMOCODE_IN(55 downto 47); - when "001000" => interval_reg <= THERMOCODE_IN(63 downto 55); - when "001001" => interval_reg <= THERMOCODE_IN(71 downto 63); - when "001010" => interval_reg <= THERMOCODE_IN(79 downto 71); - when "001011" => interval_reg <= THERMOCODE_IN(87 downto 79); - when "001100" => interval_reg <= THERMOCODE_IN(95 downto 87); - when "001101" => interval_reg <= THERMOCODE_IN(103 downto 95); - when "001110" => interval_reg <= THERMOCODE_IN(111 downto 103); - when "001111" => interval_reg <= THERMOCODE_IN(119 downto 111); - when "010000" => interval_reg <= THERMOCODE_IN(127 downto 119); - when "010001" => interval_reg <= THERMOCODE_IN(135 downto 127); - when "010010" => interval_reg <= THERMOCODE_IN(143 downto 135); - when "010011" => interval_reg <= THERMOCODE_IN(151 downto 143); - when "010100" => interval_reg <= THERMOCODE_IN(159 downto 151); - when "010101" => interval_reg <= THERMOCODE_IN(167 downto 159); - when "010110" => interval_reg <= THERMOCODE_IN(175 downto 167); - when "010111" => interval_reg <= THERMOCODE_IN(183 downto 175); - when "011000" => interval_reg <= THERMOCODE_IN(191 downto 183); - when "011001" => interval_reg <= THERMOCODE_IN(199 downto 191); - when "011010" => interval_reg <= THERMOCODE_IN(207 downto 199); - when "011011" => interval_reg <= THERMOCODE_IN(215 downto 207); - when "011100" => interval_reg <= THERMOCODE_IN(223 downto 215); - when "011101" => interval_reg <= THERMOCODE_IN(231 downto 223); - when "011110" => interval_reg <= THERMOCODE_IN(239 downto 231); - when "011111" => interval_reg <= THERMOCODE_IN(247 downto 239); - when "100000" => interval_reg <= THERMOCODE_IN(255 downto 247); - when "100001" => interval_reg <= THERMOCODE_IN(263 downto 255); - when "100010" => interval_reg <= THERMOCODE_IN(271 downto 263); - when "100011" => interval_reg <= THERMOCODE_IN(279 downto 271); - when "100100" => interval_reg <= THERMOCODE_IN(287 downto 279); - when "100101" => interval_reg <= THERMOCODE_IN(295 downto 287); - when "100110" => interval_reg <= THERMOCODE_IN(303 downto 295); - when others => interval_reg <= (others => '0'); - end case; - end if; + tmp := (others => '0'); + make_mux : for i in 0 to 37 loop + make_mux_2 : for j in 1 to 9 loop + tmp(j) := tmp(j) or (thermocode_i(i*8-1+j) and P_one(i)); + end loop; + end loop; + interval_reg <= tmp; end if; end process Interval_Selection; - ROM_Encoder_1 : ROM_Encoder + ROM_Encoder_1 : ROM_encoder_3 port map ( Address => address_i, OutClock => CLK, OutClockEn => '1', Reset => RESET, Q => q_reg); - address_i <= start_3reg & interval_reg; - rom_done_i <= q_2reg(7); - interval_binary <= q_2reg(2 downto 0); - Binary_Code_Calculation_rf : process (CLK, RESET) + address_i <= start_2reg & interval_reg; + interval_binary <= q_reg(2 downto 0) when rising_edge(CLK); + info <= q_reg(7 downto 6) when rising_edge(CLK); + info_reg <= info when rising_edge(CLK); + info_2reg <= info_reg when rising_edge(CLK); + + Binary_Code_Calculation_rf : process (CLK) begin if rising_edge(CLK) then - if RESET = '1' then - binary_code_f <= (others => '0'); - binary_code_r <= (others => '0'); - elsif rom_done_i = '1' then - binary_code_r <= (mux_control_4reg - 1) & interval_binary; - binary_code_f <= binary_code_r; - end if; + binary_code_r <= (mux_control_3reg - 1) & interval_binary; + binary_code_f <= binary_code_r; end if; end process Binary_Code_Calculation_rf; - --purpose: FSMs the encoder - FSM_CLK : process (CLK, RESET) + Binary_Code_Calculation : process (CLK) begin if rising_edge(CLK) then - if RESET = '1' then - FSM_CURRENT <= IDLE; - start_cnt_1_i <= '0'; - start_cnt_2_i <= '0'; - start_cnt_3_i <= '0'; - start_cnt_4_i <= '0'; - else - FSM_CURRENT <= FSM_NEXT; - start_cnt_1_i <= start_cnt_1_fsm; - start_cnt_2_i <= start_cnt_2_fsm; - start_cnt_3_i <= start_cnt_3_fsm; - start_cnt_4_i <= start_cnt_4_fsm; - end if; - end if; - end process FSM_CLK; - - FSM_PROC : process (FSM_CURRENT, START_IN) - begin - - FSM_NEXT <= IDLE; - start_cnt_1_fsm <= '0'; - start_cnt_2_fsm <= '0'; - start_cnt_3_fsm <= '0'; - start_cnt_4_fsm <= '0'; - - case (FSM_CURRENT) is - when IDLE => - if START_IN = '1' then - FSM_NEXT <= START_CNT_2; - start_cnt_1_fsm <= '1'; - end if; - - when START_CNT_2 => - if START_IN = '1' then - FSM_NEXT <= START_CNT_3; - start_cnt_2_fsm <= '1'; - else - FSM_NEXT <= START_CNT_2; - end if; - - when START_CNT_3 => - if START_IN = '1' then - FSM_NEXT <= START_CNT_4; - start_cnt_3_fsm <= '1'; + if conv_finished_i = '1' then + if info_reg(1) = '1' and info_2reg(1) = '1' then + BINARY_CODE_OUT <= ('0' & binary_code_r) + ('0' & binary_code_f); else - FSM_NEXT <= START_CNT_3; + BINARY_CODE_OUT <= (others => '1'); end if; - - when START_CNT_4 => - if START_IN = '1' then - FSM_NEXT <= IDLE; - start_cnt_4_fsm <= '1'; - else - FSM_NEXT <= START_CNT_4; - end if; - - when others => - FSM_NEXT <= IDLE; - end case; - end process FSM_PROC; - - --purpose : Conversion number 1 - Conv_1 : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - proc_cnt_1 <= x"6"; - proc_finished_1 <= '0'; - elsif start_cnt_1_i = '1' then - proc_cnt_1 <= x"1"; - proc_finished_1 <= '0'; - elsif proc_cnt_1 = x"5" then - proc_cnt_1 <= proc_cnt_1 + 1; - proc_finished_1 <= '1'; - elsif proc_cnt_1 = x"6" then - proc_cnt_1 <= x"6"; - proc_finished_1 <= '0'; - else - proc_cnt_1 <= proc_cnt_1 + 1; - proc_finished_1 <= '0'; - end if; - end if; - end process Conv_1; - - --purpose : Conversion number 2 - Conv_2 : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - proc_cnt_2 <= x"6"; - proc_finished_2 <= '0'; - elsif start_cnt_2_i = '1' then - proc_cnt_2 <= x"1"; - proc_finished_2 <= '0'; - elsif proc_cnt_2 = x"5" then - proc_cnt_2 <= proc_cnt_2 + 1; - proc_finished_2 <= '1'; - elsif proc_cnt_2 = x"6" then - proc_cnt_2 <= x"6"; - proc_finished_2 <= '0'; + ENCODER_INFO_OUT <= (others => '0'); --info_reg or info_2reg; + FINISHED_OUT <= '1'; else - proc_cnt_2 <= proc_cnt_2 + 1; - proc_finished_2 <= '0'; - end if; - end if; - end process Conv_2; - - --purpose : Conversion number 3 - Conv_3 : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - proc_cnt_3 <= x"6"; - proc_finished_3 <= '0'; - elsif start_cnt_3_i = '1' then - proc_cnt_3 <= x"1"; - proc_finished_3 <= '0'; - elsif proc_cnt_3 = x"5" then - proc_cnt_3 <= proc_cnt_3 + 1; - proc_finished_3 <= '1'; - elsif proc_cnt_3 = x"6" then - proc_cnt_3 <= x"6"; - proc_finished_3 <= '0'; - else - proc_cnt_3 <= proc_cnt_3 + 1; - proc_finished_3 <= '0'; - end if; - end if; - end process Conv_3; - - --purpose : Conversion number 4 - Conv_4 : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - proc_cnt_4 <= x"6"; - proc_finished_4 <= '0'; - elsif start_cnt_4_i = '1' then - proc_cnt_4 <= x"1"; - proc_finished_4 <= '0'; - elsif proc_cnt_4 = x"5" then - proc_cnt_4 <= proc_cnt_4 + 1; - proc_finished_4 <= '1'; - elsif proc_cnt_4 = x"6" then - proc_cnt_4 <= x"6"; - proc_finished_4 <= '0'; - else - proc_cnt_4 <= proc_cnt_4 + 1; - proc_finished_4 <= '0'; + FINISHED_OUT <= '0'; end if; end if; - end process Conv_4; + end process Binary_Code_Calculation; - Binary_Code_Calculation : process (CLK, RESET) + StartSignalPipeLine : process (CLK) begin if rising_edge(CLK) then - if RESET = '1' then - BINARY_CODE_OUT <= (others => '0'); - FINISHED_OUT <= '0'; - elsif conv_finished_i = '1' and interval_detected_i = '1' then - BINARY_CODE_OUT <= ('0' & binary_code_r) + ('0' & binary_code_f); - FINISHED_OUT <= '1'; - else --- BINARY_CODE_OUT <= (others => '0'); - FINISHED_OUT <= '0'; - end if; + start_pipeline <= start_pipeline(5 downto 0) & START_IN; end if; - end process Binary_Code_Calculation; - - conv_finished_i <= proc_finished_1 or proc_finished_2 or proc_finished_3 or proc_finished_4; - + end process StartSignalPipeLine; + conv_finished_i <= start_pipeline(6); ------------------------------------------------------------------------------- -- DEBUG ------------------------------------------------------------------------------- - ----purpose : Conversion number 1 - --Conv_1 : process (CLK, RESET) - --begin - -- if rising_edge(CLK) then - -- if RESET = '1' then - -- proc_cnt_1 <= x"3"; - -- proc_finished_1 <= '0'; - -- elsif START_IN = '1' then - -- proc_cnt_1 <= x"1"; - -- proc_finished_1 <= '0'; - -- elsif proc_cnt_1 = x"1" or proc_cnt_1 = x"2" then - -- proc_cnt_1 <= proc_cnt_1 + 1; - -- proc_finished_1 <= '1'; - -- elsif proc_cnt_1 = x"3" then - -- proc_cnt_1 <= x"3"; - -- proc_finished_1 <= '0'; - -- else - -- proc_cnt_1 <= proc_cnt_1 + 1; - -- proc_finished_1 <= '0'; - -- end if; - -- end if; - --end process Conv_1; --Binary_Code_Calculation : process (CLK, RESET) --begin - -- if rising_edge(CLK) then - -- if RESET = '1' then - -- BINARY_CODE_OUT <= (others => '0'); - -- FINISHED_OUT <= '0'; - -- elsif proc_finished_1 = '1' then - -- BINARY_CODE_OUT <= address_i; --'0' & interval_reg; - -- FINISHED_OUT <= '1'; - -- else - -- BINARY_CODE_OUT <= (others => '0'); - -- FINISHED_OUT <= '0'; - -- end if; - -- end if; + -- if rising_edge(CLK) then + -- if RESET = '1' then + -- BINARY_CODE_OUT <= (others => '0'); + -- FINISHED_OUT <= '0'; + -- elsif proc_finished_1 = '1' then + -- BINARY_CODE_OUT <= address_i; --'0' & interval_reg; + -- FINISHED_OUT <= '1'; + -- else + -- BINARY_CODE_OUT <= (others => '0'); + -- FINISHED_OUT <= '0'; + -- end if; + -- end if; --end process Binary_Code_Calculation; - ----ENCODER_DEBUG(8 downto 0) <= interval_reg; + --ENCODER_DEBUG(8 downto 0) <= interval_reg; end behavioral; diff --git a/tdc_releases/tdc_v2.0/FIFO_36x128_OutReg_Counter.vhd b/tdc_releases/tdc_v2.0/FIFO_36x128_OutReg_Counter.vhd new file mode 100644 index 0000000..14b4942 --- /dev/null +++ b/tdc_releases/tdc_v2.0/FIFO_36x128_OutReg_Counter.vhd @@ -0,0 +1,1094 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.4 +--/opt/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe -1 -pf -1 -fill -e + +-- Wed Jan 30 11:50:36 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_36x128_OutReg_Counter is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic); +end FIFO_36x128_OutReg_Counter; + +architecture Structure of FIFO_36x128_OutReg_Counter is + + -- internal signal declarations + signal invout_1 : std_logic; + signal invout_0 : std_logic; + signal w_g2b_xor_cluster_1 : std_logic; + signal r_g2b_xor_cluster_1 : std_logic; + signal w_gdata_0 : std_logic; + signal w_gdata_1 : std_logic; + signal w_gdata_2 : std_logic; + signal w_gdata_3 : std_logic; + signal w_gdata_4 : std_logic; + signal w_gdata_5 : std_logic; + signal w_gdata_6 : std_logic; + signal wptr_7 : std_logic; + signal r_gdata_0 : std_logic; + signal r_gdata_1 : std_logic; + signal r_gdata_2 : std_logic; + signal r_gdata_3 : std_logic; + signal r_gdata_4 : std_logic; + signal r_gdata_5 : std_logic; + signal r_gdata_6 : std_logic; + signal rptr_0 : std_logic; + signal rptr_1 : std_logic; + signal rptr_2 : std_logic; + signal rptr_3 : std_logic; + signal rptr_4 : std_logic; + signal rptr_5 : std_logic; + signal rptr_6 : std_logic; + signal rptr_7 : std_logic; + signal w_gcount_0 : std_logic; + signal w_gcount_1 : std_logic; + signal w_gcount_2 : std_logic; + signal w_gcount_3 : std_logic; + signal w_gcount_4 : std_logic; + signal w_gcount_5 : std_logic; + signal w_gcount_6 : std_logic; + signal w_gcount_7 : std_logic; + signal r_gcount_0 : std_logic; + signal r_gcount_1 : std_logic; + signal r_gcount_2 : std_logic; + signal r_gcount_3 : std_logic; + signal r_gcount_4 : std_logic; + signal r_gcount_5 : std_logic; + signal r_gcount_6 : std_logic; + signal r_gcount_7 : std_logic; + signal w_gcount_r20 : std_logic; + signal w_gcount_r0 : std_logic; + signal w_gcount_r21 : std_logic; + signal w_gcount_r1 : std_logic; + signal w_gcount_r22 : std_logic; + signal w_gcount_r2 : std_logic; + signal w_gcount_r23 : std_logic; + signal w_gcount_r3 : std_logic; + signal w_gcount_r24 : std_logic; + signal w_gcount_r4 : std_logic; + signal w_gcount_r25 : std_logic; + signal w_gcount_r5 : std_logic; + signal w_gcount_r26 : std_logic; + signal w_gcount_r6 : std_logic; + signal w_gcount_r27 : std_logic; + signal w_gcount_r7 : std_logic; + signal r_gcount_w20 : std_logic; + signal r_gcount_w0 : std_logic; + signal r_gcount_w21 : std_logic; + signal r_gcount_w1 : std_logic; + signal r_gcount_w22 : std_logic; + signal r_gcount_w2 : std_logic; + signal r_gcount_w23 : std_logic; + signal r_gcount_w3 : std_logic; + signal r_gcount_w24 : std_logic; + signal r_gcount_w4 : std_logic; + signal r_gcount_w25 : std_logic; + signal r_gcount_w5 : std_logic; + signal r_gcount_w26 : std_logic; + signal r_gcount_w6 : std_logic; + signal r_gcount_w27 : std_logic; + signal r_gcount_w7 : std_logic; + signal empty_i : std_logic; + signal rRst : std_logic; + signal full_i : std_logic; + signal iwcount_0 : std_logic; + signal iwcount_1 : std_logic; + signal w_gctr_ci : std_logic; + signal iwcount_2 : std_logic; + signal iwcount_3 : std_logic; + signal co0 : std_logic; + signal iwcount_4 : std_logic; + signal iwcount_5 : std_logic; + signal co1 : std_logic; + signal iwcount_6 : std_logic; + signal iwcount_7 : std_logic; + signal co3 : std_logic; + signal wcount_7 : std_logic; + signal co2 : std_logic; + signal ircount_0 : std_logic; + signal ircount_1 : std_logic; + signal r_gctr_ci : std_logic; + signal ircount_2 : std_logic; + signal ircount_3 : std_logic; + signal co0_1 : std_logic; + signal ircount_4 : std_logic; + signal ircount_5 : std_logic; + signal co1_1 : std_logic; + signal ircount_6 : std_logic; + signal ircount_7 : std_logic; + signal co3_1 : std_logic; + signal rcount_7 : std_logic; + signal co2_1 : std_logic; + signal wfill_sub_0 : std_logic; + signal scuba_vhi : std_logic; + signal wptr_0 : std_logic; + signal wfill_sub_1 : std_logic; + signal wfill_sub_2 : std_logic; + signal co0_2 : std_logic; + signal wptr_1 : std_logic; + signal wptr_2 : std_logic; + signal wfill_sub_3 : std_logic; + signal wfill_sub_4 : std_logic; + signal co1_2 : std_logic; + signal wptr_3 : std_logic; + signal wptr_4 : std_logic; + signal wfill_sub_5 : std_logic; + signal wfill_sub_6 : std_logic; + signal co2_2 : std_logic; + signal wptr_5 : std_logic; + signal wptr_6 : std_logic; + signal wfill_sub_7 : std_logic; + signal co3_2 : std_logic; + signal wfill_sub_msb : std_logic; + signal rden_i : std_logic; + signal cmp_ci : std_logic; + signal wcount_r0 : std_logic; + signal wcount_r1 : std_logic; + signal rcount_0 : std_logic; + signal rcount_1 : std_logic; + signal co0_3 : std_logic; + signal wcount_r2 : std_logic; + signal wcount_r3 : std_logic; + signal rcount_2 : std_logic; + signal rcount_3 : std_logic; + signal co1_3 : std_logic; + signal w_g2b_xor_cluster_0 : std_logic; + signal wcount_r5 : std_logic; + signal rcount_4 : std_logic; + signal rcount_5 : std_logic; + signal co2_3 : std_logic; + signal wcount_r6 : std_logic; + signal empty_cmp_clr : std_logic; + signal rcount_6 : std_logic; + signal empty_cmp_set : std_logic; + signal empty_d : std_logic; + signal empty_d_c : std_logic; + signal wren_i : std_logic; + signal cmp_ci_1 : std_logic; + signal rcount_w0 : std_logic; + signal rcount_w1 : std_logic; + signal wcount_0 : std_logic; + signal wcount_1 : std_logic; + signal co0_4 : std_logic; + signal rcount_w2 : std_logic; + signal rcount_w3 : std_logic; + signal wcount_2 : std_logic; + signal wcount_3 : std_logic; + signal co1_4 : std_logic; + signal r_g2b_xor_cluster_0 : std_logic; + signal rcount_w5 : std_logic; + signal wcount_4 : std_logic; + signal wcount_5 : std_logic; + signal co2_4 : std_logic; + signal rcount_w6 : std_logic; + signal full_cmp_clr : std_logic; + signal wcount_6 : std_logic; + signal full_cmp_set : std_logic; + signal full_d : std_logic; + signal full_d_c : std_logic; + signal scuba_vlo : std_logic; + + -- local component declarations + component AGEB2 + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; GE : out std_logic); + end component; + component AND2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component CU2 + port (CI : in std_logic; PC0 : in std_logic; PC1 : in std_logic; + CO : out std_logic; NC0 : out std_logic; NC1 : out std_logic); + end component; + component FADD2B + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; CI : in std_logic; COUT : out std_logic; + S0 : out std_logic; S1 : out std_logic); + end component; + component FSUB2B + port (A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; + B1 : in std_logic; BI : in std_logic; BOUT : out std_logic; + S0 : out std_logic; S1 : out std_logic); + end component; + component FD1P3BX + port (D : in std_logic; SP : in std_logic; CK : in std_logic; + PD : in std_logic; Q : out std_logic); + end component; + component FD1P3DX + port (D : in std_logic; SP : in std_logic; CK : in std_logic; + CD : in std_logic; Q : out std_logic); + end component; + component FD1S3BX + port (D : in std_logic; CK : in std_logic; PD : in std_logic; + Q : out std_logic); + end component; + component FD1S3DX + port (D : in std_logic; CK : in std_logic; CD : in std_logic; + Q : out std_logic); + end component; + component INV + port (A : in std_logic; Z : out std_logic); + end component; + component OR2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3 : in std_logic; AD2 : in std_logic; AD1 : in std_logic; + AD0 : in std_logic; DO0 : out std_logic); + end component; + component VHI + port (Z : out std_logic); + end component; + component VLO + port (Z : out std_logic); + end component; + component XOR2 + port (A : in std_logic; B : in std_logic; Z : out std_logic); + end component; + component PDPW16KC + generic (GSR : in string; CSDECODE_R : in string; + CSDECODE_W : in string; REGMODE : in string; + DATA_WIDTH_R : in integer; DATA_WIDTH_W : in integer); + port (DI0 : in std_logic; DI1 : in std_logic; DI2 : in std_logic; + DI3 : in std_logic; DI4 : in std_logic; DI5 : in std_logic; + DI6 : in std_logic; DI7 : in std_logic; DI8 : in std_logic; + DI9 : in std_logic; DI10 : in std_logic; DI11 : in std_logic; + DI12 : in std_logic; DI13 : in std_logic; + DI14 : in std_logic; DI15 : in std_logic; + DI16 : in std_logic; DI17 : in std_logic; + DI18 : in std_logic; DI19 : in std_logic; + DI20 : in std_logic; DI21 : in std_logic; + DI22 : in std_logic; DI23 : in std_logic; + DI24 : in std_logic; DI25 : in std_logic; + DI26 : in std_logic; DI27 : in std_logic; + DI28 : in std_logic; DI29 : in std_logic; + DI30 : in std_logic; DI31 : in std_logic; + DI32 : in std_logic; DI33 : in std_logic; + DI34 : in std_logic; DI35 : in std_logic; + ADW0 : in std_logic; ADW1 : in std_logic; + ADW2 : in std_logic; ADW3 : in std_logic; + ADW4 : in std_logic; ADW5 : in std_logic; + ADW6 : in std_logic; ADW7 : in std_logic; + ADW8 : in std_logic; BE0 : in std_logic; BE1 : in std_logic; + BE2 : in std_logic; BE3 : in std_logic; CEW : in std_logic; + CLKW : in std_logic; CSW0 : in std_logic; + CSW1 : in std_logic; CSW2 : in std_logic; + ADR0 : in std_logic; ADR1 : in std_logic; + ADR2 : in std_logic; ADR3 : in std_logic; + ADR4 : in std_logic; ADR5 : in std_logic; + ADR6 : in std_logic; ADR7 : in std_logic; + ADR8 : in std_logic; ADR9 : in std_logic; + ADR10 : in std_logic; ADR11 : in std_logic; + ADR12 : in std_logic; ADR13 : in std_logic; + CER : in std_logic; CLKR : in std_logic; CSR0 : in std_logic; + CSR1 : in std_logic; CSR2 : in std_logic; RST : in std_logic; + DO0 : out std_logic; DO1 : out std_logic; + DO2 : out std_logic; DO3 : out std_logic; + DO4 : out std_logic; DO5 : out std_logic; + DO6 : out std_logic; DO7 : out std_logic; + DO8 : out std_logic; DO9 : out std_logic; + DO10 : out std_logic; DO11 : out std_logic; + DO12 : out std_logic; DO13 : out std_logic; + DO14 : out std_logic; DO15 : out std_logic; + DO16 : out std_logic; DO17 : out std_logic; + DO18 : out std_logic; DO19 : out std_logic; + DO20 : out std_logic; DO21 : out std_logic; + DO22 : out std_logic; DO23 : out std_logic; + DO24 : out std_logic; DO25 : out std_logic; + DO26 : out std_logic; DO27 : out std_logic; + DO28 : out std_logic; DO29 : out std_logic; + DO30 : out std_logic; DO31 : out std_logic; + DO32 : out std_logic; DO33 : out std_logic; + DO34 : out std_logic; DO35 : out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x128_OutReg_Counter.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t17 : AND2 + port map (A => WrEn, B => invout_1, Z => wren_i); + + INV_1 : INV + port map (A => full_i, Z => invout_1); + + AND2_t16 : AND2 + port map (A => RdEn, B => invout_0, Z => rden_i); + + INV_0 : INV + port map (A => empty_i, Z => invout_0); + + OR2_t15 : OR2 + port map (A => Reset, B => RPReset, Z => rRst); + + XOR2_t14 : XOR2 + port map (A => wcount_0, B => wcount_1, Z => w_gdata_0); + + XOR2_t13 : XOR2 + port map (A => wcount_1, B => wcount_2, Z => w_gdata_1); + + XOR2_t12 : XOR2 + port map (A => wcount_2, B => wcount_3, Z => w_gdata_2); + + XOR2_t11 : XOR2 + port map (A => wcount_3, B => wcount_4, Z => w_gdata_3); + + XOR2_t10 : XOR2 + port map (A => wcount_4, B => wcount_5, Z => w_gdata_4); + + XOR2_t9 : XOR2 + port map (A => wcount_5, B => wcount_6, Z => w_gdata_5); + + XOR2_t8 : XOR2 + port map (A => wcount_6, B => wcount_7, Z => w_gdata_6); + + XOR2_t7 : XOR2 + port map (A => rcount_0, B => rcount_1, Z => r_gdata_0); + + XOR2_t6 : XOR2 + port map (A => rcount_1, B => rcount_2, Z => r_gdata_1); + + XOR2_t5 : XOR2 + port map (A => rcount_2, B => rcount_3, Z => r_gdata_2); + + XOR2_t4 : XOR2 + port map (A => rcount_3, B => rcount_4, Z => r_gdata_3); + + XOR2_t3 : XOR2 + port map (A => rcount_4, B => rcount_5, Z => r_gdata_4); + + XOR2_t2 : XOR2 + port map (A => rcount_5, B => rcount_6, Z => r_gdata_5); + + XOR2_t1 : XOR2 + port map (A => rcount_6, B => rcount_7, Z => r_gdata_6); + + LUT4_19 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r24, AD2 => w_gcount_r25, + AD1 => w_gcount_r26, AD0 => w_gcount_r27, + DO0 => w_g2b_xor_cluster_0); + + LUT4_18 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r20, AD2 => w_gcount_r21, + AD1 => w_gcount_r22, AD0 => w_gcount_r23, + DO0 => w_g2b_xor_cluster_1); + + LUT4_17 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r26, AD2 => w_gcount_r27, AD1 => scuba_vlo, + AD0 => scuba_vlo, DO0 => wcount_r6); + + LUT4_16 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r25, AD2 => w_gcount_r26, + AD1 => w_gcount_r27, AD0 => scuba_vlo, DO0 => wcount_r5); + + LUT4_15 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r23, AD2 => w_gcount_r24, + AD1 => w_gcount_r25, AD0 => wcount_r6, DO0 => wcount_r3); + + LUT4_14 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r22, AD2 => w_gcount_r23, + AD1 => w_gcount_r24, AD0 => wcount_r5, DO0 => wcount_r2); + + LUT4_13 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_gcount_r21, AD2 => w_gcount_r22, + AD1 => w_gcount_r23, AD0 => w_g2b_xor_cluster_0, DO0 => wcount_r1); + + LUT4_12 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => w_g2b_xor_cluster_0, AD2 => w_g2b_xor_cluster_1, + AD1 => scuba_vlo, AD0 => scuba_vlo, DO0 => wcount_r0); + + LUT4_11 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w24, AD2 => r_gcount_w25, + AD1 => r_gcount_w26, AD0 => r_gcount_w27, + DO0 => r_g2b_xor_cluster_0); + + LUT4_10 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w20, AD2 => r_gcount_w21, + AD1 => r_gcount_w22, AD0 => r_gcount_w23, + DO0 => r_g2b_xor_cluster_1); + + LUT4_9 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w26, AD2 => r_gcount_w27, AD1 => scuba_vlo, + AD0 => scuba_vlo, DO0 => rcount_w6); + + LUT4_8 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w25, AD2 => r_gcount_w26, + AD1 => r_gcount_w27, AD0 => scuba_vlo, DO0 => rcount_w5); + + LUT4_7 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w23, AD2 => r_gcount_w24, + AD1 => r_gcount_w25, AD0 => rcount_w6, DO0 => rcount_w3); + + LUT4_6 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w22, AD2 => r_gcount_w23, + AD1 => r_gcount_w24, AD0 => rcount_w5, DO0 => rcount_w2); + + LUT4_5 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_gcount_w21, AD2 => r_gcount_w22, + AD1 => r_gcount_w23, AD0 => r_g2b_xor_cluster_0, DO0 => rcount_w1); + + LUT4_4 : ROM16X1A + generic map (initval => X"6996") + port map (AD3 => r_g2b_xor_cluster_0, AD2 => r_g2b_xor_cluster_1, + AD1 => scuba_vlo, AD0 => scuba_vlo, DO0 => rcount_w0); + + XOR2_t0 : XOR2 + port map (A => wptr_7, B => r_gcount_w27, Z => wfill_sub_msb); + + LUT4_3 : ROM16X1A + generic map (initval => X"0410") + port map (AD3 => rptr_7, AD2 => rcount_7, AD1 => w_gcount_r27, + AD0 => scuba_vlo, DO0 => empty_cmp_set); + + LUT4_2 : ROM16X1A + generic map (initval => X"1004") + port map (AD3 => rptr_7, AD2 => rcount_7, AD1 => w_gcount_r27, + AD0 => scuba_vlo, DO0 => empty_cmp_clr); + + LUT4_1 : ROM16X1A + generic map (initval => X"0140") + port map (AD3 => wptr_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => scuba_vlo, DO0 => full_cmp_set); + + LUT4_0 : ROM16X1A + generic map (initval => X"4001") + port map (AD3 => wptr_7, AD2 => wcount_7, AD1 => r_gcount_w27, + AD0 => scuba_vlo, DO0 => full_cmp_clr); + + pdp_ram_0_0_0 : PDPW16KC + generic map (CSDECODE_R => "0b001", CSDECODE_W => "0b001", GSR => "DISABLED", + REGMODE => "OUTREG", DATA_WIDTH_R => 36, DATA_WIDTH_W => 36) + port map (DI0 => Data(0), DI1 => Data(1), DI2 => Data(2), DI3 => Data(3), + DI4 => Data(4), DI5 => Data(5), DI6 => Data(6), DI7 => Data(7), + DI8 => Data(8), DI9 => Data(9), DI10 => Data(10), DI11 => Data(11), + DI12 => Data(12), DI13 => Data(13), DI14 => Data(14), + DI15 => Data(15), DI16 => Data(16), DI17 => Data(17), + DI18 => Data(18), DI19 => Data(19), DI20 => Data(20), + DI21 => Data(21), DI22 => Data(22), DI23 => Data(23), + DI24 => Data(24), DI25 => Data(25), DI26 => Data(26), + DI27 => Data(27), DI28 => Data(28), DI29 => Data(29), + DI30 => Data(30), DI31 => Data(31), DI32 => Data(32), + DI33 => Data(33), DI34 => Data(34), DI35 => Data(35), ADW0 => wptr_0, + ADW1 => wptr_1, ADW2 => wptr_2, ADW3 => wptr_3, ADW4 => wptr_4, + ADW5 => wptr_5, ADW6 => wptr_6, ADW7 => scuba_vlo, ADW8 => scuba_vlo, + BE0 => scuba_vhi, BE1 => scuba_vhi, BE2 => scuba_vhi, + BE3 => scuba_vhi, CEW => wren_i, CLKW => WrClock, CSW0 => scuba_vhi, + CSW1 => scuba_vlo, CSW2 => scuba_vlo, ADR0 => scuba_vlo, + ADR1 => scuba_vlo, ADR2 => scuba_vlo, ADR3 => scuba_vlo, + ADR4 => scuba_vlo, ADR5 => rptr_0, ADR6 => rptr_1, ADR7 => rptr_2, + ADR8 => rptr_3, ADR9 => rptr_4, ADR10 => rptr_5, ADR11 => rptr_6, + ADR12 => scuba_vlo, ADR13 => scuba_vlo, CER => scuba_vhi, + CLKR => RdClock, CSR0 => rden_i, CSR1 => scuba_vlo, + CSR2 => scuba_vlo, RST => Reset, DO0 => Q(18), DO1 => Q(19), + DO2 => Q(20), DO3 => Q(21), DO4 => Q(22), DO5 => Q(23), DO6 => Q(24), + DO7 => Q(25), DO8 => Q(26), DO9 => Q(27), DO10 => Q(28), DO11 => Q(29), + DO12 => Q(30), DO13 => Q(31), DO14 => Q(32), DO15 => Q(33), + DO16 => Q(34), DO17 => Q(35), DO18 => Q(0), DO19 => Q(1), DO20 => Q(2), + DO21 => Q(3), DO22 => Q(4), DO23 => Q(5), DO24 => Q(6), DO25 => Q(7), + DO26 => Q(8), DO27 => Q(9), DO28 => Q(10), DO29 => Q(11), + DO30 => Q(12), DO31 => Q(13), DO32 => Q(14), DO33 => Q(15), + DO34 => Q(16), DO35 => Q(17)); + + FF_89 : FD1P3BX + port map (D => iwcount_0, SP => wren_i, CK => WrClock, PD => Reset, + Q => wcount_0); + + FF_88 : FD1P3DX + port map (D => iwcount_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_1); + + FF_87 : FD1P3DX + port map (D => iwcount_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_2); + + FF_86 : FD1P3DX + port map (D => iwcount_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_3); + + FF_85 : FD1P3DX + port map (D => iwcount_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_4); + + FF_84 : FD1P3DX + port map (D => iwcount_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_5); + + FF_83 : FD1P3DX + port map (D => iwcount_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_6); + + FF_82 : FD1P3DX + port map (D => iwcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => wcount_7); + + FF_81 : FD1P3DX + port map (D => w_gdata_0, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_0); + + FF_80 : FD1P3DX + port map (D => w_gdata_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_1); + + FF_79 : FD1P3DX + port map (D => w_gdata_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_2); + + FF_78 : FD1P3DX + port map (D => w_gdata_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_3); + + FF_77 : FD1P3DX + port map (D => w_gdata_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_4); + + FF_76 : FD1P3DX + port map (D => w_gdata_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_5); + + FF_75 : FD1P3DX + port map (D => w_gdata_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_6); + + FF_74 : FD1P3DX + port map (D => wcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => w_gcount_7); + + FF_73 : FD1P3DX + port map (D => wcount_0, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_0); + + FF_72 : FD1P3DX + port map (D => wcount_1, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_1); + + FF_71 : FD1P3DX + port map (D => wcount_2, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_2); + + FF_70 : FD1P3DX + port map (D => wcount_3, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_3); + + FF_69 : FD1P3DX + port map (D => wcount_4, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_4); + + FF_68 : FD1P3DX + port map (D => wcount_5, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_5); + + FF_67 : FD1P3DX + port map (D => wcount_6, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_6); + + FF_66 : FD1P3DX + port map (D => wcount_7, SP => wren_i, CK => WrClock, CD => Reset, + Q => wptr_7); + + FF_65 : FD1P3BX + port map (D => ircount_0, SP => rden_i, CK => RdClock, PD => rRst, + Q => rcount_0); + + FF_64 : FD1P3DX + port map (D => ircount_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_1); + + FF_63 : FD1P3DX + port map (D => ircount_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_2); + + FF_62 : FD1P3DX + port map (D => ircount_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_3); + + FF_61 : FD1P3DX + port map (D => ircount_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_4); + + FF_60 : FD1P3DX + port map (D => ircount_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_5); + + FF_59 : FD1P3DX + port map (D => ircount_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_6); + + FF_58 : FD1P3DX + port map (D => ircount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => rcount_7); + + FF_57 : FD1P3DX + port map (D => r_gdata_0, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_0); + + FF_56 : FD1P3DX + port map (D => r_gdata_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_1); + + FF_55 : FD1P3DX + port map (D => r_gdata_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_2); + + FF_54 : FD1P3DX + port map (D => r_gdata_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_3); + + FF_53 : FD1P3DX + port map (D => r_gdata_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_4); + + FF_52 : FD1P3DX + port map (D => r_gdata_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_5); + + FF_51 : FD1P3DX + port map (D => r_gdata_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_6); + + FF_50 : FD1P3DX + port map (D => rcount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => r_gcount_7); + + FF_49 : FD1P3DX + port map (D => rcount_0, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_0); + + FF_48 : FD1P3DX + port map (D => rcount_1, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_1); + + FF_47 : FD1P3DX + port map (D => rcount_2, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_2); + + FF_46 : FD1P3DX + port map (D => rcount_3, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_3); + + FF_45 : FD1P3DX + port map (D => rcount_4, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_4); + + FF_44 : FD1P3DX + port map (D => rcount_5, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_5); + + FF_43 : FD1P3DX + port map (D => rcount_6, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_6); + + FF_42 : FD1P3DX + port map (D => rcount_7, SP => rden_i, CK => RdClock, CD => rRst, + Q => rptr_7); + + FF_41 : FD1S3DX + port map (D => w_gcount_0, CK => RdClock, CD => Reset, Q => w_gcount_r0); + + FF_40 : FD1S3DX + port map (D => w_gcount_1, CK => RdClock, CD => Reset, Q => w_gcount_r1); + + FF_39 : FD1S3DX + port map (D => w_gcount_2, CK => RdClock, CD => Reset, Q => w_gcount_r2); + + FF_38 : FD1S3DX + port map (D => w_gcount_3, CK => RdClock, CD => Reset, Q => w_gcount_r3); + + FF_37 : FD1S3DX + port map (D => w_gcount_4, CK => RdClock, CD => Reset, Q => w_gcount_r4); + + FF_36 : FD1S3DX + port map (D => w_gcount_5, CK => RdClock, CD => Reset, Q => w_gcount_r5); + + FF_35 : FD1S3DX + port map (D => w_gcount_6, CK => RdClock, CD => Reset, Q => w_gcount_r6); + + FF_34 : FD1S3DX + port map (D => w_gcount_7, CK => RdClock, CD => Reset, Q => w_gcount_r7); + + FF_33 : FD1S3DX + port map (D => r_gcount_0, CK => WrClock, CD => rRst, Q => r_gcount_w0); + + FF_32 : FD1S3DX + port map (D => r_gcount_1, CK => WrClock, CD => rRst, Q => r_gcount_w1); + + FF_31 : FD1S3DX + port map (D => r_gcount_2, CK => WrClock, CD => rRst, Q => r_gcount_w2); + + FF_30 : FD1S3DX + port map (D => r_gcount_3, CK => WrClock, CD => rRst, Q => r_gcount_w3); + + FF_29 : FD1S3DX + port map (D => r_gcount_4, CK => WrClock, CD => rRst, Q => r_gcount_w4); + + FF_28 : FD1S3DX + port map (D => r_gcount_5, CK => WrClock, CD => rRst, Q => r_gcount_w5); + + FF_27 : FD1S3DX + port map (D => r_gcount_6, CK => WrClock, CD => rRst, Q => r_gcount_w6); + + FF_26 : FD1S3DX + port map (D => r_gcount_7, CK => WrClock, CD => rRst, Q => r_gcount_w7); + + FF_25 : FD1S3DX + port map (D => w_gcount_r0, CK => RdClock, CD => Reset, + Q => w_gcount_r20); + + FF_24 : FD1S3DX + port map (D => w_gcount_r1, CK => RdClock, CD => Reset, + Q => w_gcount_r21); + + FF_23 : FD1S3DX + port map (D => w_gcount_r2, CK => RdClock, CD => Reset, + Q => w_gcount_r22); + + FF_22 : FD1S3DX + port map (D => w_gcount_r3, CK => RdClock, CD => Reset, + Q => w_gcount_r23); + + FF_21 : FD1S3DX + port map (D => w_gcount_r4, CK => RdClock, CD => Reset, + Q => w_gcount_r24); + + FF_20 : FD1S3DX + port map (D => w_gcount_r5, CK => RdClock, CD => Reset, + Q => w_gcount_r25); + + FF_19 : FD1S3DX + port map (D => w_gcount_r6, CK => RdClock, CD => Reset, + Q => w_gcount_r26); + + FF_18 : FD1S3DX + port map (D => w_gcount_r7, CK => RdClock, CD => Reset, + Q => w_gcount_r27); + + FF_17 : FD1S3DX + port map (D => r_gcount_w0, CK => WrClock, CD => rRst, Q => r_gcount_w20); + + FF_16 : FD1S3DX + port map (D => r_gcount_w1, CK => WrClock, CD => rRst, Q => r_gcount_w21); + + FF_15 : FD1S3DX + port map (D => r_gcount_w2, CK => WrClock, CD => rRst, Q => r_gcount_w22); + + FF_14 : FD1S3DX + port map (D => r_gcount_w3, CK => WrClock, CD => rRst, Q => r_gcount_w23); + + FF_13 : FD1S3DX + port map (D => r_gcount_w4, CK => WrClock, CD => rRst, Q => r_gcount_w24); + + FF_12 : FD1S3DX + port map (D => r_gcount_w5, CK => WrClock, CD => rRst, Q => r_gcount_w25); + + FF_11 : FD1S3DX + port map (D => r_gcount_w6, CK => WrClock, CD => rRst, Q => r_gcount_w26); + + FF_10 : FD1S3DX + port map (D => r_gcount_w7, CK => WrClock, CD => rRst, Q => r_gcount_w27); + + FF_9 : FD1S3DX + port map (D => wfill_sub_0, CK => WrClock, CD => Reset, Q => WCNT(0)); + + FF_8 : FD1S3DX + port map (D => wfill_sub_1, CK => WrClock, CD => Reset, Q => WCNT(1)); + + FF_7 : FD1S3DX + port map (D => wfill_sub_2, CK => WrClock, CD => Reset, Q => WCNT(2)); + + FF_6 : FD1S3DX + port map (D => wfill_sub_3, CK => WrClock, CD => Reset, Q => WCNT(3)); + + FF_5 : FD1S3DX + port map (D => wfill_sub_4, CK => WrClock, CD => Reset, Q => WCNT(4)); + + FF_4 : FD1S3DX + port map (D => wfill_sub_5, CK => WrClock, CD => Reset, Q => WCNT(5)); + + FF_3 : FD1S3DX + port map (D => wfill_sub_6, CK => WrClock, CD => Reset, Q => WCNT(6)); + + FF_2 : FD1S3DX + port map (D => wfill_sub_7, CK => WrClock, CD => Reset, Q => WCNT(7)); + + FF_1 : FD1S3BX + port map (D => empty_d, CK => RdClock, PD => rRst, Q => empty_i); + + FF_0 : FD1S3DX + port map (D => full_d, CK => WrClock, CD => Reset, Q => full_i); + + w_gctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => w_gctr_ci, S0 => open, + S1 => open); + + w_gctr_0 : CU2 + port map (CI => w_gctr_ci, PC0 => wcount_0, PC1 => wcount_1, CO => co0, + NC0 => iwcount_0, NC1 => iwcount_1); + + w_gctr_1 : CU2 + port map (CI => co0, PC0 => wcount_2, PC1 => wcount_3, CO => co1, + NC0 => iwcount_2, NC1 => iwcount_3); + + w_gctr_2 : CU2 + port map (CI => co1, PC0 => wcount_4, PC1 => wcount_5, CO => co2, + NC0 => iwcount_4, NC1 => iwcount_5); + + w_gctr_3 : CU2 + port map (CI => co2, PC0 => wcount_6, PC1 => wcount_7, CO => co3, + NC0 => iwcount_6, NC1 => iwcount_7); + + r_gctr_cia : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vhi, B0 => scuba_vlo, + B1 => scuba_vhi, CI => scuba_vlo, COUT => r_gctr_ci, S0 => open, + S1 => open); + + r_gctr_0 : CU2 + port map (CI => r_gctr_ci, PC0 => rcount_0, PC1 => rcount_1, CO => co0_1, + NC0 => ircount_0, NC1 => ircount_1); + + r_gctr_1 : CU2 + port map (CI => co0_1, PC0 => rcount_2, PC1 => rcount_3, CO => co1_1, + NC0 => ircount_2, NC1 => ircount_3); + + r_gctr_2 : CU2 + port map (CI => co1_1, PC0 => rcount_4, PC1 => rcount_5, CO => co2_1, + NC0 => ircount_4, NC1 => ircount_5); + + r_gctr_3 : CU2 + port map (CI => co2_1, PC0 => rcount_6, PC1 => rcount_7, CO => co3_1, + NC0 => ircount_6, NC1 => ircount_7); + + scuba_vhi_inst : VHI + port map (Z => scuba_vhi); + + wfill_0 : FSUB2B + port map (A0 => scuba_vhi, A1 => wptr_0, B0 => scuba_vlo, + B1 => rcount_w0, BI => scuba_vlo, BOUT => co0_2, S0 => open, + S1 => wfill_sub_0); + + wfill_1 : FSUB2B + port map (A0 => wptr_1, A1 => wptr_2, B0 => rcount_w1, B1 => rcount_w2, + BI => co0_2, BOUT => co1_2, S0 => wfill_sub_1, S1 => wfill_sub_2); + + wfill_2 : FSUB2B + port map (A0 => wptr_3, A1 => wptr_4, B0 => rcount_w3, + B1 => r_g2b_xor_cluster_0, BI => co1_2, BOUT => co2_2, + S0 => wfill_sub_3, S1 => wfill_sub_4); + + wfill_3 : FSUB2B + port map (A0 => wptr_5, A1 => wptr_6, B0 => rcount_w5, B1 => rcount_w6, + BI => co2_2, BOUT => co3_2, S0 => wfill_sub_5, S1 => wfill_sub_6); + + wfill_4 : FSUB2B + port map (A0 => wfill_sub_msb, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, BI => co3_2, BOUT => open, S0 => wfill_sub_7, + S1 => open); + + empty_cmp_ci_a : FADD2B + port map (A0 => scuba_vlo, A1 => rden_i, B0 => scuba_vlo, B1 => rden_i, + CI => scuba_vlo, COUT => cmp_ci, S0 => open, S1 => open); + + empty_cmp_0 : AGEB2 + port map (A0 => rcount_0, A1 => rcount_1, B0 => wcount_r0, + B1 => wcount_r1, CI => cmp_ci, GE => co0_3); + + empty_cmp_1 : AGEB2 + port map (A0 => rcount_2, A1 => rcount_3, B0 => wcount_r2, + B1 => wcount_r3, CI => co0_3, GE => co1_3); + + empty_cmp_2 : AGEB2 + port map (A0 => rcount_4, A1 => rcount_5, B0 => w_g2b_xor_cluster_0, + B1 => wcount_r5, CI => co1_3, GE => co2_3); + + empty_cmp_3 : AGEB2 + port map (A0 => rcount_6, A1 => empty_cmp_set, B0 => wcount_r6, + B1 => empty_cmp_clr, CI => co2_3, GE => empty_d_c); + + a0 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => empty_d_c, COUT => open, S0 => empty_d, + S1 => open); + + full_cmp_ci_a : FADD2B + port map (A0 => scuba_vlo, A1 => wren_i, B0 => scuba_vlo, B1 => wren_i, + CI => scuba_vlo, COUT => cmp_ci_1, S0 => open, S1 => open); + + full_cmp_0 : AGEB2 + port map (A0 => wcount_0, A1 => wcount_1, B0 => rcount_w0, + B1 => rcount_w1, CI => cmp_ci_1, GE => co0_4); + + full_cmp_1 : AGEB2 + port map (A0 => wcount_2, A1 => wcount_3, B0 => rcount_w2, + B1 => rcount_w3, CI => co0_4, GE => co1_4); + + full_cmp_2 : AGEB2 + port map (A0 => wcount_4, A1 => wcount_5, B0 => r_g2b_xor_cluster_0, + B1 => rcount_w5, CI => co1_4, GE => co2_4); + + full_cmp_3 : AGEB2 + port map (A0 => wcount_6, A1 => full_cmp_set, B0 => rcount_w6, + B1 => full_cmp_clr, CI => co2_4, GE => full_d_c); + + scuba_vlo_inst : VLO + port map (Z => scuba_vlo); + + a1 : FADD2B + port map (A0 => scuba_vlo, A1 => scuba_vlo, B0 => scuba_vlo, + B1 => scuba_vlo, CI => full_d_c, COUT => open, S0 => full_d, + S1 => open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_36x128_OutReg_Counter is + for Structure + for all : AGEB2 use entity ecp3.AGEB2(V); end for; + for all : AND2 use entity ecp3.AND2(V); end for; + for all : CU2 use entity ecp3.CU2(V); end for; + for all : FADD2B use entity ecp3.FADD2B(V); end for; + for all : FSUB2B use entity ecp3.FSUB2B(V); end for; + for all : FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all : FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all : FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all : INV use entity ecp3.INV(V); end for; + for all : OR2 use entity ecp3.OR2(V); end for; + for all : ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all : VHI use entity ecp3.VHI(V); end for; + for all : VLO use entity ecp3.VLO(V); end for; + for all : XOR2 use entity ecp3.XOR2(V); end for; + for all : PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/tdc_releases/tdc_v2.0/LogicAnalyser.vhd b/tdc_releases/tdc_v2.0/LogicAnalyser.vhd index 66df513..52320bc 100644 --- a/tdc_releases/tdc_v2.0/LogicAnalyser.vhd +++ b/tdc_releases/tdc_v2.0/LogicAnalyser.vhd @@ -5,7 +5,7 @@ -- File : LogicAnalyser.vhd -- Author : cugur@gsi.de -- Created : 2012-10-26 --- Last update: 2012-10-26 +-- Last update: 2014-06-16 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -21,8 +21,7 @@ use work.trb3_components.all; entity LogicAnalyser is generic ( - CHANNEL_NUMBER : integer range 2 to 65; - STATUS_REG_NR : integer range 0 to 6); + CHANNEL_NUMBER : integer range 2 to 64); port ( CLK : in std_logic; diff --git a/tdc_releases/tdc_v2.0/ROM_encoder_3.vhd b/tdc_releases/tdc_v2.0/ROM_encoder_3.vhd deleted file mode 100644 index 765bf32..0000000 --- a/tdc_releases/tdc_v2.0/ROM_encoder_3.vhd +++ /dev/null @@ -1,262 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) --- Module Version: 5.0 ---/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 8 -num_rows 1024 -outdata REGISTERED -memfile /home/ugur/projects/encoder/encoder_304_with_more_bbl_errors/source/rom_encoder.mem -memformat orca -cascade -1 -e - --- Mon Apr 16 15:10:22 2012 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity ROM_Encoder is - port ( - Address : in std_logic_vector(9 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(7 downto 0)); -end ROM_Encoder; - -architecture Structure of ROM_Encoder is - - -- internal signal declarations - signal scuba_vhi : std_logic; - signal scuba_vlo : std_logic; - - -- local component declarations - component VHI - port (Z : out std_logic); - end component; - component VLO - port (Z : out std_logic); - end component; - component DP16KC - generic (INITVAL_3F : in string; INITVAL_3E : in string; - INITVAL_3D : in string; INITVAL_3C : in string; - INITVAL_3B : in string; INITVAL_3A : in string; - INITVAL_39 : in string; INITVAL_38 : in string; - INITVAL_37 : in string; INITVAL_36 : in string; - INITVAL_35 : in string; INITVAL_34 : in string; - INITVAL_33 : in string; INITVAL_32 : in string; - INITVAL_31 : in string; INITVAL_30 : in string; - INITVAL_2F : in string; INITVAL_2E : in string; - INITVAL_2D : in string; INITVAL_2C : in string; - INITVAL_2B : in string; INITVAL_2A : in string; - INITVAL_29 : in string; INITVAL_28 : in string; - INITVAL_27 : in string; INITVAL_26 : in string; - INITVAL_25 : in string; INITVAL_24 : in string; - INITVAL_23 : in string; INITVAL_22 : in string; - INITVAL_21 : in string; INITVAL_20 : in string; - INITVAL_1F : in string; INITVAL_1E : in string; - INITVAL_1D : in string; INITVAL_1C : in string; - INITVAL_1B : in string; INITVAL_1A : in string; - INITVAL_19 : in string; INITVAL_18 : in string; - INITVAL_17 : in string; INITVAL_16 : in string; - INITVAL_15 : in string; INITVAL_14 : in string; - INITVAL_13 : in string; INITVAL_12 : in string; - INITVAL_11 : in string; INITVAL_10 : in string; - INITVAL_0F : in string; INITVAL_0E : in string; - INITVAL_0D : in string; INITVAL_0C : in string; - INITVAL_0B : in string; INITVAL_0A : in string; - INITVAL_09 : in string; INITVAL_08 : in string; - INITVAL_07 : in string; INITVAL_06 : in string; - INITVAL_05 : in string; INITVAL_04 : in string; - INITVAL_03 : in string; INITVAL_02 : in string; - INITVAL_01 : in string; INITVAL_00 : in string; - GSR : in string; WRITEMODE_B : in string; - WRITEMODE_A : in string; CSDECODE_B : in string; - CSDECODE_A : in string; REGMODE_B : in string; - REGMODE_A : in string; DATA_WIDTH_B : in integer; - DATA_WIDTH_A : in integer); - port (DIA0 : in std_logic; DIA1 : in std_logic; - DIA2 : in std_logic; DIA3 : in std_logic; - DIA4 : in std_logic; DIA5 : in std_logic; - DIA6 : in std_logic; DIA7 : in std_logic; - DIA8 : in std_logic; DIA9 : in std_logic; - DIA10 : in std_logic; DIA11 : in std_logic; - DIA12 : in std_logic; DIA13 : in std_logic; - DIA14 : in std_logic; DIA15 : in std_logic; - DIA16 : in std_logic; DIA17 : in std_logic; - ADA0 : in std_logic; ADA1 : in std_logic; - ADA2 : in std_logic; ADA3 : in std_logic; - ADA4 : in std_logic; ADA5 : in std_logic; - ADA6 : in std_logic; ADA7 : in std_logic; - ADA8 : in std_logic; ADA9 : in std_logic; - ADA10 : in std_logic; ADA11 : in std_logic; - ADA12 : in std_logic; ADA13 : in std_logic; - CEA : in std_logic; CLKA : in std_logic; OCEA : in std_logic; - WEA : in std_logic; CSA0 : in std_logic; CSA1 : in std_logic; - CSA2 : in std_logic; RSTA : in std_logic; - DIB0 : in std_logic; DIB1 : in std_logic; - DIB2 : in std_logic; DIB3 : in std_logic; - DIB4 : in std_logic; DIB5 : in std_logic; - DIB6 : in std_logic; DIB7 : in std_logic; - DIB8 : in std_logic; DIB9 : in std_logic; - DIB10 : in std_logic; DIB11 : in std_logic; - DIB12 : in std_logic; DIB13 : in std_logic; - DIB14 : in std_logic; DIB15 : in std_logic; - DIB16 : in std_logic; DIB17 : in std_logic; - ADB0 : in std_logic; ADB1 : in std_logic; - ADB2 : in std_logic; ADB3 : in std_logic; - ADB4 : in std_logic; ADB5 : in std_logic; - ADB6 : in std_logic; ADB7 : in std_logic; - ADB8 : in std_logic; ADB9 : in std_logic; - ADB10 : in std_logic; ADB11 : in std_logic; - ADB12 : in std_logic; ADB13 : in std_logic; - CEB : in std_logic; CLKB : in std_logic; OCEB : in std_logic; - WEB : in std_logic; CSB0 : in std_logic; CSB1 : in std_logic; - CSB2 : in std_logic; RSTB : in std_logic; - DOA0 : out std_logic; DOA1 : out std_logic; - DOA2 : out std_logic; DOA3 : out std_logic; - DOA4 : out std_logic; DOA5 : out std_logic; - DOA6 : out std_logic; DOA7 : out std_logic; - DOA8 : out std_logic; DOA9 : out std_logic; - DOA10 : out std_logic; DOA11 : out std_logic; - DOA12 : out std_logic; DOA13 : out std_logic; - DOA14 : out std_logic; DOA15 : out std_logic; - DOA16 : out std_logic; DOA17 : out std_logic; - DOB0 : out std_logic; DOB1 : out std_logic; - DOB2 : out std_logic; DOB3 : out std_logic; - DOB4 : out std_logic; DOB5 : out std_logic; - DOB6 : out std_logic; DOB7 : out std_logic; - DOB8 : out std_logic; DOB9 : out std_logic; - DOB10 : out std_logic; DOB11 : out std_logic; - DOB12 : out std_logic; DOB13 : out std_logic; - DOB14 : out std_logic; DOB15 : out std_logic; - DOB16 : out std_logic; DOB17 : out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute MEM_LPC_FILE of ROM_Encoder_0_0_0 : label is "ROM_Encoder.lpc"; - attribute MEM_INIT_FILE of ROM_Encoder_0_0_0 : label is "rom_encoder.mem"; - attribute RESETMODE of ROM_Encoder_0_0_0 : label is "SYNC"; - -begin - -- component instantiation statements - scuba_vhi_inst : VHI - port map (Z => scuba_vhi); - - scuba_vlo_inst : VLO - port map (Z => scuba_vlo); - - ROM_Encoder_0_0_0 : DP16KC - generic map (INITVAL_3F => "0x00000000800008000081000000000000000000820000000081000820008200000000000008200083", - INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000084", - INITVAL_3D => "0x00000000000000000000000000000000000000000000000083000830008300000000000008400084", - INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000840008400000000000008500085", - INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", - INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000008500000000000008600086", - INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", - INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000008600000000000008600086", - INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086", - INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000008700000000000008700087", - INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12 => "0x00084000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10 => "0x00083000000000000000000000000000000000000008200000000000000000081000800000000000", - INITVAL_0F => "0x00087000000000000000000870000000000000000000000000000000000000000000000000000000", - INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B => "0x00086000000000000000000860000000000000000000000000000000000000000000000000000000", - INITVAL_0A => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07 => "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05 => "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04 => "0x00084000000000000000000840000000000000000000000000000000000000083000830000000000", - INITVAL_03 => "0x00085000000000000000000840000000000000000000000000000000000000000000000000000000", - INITVAL_02 => "0x00084000000000000000000840008400000000000000000000000000000000000000000000000000", - INITVAL_01 => "0x00084000000000000000000830000000000000000000000000000000000000082000820000000000", - INITVAL_00 => "0x00083000000000000000000820008200081000000008200082000810000000081000800008000000", - CSDECODE_B => "0b111", CSDECODE_A => "0b000", WRITEMODE_B => "NORMAL", - WRITEMODE_A => "NORMAL", GSR => "DISABLED", REGMODE_B => "NOREG", - REGMODE_A => "OUTREG", DATA_WIDTH_B => 18, DATA_WIDTH_A => 18) - port map (DIA0 => scuba_vlo, DIA1 => scuba_vlo, DIA2 => scuba_vlo, - DIA3 => scuba_vlo, DIA4 => scuba_vlo, DIA5 => scuba_vlo, - DIA6 => scuba_vlo, DIA7 => scuba_vlo, DIA8 => scuba_vlo, - DIA9 => scuba_vlo, DIA10 => scuba_vlo, DIA11 => scuba_vlo, - DIA12 => scuba_vlo, DIA13 => scuba_vlo, DIA14 => scuba_vlo, - DIA15 => scuba_vlo, DIA16 => scuba_vlo, DIA17 => scuba_vlo, - ADA0 => scuba_vlo, ADA1 => scuba_vlo, ADA2 => scuba_vlo, - ADA3 => scuba_vlo, ADA4 => Address(0), ADA5 => Address(1), - ADA6 => Address(2), ADA7 => Address(3), ADA8 => Address(4), - ADA9 => Address(5), ADA10 => Address(6), ADA11 => Address(7), - ADA12 => Address(8), ADA13 => Address(9), CEA => OutClockEn, - CLKA => OutClock, OCEA => OutClockEn, WEA => scuba_vlo, - CSA0 => scuba_vlo, CSA1 => scuba_vlo, CSA2 => scuba_vlo, - RSTA => Reset, DIB0 => scuba_vlo, DIB1 => scuba_vlo, - DIB2 => scuba_vlo, DIB3 => scuba_vlo, DIB4 => scuba_vlo, - DIB5 => scuba_vlo, DIB6 => scuba_vlo, DIB7 => scuba_vlo, - DIB8 => scuba_vlo, DIB9 => scuba_vlo, DIB10 => scuba_vlo, - DIB11 => scuba_vlo, DIB12 => scuba_vlo, DIB13 => scuba_vlo, - DIB14 => scuba_vlo, DIB15 => scuba_vlo, DIB16 => scuba_vlo, - DIB17 => scuba_vlo, ADB0 => scuba_vlo, ADB1 => scuba_vlo, - ADB2 => scuba_vlo, ADB3 => scuba_vlo, ADB4 => scuba_vlo, - ADB5 => scuba_vlo, ADB6 => scuba_vlo, ADB7 => scuba_vlo, - ADB8 => scuba_vlo, ADB9 => scuba_vlo, ADB10 => scuba_vlo, - ADB11 => scuba_vlo, ADB12 => scuba_vlo, ADB13 => scuba_vlo, - CEB => scuba_vhi, CLKB => scuba_vlo, OCEB => scuba_vhi, - WEB => scuba_vlo, CSB0 => scuba_vlo, CSB1 => scuba_vlo, - CSB2 => scuba_vlo, RSTB => scuba_vlo, DOA0 => Q(0), DOA1 => Q(1), - DOA2 => Q(2), DOA3 => Q(3), DOA4 => Q(4), DOA5 => Q(5), DOA6 => Q(6), - DOA7 => Q(7), DOA8 => open, DOA9 => open, DOA10 => open, DOA11 => open, - DOA12 => open, DOA13 => open, DOA14 => open, DOA15 => open, - DOA16 => open, DOA17 => open, DOB0 => open, DOB1 => open, DOB2 => open, - DOB3 => open, DOB4 => open, DOB5 => open, DOB6 => open, DOB7 => open, - DOB8 => open, DOB9 => open, DOB10 => open, DOB11 => open, - DOB12 => open, DOB13 => open, DOB14 => open, DOB15 => open, - DOB16 => open, DOB17 => open); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of ROM_Encoder is - for Structure - for all : VHI use entity ecp3.VHI(V); end for; - for all : VLO use entity ecp3.VLO(V); end for; - for all : DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/tdc_releases/tdc_v2.0/ROM_encoder_3.vhd b/tdc_releases/tdc_v2.0/ROM_encoder_3.vhd new file mode 120000 index 0000000..eb27ebb --- /dev/null +++ b/tdc_releases/tdc_v2.0/ROM_encoder_3.vhd @@ -0,0 +1 @@ +rom_encoder/ROM_encoder_3.vhd \ No newline at end of file diff --git a/tdc_releases/tdc_v2.0/Readout.vhd b/tdc_releases/tdc_v2.0/Readout.vhd index 3850081..8d40db6 100644 --- a/tdc_releases/tdc_v2.0/Readout.vhd +++ b/tdc_releases/tdc_v2.0/Readout.vhd @@ -5,7 +5,7 @@ -- File : Readout.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2012-11-09 +-- Last update: 2014-08-06 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -23,30 +23,22 @@ use work.trb3_components.all; entity Readout is generic ( + MODULE_NUMBER : integer range 1 to 4; CHANNEL_NUMBER : integer range 2 to 65; - STATUS_REG_NR : integer range 0 to 6); - + STATUS_REG_NR : integer range 0 to 31; + TDC_VERSION : std_logic_vector(11 downto 0)); port ( - CLK_200 : in std_logic; - RESET_200 : in std_logic; - CLK_100 : in std_logic; - RESET_100 : in std_logic; - RESET_COUNTERS : in std_logic; --- - HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); - REFERENCE_TIME : in std_logic; - TRIGGER_TIME_IN : in std_logic_vector(38 downto 0); - TRG_WIN_PRE : in std_logic_vector(10 downto 0); - TRG_WIN_POST : in std_logic_vector(10 downto 0); --- slow control - DEBUG_MODE_EN_IN : in std_logic; - TRIGGER_WIN_EN_IN : in std_logic; - + RESET_100 : in std_logic; + RESET_200 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_100 : in std_logic; + CLK_200 : in std_logic; -- from the channels - CH_DATA_IN : in std_logic_vector_array_32(0 to CHANNEL_NUMBER); - CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER downto 0); + CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); + CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_ALMOST_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); -- from the endpoint TRG_DATA_VALID_IN : in std_logic; VALID_TIMING_TRG_IN : in std_logic; @@ -60,6 +52,7 @@ entity Readout is TRG_CODE_IN : in std_logic_vector(7 downto 0); TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); TRG_TYPE_IN : in std_logic_vector(3 downto 0); + DATA_LIMIT_IN : in unsigned(7 downto 0); -- to the endpoint TRG_RELEASE_OUT : out std_logic; TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); @@ -67,16 +60,25 @@ entity Readout is DATA_WRITE_OUT : out std_logic; DATA_FINISHED_OUT : out std_logic; -- to the channels - READOUT_BUSY_OUT : out std_logic; READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); - TRIGGER_WIN_END_OUT : out std_logic; --- - SLOW_CONTROL_REG_OUT : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0); - STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 23); - READOUT_DEBUG : out std_logic_vector(31 downto 0) +-- trigger window settings + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); + TRIGGER_WIN_EN_IN : in std_logic; +-- from the trigger handler + TRIG_WIN_END_TDC_IN : in std_logic; + TRIG_WIN_END_RDO_IN : in std_logic; + TRIGGER_TDC_IN : in std_logic; + TRIG_TIME_IN : in std_logic_vector(38 downto 0); +-- miscellaneous + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + DEBUG_MODE_EN_IN : in std_logic; + STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to STATUS_REG_NR-1); + READOUT_DEBUG : out std_logic_vector(31 downto 0); + REFERENCE_TIME : in std_logic ); - -end Readout; +end entity Readout; architecture behavioral of Readout is @@ -85,619 +87,579 @@ architecture behavioral of Readout is ------------------------------------------------------------------------------- -- slow control - signal slow_control_ch_empty_i : std_logic_vector(64 downto 0); - + signal slow_control_ch_empty_i : std_logic_vector(63 downto 0); -- trigger window - signal start_trg_win_cnt : std_logic; - signal start_trg_win_cnt_200 : std_logic; - signal start_trg_win_cnt_200_p : std_logic; - signal trg_win_post_200 : std_logic_vector(10 downto 0); - signal trg_win_cnt : std_logic_vector(11 downto 0); - signal trg_win_end_200 : std_logic; - signal trg_win_end_200_p : std_logic; - signal trg_win_end_100 : std_logic; - signal trg_win_end_100_p : std_logic; - signal TW_pre : std_logic_vector(38 downto 0); - signal TW_post : std_logic_vector(38 downto 0); - signal trg_win_l : std_logic; - signal trg_win_r : std_logic; + signal trig_win_pre : unsigned(10 downto 0); + signal trig_win_post : unsigned(10 downto 0); + signal trig_win_en : std_logic; + signal trig_time_i : std_logic_vector(38 downto 0); + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + signal coarse_cntr_2reg : std_logic_vector(10 downto 0); + signal coarse_cntr_3reg : std_logic_vector(10 downto 0); + signal coarse_cntr_4reg : std_logic_vector(10 downto 0); + signal coarse_cntr_5reg : std_logic_vector(10 downto 0); + signal coarse_cntr_6reg : std_logic_vector(10 downto 0); + signal coarse_cntr_7reg : std_logic_vector(10 downto 0); + signal coarse_cntr_8reg : std_logic_vector(10 downto 0); + signal coarse_cntr_9reg : std_logic_vector(10 downto 0); + signal coarse_cntr_10reg : std_logic_vector(10 downto 0); + signal coarse_cntr_11reg : std_logic_vector(10 downto 0); + signal coarse_cntr_12reg : std_logic_vector(10 downto 0); + signal epoch_cntr_reg : std_logic_vector(27 downto 0); + signal epoch_cntr_2reg : std_logic_vector(27 downto 0); + signal epoch_cntr_3reg : std_logic_vector(27 downto 0); + signal epoch_cntr_4reg : std_logic_vector(27 downto 0); + signal epoch_cntr_5reg : std_logic_vector(27 downto 0); + signal epoch_cntr_6reg : std_logic_vector(27 downto 0); + signal epoch_cntr_7reg : std_logic_vector(27 downto 0); + signal epoch_cntr_8reg : std_logic_vector(27 downto 0); + signal epoch_cntr_9reg : std_logic_vector(27 downto 0); + signal epoch_cntr_10reg : std_logic_vector(27 downto 0); + signal epoch_cntr_11reg : std_logic_vector(27 downto 0); + signal epoch_cntr_12reg : std_logic_vector(27 downto 0); + signal TW_pre : std_logic_vector(38 downto 0); + signal TW_post : std_logic_vector(38 downto 0); + signal trig_win_l : std_logic; + signal trig_win_r : std_logic; + signal start_trig_win_cnt : std_logic := '0'; + signal start_trig_win_cnt_200_p : std_logic; + signal trig_win_post_200 : std_logic_vector(10 downto 0); + signal trig_win_cnt : std_logic_vector(11 downto 0); + signal trig_win_end_200 : std_logic := '0'; + signal trig_win_end_200_p : std_logic; + signal trig_win_end_100_p : std_logic; + signal trig_win_end_100_reg : std_logic; + signal trig_win_end_100_2reg : std_logic; + signal trig_win_end_100_3reg : std_logic; + signal trig_win_end_100_4reg : std_logic; -- channel signals - signal ch_data_reg : std_logic_vector_array_32(0 to CHANNEL_NUMBER); - signal ch_data_2reg : std_logic_vector_array_32(0 to CHANNEL_NUMBER); - --signal ch_data_3reg : std_logic_vector_array_32(0 to CHANNEL_NUMBER); - signal ch_empty_reg : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_empty_2reg : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_empty_3reg : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_empty_4reg : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_hit_time : std_logic_vector(38 downto 0); - signal ch_epoch_cntr_i : std_logic_vector(27 downto 0); + signal ch_data_reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); + signal ch_data_2reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); + signal ch_data_3reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); +-- signal ch_data_4reg : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); + signal ch_data_4reg : std_logic_vector(31 downto 0); + signal ch_empty_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_empty_2reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_empty_3reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_empty_4reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal ch_hit_time : std_logic_vector(38 downto 0); + signal ch_epoch_cntr_i : std_logic_vector(27 downto 0); + signal buffer_transfer_done : std_logic; + signal buffer_transfer_done_reg : std_logic; + signal buffer_transfer_done_2reg : std_logic; -- readout fsm - type FSM is (IDLE, WAIT_FOR_TRG_WIND_END, WAIT_FOR_LVL1_TRG_A, WAIT_FOR_LVL1_TRG_B, - WAIT_FOR_LVL1_TRG_C, SEND_STATUS, SEND_TRG_RELEASE_A, SEND_TRG_RELEASE_B, - WAIT_FOR_FIFO_NR_A, WAIT_FOR_FIFO_NR_B, WAIT_FOR_FIFO_NR_C, WR_HEADER_A, - APPLY_MASK, RD_CHANNEL_A, RD_CHANNEL_B, RD_CHANNEL_C); - signal FSM_CURRENT, FSM_NEXT : FSM; - signal start_trg_win_cnt_fsm : std_logic; - signal fsm_debug_fsm : std_logic_vector(7 downto 0); - signal updt_index_fsm : std_logic; - signal updt_mask_fsm : std_logic; + type FSM_READ is (IDLE, WAIT_FOR_TRIG_WIND_END, RD_CH, WAIT_FOR_DATA_FINISHED, WAIT_FOR_LVL1_TRIG_A, + WAIT_FOR_LVL1_TRIG_B, WAIT_FOR_LVL1_TRIG_C, SEND_STATUS, SEND_TRIG_RELEASE_A, + SEND_TRIG_RELEASE_B, SEND_TRIG_RELEASE_C, WAIT_FOR_BUFFER_TRANSFER); + signal RD_CURRENT : FSM_READ := IDLE; + signal RD_NEXT : FSM_READ; + type FSM_WRITE is (IDLE, WR_CH, WAIT_A, WAIT_B, WAIT_C, WAIT_D); + signal WR_CURRENT : FSM_WRITE := IDLE; + signal WR_NEXT : FSM_WRITE; + signal start_trig_win_cnt_fsm : std_logic; + signal rd_fsm_debug_fsm : std_logic_vector(3 downto 0); + signal wr_fsm_debug_fsm : std_logic_vector(3 downto 0); signal rd_en_fsm : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal data_finished_fsm : std_logic; - signal trg_release_fsm : std_logic; - signal wr_header_fsm : std_logic; + signal wr_finished_fsm : std_logic; + signal trig_release_fsm : std_logic; + signal wr_trailer_fsm : std_logic; signal wr_ch_data_fsm : std_logic; signal wr_status_fsm : std_logic; signal wrong_readout_fsm : std_logic; + signal wrong_reference_fsm : std_logic; + signal wr_number_fsm : unsigned(7 downto 0); + signal wr_number : unsigned(7 downto 0); + signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER := 0; + signal buf_delay_fsm : integer range 0 to 63 := 0; + signal buf_delay_i : integer range 0 to 63 := 0; -- signal wr_trailer_fsm : std_logic; signal idle_fsm : std_logic; signal readout_fsm : std_logic; signal wait_fsm : std_logic; - -- readout busy fsm - type FSM_RDO_BUSY is (NOT_BUSY, BUSY, WAIT_FOR_SILINCE); - signal FSM_RDO_BUSY_CURRENT : FSM_RDO_BUSY; - signal FSM_RDO_BUSY_NEXT : FSM_RDO_BUSY; - signal readout_busy : std_logic; -- fifo number - type Std_Logic_8_array is array (0 to 8) of std_logic_vector(3 downto 0); - signal updt_index : std_logic; - signal fifo_nr : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; - signal fifo_nr_reg : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; - signal fifo_nr_next : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER; - signal fifo_nr_hex : Std_Logic_8_array; + type Std_Logic_8_array is array (0 to 8) of std_logic_vector(3 downto 0); signal empty_channels : std_logic_vector(CHANNEL_NUMBER downto 0); - signal updt_index_reg : std_logic; - signal updt_mask : std_logic; - signal mask : std_logic_vector(71 downto 0); + signal fifo_nr_rd : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_reg : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_2reg : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_3reg : integer range 0 to CHANNEL_NUMBER := 0; -- fifo read signal rd_en : std_logic_vector(CHANNEL_NUMBER-1 downto 0); -- data mux - signal wr_header : std_logic; - signal wr_ch_data : std_logic; + signal start_write : std_logic := '0'; + signal wr_ch_data_i : std_logic; signal wr_ch_data_reg : std_logic; - signal wr_ch_data_2reg : std_logic; signal wr_status : std_logic; signal wr_trailer : std_logic; + signal wr_info : std_logic; + signal wr_time : std_logic; + signal wr_epoch : std_logic; signal stop_status_i : std_logic; -- to endpoint signal data_out_reg : std_logic_vector(31 downto 0); signal data_wr_reg : std_logic; signal data_finished : std_logic; - signal data_finished_reg : std_logic; - signal trg_release_reg : std_logic; + signal wr_finished : std_logic; + signal trig_release : std_logic; -- statistics - signal trig_number : unsigned(23 downto 0); - signal release_number : unsigned(23 downto 0); - signal valid_tmg_trig_number : unsigned(23 downto 0); - signal valid_NOtmg_trig_number : unsigned(23 downto 0); - signal invalid_trig_number : unsigned(23 downto 0); - signal multi_tmg_trig_number : unsigned(23 downto 0); - signal spurious_trig_number : unsigned(23 downto 0); - signal wrong_readout_number : unsigned(23 downto 0); - signal spike_number : unsigned(23 downto 0); - signal timeout_number : unsigned(23 downto 0); - signal total_empty_channel : unsigned(23 downto 0); - signal idle_time : unsigned(23 downto 0); - signal readout_time : unsigned(23 downto 0); - signal wait_time : unsigned(23 downto 0); - signal valid_timing_trg_p : std_logic; - signal valid_notiming_trg_p : std_logic; - signal invalid_trg_p : std_logic; - signal multi_tmg_trg_p : std_logic; - signal spurious_trg_p : std_logic; + signal trig_number : unsigned(23 downto 0) := (others => '0'); + signal release_number : unsigned(23 downto 0) := (others => '0'); + signal valid_tmg_trig_number : unsigned(23 downto 0) := (others => '0'); + signal valid_NOtmg_trig_number : unsigned(23 downto 0) := (others => '0'); + signal invalid_trig_number : unsigned(23 downto 0) := (others => '0'); + signal multi_tmg_trig_number : unsigned(23 downto 0) := (others => '0'); + signal spurious_trig_number : unsigned(23 downto 0) := (others => '0'); + signal wrong_readout_number : unsigned(23 downto 0) := (others => '0'); + signal spike_number : unsigned(23 downto 0) := (others => '0'); + signal timeout_number : unsigned(23 downto 0) := (others => '0'); + signal total_empty_channel : unsigned(23 downto 0) := (others => '0'); + signal idle_time : unsigned(23 downto 0) := (others => '0'); + signal readout_time : unsigned(23 downto 0) := (others => '0'); + signal wait_time : unsigned(23 downto 0) := (others => '0'); + signal finished_number : unsigned(23 downto 0) := (others => '0'); + signal valid_timing_trig_p : std_logic; + signal valid_notiming_trig_p : std_logic; + signal invalid_trig_p : std_logic; + signal multi_tmg_trig_p : std_logic; + signal spurious_trig_p : std_logic; signal spike_detected_p : std_logic; signal timeout_detected_p : std_logic; signal idle_time_up : std_logic; signal readout_time_up : std_logic; signal wait_time_up : std_logic; signal wrong_readout_up : std_logic; + signal wrong_reference : std_logic; + signal finished_i : std_logic; -- debug signal header_error_bits : std_logic_vector(15 downto 0); signal trailer_error_bits : std_logic_vector(15 downto 0); signal ch_full_i : std_logic; - signal ch_almost_full_i : std_logic; - signal fsm_debug : std_logic_vector(7 downto 0); + signal rd_fsm_debug : std_logic_vector(3 downto 0); + signal rd_fsm_debug_reg : std_logic_vector(3 downto 0); + signal history_rd_fsm : std_logic_vector(31 downto 0) := (others => '0'); + signal wr_fsm_debug : std_logic_vector(3 downto 0); + signal wr_fsm_debug_reg : std_logic_vector(3 downto 0); + signal history_wr_fsm : std_logic_vector(31 downto 0) := (others => '0'); + signal status_registers_bus_i : std_logic_vector(31 downto 0); begin -- behavioral + + trig_win_pre <= unsigned(TRG_WIN_PRE); + trig_win_post <= unsigned(TRG_WIN_POST); + trig_win_en <= TRIGGER_WIN_EN_IN when rising_edge(CLK_100); + ------------------------------------------------------------------------------- -- Trigger window ------------------------------------------------------------------------------- --- Trigger window start logic - StartTrgWinCntSync : bit_sync - generic map ( - DEPTH => 3) - port map ( - RESET => RESET_200, - CLK0 => CLK_100, - CLK1 => CLK_200, - D_IN => start_trg_win_cnt, - D_OUT => start_trg_win_cnt_200); - - StartTrgWinCntPulse : edge_to_pulse - port map ( - clock => CLK_200, - en_clk => '1', - signal_in => start_trg_win_cnt_200, - pulse => start_trg_win_cnt_200_p); +-- Trigger window borders + TrigWinCalculation : process (CLK_100) + begin + if rising_edge(CLK_100) then + TW_pre <= std_logic_vector(unsigned(trig_time_i)-trig_win_pre); + TW_post <= std_logic_vector(unsigned(trig_time_i)+trig_win_post); + end if; + end process TrigWinCalculation; --- Trigger window end logic - Check_Trg_Win_End_Conrollers : process (CLK_200) +-- Trigger Time Determination + DefineTriggerTime : process (CLK_200) begin if rising_edge(CLK_200) then if RESET_200 = '1' then - trg_win_end_200 <= '0'; - trg_win_cnt <= '1' & trg_win_post_200; - elsif start_trg_win_cnt_200_p = '1' then - trg_win_end_200 <= '0'; - trg_win_cnt <= "000000000001"; - elsif trg_win_cnt(10 downto 0) = trg_win_post_200 then - trg_win_end_200 <= '1'; - trg_win_cnt(11) <= '1'; - else - trg_win_end_200 <= '0'; - trg_win_cnt <= std_logic_vector(unsigned(trg_win_cnt) + to_unsigned(1, 1)); + trig_time_i <= (others => '0'); + elsif TRIGGER_TDC_IN = '1' then + trig_time_i <= TRIG_TIME_IN; --epoch_cntr_12reg & coarse_cntr_12reg; end if; end if; - end process Check_Trg_Win_End_Conrollers; + end process DefineTriggerTime; + coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200); + coarse_cntr_2reg <= coarse_cntr_reg when rising_edge(CLK_200); + coarse_cntr_3reg <= coarse_cntr_2reg when rising_edge(CLK_200); + coarse_cntr_4reg <= coarse_cntr_3reg when rising_edge(CLK_200); + coarse_cntr_5reg <= coarse_cntr_4reg when rising_edge(CLK_200); + coarse_cntr_6reg <= coarse_cntr_5reg when rising_edge(CLK_200); + coarse_cntr_7reg <= coarse_cntr_6reg when rising_edge(CLK_200); + coarse_cntr_8reg <= coarse_cntr_7reg when rising_edge(CLK_200); + coarse_cntr_9reg <= coarse_cntr_8reg when rising_edge(CLK_200); + coarse_cntr_10reg <= coarse_cntr_9reg when rising_edge(CLK_200); + coarse_cntr_11reg <= coarse_cntr_10reg when rising_edge(CLK_200); + coarse_cntr_12reg <= coarse_cntr_11reg when rising_edge(CLK_200); + + epoch_cntr_reg <= EPOCH_COUNTER_IN when rising_edge(CLK_200); + epoch_cntr_2reg <= epoch_cntr_reg when rising_edge(CLK_200); + epoch_cntr_3reg <= epoch_cntr_2reg when rising_edge(CLK_200); + epoch_cntr_4reg <= epoch_cntr_3reg when rising_edge(CLK_200); + epoch_cntr_5reg <= epoch_cntr_4reg when rising_edge(CLK_200); + epoch_cntr_6reg <= epoch_cntr_5reg when rising_edge(CLK_200); + epoch_cntr_7reg <= epoch_cntr_6reg when rising_edge(CLK_200); + epoch_cntr_8reg <= epoch_cntr_7reg when rising_edge(CLK_200); + epoch_cntr_9reg <= epoch_cntr_8reg when rising_edge(CLK_200); + epoch_cntr_10reg <= epoch_cntr_9reg when rising_edge(CLK_200); + epoch_cntr_11reg <= epoch_cntr_10reg when rising_edge(CLK_200); + epoch_cntr_12reg <= epoch_cntr_11reg when rising_edge(CLK_200); - TriggerWinEndPulse200 : edge_to_pulse - port map ( - clock => CLK_200, - en_clk => '1', - signal_in => trg_win_end_200, - pulse => trg_win_end_200_p); - TRIGGER_WIN_END_OUT <= trg_win_end_200_p; - - TriggerWinEndSync : bit_sync - generic map ( - DEPTH => 3) - port map ( - RESET => RESET_100, - CLK0 => CLK_200, - CLK1 => CLK_100, - D_IN => trg_win_end_200, - D_OUT => trg_win_end_100); - - TriggerWinEndPulse100 : edge_to_pulse - port map ( - clock => CLK_100, - en_clk => '1', - signal_in => trg_win_end_100, - pulse => trg_win_end_100_p); - --- Trigger window borders - Trg_Win_Calculation : process (CLK_100, RESET_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - TW_pre <= (others => '0'); - TW_post <= (others => '0'); - else - TW_pre <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN)) - to_integer(unsigned(TRG_WIN_PRE)), 39)); - TW_post <= std_logic_vector(to_unsigned(to_integer(unsigned(TRIGGER_TIME_IN)) + to_integer(unsigned(TRG_WIN_POST)), 39)); - end if; - end if; - end process Trg_Win_Calculation; -- Channel Hit Time Determination - ChannelEpochCounter : process (CLK_100) + ChannelHitTime : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' then - ch_epoch_cntr_i <= (others => '0'); - elsif ch_empty_3reg(fifo_nr_reg) = '1' and ch_empty_4reg(fifo_nr_reg) = '0' then - ch_epoch_cntr_i <= (others => '0'); - elsif ch_data_reg(fifo_nr_reg)(31 downto 29) = "011" then - ch_epoch_cntr_i <= ch_data_reg(fifo_nr_reg)(27 downto 0); + if ch_data_reg(fifo_nr_wr)(35 downto 32) = x"1" and ch_data_reg(fifo_nr_wr)(31 downto 29) = "011" then + ch_epoch_cntr_i <= ch_data_reg(fifo_nr_wr)(27 downto 0); end if; - end if; - end process ChannelEpochCounter; - ChannelHitTime : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - ch_hit_time <= (others => '0'); - elsif ch_data_reg(fifo_nr_reg)(31) = '1' then - ch_hit_time <= ch_epoch_cntr_i & ch_data_reg(fifo_nr_reg)(10 downto 0); - elsif ch_data_reg(fifo_nr_reg)(31 downto 29) = "011" then + if ch_data_reg(fifo_nr_wr)(35 downto 32) = x"1" and ch_data_reg(fifo_nr_wr)(31) = '1' then + ch_hit_time <= ch_epoch_cntr_i & ch_data_reg(fifo_nr_wr)(10 downto 0); + elsif ch_data_reg(fifo_nr_wr)(35 downto 32) = x"1" and ch_data_reg(fifo_nr_wr)(31 downto 29) = "011" then ch_hit_time <= (others => '0'); end if; end if; end process ChannelHitTime; -- Controls if the data coming from the channel is greater than the trigger window pre-edge - Check_Trg_Win_Left : process (RESET_100, TW_pre, ch_hit_time) + Check_Trig_Win_Left : process (CLK_100) begin - --if rising_edge(CLK_100) then - if RESET_100 = '1' then - trg_win_l <= '0'; - elsif to_integer(unsigned(TW_pre)) <= to_integer(unsigned(ch_hit_time)) then - trg_win_l <= '1'; - else - trg_win_l <= '0'; + if rising_edge(CLK_100) then + if unsigned(TW_pre) <= unsigned(ch_hit_time) then + trig_win_l <= '1'; + else + trig_win_l <= '0'; + end if; end if; - --end if; - end process Check_Trg_Win_Left; + end process Check_Trig_Win_Left; -- Controls if the data coming from the channel is smaller than the trigger window post-edge - Check_Trg_Win_Right : process (RESET_100, TW_post, ch_hit_time) + Check_Trig_Win_Right : process (CLK_100) begin - --if rising_edge(CLK_100) then - if RESET_100 = '1' then - trg_win_r <= '0'; - elsif to_integer(unsigned(ch_hit_time)) <= to_integer(unsigned(TW_post)) then - trg_win_r <= '1'; - else - trg_win_r <= '0'; + if rising_edge(CLK_100) then + if unsigned(ch_hit_time) <= unsigned(TW_post) then + trig_win_r <= '1'; + else + trig_win_r <= '0'; + end if; end if; - --end if; - end process Check_Trg_Win_Right; + end process Check_Trig_Win_Right; ------------------------------------------------------------------------------- -- Readout ------------------------------------------------------------------------------- -- Readout fsm - FSM_CLK : process (CLK_100, RESET_100) + RD_FSM_CLK : process (CLK_100) begin if rising_edge(CLK_100) then if RESET_100 = '1' then - FSM_CURRENT <= IDLE; - start_trg_win_cnt <= '0'; - updt_index <= '0'; - updt_mask <= '0'; - rd_en <= (others => '0'); - wr_ch_data <= '0'; - wr_header <= '0'; - wr_status <= '0'; - data_finished <= '0'; - trg_release_reg <= '0'; - wrong_readout_up <= '0'; - idle_time_up <= '0'; - readout_time_up <= '0'; - wait_time_up <= '0'; - fsm_debug <= x"00"; + RD_CURRENT <= IDLE; + fifo_nr_rd <= 0; else - FSM_CURRENT <= FSM_NEXT; - start_trg_win_cnt <= start_trg_win_cnt_fsm; - updt_index <= updt_index_fsm; - updt_mask <= updt_mask_fsm; - rd_en <= rd_en_fsm; - wr_ch_data <= wr_ch_data_fsm; - wr_header <= wr_header_fsm; - wr_status <= wr_status_fsm; - data_finished <= data_finished_fsm; - trg_release_reg <= trg_release_fsm; - wrong_readout_up <= wrong_readout_fsm; - idle_time_up <= idle_fsm; - readout_time_up <= readout_fsm; - wait_time_up <= wait_fsm; - fsm_debug <= fsm_debug_fsm; + RD_CURRENT <= RD_NEXT; + rd_en <= rd_en_fsm; + wr_trailer <= wr_trailer_fsm; + wr_status <= wr_status_fsm; + data_finished <= data_finished_fsm; + trig_release <= trig_release_fsm; + buf_delay_i <= buf_delay_fsm; + wrong_readout_up <= wrong_readout_fsm; + wrong_reference <= wrong_reference_fsm; + idle_time_up <= idle_fsm; + readout_time_up <= readout_fsm; + wait_time_up <= wait_fsm; + fifo_nr_rd <= fifo_nr_rd_fsm; + rd_fsm_debug <= rd_fsm_debug_fsm; + buffer_transfer_done <= and_all(CH_EMPTY_IN); + buffer_transfer_done_reg <= buffer_transfer_done; + buffer_transfer_done_2reg <= buffer_transfer_done_reg; end if; end if; - end process FSM_CLK; + end process RD_FSM_CLK; READ_EN_OUT <= rd_en; - FSM_PROC : process (FSM_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, trg_win_end_100_p, fifo_nr_next, - fifo_nr, ch_empty_reg, TRG_DATA_VALID_IN, INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, - TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status_i, DEBUG_MODE_EN_IN) + RD_FSM_PROC : process (RD_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, TRG_DATA_VALID_IN, + INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, TRG_TYPE_IN, finished_i, + SPURIOUS_TRG_IN, stop_status_i, DEBUG_MODE_EN_IN, fifo_nr_rd, + TRIG_WIN_END_RDO_IN, buf_delay_i, CH_EMPTY_IN, CLK_100, buffer_transfer_done_2reg) begin - start_trg_win_cnt_fsm <= '0'; - updt_index_fsm <= '0'; - updt_mask_fsm <= '0'; - rd_en_fsm <= (others => '0'); - wr_ch_data_fsm <= '0'; - wr_header_fsm <= '0'; - data_finished_fsm <= '0'; - trg_release_fsm <= '0'; - wrong_readout_fsm <= '0'; - idle_fsm <= '0'; - readout_fsm <= '0'; - wait_fsm <= '0'; - wr_status_fsm <= '0'; - fsm_debug_fsm <= x"00"; - FSM_NEXT <= IDLE; - - case (FSM_CURRENT) is + rd_en_fsm <= (others => '0'); + wr_trailer_fsm <= '0'; + data_finished_fsm <= '0'; + trig_release_fsm <= '0'; + wrong_readout_fsm <= '0'; + wrong_reference_fsm <= '0'; + idle_fsm <= '0'; + readout_fsm <= '0'; + wait_fsm <= '0'; + wr_status_fsm <= '0'; + buf_delay_fsm <= 0; + fifo_nr_rd_fsm <= fifo_nr_rd; + rd_fsm_debug_fsm <= x"0"; + RD_NEXT <= RD_CURRENT; + + case (RD_CURRENT) is when IDLE => - if VALID_TIMING_TRG_IN = '1' then - FSM_NEXT <= WAIT_FOR_TRG_WIND_END; - start_trg_win_cnt_fsm <= '1'; + if VALID_TIMING_TRG_IN = '1' then -- physical trigger + RD_NEXT <= WAIT_FOR_TRIG_WIND_END; + readout_fsm <= '1'; elsif VALID_NOTIMING_TRG_IN = '1' then - if TRG_TYPE_IN = x"E" then - FSM_NEXT <= SEND_STATUS; - else - FSM_NEXT <= SEND_TRG_RELEASE_A; + if TRG_TYPE_IN = x"E" then -- status trigger + RD_NEXT <= SEND_STATUS; + elsif TRG_TYPE_IN = x"D" then -- tdc calibration trigger + RD_NEXT <= WAIT_FOR_BUFFER_TRANSFER; + readout_fsm <= '1'; + else -- the other triggers + RD_NEXT <= SEND_TRIG_RELEASE_C; + data_finished_fsm <= '1'; end if; - wr_header_fsm <= '1'; - elsif INVALID_TRG_IN = '1' then - FSM_NEXT <= SEND_TRG_RELEASE_A; + elsif INVALID_TRG_IN = '1' then -- invalid trigger + RD_NEXT <= SEND_TRIG_RELEASE_C; data_finished_fsm <= '1'; - else - FSM_NEXT <= IDLE; end if; - idle_fsm <= '1'; - fsm_debug_fsm <= x"01"; + idle_fsm <= '1'; + rd_fsm_debug_fsm <= x"1"; + + when WAIT_FOR_TRIG_WIND_END => + if TRIG_WIN_END_RDO_IN = '1' then + RD_NEXT <= WAIT_FOR_BUFFER_TRANSFER; + end if; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"2"; - when WAIT_FOR_TRG_WIND_END => - if trg_win_end_100_p = '1' then - FSM_NEXT <= WR_HEADER_A; + when WAIT_FOR_BUFFER_TRANSFER => -- the data from channel fifo is written to the buffer + if buffer_transfer_done_2reg = '0' or buf_delay_i = 63 then + RD_NEXT <= RD_CH; else - FSM_NEXT <= WAIT_FOR_TRG_WIND_END; + buf_delay_fsm <= buf_delay_i + 1; end if; - wait_fsm <= '1'; - fsm_debug_fsm <= x"02"; -------------------------------------------------------------------------------- --- Readout process starts - when WR_HEADER_A => - FSM_NEXT <= WAIT_FOR_FIFO_NR_A; - wr_header_fsm <= '1'; - readout_fsm <= '1'; - fsm_debug_fsm <= x"03"; - - when WAIT_FOR_FIFO_NR_A => - FSM_NEXT <= WAIT_FOR_FIFO_NR_B; - updt_index_fsm <= '1'; - wait_fsm <= '1'; - fsm_debug_fsm <= x"04"; - - when WAIT_FOR_FIFO_NR_B => - FSM_NEXT <= APPLY_MASK; - wait_fsm <= '1'; - fsm_debug_fsm <= x"05"; - - when APPLY_MASK => - if fifo_nr_next = CHANNEL_NUMBER then - if DEBUG_MODE_EN_IN = '1' then - FSM_NEXT <= SEND_STATUS; + rd_fsm_debug_fsm <= x"3"; + + when RD_CH => + if CH_EMPTY_IN(fifo_nr_rd) = '0' then -- read from channel if not empty + rd_en_fsm(fifo_nr_rd) <= '1'; + fifo_nr_rd_fsm <= fifo_nr_rd; + elsif fifo_nr_rd = CHANNEL_NUMBER-1 then -- the last channel + rd_en_fsm(fifo_nr_rd) <= '0'; + if DEBUG_MODE_EN_IN = '1' then -- send status after channel data + RD_NEXT <= SEND_STATUS; else - FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; - data_finished_fsm <= '1'; + RD_NEXT <= WAIT_FOR_LVL1_TRIG_A; end if; - else - FSM_NEXT <= RD_CHANNEL_A; - rd_en_fsm(fifo_nr_next) <= '1'; - updt_mask_fsm <= '1'; + else -- go to the next channel + fifo_nr_rd_fsm <= fifo_nr_rd + 1 after 10 ps; end if; - wait_fsm <= '1'; - fsm_debug_fsm <= x"06"; - - when RD_CHANNEL_A => - FSM_NEXT <= RD_CHANNEL_B; - rd_en_fsm(fifo_nr) <= '1'; - readout_fsm <= '1'; - fsm_debug_fsm <= x"07"; - - when RD_CHANNEL_B => - FSM_NEXT <= RD_CHANNEL_C; - rd_en_fsm(fifo_nr) <= '1'; - readout_fsm <= '1'; - fsm_debug_fsm <= x"08"; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"4"; + + --when WAIT_FOR_DATA_FINISHED => -- wait until the end of the data transfer + -- if finished_i = '1' then + -- RD_NEXT <= WAIT_FOR_LVL1_TRIG_A; + -- end if; + -- wait_fsm <= '1'; + -- rd_fsm_debug_fsm <= x"5"; - when RD_CHANNEL_C => - if ch_empty_reg(fifo_nr) = '1' then - FSM_NEXT <= WAIT_FOR_FIFO_NR_B; - wr_ch_data_fsm <= '0'; - updt_index_fsm <= '1'; - else - FSM_NEXT <= RD_CHANNEL_C; - wr_ch_data_fsm <= '1'; - rd_en_fsm(fifo_nr) <= '1'; - end if; - readout_fsm <= '1'; - fsm_debug_fsm <= x"09"; -------------------------------------------------------------------------------- - when WAIT_FOR_LVL1_TRG_A => + when WAIT_FOR_LVL1_TRIG_A => -- wait for trigger data valid if TRG_DATA_VALID_IN = '1' then - FSM_NEXT <= WAIT_FOR_LVL1_TRG_B; + RD_NEXT <= WAIT_FOR_LVL1_TRIG_B; elsif TMGTRG_TIMEOUT_IN = '1' then - FSM_NEXT <= IDLE; - else - FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; + RD_NEXT <= SEND_TRIG_RELEASE_C; + data_finished_fsm <= '1'; end if; - wait_fsm <= '1'; - fsm_debug_fsm <= x"0A"; - - when WAIT_FOR_LVL1_TRG_B => - FSM_NEXT <= WAIT_FOR_LVL1_TRG_C; - wait_fsm <= '1'; - fsm_debug_fsm <= x"0B"; - - when WAIT_FOR_LVL1_TRG_C => + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"6"; + + when WAIT_FOR_LVL1_TRIG_B => + --if MULTI_TMG_TRG_IN = '1' or SPIKE_DETECTED_IN = '1' then + -- wrong_reference_fsm <= '1'; + -- wr_trailer_fsm <= '1'; + --end if; + RD_NEXT <= WAIT_FOR_LVL1_TRIG_C; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"7"; + + when WAIT_FOR_LVL1_TRIG_C => if SPURIOUS_TRG_IN = '1' then wrong_readout_fsm <= '1'; +-- wr_trailer_fsm <= '1'; end if; - FSM_NEXT <= SEND_TRG_RELEASE_A; - wait_fsm <= '1'; - fsm_debug_fsm <= x"0C"; + RD_NEXT <= SEND_TRIG_RELEASE_A; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"8"; when SEND_STATUS => if stop_status_i = '1' then if DEBUG_MODE_EN_IN = '1' then - FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; + RD_NEXT <= WAIT_FOR_LVL1_TRIG_A; else - FSM_NEXT <= SEND_TRG_RELEASE_A; + RD_NEXT <= SEND_TRIG_RELEASE_C; + data_finished_fsm <= '1'; end if; - data_finished_fsm <= '1'; else - FSM_NEXT <= SEND_STATUS; wr_status_fsm <= '1'; end if; - fsm_debug_fsm <= x"0D"; - - when SEND_TRG_RELEASE_A => - FSM_NEXT <= SEND_TRG_RELEASE_B; - trg_release_fsm <= '1'; - fsm_debug_fsm <= x"0E"; - - when SEND_TRG_RELEASE_B => - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"0F"; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"9"; + + when SEND_TRIG_RELEASE_A => + RD_NEXT <= SEND_TRIG_RELEASE_B; + fifo_nr_rd_fsm <= 0; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"A"; + + when SEND_TRIG_RELEASE_B => + RD_NEXT <= SEND_TRIG_RELEASE_C; + data_finished_fsm <= '1'; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"B"; + + when SEND_TRIG_RELEASE_C => + RD_NEXT <= IDLE; + trig_release_fsm <= '1'; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"C"; when others => - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"FF"; + RD_NEXT <= IDLE; + rd_fsm_debug_fsm <= x"F"; end case; - end process FSM_PROC; + end process RD_FSM_PROC; + --- Readout busy fsm - FSM_READOUT_BUSY_CLK : process (CLK_200) + --purpose: FSM for writing data to endpoint buffer + WR_FSM_CLK : process (CLK_100) begin - if rising_edge(CLK_200) then - if RESET_200 = '1' then - FSM_RDO_BUSY_CURRENT <= NOT_BUSY; + if rising_edge(CLK_100) then + if RESET_100 = '1' then + WR_CURRENT <= IDLE; else - FSM_RDO_BUSY_CURRENT <= FSM_RDO_BUSY_NEXT; + WR_CURRENT <= WR_NEXT; + wr_ch_data_i <= wr_ch_data_fsm; + wr_number <= wr_number_fsm; + fifo_nr_wr <= fifo_nr_wr_fsm; + wr_finished <= wr_finished_fsm; + wr_fsm_debug <= wr_fsm_debug_fsm; + start_write <= or_all(CH_DATA_VALID_IN); end if; end if; - end process FSM_READOUT_BUSY_CLK; - - FSM_READOUT_BUSY : process (FSM_RDO_BUSY_CURRENT, trg_win_end_200_p, data_finished_reg, HIT_IN) + end process WR_FSM_CLK; + + WR_FSM : process (WR_CURRENT, wr_number, fifo_nr_wr, DATA_LIMIT_IN, start_write, CH_DATA_VALID_IN, + ch_data_2reg) + begin - FSM_RDO_BUSY_NEXT <= NOT_BUSY; - readout_busy <= '0'; - case FSM_RDO_BUSY_CURRENT is - when NOT_BUSY => - if trg_win_end_200_p = '1' then - FSM_RDO_BUSY_NEXT <= BUSY; - else - FSM_RDO_BUSY_NEXT <= NOT_BUSY; - end if; - readout_busy <= '0'; + WR_NEXT <= WR_CURRENT; + wr_ch_data_fsm <= '0'; + wr_number_fsm <= (others => '0'); + fifo_nr_wr_fsm <= 0; + wr_finished_fsm <= '0'; - when BUSY => - if data_finished_reg = '1' then - FSM_RDO_BUSY_NEXT <= WAIT_FOR_SILINCE; -- waits until the hit input is zero - else - FSM_RDO_BUSY_NEXT <= BUSY; + case (WR_CURRENT) is + when IDLE => + if start_write = '1' then + fifo_nr_wr_fsm <= 0; + WR_NEXT <= WR_CH; end if; - readout_busy <= '1'; - - when WAIT_FOR_SILINCE => - if or_all(HIT_IN) = '0' then - FSM_RDO_BUSY_NEXT <= NOT_BUSY; + wr_fsm_debug_fsm <= x"1"; +-- + when WR_CH => + if ch_data_2reg(fifo_nr_wr)(35 downto 32) /= x"f" then + if wr_number >= DATA_LIMIT_IN then + wr_ch_data_fsm <= '0'; + else + wr_ch_data_fsm <= '1'; + end if; + wr_number_fsm <= wr_number + to_unsigned(1, 8); + fifo_nr_wr_fsm <= fifo_nr_wr; + --wr_fsm_debug_fsm <= x"4"; + elsif CH_DATA_VALID_IN(fifo_nr_wr) = '1' then + wr_number_fsm <= wr_number; + fifo_nr_wr_fsm <= fifo_nr_wr; + --wr_fsm_debug_fsm <= x"6"; + elsif fifo_nr_wr = CHANNEL_NUMBER-1 then + wr_number_fsm <= (others => '0'); + wr_finished_fsm <= '1'; + WR_NEXT <= IDLE; + --wr_fsm_debug_fsm <= x"5"; else - FSM_RDO_BUSY_NEXT <= WAIT_FOR_SILINCE; + wr_number_fsm <= (others => '0'); + fifo_nr_wr_fsm <= fifo_nr_wr + 1; + WR_NEXT <= WAIT_A; + --wr_fsm_debug_fsm <= x"7"; end if; - readout_busy <= '1'; - + wr_fsm_debug_fsm <= x"2"; +-- + when WAIT_A => + WR_NEXT <= WAIT_B; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"3"; +-- + when WAIT_B => + WR_NEXT <= WR_CH; --WAIT_C; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"3"; +-- + when WAIT_C => + WR_NEXT <= WAIT_D; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"3"; +-- + when WAIT_D => + WR_NEXT <= WR_CH; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_fsm_debug_fsm <= x"3"; +-- when others => - FSM_RDO_BUSY_NEXT <= NOT_BUSY; + WR_NEXT <= IDLE; + wr_fsm_debug_fsm <= x"F"; + end case; - end process FSM_READOUT_BUSY; + end process WR_FSM; - READOUT_BUSY_OUT <= readout_busy; + fifo_nr_wr_reg <= fifo_nr_wr when rising_edge(CLK_100); + fifo_nr_wr_2reg <= fifo_nr_wr_reg when rising_edge(CLK_100); + fifo_nr_wr_3reg <= fifo_nr_wr_2reg when rising_edge(CLK_100); + wr_ch_data_reg <= wr_ch_data_i when rising_edge(CLK_100); --- Fifo number determination - CREAT_MASK : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - mask <= (others => '1'); - empty_channels <= (others => '1'); - elsif trg_win_end_100_p = '1' then - mask(CHANNEL_NUMBER-1 downto 0) <= CH_EMPTY_IN(CHANNEL_NUMBER-1 downto 0); - empty_channels(CHANNEL_NUMBER-1 downto 0) <= CH_EMPTY_IN(CHANNEL_NUMBER-1 downto 0); - elsif updt_mask = '1' then - mask(fifo_nr) <= '1'; - end if; - end if; - end process CREAT_MASK; - - GEN : for i in 0 to 8 generate - ROM : ROM_FIFO - port map ( - Address => mask(8*(i+1)-1 downto 8*i), - OutClock => CLK_100, - OutClockEn => '1', - Reset => RESET_100, - Q => fifo_nr_hex(i)); - end generate GEN; - - CON_FIFO_NR_HEX_TO_INT : process (CLK_100) +------------------------------------------------------------------------------- +-- Data out mux +------------------------------------------------------------------------------- + -- Trigger window selection + TriggerWindowElimination : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' then - fifo_nr_next <= CHANNEL_NUMBER; - elsif fifo_nr_hex(0)(3) /= '1' then - fifo_nr_next <= to_integer("00000" & unsigned(fifo_nr_hex(0)(2 downto 0))); - elsif fifo_nr_hex(1)(3) /= '1' then - fifo_nr_next <= to_integer("00001" & unsigned(fifo_nr_hex(1)(2 downto 0))); - elsif fifo_nr_hex(2)(3) /= '1' then - fifo_nr_next <= to_integer("00010" & unsigned(fifo_nr_hex(2)(2 downto 0))); - elsif fifo_nr_hex(3)(3) /= '1' then - fifo_nr_next <= to_integer("00011" & unsigned(fifo_nr_hex(3)(2 downto 0))); - elsif fifo_nr_hex(4)(3) /= '1' then - fifo_nr_next <= to_integer("00100" & unsigned(fifo_nr_hex(4)(2 downto 0))); - elsif fifo_nr_hex(5)(3) /= '1' then - fifo_nr_next <= to_integer("00101" & unsigned(fifo_nr_hex(5)(2 downto 0))); - elsif fifo_nr_hex(6)(3) /= '1' then - fifo_nr_next <= to_integer("00110" & unsigned(fifo_nr_hex(6)(2 downto 0))); - elsif fifo_nr_hex(7)(3) /= '1' then - fifo_nr_next <= to_integer("00111" & unsigned(fifo_nr_hex(7)(2 downto 0))); - elsif fifo_nr_hex(8)(3) /= '1' then - fifo_nr_next <= to_integer("01000" & unsigned(fifo_nr_hex(8)(2 downto 0))); + if ch_data_3reg(fifo_nr_wr_reg)(35 downto 32) = x"1" and ch_data_3reg(fifo_nr_wr_reg)(31) = '1' then --DATA word + if TRIGGER_WIN_EN_IN = '1' then -- trigger window enabled + --elsif (TW_pre(10) = '1' and ref_time_coarse(10) = '0') or (TW_post(10) = '0' and ref_time_coarse(10) = '1') then -- if one of the trigger window edges has an overflow + -- if (trig_win_l = '0' and trig_win_r = '1') or (trig_win_l = '1' and trig_win_r = '0') then + -- ch_data_4reg <= ch_data_3reg(fifo_nr); + -- data_wr_reg <= '1'; + -- else + -- ch_data_4reg <= (others => '1'); + -- data_wr_reg <= '0'; + -- end if; + if trig_win_l = '1' and trig_win_r = '1' then -- if both of the trigger window edges are in the coarse counter boundries + ch_data_4reg <= ch_data_3reg(fifo_nr_wr_reg)(31 downto 0); + elsif trig_win_r = '0' then -- any hit that might come after the trigger window + ch_data_4reg <= (others => '0'); + --else + -- ch_data_4reg <= (others => '0'); + end if; + else + ch_data_4reg <= ch_data_3reg(fifo_nr_wr_reg)(31 downto 0); + end if; else - fifo_nr_next <= CHANNEL_NUMBER; + ch_data_4reg <= ch_data_3reg(fifo_nr_wr_reg)(31 downto 0); end if; end if; - end process CON_FIFO_NR_HEX_TO_INT; + end process TriggerWindowElimination; - UPDATE_INDEX_NR : process (CLK_100) - begin - if rising_edge(CLK_100) then - if RESET_100 = '1' then - fifo_nr <= CHANNEL_NUMBER; - elsif updt_index_reg = '1' then - fifo_nr <= fifo_nr_next; - end if; - end if; - end process UPDATE_INDEX_NR; -------------------------------------------------------------------------------- --- Data out mux -------------------------------------------------------------------------------- - Data_Out_MUX : process (CLK_100, RESET_100) + Data_Out_MUX : process (CLK_100) variable i : integer := 0; begin if rising_edge(CLK_100) then - if RESET_100 = '1' then - data_out_reg <= (others => '1'); - data_wr_reg <= '0'; + if wr_ch_data_reg = '1' then + data_out_reg <= ch_data_4reg; stop_status_i <= '0'; - elsif wr_header = '1' then - data_out_reg <= "001" & "00000" & TRG_CODE_IN & header_error_bits; - data_wr_reg <= '1'; - stop_status_i <= '0'; - elsif wr_ch_data_2reg = '1' then - if TRIGGER_WIN_EN_IN = '1' then -- if the trigger window is enabled - if ch_data_2reg(fifo_nr)(31 downto 29) = "011" then - data_out_reg <= ch_data_2reg(fifo_nr); - data_wr_reg <= '1'; - --elsif (TW_pre(10) = '1' and ref_time_coarse(10) = '0') or (TW_post(10) = '0' and ref_time_coarse(10) = '1') then -- if one of the trigger window edges has an overflow - -- if (trg_win_l = '0' and trg_win_r = '1') or (trg_win_l = '1' and trg_win_r = '0') then - -- data_out_reg <= ch_data_2reg(fifo_nr); - -- data_wr_reg <= '1'; - -- else - -- data_out_reg <= (others => '1'); - -- data_wr_reg <= '0'; - -- end if; - else -- if both of the trigger window edges are in the coarse counter boundries - if (trg_win_l = '1' and trg_win_r = '1') then - data_out_reg <= ch_data_2reg(fifo_nr); - data_wr_reg <= '1'; - else - data_out_reg <= (others => '1'); - data_wr_reg <= '0'; - end if; - end if; - stop_status_i <= '0'; - elsif TRIGGER_WIN_EN_IN = '0' then - data_out_reg <= ch_data_2reg(fifo_nr); - data_wr_reg <= '1'; - stop_status_i <= '0'; - end if; elsif wr_status = '1' then case i is when 0 => data_out_reg <= "010" & "00000" & std_logic_vector(trig_number); @@ -718,29 +680,35 @@ begin -- behavioral i := -1; when others => null; end case; - data_wr_reg <= '1'; - i := i+1; - elsif wr_trailer = '1' then - data_out_reg <= "011" & "0000000000000" & trailer_error_bits; - data_wr_reg <= '1'; - stop_status_i <= '0'; + i := i+1; + --elsif wr_trailer = '1' then + -- data_out_reg <= "011" & "0000000000000" & trailer_error_bits; + -- data_wr_reg <= '1'; + -- stop_status_i <= '0'; else data_out_reg <= (others => '1'); - data_wr_reg <= '0'; stop_status_i <= '0'; end if; end if; end process Data_Out_MUX; + wr_info <= wr_status when rising_edge(CLK_100); + wr_time <= wr_ch_data_reg and ch_data_4reg(31) when rising_edge(CLK_100); + wr_epoch <= wr_ch_data_reg and not data_out_reg(31) and data_out_reg(30) and data_out_reg(29) and ch_data_4reg(31); + + -- and not (and_all(ch_data_4reg(31 downto 29))) + + DATA_OUT <= data_out_reg; - DATA_WRITE_OUT <= data_wr_reg; - DATA_FINISHED_OUT <= data_finished_reg; - TRG_RELEASE_OUT <= trg_release_reg; + DATA_WRITE_OUT <= wr_info or wr_time or wr_epoch; --data_wr_reg; + DATA_FINISHED_OUT <= data_finished; + TRG_RELEASE_OUT <= trig_release; TRG_STATUSBIT_OUT <= (others => '0'); - READOUT_DEBUG(7 downto 0) <= fsm_debug; + READOUT_DEBUG(3 downto 0) <= rd_fsm_debug; + READOUT_DEBUG(7 downto 4) <= wr_fsm_debug; READOUT_DEBUG(8) <= data_wr_reg; - READOUT_DEBUG(9) <= data_finished_reg; - READOUT_DEBUG(10) <= trg_release_reg; + READOUT_DEBUG(9) <= finished_i; + READOUT_DEBUG(10) <= trig_release; READOUT_DEBUG(16 downto 11) <= data_out_reg(27 downto 22); READOUT_DEBUG(31 downto 17) <= (others => '0'); @@ -748,15 +716,14 @@ begin -- behavioral header_error_bits(15 downto 3) <= (others => '0'); header_error_bits(0) <= '0'; --header_error_bits(0) <= lost_hit_i; -- if there is at least one lost hit (can be more if the FIFO is full). - header_error_bits(1) <= ch_full_i; -- if the channel FIFO is full. - header_error_bits(2) <= ch_almost_full_i; -- if the channel FIFO is almost full. + header_error_bits(1) <= '0'; -- ch_full_i; + header_error_bits(2) <= '0'; -- Error, warning bits set in the trailer trailer_error_bits <= (others => '0'); - -- trailer_error_bits (0) <= wrong_readout_i; -- if there is a wrong readout because of a spurious timing trigger. + -- trailer_error_bits (0) <= wrong_readout_i; -- if there is a wrong readout because of a spurious timing trigger ch_full_i <= or_all(CH_FULL_IN); - ch_almost_full_i <= or_all(CH_ALMOST_FULL_IN); @@ -769,35 +736,35 @@ begin -- behavioral clock => CLK_100, en_clk => '1', signal_in => VALID_TIMING_TRG_IN, - pulse => valid_timing_trg_p); + pulse => valid_timing_trig_p); edge_to_pulse_2 : edge_to_pulse port map ( clock => CLK_100, en_clk => '1', signal_in => VALID_NOTIMING_TRG_IN, - pulse => valid_notiming_trg_p); + pulse => valid_notiming_trig_p); edge_to_pulse_3 : edge_to_pulse port map ( clock => CLK_100, en_clk => '1', signal_in => INVALID_TRG_IN, - pulse => invalid_trg_p); + pulse => invalid_trig_p); edge_to_pulse_4 : edge_to_pulse port map ( clock => CLK_100, en_clk => '1', signal_in => MULTI_TMG_TRG_IN, - pulse => multi_tmg_trg_p); + pulse => multi_tmg_trig_p); edge_to_pulse_5 : edge_to_pulse port map ( clock => CLK_100, en_clk => '1', signal_in => SPURIOUS_TRG_IN, - pulse => spurious_trg_p); + pulse => spurious_trig_p); edge_to_pulse_6 : edge_to_pulse port map ( @@ -814,94 +781,94 @@ begin -- behavioral pulse => timeout_detected_p); -- Internal trigger number counter (only valid triggers) - Statistics_Trigger_Number : process (CLK_100, RESET_100) + Statistics_Trigger_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then trig_number <= (others => '0'); - elsif valid_timing_trg_p = '1' or valid_notiming_trg_p = '1' then + elsif valid_timing_trig_p = '1' or valid_notiming_trig_p = '1' then trig_number <= trig_number + to_unsigned(1, 1); end if; end if; end process Statistics_Trigger_Number; -- Internal release number counter - Statistics_Release_Number : process (CLK_100, RESET_100) + Statistics_Release_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then release_number <= (others => '0'); - elsif trg_release_reg = '1' then + elsif trig_release = '1' then release_number <= release_number + to_unsigned(1, 1); end if; end if; end process Statistics_Release_Number; -- Internal valid timing trigger number counter - Statistics_Valid_Timing_Trigger_Number : process (CLK_100, RESET_100) + Statistics_Valid_Timing_Trigger_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then valid_tmg_trig_number <= (others => '0'); - elsif valid_timing_trg_p = '1' then + elsif valid_timing_trig_p = '1' then valid_tmg_trig_number <= valid_tmg_trig_number + to_unsigned(1, 1); end if; end if; end process Statistics_Valid_Timing_Trigger_Number; -- Internal valid NOtiming trigger number counter - Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100, RESET_100) + Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then valid_NOtmg_trig_number <= (others => '0'); - elsif valid_notiming_trg_p = '1' then + elsif valid_notiming_trig_p = '1' then valid_NOtmg_trig_number <= valid_NOtmg_trig_number + to_unsigned(1, 1); end if; end if; end process Statistics_Valid_NoTiming_Trigger_Number; -- Internal invalid trigger number counter - Statistics_Invalid_Trigger_Number : process (CLK_100, RESET_100) + Statistics_Invalid_Trigger_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then invalid_trig_number <= (others => '0'); - elsif invalid_trg_p = '1' then + elsif invalid_trig_p = '1' then invalid_trig_number <= invalid_trig_number + to_unsigned(1, 1); end if; end if; end process Statistics_Invalid_Trigger_Number; -- Internal multi timing trigger number counter - Statistics_Multi_Timing_Trigger_Number : process (CLK_100, RESET_100) + Statistics_Multi_Timing_Trigger_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then multi_tmg_trig_number <= (others => '0'); - elsif multi_tmg_trg_p = '1' then + elsif multi_tmg_trig_p = '1' then multi_tmg_trig_number <= multi_tmg_trig_number + to_unsigned(1, 1); end if; end if; end process Statistics_Multi_Timing_Trigger_Number; -- Internal spurious trigger number counter - Statistics_Spurious_Trigger_Number : process (CLK_100, RESET_100) + Statistics_Spurious_Trigger_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then spurious_trig_number <= (others => '0'); - elsif spurious_trg_p = '1' then + elsif spurious_trig_p = '1' then spurious_trig_number <= spurious_trig_number + to_unsigned(1, 1); end if; end if; end process Statistics_Spurious_Trigger_Number; -- Number of wrong readout becasue of spurious trigger - Statistics_Wrong_Readout_Number : process (CLK_100, RESET_100) + Statistics_Wrong_Readout_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then wrong_readout_number <= (others => '0'); elsif wrong_readout_up = '1' then wrong_readout_number <= wrong_readout_number + to_unsigned(1, 1); @@ -910,10 +877,10 @@ begin -- behavioral end process Statistics_Wrong_Readout_Number; -- Internal spike number counter - Statistics_Spike_Number : process (CLK_100, RESET_100) + Statistics_Spike_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then spike_number <= (others => '0'); elsif spike_detected_p = '1' then spike_number <= spike_number + to_unsigned(1, 1); @@ -922,10 +889,10 @@ begin -- behavioral end process Statistics_Spike_Number; -- Internal timeout number counter - Statistics_Timeout_Number : process (CLK_100, RESET_100) + Statistics_Timeout_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then timeout_number <= (others => '0'); elsif timeout_detected_p = '1' then timeout_number <= timeout_number + to_unsigned(1, 1); @@ -934,10 +901,10 @@ begin -- behavioral end process Statistics_Timeout_Number; -- IDLE time of the TDC readout - Statistics_Idle_Time : process (CLK_100, RESET_100) + Statistics_Idle_Time : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then idle_time <= (others => '0'); elsif idle_time_up = '1' then idle_time <= idle_time + to_unsigned(1, 1); @@ -946,10 +913,10 @@ begin -- behavioral end process Statistics_Idle_Time; -- Readout and Wait time of the TDC readout - Statistics_Readout_Wait_Time : process (CLK_100, RESET_100) + Statistics_Readout_Wait_Time : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then + if RESET_COUNTERS = '1' then readout_time <= (others => '0'); wait_time <= (others => '0'); elsif readout_time_up = '1' then @@ -960,97 +927,50 @@ begin -- behavioral end if; end process Statistics_Readout_Wait_Time; --- Empty channel number - Statistics_Empty_Channel_Number : process (CLK_100, RESET_100) - variable i : integer := CHANNEL_NUMBER; + -- Number of sent data finished + Statistics_Finished_Number : process (CLK_100) begin if rising_edge(CLK_100) then - if RESET_100 = '1' or RESET_COUNTERS = '1' then - total_empty_channel <= (others => '0'); - i := CHANNEL_NUMBER; - elsif trg_win_end_100_p = '1' then - i := 0; - elsif i = CHANNEL_NUMBER then - i := i; - elsif empty_channels(i) = '1' then - total_empty_channel <= total_empty_channel + to_unsigned(1, 1); - i := i + 1; - else - i := i + 1; + if RESET_COUNTERS = '1' then + finished_number <= (others => '0'); + elsif data_finished = '1' then --finished_i = '1' then + finished_number <= finished_number + to_unsigned(1, 1); end if; end if; - end process Statistics_Empty_Channel_Number; + end process Statistics_Finished_Number; -------------------------------------------------------------------------------- --- SLOW CONTROL REGISTERS -------------------------------------------------------------------------------- + HistoryReadDebug : process (CLK_100) + begin + if rising_edge(CLK_100) then + if rd_fsm_debug_reg /= rd_fsm_debug then + history_rd_fsm <= history_rd_fsm(27 downto 0) & rd_fsm_debug; + end if; + rd_fsm_debug_reg <= rd_fsm_debug; + end if; + end process HistoryReadDebug; ----- Register 0x80 --- SLOW_CONTROL_REG_OUT(31 downto 0) <= ----- Register 0x81 --- SLOW_CONTROL_REG_OUT(1*32+31 downto 1*32+0) <= ----- Register 0x82 --- SLOW_CONTROL_REG_OUT(2*32+31 downto 2*32+0) <= ----- Register 0x83 --- SLOW_CONTROL_REG_OUT(3*32+31 downto 3*32+0) <= ----- Register 0x84 --- SLOW_CONTROL_REG_OUT(4*32+31 downto 4*32+0) <= ----- Register 0x85 --- SLOW_CONTROL_REG_OUT(5*32+31 downto 5*32+0) <= ----- Register 0x86 --- SLOW_CONTROL_REG_OUT(6*32+31 downto 6*32+0) <= ----- Register 0x87 --- SLOW_CONTROL_REG_OUT(7*32+31 downto 7*32+0) <= ----- Register 0x88 --- SLOW_CONTROL_REG_OUT(8*32+31 downto 8*32+0) <= ----- Register 0x89 --- SLOW_CONTROL_REG_OUT(9*32+31 downto 9*32+0) <= ----- Register 0x8a --- SLOW_CONTROL_REG_OUT(10*32+31 downto 10*32+0) <= ----- Register 0x8b --- SLOW_CONTROL_REG_OUT(11*32+31 downto 11*32+0) <= ----- Register 0x8c --- SLOW_CONTROL_REG_OUT(12*32+31 downto 12*32+0) <= ----- Register 0x8d --- SLOW_CONTROL_REG_OUT(13*32+31 downto 13*32+0) <= ----- Register 0x8e --- SLOW_CONTROL_REG_OUT(14*32+31 downto 14*32+0) <= ----- Register 0x8f --- SLOW_CONTROL_REG_OUT(15*32+31 downto 15*32+0) <= ----- Register 0x90 --- SLOW_CONTROL_REG_OUT(16*32+31 downto 16*32+0) <= ----- Register 0x91 --- SLOW_CONTROL_REG_OUT(17*32+31 downto 17*32+0) <= ----- Register 0x93 --- SLOW_CONTROL_REG_OUT(19*32+31 downto 19*32+0) <= ----- Register 0x94 --- SLOW_CONTROL_REG_OUT(20*32+31 downto 20*32+0) <= ----- Register 0x95 --- SLOW_CONTROL_REG_OUT(21*32+31 downto 21*32+0) <= ----- Register 0x96 --- SLOW_CONTROL_REG_OUT(22*32+31 downto 22*32+0) <= ----- Register 0x97 --- SLOW_CONTROL_REG_OUT(23*32+31 downto 23*32+0) <= ----- Register 0x98 --- SLOW_CONTROL_REG_OUT(24*32+31 downto 24*32+0) <= ----- Register 0x99 --- SLOW_CONTROL_REG_OUT(25*32+31 downto 25*32+0) <= ----- Register 0x9a --- SLOW_CONTROL_REG_OUT(26*32+31 downto 26*32+0) <= ----- Register 0x9f --- SLOW_CONTROL_REG_OUT(27*32+31 downto 27*32+0) <= - - SLOW_CONTROL_REG_OUT(32*2**STATUS_REG_NR-1 downto 0) <= (others => '0'); + HistoryWriteDebug : process (CLK_100) + begin + if rising_edge(CLK_100) then + if wr_fsm_debug_reg /= wr_fsm_debug then + history_wr_fsm <= history_wr_fsm(27 downto 0) & wr_fsm_debug; + end if; + wr_fsm_debug_reg <= wr_fsm_debug; + end if; + end process HistoryWriteDebug; ------------------------------------------------------------------------------- -- STATUS REGISTERS BUS ------------------------------------------------------------------------------- - STATUS_REGISTERS_BUS_OUT(0)(7 downto 0) <= fsm_debug; - STATUS_REGISTERS_BUS_OUT(0)(15 downto 8) <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8)); + STATUS_REGISTERS_BUS_OUT(0)(3 downto 0) <= rd_fsm_debug; + STATUS_REGISTERS_BUS_OUT(0)(7 downto 4) <= wr_fsm_debug; + STATUS_REGISTERS_BUS_OUT(0)(15 downto 8) <= std_logic_vector(to_unsigned(MODULE_NUMBER*(CHANNEL_NUMBER-1), 8)); STATUS_REGISTERS_BUS_OUT(0)(16) <= REFERENCE_TIME when rising_edge(CLK_100); - STATUS_REGISTERS_BUS_OUT(0)(31 downto 17) <= (others => '0'); - STATUS_REGISTERS_BUS_OUT(1) <= slow_control_ch_empty_i(31 downto 0); - STATUS_REGISTERS_BUS_OUT(2) <= slow_control_ch_empty_i(63 downto 32); + STATUS_REGISTERS_BUS_OUT(0)(27 downto 17) <= TDC_VERSION(10 downto 0); + STATUS_REGISTERS_BUS_OUT(0)(31 downto 28) <= TRG_TYPE_IN when rising_edge(CLK_100); + + STATUS_REGISTERS_BUS_OUT(1) <= (others => '0'); + STATUS_REGISTERS_BUS_OUT(2) <= (others => '0'); STATUS_REGISTERS_BUS_OUT(3)(10 downto 0) <= TRG_WIN_PRE; STATUS_REGISTERS_BUS_OUT(3)(15 downto 11) <= (others => '0'); STATUS_REGISTERS_BUS_OUT(3)(26 downto 16) <= TRG_WIN_POST; @@ -1070,36 +990,27 @@ begin -- behavioral STATUS_REGISTERS_BUS_OUT(15)(23 downto 0) <= std_logic_vector(release_number); STATUS_REGISTERS_BUS_OUT(16)(23 downto 0) <= std_logic_vector(readout_time); STATUS_REGISTERS_BUS_OUT(17)(23 downto 0) <= std_logic_vector(timeout_number); + STATUS_REGISTERS_BUS_OUT(18)(23 downto 0) <= std_logic_vector(finished_number); + + STATUS_REGISTERS_BUS_OUT(19) <= history_rd_fsm; + STATUS_REGISTERS_BUS_OUT(20) <= history_wr_fsm; - FILL_BUS1 : for i in 4 to 17 generate + FILL_BUS1 : for i in 4 to 18 generate STATUS_REGISTERS_BUS_OUT(i)(31 downto 24) <= (others => '0'); end generate FILL_BUS1; - FILL_BUS2 : for i in 18 to 23 generate - STATUS_REGISTERS_BUS_OUT(i) <= (others => '0'); - end generate FILL_BUS2; - - slow_control_ch_empty_i(64 downto CHANNEL_NUMBER-1) <= (others => '1'); - slow_control_ch_empty_i(CHANNEL_NUMBER-2 downto 0) <= ch_empty_2reg(CHANNEL_NUMBER-1 downto 1); - ------------------------------------------------------------------------------- -- Registering ------------------------------------------------------------------------------- --- 100 MHz - updt_index_reg <= updt_index when rising_edge(CLK_100); - wr_ch_data_reg <= wr_ch_data when rising_edge(CLK_100); - wr_ch_data_2reg <= wr_ch_data_reg when rising_edge(CLK_100); - data_finished_reg <= data_finished when rising_edge(CLK_100); - fifo_nr_reg <= fifo_nr when rising_edge(CLK_100); - ch_data_reg <= CH_DATA_IN when rising_edge(CLK_100); - ch_data_2reg <= ch_data_reg when rising_edge(CLK_100); --- ch_data_3reg <= ch_data_2reg when rising_edge(CLK_100); - ch_empty_reg <= CH_EMPTY_IN when rising_edge(CLK_100); - ch_empty_2reg <= ch_empty_reg when rising_edge(CLK_100); - ch_empty_3reg <= ch_empty_2reg when rising_edge(CLK_100); - ch_empty_4reg <= ch_empty_3reg when rising_edge(CLK_100); - --- 200 MHz - trg_win_post_200 <= TRG_WIN_POST when rising_edge(CLK_200); + ch_data_reg <= CH_DATA_IN when rising_edge(CLK_100); + ch_data_2reg <= ch_data_reg when rising_edge(CLK_100); + ch_data_3reg <= ch_data_2reg when rising_edge(CLK_100); +-- ch_data_4reg <= ch_data_3reg when rising_edge(CLK_100); + ch_empty_reg <= CH_EMPTY_IN when rising_edge(CLK_100); + ch_empty_2reg <= ch_empty_reg when rising_edge(CLK_100); + ch_empty_3reg <= ch_empty_2reg when rising_edge(CLK_100); + ch_empty_4reg <= ch_empty_3reg when rising_edge(CLK_100); + + trig_win_post_200 <= std_logic_vector(unsigned(TRIG_WIN_POST)-8) when rising_edge(CLK_200); end behavioral; diff --git a/tdc_releases/tdc_v2.0/Readout_header.vhd b/tdc_releases/tdc_v2.0/Readout_header.vhd new file mode 100644 index 0000000..7bd4096 --- /dev/null +++ b/tdc_releases/tdc_v2.0/Readout_header.vhd @@ -0,0 +1,151 @@ +------------------------------------------------------------------------------- +-- Title : Readout Header Entity +-- Project : +------------------------------------------------------------------------------- +-- File : Readout_header.vhd +-- Author : cugur@gsi.de +-- Created : 2012-10-25 +-- Last update: 2014-08-06 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--library work; +--use work.trb_net_std.all; +--use work.trb_net_components.all; +--use work.trb3_components.all; + +entity Readout_Header is + port ( + RESET_100 : in std_logic; + CLK_100 : in std_logic; +-- from the endpoint + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + INVALID_TRG_IN : in std_logic; + TRG_CODE_IN : in std_logic_vector(7 downto 0); + TRG_TYPE_IN : in std_logic_vector(3 downto 0); +-- to the endpoint + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic + ); +end entity Readout_Header; + +architecture behavioral of Readout_Header is + +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + + -- readout fsm + type FSM_READ is (IDLE, SEND_TRIG_RELEASE_A, SEND_TRIG_RELEASE_B, SEND_TRIG_RELEASE_C); + signal RD_CURRENT : FSM_READ := IDLE; + signal RD_NEXT : FSM_READ; + + signal data_finished_fsm : std_logic; + signal trig_release_fsm : std_logic; + signal wr_header_fsm : std_logic; + -- data mux + signal wr_header : std_logic; + -- to endpoint + signal data_out_reg : std_logic_vector(31 downto 0); + signal data_write : std_logic; + signal data_finished : std_logic; + signal trig_release : std_logic; + -- debug + signal header_error_bits : std_logic_vector(15 downto 0); + +begin -- behavioral + +------------------------------------------------------------------------------- +-- Readout +------------------------------------------------------------------------------- +-- Readout fsm + RD_FSM_CLK : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_100 = '1' then + RD_CURRENT <= IDLE; + else + RD_CURRENT <= RD_NEXT; + wr_header <= wr_header_fsm; + data_finished <= data_finished_fsm; + trig_release <= trig_release_fsm; + end if; + end if; + end process RD_FSM_CLK; + + RD_FSM_PROC : process (RD_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, INVALID_TRG_IN, + TRG_TYPE_IN) + begin + + RD_NEXT <= RD_CURRENT; + wr_header_fsm <= '0'; + data_finished_fsm <= '0'; + trig_release_fsm <= '0'; + + case (RD_CURRENT) is + when IDLE => + if VALID_TIMING_TRG_IN = '1' then + RD_NEXT <= SEND_TRIG_RELEASE_A; + wr_header_fsm <= '1'; + elsif VALID_NOTIMING_TRG_IN = '1' then + RD_NEXT <= SEND_TRIG_RELEASE_A; + if TRG_TYPE_IN = x"E" or TRG_TYPE_IN = x"D" then + wr_header_fsm <= '1'; + end if; + elsif INVALID_TRG_IN = '1' then + RD_NEXT <= SEND_TRIG_RELEASE_A; + end if; + + when SEND_TRIG_RELEASE_A => + RD_NEXT <= SEND_TRIG_RELEASE_B; + + when SEND_TRIG_RELEASE_B => + RD_NEXT <= SEND_TRIG_RELEASE_C; + data_finished_fsm <= '1'; + + when SEND_TRIG_RELEASE_C => + RD_NEXT <= IDLE; + trig_release_fsm <= '1'; + + when others => + RD_NEXT <= IDLE; + end case; + end process RD_FSM_PROC; + +------------------------------------------------------------------------------- +-- Data out mux +------------------------------------------------------------------------------- + + Data_Out_MUX : process (CLK_100) + begin + if rising_edge(CLK_100) then + if wr_header = '1' then + data_out_reg <= "001" & "0" & TRG_TYPE_IN & TRG_CODE_IN & header_error_bits; + else + data_out_reg <= (others => '1'); + end if; + data_write <= wr_header; + end if; + end process Data_Out_MUX; + + DATA_OUT <= data_out_reg; + DATA_WRITE_OUT <= data_write; + DATA_FINISHED_OUT <= data_finished; + TRG_RELEASE_OUT <= trig_release; + TRG_STATUSBIT_OUT <= (others => '0'); + + -- Error, warning bits set in the header + header_error_bits <= (others => '0'); + +end behavioral; diff --git a/tdc_releases/tdc_v2.0/ShiftRegisterSISO.vhd b/tdc_releases/tdc_v2.0/ShiftRegisterSISO.vhd index 497d384..a82160b 100644 --- a/tdc_releases/tdc_v2.0/ShiftRegisterSISO.vhd +++ b/tdc_releases/tdc_v2.0/ShiftRegisterSISO.vhd @@ -5,7 +5,7 @@ -- File : Register.vhd -- Author : c.ugur@gsi.de -- Created : 2012-10-02 --- Last update: 2012-10-04 +-- Last update: 2013-03-06 ------------------------------------------------------------------------------- -- Description: Used to register signals n levels. ------------------------------------------------------------------------------- @@ -23,7 +23,6 @@ entity ShiftRegisterSISO is port ( CLK : in std_logic; -- register clock - RESET : in std_logic; -- register reset D_IN : in std_logic_vector(WIDTH-1 downto 0); -- register input D_OUT : out std_logic_vector(WIDTH-1 downto 0)); -- register out @@ -42,14 +41,10 @@ begin -- RTL reg(0) <= D_IN; GEN_Registers : for i in 1 to DEPTH generate - Registers : process (CLK, RESET) + Registers : process (CLK) begin if rising_edge(CLK) then - if RESET = '1' then - reg(i) <= (others => '0'); - else - reg(i) <= reg(i-1); - end if; + reg(i) <= reg(i-1); end if; end process Registers; end generate GEN_Registers; diff --git a/tdc_releases/tdc_v2.0/Stretcher.vhd b/tdc_releases/tdc_v2.0/Stretcher.vhd index 370f86e..684beed 100644 --- a/tdc_releases/tdc_v2.0/Stretcher.vhd +++ b/tdc_releases/tdc_v2.0/Stretcher.vhd @@ -5,7 +5,7 @@ -- File : Stretcher.vhd -- Author : cugur@gsi.de -- Created : 2012-11-07 --- Last update: 2012-11-08 +-- Last update: 2014-08-27 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -30,42 +30,34 @@ end Stretcher; architecture behavioral of Stretcher is - signal pulse_inverse1 : std_logic; - signal pulse_inverse2 : std_logic; - signal pulse_inverse3 : std_logic; - signal pulse_latch : std_logic; - - attribute syn_keep : boolean; - attribute syn_keep of pulse_inverse1 : signal is true; - attribute syn_keep of pulse_inverse2 : signal is true; - attribute syn_keep of pulse_inverse3 : signal is true; - attribute syn_keep of pulse_latch : signal is true; - attribute syn_preserve : boolean; - attribute syn_preserve of pulse_inverse1 : signal is true; - attribute syn_preserve of pulse_inverse2 : signal is true; - attribute syn_preserve of pulse_inverse3 : signal is true; - attribute syn_preserve of pulse_latch : signal is true; - attribute NOMERGE : string; - attribute NOMERGE of pulse_inverse1 : signal is "KEEP"; - attribute NOMERGE of pulse_inverse2 : signal is "KEEP"; - attribute NOMERGE of pulse_inverse3 : signal is "KEEP"; - attribute NOMERGE of pulse_latch : signal is "KEEP"; + signal pulse_d1 : std_logic; + signal pulse_d2 : std_logic; + signal pulse_d3 : std_logic; + signal pulse_d4 : std_logic; + + attribute syn_keep : boolean; + attribute syn_keep of pulse_d1 : signal is true; + attribute syn_keep of pulse_d2 : signal is true; + attribute syn_keep of pulse_d3 : signal is true; + attribute syn_keep of pulse_d4 : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of pulse_d1 : signal is true; + attribute syn_preserve of pulse_d2 : signal is true; + attribute syn_preserve of pulse_d3 : signal is true; + attribute syn_preserve of pulse_d4 : signal is true; + attribute NOMERGE : string; + attribute NOMERGE of pulse_d1 : signal is "KEEP"; + attribute NOMERGE of pulse_d2 : signal is "KEEP"; + attribute NOMERGE of pulse_d3 : signal is "KEEP"; + attribute NOMERGE of pulse_d4 : signal is "KEEP"; begin -- behavioral - pulse_inverse1 <= not PULSE_IN; - pulse_inverse2 <= not pulse_inverse1; - pulse_inverse3 <= not pulse_inverse2; - - TheStretcher : process (PULSE_IN, pulse_inverse3) - begin - if PULSE_IN = '1' then - pulse_latch <= '1'; - elsif rising_edge(pulse_inverse3) then - pulse_latch <= '0'; - end if; - end process TheStretcher; + pulse_d1 <= not PULSE_IN; + pulse_d2 <= not pulse_d1; + pulse_d3 <= not pulse_d2; + pulse_d4 <= not pulse_d3; - PULSE_OUT <= pulse_latch; + PULSE_OUT <= transport pulse_d4 after 30 ns; end behavioral; diff --git a/tdc_releases/tdc_v2.0/TDC.vhd b/tdc_releases/tdc_v2.0/TDC.vhd index 8021d08..f219316 100644 --- a/tdc_releases/tdc_v2.0/TDC.vhd +++ b/tdc_releases/tdc_v2.0/TDC.vhd @@ -7,43 +7,50 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; +use work.config.all; +use work.tdc_components.all; use work.version.all; entity TDC is generic ( - CHANNEL_NUMBER : integer range 2 to 65; - STATUS_REG_NR : integer range 0 to 6; - CONTROL_REG_NR : integer range 0 to 6); + MODULE_NUMBER : integer range 1 to 4; + CHANNEL_NUMBER : integer range 2 to 64; + STATUS_REG_NR : integer range 0 to 31; + CONTROL_REG_NR : integer range 0 to 6; + TDC_VERSION : std_logic_vector(11 downto 0); + DEBUG : integer range 0 to 1 := c_NO; + SIMULATION : integer range 0 to 1 := c_NO); port ( RESET : in std_logic; CLK_TDC : in std_logic; CLK_READOUT : in std_logic; REFERENCE_TIME : in std_logic; - HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); + HIT_IN : in std_logic_vector(MODULE_NUMBER*CHANNEL_NUMBER downto 1); + HIT_CALIBRATION : in std_logic; TRG_WIN_PRE : in std_logic_vector(10 downto 0); TRG_WIN_POST : in std_logic_vector(10 downto 0); -- -- Trigger signals from handler - TRG_DATA_VALID_IN : in std_logic; - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - INVALID_TRG_IN : in std_logic; - TMGTRG_TIMEOUT_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - SPURIOUS_TRG_IN : in std_logic; + TRG_DATA_VALID_IN : in std_logic := '0'; + VALID_TIMING_TRG_IN : in std_logic := '0'; + VALID_NOTIMING_TRG_IN : in std_logic := '0'; + INVALID_TRG_IN : in std_logic := '0'; + TMGTRG_TIMEOUT_IN : in std_logic := '0'; + SPIKE_DETECTED_IN : in std_logic := '0'; + MULTI_TMG_TRG_IN : in std_logic := '0'; + SPURIOUS_TRG_IN : in std_logic := '0'; -- - TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - TRG_CODE_IN : in std_logic_vector(7 downto 0); - TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - TRG_TYPE_IN : in std_logic_vector(3 downto 0); + TRG_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0'); + TRG_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0'); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0) := (others => '0'); + TRG_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0'); -- --Response to handler - TRG_RELEASE_OUT : out std_logic; - TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_WRITE_OUT : out std_logic; - DATA_FINISHED_OUT : out std_logic; + TRG_RELEASE_OUT : out std_logic_vector(MODULE_NUMBER downto 0); + TRG_STATUSBIT_OUT : out std_logic_vector_array_32(0 to MODULE_NUMBER); + DATA_OUT : out std_logic_vector_array_32(0 to MODULE_NUMBER); + DATA_WRITE_OUT : out std_logic_vector(MODULE_NUMBER downto 0); + DATA_FINISHED_OUT : out std_logic_vector(MODULE_NUMBER downto 0); -- --To Bus Handler HCB_READ_EN_IN : in std_logic; @@ -58,18 +65,24 @@ entity TDC is SRB_DATA_OUT : out std_logic_vector(31 downto 0); SRB_DATAREADY_OUT : out std_logic; SRB_UNKNOWN_ADDR_OUT : out std_logic; + CDB_READ_EN_IN : in std_logic; + CDB_WRITE_EN_IN : in std_logic; + CDB_ADDR_IN : in std_logic_vector(6 downto 0); + CDB_DATA_OUT : out std_logic_vector(31 downto 0); + CDB_DATAREADY_OUT : out std_logic; + CDB_UNKNOWN_ADDR_OUT : out std_logic; ESB_READ_EN_IN : in std_logic; ESB_WRITE_EN_IN : in std_logic; ESB_ADDR_IN : in std_logic_vector(6 downto 0); ESB_DATA_OUT : out std_logic_vector(31 downto 0); ESB_DATAREADY_OUT : out std_logic; ESB_UNKNOWN_ADDR_OUT : out std_logic; - FWB_READ_EN_IN : in std_logic; - FWB_WRITE_EN_IN : in std_logic; - FWB_ADDR_IN : in std_logic_vector(6 downto 0); - FWB_DATA_OUT : out std_logic_vector(31 downto 0); - FWB_DATAREADY_OUT : out std_logic; - FWB_UNKNOWN_ADDR_OUT : out std_logic; + EFB_READ_EN_IN : in std_logic; + EFB_WRITE_EN_IN : in std_logic; + EFB_ADDR_IN : in std_logic_vector(6 downto 0); + EFB_DATA_OUT : out std_logic_vector(31 downto 0); + EFB_DATAREADY_OUT : out std_logic; + EFB_UNKNOWN_ADDR_OUT : out std_logic; LHB_READ_EN_IN : in std_logic; LHB_WRITE_EN_IN : in std_logic; LHB_ADDR_IN : in std_logic_vector(6 downto 0); @@ -77,9 +90,8 @@ entity TDC is LHB_DATAREADY_OUT : out std_logic; LHB_UNKNOWN_ADDR_OUT : out std_logic; -- - SLOW_CONTROL_REG_OUT : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0); LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0); - CONTROL_REG_IN : in std_logic_vector(32*2**CONTROL_REG_NR-1 downto 0) + CONTROL_REG_IN : in std_logic_vector(32*CONTROL_REG_NR-1 downto 0) ); end TDC; @@ -88,147 +100,522 @@ architecture TDC of TDC is ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- + constant total_ch_number : integer range 1 to 64 := MODULE_NUMBER * CHANNEL_NUMBER; -- Reset Signals - signal reset_tdc : std_logic; + signal reset_rdo : std_logic; + signal reset_rdo_i : std_logic; + signal reset_tdc : std_logic; + signal reset_tdc_i : std_logic; -- Coarse counters - signal coarse_cntr : std_logic_vector_array_11(1 to 4); - signal coarse_cntr_reset : std_logic; - signal coarse_cntr_reset_r : std_logic_vector(4 downto 1); + signal coarse_cntr : std_logic_vector_array_11(0 to 8); + signal coarse_cntr_reset : std_logic; + signal coarse_cntr_reset_r : std_logic_vector(8 downto 0); -- Slow control - signal logic_anal_control : std_logic_vector(3 downto 0); - signal debug_mode_en_i : std_logic; - signal reset_counters_i : std_logic; - signal run_mode_i : std_logic; -- 1: cc reset every trigger - -- 0: free running mode - signal run_mode_200 : std_logic; - signal trigger_win_en_i : std_logic; - signal ch_en_i : std_logic_vector(64 downto 1); - signal ref_ch_en_i : std_logic; + signal logic_anal_control : std_logic_vector(3 downto 0); + signal debug_mode_en_i : std_logic; + signal reset_counters_i : std_logic; + signal run_mode_i : std_logic; -- 1: cc reset every trigger + -- 0: free running mode + signal run_mode_200 : std_logic; + signal run_mode_edge_200 : std_logic; + signal reset_coarse_cntr_i : std_logic; + signal reset_coarse_cntr_200 : std_logic; + signal reset_coarse_cntr_edge_200 : std_logic; + signal reset_coarse_cntr_flag : std_logic := '0'; + signal ch_en_i : std_logic_vector(64 downto 1); + signal data_limit_i : unsigned(7 downto 0); + signal calibration_on : std_logic; -- turns on calibration for trig type 0xC -- Logic analyser - signal logic_anal_data_i : std_logic_vector(3*32-1 downto 0); + signal logic_anal_data_i : std_logic_vector(3*32-1 downto 0); -- Hit signals - signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); - signal scaler_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); - signal ref_time_i : std_logic; + signal hit_in_d : std_logic_vector(total_ch_number downto 0); + signal hit_in_i : std_logic_vector(total_ch_number downto 0); + signal hit_latch : std_logic_vector(total_ch_number downto 1) := (others => '0'); + signal hit_edge_i : std_logic_vector(total_ch_number downto 1); + signal hit_reg : std_logic_vector(total_ch_number downto 1); + signal hit_2reg : std_logic_vector(total_ch_number downto 1); + signal hit_3reg : std_logic_vector(total_ch_number downto 1); + signal edge_rising : std_logic_vector(total_ch_number downto 1) := (others => '0'); + signal edge_rising_reg : std_logic_vector(total_ch_number downto 1); + signal edge_rising_2reg : std_logic_vector(total_ch_number downto 1); + signal edge_rising_3reg : std_logic_vector(total_ch_number downto 1); + signal edge_falling : std_logic_vector(total_ch_number downto 1) := (others => '0'); + signal edge_falling_reg : std_logic_vector(total_ch_number downto 1); + signal edge_falling_2reg : std_logic_vector(total_ch_number downto 1); + signal edge_falling_3reg : std_logic_vector(total_ch_number downto 1); +-- Calibration + signal hit_calibration_cntr : unsigned(15 downto 0) := (others => '0'); + signal hit_calibration_i : std_logic; + signal calibration_freq_select : unsigned(3 downto 0) := (others => '0'); -- To the channels - signal readout_busy_i : std_logic; - signal rd_en_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal trg_win_end_i : std_logic; + signal rd_en_i : std_logic_vector(total_ch_number downto 0); + signal trig_time_i : std_logic_vector(38 downto 0); -- From the channels - signal ch_data_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER); - signal ch_empty_i : std_logic_vector(CHANNEL_NUMBER downto 0); - signal ch_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal ch_almost_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal trg_time_i : std_logic_vector(38 downto 0); - signal ch_lost_hit_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); - signal ch_hit_detect_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); - signal ch_encoder_start_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); - signal ch_fifo_wr_number_i : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); - signal ch_level_hit_number : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); - signal ch_lost_hit_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); - signal ch_encoder_start_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); - signal ch_fifo_wr_bus_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal ch_data_i : std_logic_vector_array_36(0 to total_ch_number+1); + signal ch_data_valid_i : std_logic_vector(total_ch_number downto 0); + signal ch_wcnt_i : unsigned_array_8(0 to total_ch_number); + signal ch_empty_i : std_logic_vector(total_ch_number downto 0); + signal ch_full_i : std_logic_vector(total_ch_number downto 0); + signal ch_almost_empty_i : std_logic_vector(total_ch_number downto 0); + signal trg_time_i : std_logic_vector(38 downto 0); + signal ch_lost_hit_number_i : std_logic_vector_array_24(0 to total_ch_number); + signal ch_hit_detect_number_i : std_logic_vector_array_31(0 to total_ch_number); + signal ch_encoder_start_number_i : std_logic_vector_array_24(0 to total_ch_number); + signal ch_encoder_finished_number_i : std_logic_vector_array_24(0 to total_ch_number); + signal ch_level_hit_number : std_logic_vector_array_32(0 to total_ch_number); + signal ch_lost_hit_bus_i : std_logic_vector_array_32(0 to total_ch_number); + signal ch_encoder_start_bus_i : std_logic_vector_array_32(0 to total_ch_number); + signal ch_encoder_finished_bus_i : std_logic_vector_array_32(0 to total_ch_number); + signal ch_fifo_write_number_i : std_logic_vector_array_24(0 to total_ch_number); -- To the endpoint - signal data_finished_i : std_logic; + signal trg_release_out_i : std_logic_vector(MODULE_NUMBER downto 0); + signal trg_statusbit_out_i : std_logic_vector_array_32(0 to MODULE_NUMBER); + signal data_out_i : std_logic_vector_array_32(0 to MODULE_NUMBER); + signal data_write_out_i : std_logic_vector(MODULE_NUMBER downto 0); + signal data_finished_out_i : std_logic_vector(MODULE_NUMBER downto 0); + -- Epoch counter - signal epoch_cntr : std_logic_vector(27 downto 0); - signal epoch_cntr_up_i : std_logic; - signal epoch_cntr_reset_i : std_logic; + signal epoch_cntr : std_logic_vector(27 downto 0); + signal epoch_cntr_up_i : std_logic; + signal epoch_cntr_reset_i : std_logic; +-- Trigger Handler signals + signal trig_in_i : std_logic; + signal trig_rdo_i : std_logic; + signal trig_tdc_i : std_logic; + signal trig_win_en_i : std_logic; + signal trig_win_end_rdo : std_logic; + signal trig_win_end_tdc : std_logic; + signal trig_win_end_tdc_i : std_logic_vector(total_ch_number downto 0); + signal trig_win_end_tdc_mod : std_logic_vector(MODULE_NUMBER downto 1); + signal valid_trigger_rdo : std_logic; + signal valid_trigger_tdc : std_logic; + -- Debug signals - signal ref_debug_i : std_logic_vector(31 downto 0); - signal ch_debug_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); - signal readout_debug_i : std_logic_vector(31 downto 0); + signal ref_debug_i : std_logic_vector(31 downto 0); + signal ch_debug_i : std_logic_vector_array_32(0 to total_ch_number); + signal ch_200_debug_i : std_logic_vector_array_32(0 to total_ch_number); + signal readout_debug_i : std_logic_vector(31 downto 0); -- Bus signals - signal status_registers_bus_i : std_logic_vector_array_32(0 to 23); + signal status_registers_bus_i : std_logic_vector_array_32(0 to STATUS_REG_NR-1); - attribute syn_keep : boolean; - attribute syn_keep of reset_tdc : signal is true; - attribute syn_keep of coarse_cntr : signal is true; - attribute syn_keep of ref_time_i : signal is true; - attribute syn_preserve : boolean; - attribute syn_preserve of coarse_cntr : signal is true; + attribute syn_keep : boolean; + attribute syn_keep of reset_tdc : signal is true; + attribute syn_keep of coarse_cntr : signal is true; + attribute syn_keep of coarse_cntr_reset_r : signal is true; + attribute syn_keep of trig_win_end_tdc_i : signal is true; + attribute syn_keep of hit_in_i : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of coarse_cntr : signal is true; + attribute syn_preserve of coarse_cntr_reset_r : signal is true; + attribute syn_preserve of trig_win_end_tdc_i : signal is true; + attribute syn_preserve of hit_in_i : signal is true; + attribute nomerge : string; + attribute nomerge of hit_in_i : signal is "true"; + begin -- Slow control signals - logic_anal_control <= CONTROL_REG_IN(3 downto 0) when rising_edge(CLK_READOUT); - debug_mode_en_i <= CONTROL_REG_IN(4); - reset_counters_i <= CONTROL_REG_IN(8); - run_mode_i <= CONTROL_REG_IN(12); - run_mode_200 <= run_mode_i when rising_edge(CLK_TDC); -- Run mode control register synchronised to the coarse counter clk - trigger_win_en_i <= CONTROL_REG_IN(1*32+31); - ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); - ref_ch_en_i <= CONTROL_REG_IN(16); - --- Reset signal - reset_tdc <= RESET; - --- Channel enable signals - GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate - scaler_in_i(i) <= HIT_IN(i) and ch_en_i(i); - hit_in_i(i) <= scaler_in_i(i) and not(readout_busy_i); - end generate GEN_Channel_Enable; - ref_time_i <= REFERENCE_TIME and ref_ch_en_i; - --- Reference channel - The_Reference_Time : Reference_Channel - generic map ( - CHANNEL_ID => 0) + logic_anal_control <= CONTROL_REG_IN(3 downto 0) when rising_edge(CLK_READOUT); + debug_mode_en_i <= CONTROL_REG_IN(4); + reset_counters_i <= CONTROL_REG_IN(8) or reset_tdc when rising_edge(CLK_TDC); + run_mode_i <= CONTROL_REG_IN(12); + run_mode_200 <= run_mode_i when rising_edge(CLK_TDC); + reset_coarse_cntr_i <= CONTROL_REG_IN(13) when rising_edge(CLK_TDC); + reset_coarse_cntr_200 <= reset_coarse_cntr_i when rising_edge(CLK_TDC); + calibration_freq_select <= unsigned(CONTROL_REG_IN(31 downto 28)); + + trig_win_en_i <= CONTROL_REG_IN(1*32+31); + ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); + data_limit_i <= unsigned(CONTROL_REG_IN(4*32+7 downto 4*32+0)); + + +-- Reset signals + reset_tdc_i <= RESET when rising_edge(CLK_TDC); + reset_tdc <= reset_tdc_i when rising_edge(CLK_TDC); + reset_rdo <= RESET; + +------------------------------------------------------------------------------- +-- Hit Process +------------------------------------------------------------------------------- + -- Hit for calibration generation + Calibration_Pulses : process (HIT_CALIBRATION) + begin + if rising_edge(HIT_CALIBRATION) then + hit_calibration_cntr <= hit_calibration_cntr + to_unsigned(1, 16); + end if; + end process Calibration_Pulses; + + hit_calibration_i <= hit_calibration_cntr(to_integer(calibration_freq_select)); + + -- Blocks the input after the rising edge against short pulses + GEN_HitBlock : for i in 1 to total_ch_number generate + + -- for double edge in the same channel setup + gen_double : if DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + Stretcher_1 : entity work.Stretcher + port map ( + PULSE_IN => HIT_IN(i), + PULSE_OUT => hit_in_d(i)); + + edge_rising(i) <= '0' when edge_rising_3reg(i) = '1' else + '1' when rising_edge(HIT_IN(i)); + edge_rising_reg(i) <= edge_rising(i) when rising_edge(CLK_READOUT); -- using 100MHz clk for longer reset time + edge_rising_2reg(i) <= edge_rising_reg(i) when rising_edge(CLK_READOUT); + edge_rising_3reg(i) <= edge_rising_reg(i) and not edge_rising_2reg(i) when rising_edge(CLK_READOUT); + + edge_falling(i) <= '0' when edge_falling_3reg(i) = '1' else + '1' when falling_edge(hit_in_d(i)); + edge_falling_reg(i) <= edge_falling(i) when rising_edge(CLK_READOUT); -- using 100MHz clk for longer reset time + edge_falling_2reg(i) <= edge_falling_reg(i) when rising_edge(CLK_READOUT); + edge_falling_3reg(i) <= edge_falling_reg(i) and not edge_falling_2reg(i) when rising_edge(CLK_READOUT); + + hit_latch(i) <= edge_rising(i) or edge_falling(i); + hit_edge_i(i) <= '0' when edge_falling(i) = '1' else + '1' when rising_edge(edge_rising(i)); + end generate gen_double; + + -- for single edge and double edge in alternating channel setup + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 2 generate + hit_latch(i) <= '0' when hit_3reg(i) = '1' else + '1' when rising_edge(HIT_IN(i)); + hit_edge_i(i) <= '1'; + end generate gen_single; + end generate GEN_HitBlock; + + + GEN_hit_mux : for i in 1 to total_ch_number generate + hit_mux_ch : hit_mux + port map ( + CH_EN_IN => ch_en_i(i), + CALIBRATION_EN_IN => calibration_on, + HIT_CALIBRATION_IN => hit_calibration_i, + HIT_PHYSICAL_IN => hit_latch(i), + HIT_OUT => hit_in_i(i)); + end generate GEN_hit_mux; + + hit_mux_ref : hit_mux port map ( - RESET_200 => reset_tdc, - RESET_100 => RESET, - CLK_200 => CLK_TDC, - CLK_100 => CLK_READOUT, - HIT_IN => ref_time_i, - READ_EN_IN => rd_en_i(0), - VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN, - SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, - MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, - FIFO_DATA_OUT => ch_data_i(0), - FIFO_EMPTY_OUT => ch_empty_i(0), - FIFO_FULL_OUT => ch_full_i(0), - FIFO_ALMOST_FULL_OUT => ch_almost_full_i(0), - COARSE_COUNTER_IN => coarse_cntr(1), - EPOCH_COUNTER_IN => epoch_cntr, - TRIGGER_WINDOW_END_IN => trg_win_end_i, - DATA_FINISHED_IN => data_finished_i, - RUN_MODE => run_mode_i, - TRIGGER_TIME_STAMP_OUT => trg_time_i, - REF_DEBUG_OUT => ref_debug_i); + CH_EN_IN => '1', + CALIBRATION_EN_IN => calibration_on, + HIT_CALIBRATION_IN => hit_calibration_i, + HIT_PHYSICAL_IN => REFERENCE_TIME, + HIT_OUT => hit_in_i(0)); +---- Channel and calibration enable signals +-- GEN_Channel_Enable : for i in 1 to total_ch_number generate +-- process (ch_en_i, calibration_on, hit_calibration_i, hit_latch) +-- begin +-- if ch_en_i(i) = '1' then +-- if calibration_on = '1' then +-- hit_in_i(i) <= hit_calibration_i; +-- else +-- hit_in_i(i) <= hit_latch(i); +-- end if; +-- else +-- hit_in_i(i) <= '0'; +-- end if; +-- end process; +-- end generate GEN_Channel_Enable; + + ---- purpose: Calibration trigger for the reference channel + --process (calibration_on, hit_calibration_i, REFERENCE_TIME) is + --begin -- process + -- if calibration_on = '1' then + -- hit_in_i(0) <= hit_calibration_i; + -- else + -- hit_in_i(0) <= REFERENCE_TIME; + -- end if; + --end process; + + CalibrationSwitch : process (CLK_READOUT) + begin + if rising_edge(CLK_READOUT) then + if TRG_TYPE_IN = x"D" then + calibration_on <= '1'; + else + calibration_on <= '0'; + end if; + end if; + end process CalibrationSwitch; + +------------------------------------------------------------------------------- -- Channels - GEN_Channels : for i in 1 to CHANNEL_NUMBER - 1 generate +------------------------------------------------------------------------------- + -- Reference Channel to measure the reference time + ReferenceChannel : Channel + generic map ( + CHANNEL_ID => 0, + DEBUG => DEBUG, + SIMULATION => SIMULATION, + REFERENCE => c_NO) + port map ( + RESET_200 => reset_tdc, + RESET_100 => reset_rdo, + RESET_COUNTERS => reset_counters_i, + CLK_200 => CLK_TDC, + CLK_100 => CLK_READOUT, + HIT_IN => hit_in_i(0), + HIT_EDGE_IN => '1', + TRIGGER_WIN_END_TDC => trig_win_end_tdc_i(0), + TRIGGER_WIN_END_RDO => trig_win_end_rdo, + EPOCH_COUNTER_IN => epoch_cntr, + COARSE_COUNTER_IN => coarse_cntr(1), + READ_EN_IN => rd_en_i(0), + FIFO_DATA_OUT => ch_data_i(0), + FIFO_DATA_VALID_OUT => ch_data_valid_i(0), + FIFO_EMPTY_OUT => ch_empty_i(0), + FIFO_FULL_OUT => ch_full_i(0), + FIFO_ALMOST_EMPTY_OUT => ch_almost_empty_i(0), + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + EPOCH_WRITE_EN_IN => '1', + LOST_HIT_NUMBER => ch_lost_hit_number_i(0), + HIT_DETECT_NUMBER => ch_hit_detect_number_i(0), + ENCODER_START_NUMBER => ch_encoder_start_number_i(0), + ENCODER_FINISHED_NUMBER => ch_encoder_finished_number_i(0), + FIFO_WRITE_NUMBER => ch_fifo_write_number_i(0), + Channel_200_DEBUG => ch_200_debug_i(0), + Channel_DEBUG => ch_debug_i(0)); + + -- TDC Channels + GEN_Channels : for i in 1 to total_ch_number generate Channels : Channel generic map ( - CHANNEL_ID => i) + CHANNEL_ID => i, + DEBUG => DEBUG, + SIMULATION => SIMULATION, + REFERENCE => c_NO) port map ( - RESET_200 => reset_tdc, - RESET_100 => RESET, - RESET_COUNTERS => reset_counters_i, - CLK_200 => CLK_TDC, - CLK_100 => CLK_READOUT, - HIT_IN => hit_in_i(i), - SCALER_IN => scaler_in_i(i), - READ_EN_IN => rd_en_i(i), - FIFO_DATA_OUT => ch_data_i(i), - FIFO_EMPTY_OUT => ch_empty_i(i), - FIFO_FULL_OUT => ch_full_i(i), - FIFO_ALMOST_FULL_OUT => ch_almost_full_i(i), - COARSE_COUNTER_IN => coarse_cntr(integer(ceil(real(i)/real(16)))), - EPOCH_COUNTER_IN => epoch_cntr, - TRIGGER_WINDOW_END_IN => trg_win_end_i, - DATA_FINISHED_IN => data_finished_i, - RUN_MODE => run_mode_i, - LOST_HIT_NUMBER => ch_lost_hit_number_i(i), - HIT_DETECT_NUMBER => ch_hit_detect_number_i(i), - ENCODER_START_NUMBER => ch_encoder_start_number_i(i), - FIFO_WR_NUMBER => ch_fifo_wr_number_i(i), - Channel_DEBUG => ch_debug_i(i)); + RESET_200 => reset_tdc, + RESET_100 => reset_rdo, + RESET_COUNTERS => reset_counters_i, + CLK_200 => CLK_TDC, + CLK_100 => CLK_READOUT, + HIT_IN => hit_in_i(i), + HIT_EDGE_IN => hit_edge_i(i), + TRIGGER_WIN_END_TDC => trig_win_end_tdc_i(i), + TRIGGER_WIN_END_RDO => trig_win_end_rdo, + EPOCH_COUNTER_IN => epoch_cntr, + COARSE_COUNTER_IN => coarse_cntr(integer(ceil(real(i)/real(16)))), + READ_EN_IN => rd_en_i(i), + FIFO_DATA_OUT => ch_data_i(i), + FIFO_DATA_VALID_OUT => ch_data_valid_i(i), + FIFO_EMPTY_OUT => ch_empty_i(i), + FIFO_FULL_OUT => ch_full_i(i), + FIFO_ALMOST_EMPTY_OUT => ch_almost_empty_i(i), + VALID_TIMING_TRG_IN => '0', + VALID_NOTIMING_TRG_IN => '0', + SPIKE_DETECTED_IN => '0', + MULTI_TMG_TRG_IN => '0', + EPOCH_WRITE_EN_IN => '1', + LOST_HIT_NUMBER => ch_lost_hit_number_i(i), + HIT_DETECT_NUMBER => ch_hit_detect_number_i(i), + ENCODER_START_NUMBER => ch_encoder_start_number_i(i), + ENCODER_FINISHED_NUMBER => ch_encoder_finished_number_i(i), + FIFO_WRITE_NUMBER => ch_fifo_write_number_i(i), + Channel_200_DEBUG => ch_200_debug_i(i), + Channel_DEBUG => ch_debug_i(i)); end generate GEN_Channels; - ch_data_i(CHANNEL_NUMBER) <= x"FFFFFFFF"; + ch_data_i(total_ch_number+1) <= (others => '1'); + +------------------------------------------------------------------------------- +-- Trigger +------------------------------------------------------------------------------- + -- Valid Trigger Sync + ValidTriggerPulseSync : entity work.pulse_sync + port map ( + CLK_A_IN => CLK_READOUT, + RESET_A_IN => reset_rdo, + PULSE_A_IN => valid_trigger_rdo, + CLK_B_IN => CLK_TDC, + RESET_B_IN => reset_tdc, + PULSE_B_OUT => valid_trigger_tdc); + valid_trigger_rdo <= VALID_NOTIMING_TRG_IN or VALID_TIMING_TRG_IN; + + -- Timing Trigger handler + TheTriggerHandler : TriggerHandler + generic map ( + TRIGGER_NUM => 1, + PHYSICAL_EVENT_TRG_NUM => 0) + port map ( + CLK_TRG => CLK_READOUT, + CLK_RDO => CLK_READOUT, + CLK_TDC => CLK_TDC, + RESET_TRG => reset_rdo, + RESET_RDO => reset_rdo, + RESET_TDC => reset_tdc, + TRIGGER_IN(0) => trig_in_i, + TRIGGER_RDO_OUT(0) => trig_rdo_i, + TRIGGER_TDC_OUT(0) => trig_tdc_i, + TRIGGER_WIN_EN_IN => trig_win_en_i, + TRIGGER_WIN_POST_IN => unsigned(TRG_WIN_POST), + TRIGGER_WIN_END_RDO_OUT => trig_win_end_rdo, + TRIGGER_WIN_END_TDC_OUT => trig_win_end_tdc, + COARSE_COUNTER_IN => coarse_cntr(0), + EPOCH_COUNTER_IN => epoch_cntr, + TRIGGER_TIME_OUT => trig_time_i + ); + trig_in_i <= REFERENCE_TIME or VALID_NOTIMING_TRG_IN; + GenTriggerWindowEnd : for i in 0 to total_ch_number generate + trig_win_end_tdc_i(i) <= trig_win_end_tdc when rising_edge(CLK_TDC); + end generate GenTriggerWindowEnd; + GenTriggerWindowEndMod : for i in 1 to MODULE_NUMBER generate + trig_win_end_tdc_mod(i) <= trig_win_end_tdc when rising_edge(CLK_TDC); + end generate GenTriggerWindowEndMod; + +------------------------------------------------------------------------------- +-- Readout +------------------------------------------------------------------------------- + ReadoutHeader : entity work.Readout_Header + port map ( + RESET_100 => reset_rdo, + CLK_100 => CLK_READOUT, + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, + INVALID_TRG_IN => INVALID_TRG_IN, + TRG_CODE_IN => TRG_CODE_IN, + TRG_TYPE_IN => TRG_TYPE_IN, + TRG_RELEASE_OUT => trg_release_out_i(0), + TRG_STATUSBIT_OUT => trg_statusbit_out_i(0), + DATA_OUT => data_out_i(0), + DATA_WRITE_OUT => data_write_out_i(0), + DATA_FINISHED_OUT => data_finished_out_i(0)); + -- First Readout + TheFirstReadout : Readout + generic map ( + MODULE_NUMBER => MODULE_NUMBER, + CHANNEL_NUMBER => CHANNEL_NUMBER+1, + STATUS_REG_NR => STATUS_REG_NR, + TDC_VERSION => TDC_VERSION) + port map ( + RESET_100 => reset_rdo, + RESET_200 => reset_tdc, + RESET_COUNTERS => reset_counters_i, + CLK_100 => CLK_READOUT, + CLK_200 => CLK_TDC, + -- from the channels + CH_DATA_IN => ch_data_i(0 to CHANNEL_NUMBER), + CH_DATA_VALID_IN => ch_data_valid_i(CHANNEL_NUMBER downto 0), + CH_EMPTY_IN => ch_empty_i(CHANNEL_NUMBER downto 0), + CH_FULL_IN => ch_full_i(CHANNEL_NUMBER downto 0), + CH_ALMOST_EMPTY_IN => ch_almost_empty_i(CHANNEL_NUMBER downto 0), + -- from the endpoint + TRG_DATA_VALID_IN => TRG_DATA_VALID_IN, + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, + INVALID_TRG_IN => INVALID_TRG_IN, + TMGTRG_TIMEOUT_IN => TMGTRG_TIMEOUT_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + SPURIOUS_TRG_IN => SPURIOUS_TRG_IN, + TRG_NUMBER_IN => TRG_NUMBER_IN, + TRG_CODE_IN => TRG_CODE_IN, + TRG_INFORMATION_IN => TRG_INFORMATION_IN, + TRG_TYPE_IN => TRG_TYPE_IN, + DATA_LIMIT_IN => data_limit_i, + -- to the endpoint + TRG_RELEASE_OUT => trg_release_out_i(1), + TRG_STATUSBIT_OUT => trg_statusbit_out_i(1), + DATA_OUT => data_out_i(1), + DATA_WRITE_OUT => data_write_out_i(1), + DATA_FINISHED_OUT => data_finished_out_i(1), + -- to the channels + READ_EN_OUT => rd_en_i(CHANNEL_NUMBER downto 0), + -- trigger window settings + TRG_WIN_PRE => TRG_WIN_PRE, + TRG_WIN_POST => TRG_WIN_POST, + TRIGGER_WIN_EN_IN => trig_win_en_i, + -- from the trigger handler + TRIG_WIN_END_TDC_IN => trig_win_end_tdc_mod(1), + TRIG_WIN_END_RDO_IN => trig_win_end_rdo, + TRIG_TIME_IN => trig_time_i, + TRIGGER_TDC_IN => trig_tdc_i, + -- miscellaneous + COARSE_COUNTER_IN => coarse_cntr(5), + EPOCH_COUNTER_IN => epoch_cntr, + DEBUG_MODE_EN_IN => debug_mode_en_i, + STATUS_REGISTERS_BUS_OUT => status_registers_bus_i, + READOUT_DEBUG => readout_debug_i, + REFERENCE_TIME => REFERENCE_TIME + ); + + Gen_Readout : if MODULE_NUMBER > 1 generate + Module : for i in 2 to MODULE_NUMBER generate + -- Readout + TheReadout : Readout + generic map ( + MODULE_NUMBER => MODULE_NUMBER, + CHANNEL_NUMBER => CHANNEL_NUMBER, + STATUS_REG_NR => STATUS_REG_NR, + TDC_VERSION => TDC_VERSION) + port map ( + RESET_100 => reset_rdo, + RESET_200 => reset_tdc, + RESET_COUNTERS => reset_counters_i, + CLK_100 => CLK_READOUT, + CLK_200 => CLK_TDC, + -- from the channels + CH_DATA_IN => ch_data_i((i-1)*CHANNEL_NUMBER+1 to i*CHANNEL_NUMBER), + CH_DATA_VALID_IN => ch_data_valid_i(i*CHANNEL_NUMBER downto (i-1)*CHANNEL_NUMBER+1), + CH_EMPTY_IN => ch_empty_i(i*CHANNEL_NUMBER downto (i-1)*CHANNEL_NUMBER+1), + CH_FULL_IN => ch_full_i(i*CHANNEL_NUMBER downto (i-1)*CHANNEL_NUMBER+1), + CH_ALMOST_EMPTY_IN => ch_almost_empty_i(i*CHANNEL_NUMBER downto (i-1)*CHANNEL_NUMBER+1), + -- from the endpoint + TRG_DATA_VALID_IN => TRG_DATA_VALID_IN, + VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, + VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, + INVALID_TRG_IN => INVALID_TRG_IN, + TMGTRG_TIMEOUT_IN => TMGTRG_TIMEOUT_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + SPURIOUS_TRG_IN => SPURIOUS_TRG_IN, + TRG_NUMBER_IN => TRG_NUMBER_IN, + TRG_CODE_IN => TRG_CODE_IN, + TRG_INFORMATION_IN => TRG_INFORMATION_IN, + TRG_TYPE_IN => TRG_TYPE_IN, + DATA_LIMIT_IN => data_limit_i, + -- to the endpoint + TRG_RELEASE_OUT => trg_release_out_i(i), + TRG_STATUSBIT_OUT => trg_statusbit_out_i(i), + DATA_OUT => data_out_i(i), + DATA_WRITE_OUT => data_write_out_i(i), + DATA_FINISHED_OUT => data_finished_out_i(i), + -- to the channels + READ_EN_OUT => rd_en_i(i*CHANNEL_NUMBER downto (i-1)*CHANNEL_NUMBER+1), + -- trigger window settings + TRG_WIN_PRE => TRG_WIN_PRE, + TRG_WIN_POST => TRG_WIN_POST, + TRIGGER_WIN_EN_IN => trig_win_en_i, + -- from the trigger handler + TRIG_WIN_END_TDC_IN => trig_win_end_tdc_mod(i), + TRIG_WIN_END_RDO_IN => trig_win_end_rdo, + TRIG_TIME_IN => trig_time_i, + TRIGGER_TDC_IN => trig_tdc_i, + -- miscellaneous + COARSE_COUNTER_IN => coarse_cntr(i+4), + EPOCH_COUNTER_IN => epoch_cntr, + DEBUG_MODE_EN_IN => debug_mode_en_i, + STATUS_REGISTERS_BUS_OUT => open, --status_registers_bus_i, + READOUT_DEBUG => open, --readout_debug_i, + REFERENCE_TIME => REFERENCE_TIME + ); + end generate Module; + end generate Gen_Readout; + TRG_RELEASE_OUT <= trg_release_out_i when rising_edge(CLK_READOUT); + TRG_STATUSBIT_OUT <= trg_statusbit_out_i when rising_edge(CLK_READOUT); + DATA_OUT <= data_out_i when rising_edge(CLK_READOUT); + DATA_WRITE_OUT <= data_write_out_i when rising_edge(CLK_READOUT); + DATA_FINISHED_OUT <= data_finished_out_i when rising_edge(CLK_READOUT); + +------------------------------------------------------------------------------- +-- Coarse & Epoch Counters +------------------------------------------------------------------------------- -- Coarse counter - GenCoarseCounter : for i in 1 to 4 generate + GenCoarseCounter : for i in 0 to 8 generate TheCoarseCounter : up_counter generic map ( NUMBER_OF_BITS => 11) @@ -239,20 +626,41 @@ begin UP_IN => '1'); end generate GenCoarseCounter; - Coarse_Counter_Reset : process (CLK_TDC, reset_tdc) + Coarse_Counter_Reset : process (CLK_TDC) begin if rising_edge(CLK_TDC) then if reset_tdc = '1' then coarse_cntr_reset <= '1'; - elsif run_mode_200 = '1' then - coarse_cntr_reset <= '0'; + elsif run_mode_200 = '0' then + coarse_cntr_reset <= trig_win_end_tdc_i(8); + elsif run_mode_edge_200 = '1' then + coarse_cntr_reset <= '1'; + elsif reset_coarse_cntr_flag = '1' and valid_trigger_tdc = '1' then + coarse_cntr_reset <= '1'; else - coarse_cntr_reset <= trg_win_end_i; + coarse_cntr_reset <= '0'; + end if; + if reset_coarse_cntr_edge_200 = '1' then + reset_coarse_cntr_flag <= '1'; + elsif valid_trigger_tdc = '1' then + reset_coarse_cntr_flag <= '0'; end if; end if; end process Coarse_Counter_Reset; - GenCoarseCounterReset : for i in 1 to 4 generate + Run_Mode_Edge_Detect : risingEdgeDetect + port map ( + CLK => CLK_TDC, + SIGNAL_IN => run_mode_200, + PULSE_OUT => run_mode_edge_200); + + Reset_Coarse_Counter_Edge_Detect : risingEdgeDetect + port map ( + CLK => CLK_TDC, + SIGNAL_IN => reset_coarse_cntr_200, + PULSE_OUT => reset_coarse_cntr_edge_200); + + GenCoarseCounterReset : for i in 0 to 8 generate coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC); end generate GenCoarseCounterReset; @@ -265,15 +673,18 @@ begin RESET => epoch_cntr_reset_i, COUNT_OUT => epoch_cntr, UP_IN => epoch_cntr_up_i); - epoch_cntr_up_i <= and_all(coarse_cntr(1)); - epoch_cntr_reset_i <= reset_tdc or coarse_cntr_reset; + epoch_cntr_up_i <= and_all(coarse_cntr(0)); + epoch_cntr_reset_i <= coarse_cntr_reset_r(0); --- Bus handler entities +------------------------------------------------------------------------------- +-- Slow Control Data Busses +------------------------------------------------------------------------------- +-- Hit counter TheHitCounterBus : BusHandler generic map ( - BUS_LENGTH => CHANNEL_NUMBER-1) + BUS_LENGTH => total_ch_number) port map ( - RESET => RESET, + RESET => reset_rdo, CLK => CLK_READOUT, DATA_IN => ch_level_hit_number, READ_EN_IN => HCB_READ_EN_IN, @@ -283,15 +694,19 @@ begin DATAREADY_OUT => HCB_DATAREADY_OUT, UNKNOWN_ADDR_OUT => HCB_UNKNOWN_ADDR_OUT); - GenHitCounterLevelSignals : for i in 1 to CHANNEL_NUMBER-1 generate - ch_level_hit_number(i) <= scaler_in_i(i) & "0000000" & ch_hit_detect_number_i(i) when rising_edge(CLK_READOUT); - end generate GenHitCounterLevelSignals; + ch_level_hit_number(0)(31) <= REFERENCE_TIME when rising_edge(CLK_READOUT); + ch_level_hit_number(0)(30 downto 0) <= ch_hit_detect_number_i(0) when rising_edge(CLK_READOUT); + GenHitDetectNumber : for i in 1 to total_ch_number generate + ch_level_hit_number(i)(31) <= HIT_IN(i) and ch_en_i(i) when rising_edge(CLK_READOUT); + ch_level_hit_number(i)(30 downto 0) <= ch_hit_detect_number_i(i) when rising_edge(CLK_READOUT); + end generate GenHitDetectNumber; - TheStatusRegistersBus: BusHandler +-- Status register + TheStatusRegistersBus : BusHandler generic map ( - BUS_LENGTH => 23) + BUS_LENGTH => STATUS_REG_NR - 1) port map ( - RESET => RESET, + RESET => reset_rdo, CLK => CLK_READOUT, DATA_IN => status_registers_bus_i, READ_EN_IN => SRB_READ_EN_IN, @@ -301,116 +716,99 @@ begin DATAREADY_OUT => SRB_DATAREADY_OUT, UNKNOWN_ADDR_OUT => SRB_UNKNOWN_ADDR_OUT); - TheLostHitBus : BusHandler +-- Channel debug + TheChannelDebugBus : BusHandler generic map ( - BUS_LENGTH => CHANNEL_NUMBER-1) + BUS_LENGTH => total_ch_number) port map ( - RESET => RESET, + RESET => reset_rdo, CLK => CLK_READOUT, - DATA_IN => ch_lost_hit_bus_i, - READ_EN_IN => LHB_READ_EN_IN, - WRITE_EN_IN => LHB_WRITE_EN_IN, - ADDR_IN => LHB_ADDR_IN, - DATA_OUT => LHB_DATA_OUT, - DATAREADY_OUT => LHB_DATAREADY_OUT, - UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT); - - GenLostHitBus : for i in 1 to CHANNEL_NUMBER-1 generate - ch_lost_hit_bus_i(i) <= x"00" & ch_lost_hit_number_i(i) when rising_edge(CLK_READOUT); - end generate GenLostHitBus; - - TheEncoderStartBus : BusHandler - generic map ( - BUS_LENGTH => CHANNEL_NUMBER-1) - port map ( - RESET => RESET, - CLK => CLK_READOUT, - DATA_IN => ch_encoder_start_bus_i, - READ_EN_IN => ESB_READ_EN_IN, - WRITE_EN_IN => ESB_WRITE_EN_IN, - ADDR_IN => ESB_ADDR_IN, - DATA_OUT => ESB_DATA_OUT, - DATAREADY_OUT => ESB_DATAREADY_OUT, - UNKNOWN_ADDR_OUT => ESB_UNKNOWN_ADDR_OUT); - - GenEncoderStartBus : for i in 1 to CHANNEL_NUMBER-1 generate - ch_encoder_start_bus_i(i) <= x"00" & ch_encoder_start_number_i(i) when rising_edge(CLK_READOUT); - end generate GenEncoderStartBus; - - TheFifoWriteBus : BusHandler - generic map ( - BUS_LENGTH => CHANNEL_NUMBER-1) - port map ( - RESET => RESET, - CLK => CLK_READOUT, - DATA_IN => ch_fifo_wr_bus_i, - READ_EN_IN => FWB_READ_EN_IN, - WRITE_EN_IN => FWB_WRITE_EN_IN, - ADDR_IN => FWB_ADDR_IN, - DATA_OUT => FWB_DATA_OUT, - DATAREADY_OUT => FWB_DATAREADY_OUT, - UNKNOWN_ADDR_OUT => FWB_UNKNOWN_ADDR_OUT); + DATA_IN => ch_200_debug_i, + READ_EN_IN => CDB_READ_EN_IN, + WRITE_EN_IN => CDB_WRITE_EN_IN, + ADDR_IN => CDB_ADDR_IN, + DATA_OUT => CDB_DATA_OUT, + DATAREADY_OUT => CDB_DATAREADY_OUT, + UNKNOWN_ADDR_OUT => CDB_UNKNOWN_ADDR_OUT); - GenFifoWriteBus : for i in 1 to CHANNEL_NUMBER-1 generate - ch_fifo_wr_bus_i(i) <= x"00" & ch_fifo_wr_number_i(i) when rising_edge(CLK_READOUT); - end generate GenFifoWriteBus; + --TheLostHitBus : BusHandler + -- generic map ( + -- BUS_LENGTH => total_ch_number) + -- port map ( + -- RESET => reset_rdo, + -- CLK => CLK_READOUT, + -- DATA_IN => ch_lost_hit_bus_i, + -- READ_EN_IN => LHB_READ_EN_IN, + -- WRITE_EN_IN => LHB_WRITE_EN_IN, + -- ADDR_IN => LHB_ADDR_IN, + -- DATA_OUT => LHB_DATA_OUT, + -- DATAREADY_OUT => LHB_DATAREADY_OUT, + -- UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT); --- Readout - TheReadout : Readout - generic map ( - CHANNEL_NUMBER => CHANNEL_NUMBER, - STATUS_REG_NR => STATUS_REG_NR) - port map ( - CLK_200 => CLK_TDC, - RESET_200 => reset_tdc, - CLK_100 => CLK_READOUT, - RESET_100 => RESET, - RESET_COUNTERS => reset_counters_i, - HIT_IN => scaler_in_i, - REFERENCE_TIME => REFERENCE_TIME, - TRIGGER_TIME_IN => trg_time_i, - TRG_WIN_PRE => TRG_WIN_PRE, - TRG_WIN_POST => TRG_WIN_POST, - DEBUG_MODE_EN_IN => debug_mode_en_i, - TRIGGER_WIN_EN_IN => trigger_win_en_i, - CH_DATA_IN => ch_data_i, - CH_EMPTY_IN => ch_empty_i, - CH_FULL_IN => ch_full_i, - CH_ALMOST_FULL_IN => ch_almost_full_i, - TRG_DATA_VALID_IN => TRG_DATA_VALID_IN, - VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, - VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, - INVALID_TRG_IN => INVALID_TRG_IN, - TMGTRG_TIMEOUT_IN => TMGTRG_TIMEOUT_IN, - SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, - MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, - SPURIOUS_TRG_IN => SPURIOUS_TRG_IN, - TRG_NUMBER_IN => TRG_NUMBER_IN, - TRG_CODE_IN => TRG_CODE_IN, - TRG_INFORMATION_IN => TRG_INFORMATION_IN, - TRG_TYPE_IN => TRG_TYPE_IN, - TRG_RELEASE_OUT => TRG_RELEASE_OUT, - TRG_STATUSBIT_OUT => TRG_STATUSBIT_OUT, - DATA_OUT => DATA_OUT, - DATA_WRITE_OUT => DATA_WRITE_OUT, - DATA_FINISHED_OUT => data_finished_i, - READOUT_BUSY_OUT => readout_busy_i, - READ_EN_OUT => rd_en_i, - TRIGGER_WIN_END_OUT => trg_win_end_i, - SLOW_CONTROL_REG_OUT => SLOW_CONTROL_REG_OUT, - STATUS_REGISTERS_BUS_OUT => status_registers_bus_i, - READOUT_DEBUG => readout_debug_i); - DATA_FINISHED_OUT <= data_finished_i; + --GenLostHitNumber : for i in 1 to total_ch_number generate + -- ch_lost_hit_bus_i(i) <= ch_encoder_start_number_i(i)(15 downto 0) & ch_200_debug_i(i)(15 downto 0) when rising_edge(CLK_READOUT); + --end generate GenLostHitNumber; + + LHB_DATA_OUT <= (others => '0'); + LHB_DATAREADY_OUT <= '0'; + LHB_UNKNOWN_ADDR_OUT <= '0'; + + --TheEncoderStartBus : BusHandler + -- generic map ( + -- BUS_LENGTH => total_ch_number) + -- port map ( + -- RESET => reset_rdo, + -- CLK => CLK_READOUT, + -- DATA_IN => ch_encoder_start_bus_i, + -- READ_EN_IN => ESB_READ_EN_IN, + -- WRITE_EN_IN => ESB_WRITE_EN_IN, + -- ADDR_IN => ESB_ADDR_IN, + -- DATA_OUT => ESB_DATA_OUT, + -- DATAREADY_OUT => ESB_DATAREADY_OUT, + -- UNKNOWN_ADDR_OUT => ESB_UNKNOWN_ADDR_OUT); + --GenEncoderStartNumber : for i in 1 to total_ch_number generate + -- ch_encoder_start_bus_i(i) <= x"00" & ch_encoder_start_number_i(i) when rising_edge(CLK_READOUT); + --end generate GenEncoderStartNumber; + + ESB_DATA_OUT <= (others => '0'); + ESB_DATAREADY_OUT <= '0'; + ESB_UNKNOWN_ADDR_OUT <= '0'; + + --TheEncoderFinishedBus : BusHandler + -- generic map ( + -- BUS_LENGTH => total_ch_number) + -- port map ( + -- RESET => reset_rdo, + -- CLK => CLK_READOUT, + -- DATA_IN => ch_encoder_finished_bus_i, + -- READ_EN_IN => EFB_READ_EN_IN, + -- WRITE_EN_IN => EFB_WRITE_EN_IN, + -- ADDR_IN => EFB_ADDR_IN, + -- DATA_OUT => EFB_DATA_OUT, + -- DATAREADY_OUT => EFB_DATAREADY_OUT, + -- UNKNOWN_ADDR_OUT => EFB_UNKNOWN_ADDR_OUT); + + --GenFifoWriteNumber : for i in 1 to total_ch_number generate + -- --ch_encoder_finished_bus_i(i) <= x"00" & ch_encoder_finished_number_i(i) when rising_edge(CLK_READOUT); + -- ch_encoder_finished_bus_i(i) <= ch_fifo_write_number_i(i)(15 downto 0)& ch_encoder_finished_number_i(i)(15 downto 0) when rising_edge(CLK_READOUT); + --end generate GenFifoWriteNumber; + + EFB_DATA_OUT <= (others => '0'); + EFB_DATAREADY_OUT <= '0'; + EFB_UNKNOWN_ADDR_OUT <= '0'; + +------------------------------------------------------------------------------- +-- Debug +------------------------------------------------------------------------------- -- Logic Analyser TheLogicAnalyser : LogicAnalyser generic map ( - CHANNEL_NUMBER => CHANNEL_NUMBER, - STATUS_REG_NR => STATUS_REG_NR) + CHANNEL_NUMBER => total_ch_number) port map ( CLK => CLK_READOUT, - RESET => RESET, + RESET => reset_rdo, DATA_IN => logic_anal_data_i, CONTROL_IN => logic_anal_control, DATA_OUT => LOGIC_ANALYSER_OUT); diff --git a/tdc_releases/tdc_v2.0/TriggerHandler.vhd b/tdc_releases/tdc_v2.0/TriggerHandler.vhd new file mode 100644 index 0000000..176cbff --- /dev/null +++ b/tdc_releases/tdc_v2.0/TriggerHandler.vhd @@ -0,0 +1,194 @@ +------------------------------------------------------------------------------- +-- Title : TriggerHandler +------------------------------------------------------------------------------- +-- File : TriggerHandler.vhd +-- Author : Cahit Ugur c.ugur@gsi.de +-- Created : 2013-03-13 +-- Last update: 2014-06-24 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_components.all; +use work.trb3_components.all; + +entity TriggerHandler is + generic ( + TRIGGER_NUM : integer := 2; -- number of trigger signals sent + PHYSICAL_EVENT_TRG_NUM : integer := 0); -- physical event trigger input number for the trigger window calculations + port ( + CLK_TRG : in std_logic; -- trigger clock domain + CLK_RDO : in std_logic; -- readout clock domain + CLK_TDC : in std_logic; -- tdc clock domain + RESET_TRG : in std_logic; + RESET_RDO : in std_logic; + RESET_TDC : in std_logic; + TRIGGER_IN : in std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_RDO_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_TDC_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_WIN_EN_IN : in std_logic; + TRIGGER_WIN_POST_IN : in unsigned(10 downto 0); + TRIGGER_WIN_END_RDO_OUT : out std_logic; + TRIGGER_WIN_END_TDC_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + TRIGGER_TIME_OUT : out std_logic_vector(38 downto 0) := (others => '0') + ); + +end entity TriggerHandler; + +architecture behavioral of TriggerHandler is + + -- trigger signals + signal trigger_in_reg : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_in_2reg : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_in_3reg : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_pulse_trg : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_pulse_rdo : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_pulse_tdc : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trigger_length : unsigned_array_5(TRIGGER_NUM-1 downto 0); + -- trigger window signals + type TriggerWinCounter_FSM is (IDLE, COUNT, WIN_END); + signal TrigWin_STATE : TriggerWinCounter_FSM; + signal trig_win_cnt_f : unsigned(10 downto 0); + signal trig_win_cnt_r : unsigned(10 downto 0); + signal trig_win_end_f : std_logic; + signal trig_win_end_tdc : std_logic; + signal trig_win_end_rdo : std_logic; + signal trigger_time_i : std_logic_vector(38 downto 0) := (others => '0'); + + +begin -- architecture behavioral + + -- the trigger signals have to be synced + trigger_in_reg <= TRIGGER_IN when rising_edge(CLK_TDC); + trigger_in_2reg <= trigger_in_reg when rising_edge(CLK_TDC); + trigger_in_3reg <= trigger_in_2reg when rising_edge(CLK_TDC); + + GEN_TRIGGER : for i in 0 to TRIGGER_NUM-1 generate + Validation : process (CLK_TDC) + begin + if rising_edge(CLK_TDC) then + + -- calculate trigger length + if trigger_in_3reg(i) = '0' then + trigger_length(i) <= (others => '0'); + else + trigger_length(i) <= trigger_length(i) + to_unsigned(1, 5); + end if; + + -- accept trigger if it is longer than 150 ns + if RESET_TDC = '1' then + trigger_pulse_tdc(i) <= '0'; + elsif trigger_length(i) = to_unsigned(15, 5) then + trigger_pulse_tdc(i) <= '1'; + else + trigger_pulse_tdc(i) <= '0'; + end if; + + end if; + end process Validation; + end generate GEN_TRIGGER; + + -- sync the strobes to the readout clock domain + GEN_TDC : for i in 0 to TRIGGER_NUM-1 generate + ThePulseSync : pulse_sync + port map ( + CLK_A_IN => CLK_TDC, + RESET_A_IN => RESET_TDC, + PULSE_A_IN => trigger_pulse_tdc(i), + CLK_B_IN => CLK_RDO, + RESET_B_IN => RESET_RDO, + PULSE_B_OUT => trigger_pulse_rdo(i)); + end generate GEN_TDC; + + TRIGGER_RDO_OUT <= trigger_pulse_rdo; + TRIGGER_TDC_OUT <= trigger_pulse_tdc; + + -- A Moore machine's outputs are dependent only on the current state. + -- The output is written only when the state changes. (State + -- transitions are synchronous.) + -- Logic to advance to the next state + TrigWinState : process (CLK_TDC) + begin + if rising_edge(CLK_TDC) then + if RESET_TDC = '1' then + TrigWin_STATE <= IDLE; + else + case TrigWin_STATE is + when IDLE => + if trigger_pulse_tdc(0) = '1' then + if TRIGGER_WIN_EN_IN = '1' then + TrigWin_STATE <= COUNT; + else + TrigWin_STATE <= WIN_END; + end if; + --elsif trigger_pulse_tdc(1) = '1' then + -- TrigWin_STATE <= WIN_END; + else + TrigWin_STATE <= IDLE; + end if; + when COUNT => + if trig_win_cnt_r = TRIGGER_WIN_POST_IN + to_unsigned(4,11) then + TrigWin_STATE <= WIN_END; + else + TrigWin_STATE <= COUNT; + end if; + when WIN_END => + TrigWin_STATE <= IDLE; + when others => + TrigWin_STATE <= IDLE; + end case; + end if; + end if; + end process TrigWinState; + + -- Output depends solely on the current state + TrigWinOutput : process (TrigWin_STATE, trig_win_cnt_r) + begin + trig_win_cnt_f <= "00000000011"; + trig_win_end_f <= '0'; + case TrigWin_STATE is + when IDLE => + + when COUNT => + trig_win_cnt_f <= trig_win_cnt_r + to_unsigned(1, 1); + when WIN_END => + trig_win_end_f <= '1'; + end case; + end process TrigWinOutput; + trig_win_cnt_r <= trig_win_cnt_f when rising_edge(CLK_TDC); + trig_win_end_tdc <= trig_win_end_f when rising_edge(CLK_TDC); + + -- syn trigger window end strobe to readout clock domain + ThePulseSync : pulse_sync + port map ( + CLK_A_IN => CLK_TDC, + RESET_A_IN => RESET_TDC, + PULSE_A_IN => trig_win_end_tdc, + CLK_B_IN => CLK_RDO, + RESET_B_IN => RESET_RDO, + PULSE_B_OUT => trig_win_end_rdo); + + TRIGGER_WIN_END_TDC_OUT <= trig_win_end_tdc; + TRIGGER_WIN_END_RDO_OUT <= trig_win_end_rdo; + + TriggerTime : process (CLK_TDC) + begin + if rising_edge(CLK_TDC) then + if trigger_in_2reg(0) = '1' and trigger_in_3reg(0) = '0' then + trigger_time_i <= EPOCH_COUNTER_IN & COARSE_COUNTER_IN; + end if; + if trigger_pulse_tdc(0) = '1' then + TRIGGER_TIME_OUT <= trigger_time_i; + end if; + end if; + end process TriggerTime; + + +end architecture behavioral; diff --git a/tdc_releases/tdc_v2.0/fallingEdgeDetect.vhd b/tdc_releases/tdc_v2.0/fallingEdgeDetect.vhd new file mode 100644 index 0000000..f413d0b --- /dev/null +++ b/tdc_releases/tdc_v2.0/fallingEdgeDetect.vhd @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity fallingEdgeDetect is + port (CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic); +end fallingEdgeDetect; + +architecture Behavioral of fallingEdgeDetect is + + signal signal_d : std_logic; + +begin + signal_d <= SIGNAL_IN when rising_edge(CLK); + PULSE_OUT <= (not SIGNAL_IN) and signal_d when rising_edge(CLK); +end Behavioral; diff --git a/tdc_releases/tdc_v2.0/hit_mux.vhd b/tdc_releases/tdc_v2.0/hit_mux.vhd new file mode 100644 index 0000000..538a2df --- /dev/null +++ b/tdc_releases/tdc_v2.0/hit_mux.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------- +-- Title : Hit Multiplexer +-- Project : FPGA TDC +------------------------------------------------------------------------------- +-- File : hit_mux.vhd +-- Author : Cahit Ugur +-- Created : 2014-03-26 +-- Last update: 2014-03-27 +------------------------------------------------------------------------------- +-- Description: Entity to decide the hit for the channels between physical or +-- calibration hits. +------------------------------------------------------------------------------- +-- Copyright (c) 2014 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2014-03-26 1.0 cugur Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity hit_mux is + + port ( + CH_EN_IN : in std_logic; -- channel enable signal + CALIBRATION_EN_IN : in std_logic; -- calibration enable signal + HIT_CALIBRATION_IN : in std_logic; -- hit signal for calibration purposes + HIT_PHYSICAL_IN : in std_logic; -- physical hit signal + HIT_OUT : out std_logic); -- hit signal to the delay lines +end entity hit_mux; + +architecture behavioral of hit_mux is + + signal ch_en_i : std_logic; + signal calibration_en_i : std_logic; + signal hit_calibration_i : std_logic; + signal hit_physical_i : std_logic; + signal hit_i : std_logic; + + attribute syn_keep : boolean; + attribute syn_keep of ch_en_i : signal is true; + attribute syn_keep of calibration_en_i : signal is true; + attribute syn_keep of hit_calibration_i : signal is true; + attribute syn_keep of hit_physical_i : signal is true; + attribute syn_keep of hit_i : signal is true; + --attribute syn_preserve : boolean; + --attribute syn_preserve of coarse_cntr : signal is true; + attribute nomerge : string; + attribute nomerge of ch_en_i : signal is "true"; + attribute nomerge of calibration_en_i : signal is "true"; + attribute nomerge of hit_calibration_i : signal is "true"; + attribute nomerge of hit_physical_i : signal is "true"; + attribute nomerge of hit_i : signal is "true"; + + +begin -- architecture behavioral + + ch_en_i <= CH_EN_IN; + calibration_en_i <= CALIBRATION_EN_IN; + hit_calibration_i <= HIT_CALIBRATION_IN; + hit_physical_i <= HIT_PHYSICAL_IN; + + process (ch_en_i, calibration_en_i, hit_calibration_i, hit_physical_i) + begin + if ch_en_i = '1' then + if calibration_en_i = '1' then + hit_i <= hit_calibration_i; + else + hit_i <= hit_physical_i; + end if; + else + hit_i <= '0'; + end if; + end process; + + HIT_OUT <= hit_i; + +end architecture behavioral; diff --git a/tdc_releases/tdc_v2.0/risingEdgeDetect.vhd b/tdc_releases/tdc_v2.0/risingEdgeDetect.vhd new file mode 100644 index 0000000..fad9f7e --- /dev/null +++ b/tdc_releases/tdc_v2.0/risingEdgeDetect.vhd @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity risingEdgeDetect is + port (CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic); +end risingEdgeDetect; + +architecture Behavioral of risingEdgeDetect is + + signal signal_d : std_logic; + +begin + signal_d <= SIGNAL_IN when rising_edge(CLK); + PULSE_OUT <= (not signal_d) and SIGNAL_IN when rising_edge(CLK); +end Behavioral; diff --git a/tdc_releases/tdc_v2.0/rom_encoder/ROM_encoder_3.ipx b/tdc_releases/tdc_v2.0/rom_encoder/ROM_encoder_3.ipx new file mode 100644 index 0000000..e989d8a --- /dev/null +++ b/tdc_releases/tdc_v2.0/rom_encoder/ROM_encoder_3.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/tdc_releases/tdc_v2.0/rom_encoder/ROM_encoder_3.lpc b/tdc_releases/tdc_v2.0/rom_encoder/ROM_encoder_3.lpc new file mode 100644 index 0000000..6d93ce6 --- /dev/null +++ b/tdc_releases/tdc_v2.0/rom_encoder/ROM_encoder_3.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=ROM +CoreRevision=5.1 +ModuleName=ROM_encoder_3 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/09/2014 +Time=15:03:00 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Address=1024 +Data=8 +adPipeline=0 +inPipeline=0 +outPipeline=1 +MOR=0 +InData=Registered +AdControl=Registered +MemFile=rom_encoder.mem +MemFormat=orca +Reset=Sync +Pad=0 +GSR=Enabled +EnECC=0 +Optimization=Speed +Pipeline=0 + +[FilesGenerated] +rom_encoder.mem=mem diff --git a/tdc_releases/tdc_v2.0/rom_encoder/ROM_encoder_3.vhd b/tdc_releases/tdc_v2.0/rom_encoder/ROM_encoder_3.vhd new file mode 100644 index 0000000..00c0a02 --- /dev/null +++ b/tdc_releases/tdc_v2.0/rom_encoder/ROM_encoder_3.vhd @@ -0,0 +1,264 @@ +-- VHDL netlist generated by SCUBA Diamond_3.0_Production (94) +-- Module Version: 5.1 +--/opt/lattice/diamond/3.0_x64/ispfpga/bin/lin64/scuba -w -n ROM_encoder_3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 8 -num_rows 1024 -outdata REGISTERED -memfile rom_encoder.mem -memformat orca -cascade -1 -e + +-- Fri May 9 15:03:00 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity ROM_encoder_3 is + port ( + Address: in std_logic_vector(9 downto 0); + OutClock: in std_logic; + OutClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(7 downto 0)); +end ROM_encoder_3; + +architecture Structure of ROM_encoder_3 is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KC + generic (INITVAL_3F : in String; INITVAL_3E : in String; + INITVAL_3D : in String; INITVAL_3C : in String; + INITVAL_3B : in String; INITVAL_3A : in String; + INITVAL_39 : in String; INITVAL_38 : in String; + INITVAL_37 : in String; INITVAL_36 : in String; + INITVAL_35 : in String; INITVAL_34 : in String; + INITVAL_33 : in String; INITVAL_32 : in String; + INITVAL_31 : in String; INITVAL_30 : in String; + INITVAL_2F : in String; INITVAL_2E : in String; + INITVAL_2D : in String; INITVAL_2C : in String; + INITVAL_2B : in String; INITVAL_2A : in String; + INITVAL_29 : in String; INITVAL_28 : in String; + INITVAL_27 : in String; INITVAL_26 : in String; + INITVAL_25 : in String; INITVAL_24 : in String; + INITVAL_23 : in String; INITVAL_22 : in String; + INITVAL_21 : in String; INITVAL_20 : in String; + INITVAL_1F : in String; INITVAL_1E : in String; + INITVAL_1D : in String; INITVAL_1C : in String; + INITVAL_1B : in String; INITVAL_1A : in String; + INITVAL_19 : in String; INITVAL_18 : in String; + INITVAL_17 : in String; INITVAL_16 : in String; + INITVAL_15 : in String; INITVAL_14 : in String; + INITVAL_13 : in String; INITVAL_12 : in String; + INITVAL_11 : in String; INITVAL_10 : in String; + INITVAL_0F : in String; INITVAL_0E : in String; + INITVAL_0D : in String; INITVAL_0C : in String; + INITVAL_0B : in String; INITVAL_0A : in String; + INITVAL_09 : in String; INITVAL_08 : in String; + INITVAL_07 : in String; INITVAL_06 : in String; + INITVAL_05 : in String; INITVAL_04 : in String; + INITVAL_03 : in String; INITVAL_02 : in String; + INITVAL_01 : in String; INITVAL_00 : in String; + GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of ROM_encoder_3_0_0_0 : label is "ROM_encoder_3.lpc"; + attribute MEM_INIT_FILE of ROM_encoder_3_0_0_0 : label is "rom_encoder.mem"; + attribute RESETMODE of ROM_encoder_3_0_0_0 : label is "SYNC"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + ROM_encoder_3_0_0_0: DP16KC + generic map (INITVAL_3F=> "0x00000000800008000081000000000000000000820000000081000820008200000000000008200083", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000084", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000083000830008300000000000008400084", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000840008400000000000008500085", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000008500000000000008600086", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000008600000000000008600086", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000008700000000000008700087", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00084000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00083000000000000000000000000000000000000008200000000000000000081000800000000000", + INITVAL_0F=> "0x00087000000000000000000870000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00086000000000000000000860000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00084000000000000000000840000000000000000000000000000000000000083000830000000000", + INITVAL_03=> "0x00085000000000000000000840000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00084000000000000000000840008400000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00084000000000000000000830000000000000000000000000000000000000082000820000000000", + INITVAL_00=> "0x00083000000000000000000820008200081000000008200082000810000000081000800008000000", + CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", + REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>scuba_vlo, ADA4=>Address(0), ADA5=>Address(1), + ADA6=>Address(2), ADA7=>Address(3), ADA8=>Address(4), + ADA9=>Address(5), ADA10=>Address(6), ADA11=>Address(7), + ADA12=>Address(8), ADA13=>Address(9), CEA=>OutClockEn, + CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo, + ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo, + ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo, + ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, + CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1), + DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), + DOA7=>Q(7), DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open, + DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of ROM_encoder_3 is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/tdc_releases/tdc_v2.0/rom_encoder/rom_encoder.mem b/tdc_releases/tdc_v2.0/rom_encoder/rom_encoder.mem new file mode 100644 index 0000000..6703264 --- /dev/null +++ b/tdc_releases/tdc_v2.0/rom_encoder/rom_encoder.mem @@ -0,0 +1,70 @@ +001 : 80 +002 : 80 +003 : 81 +005 : 81 +006 : 82 +007 : 82 +009 : 81 +00A : 82 +00B : 82 +00F : 83 +012 : 82 +013 : 82 +01B : 83 +01F : 84 +02A : 84 +02B : 84 +02F : 84 +03B : 84 +03F : 85 +042 : 83 +043 : 83 +04B : 84 +04F : 84 +05F : 85 +06F : 85 +07F : 86 +0AF : 85 +0BB : 86 +0BF : 86 +0FB : 87 +0FF : 87 +102 : 80 +103 : 81 +107 : 82 +10F : 83 +12F : 84 +13F : 85 +17F : 86 + +300 : 87 +301 : 87 +304 : 87 +310 : 86 +340 : 86 +341 : 86 +344 : 86 +350 : 85 +380 : 86 +381 : 86 +384 : 85 +390 : 85 +3C0 : 85 +3C1 : 85 +3C4 : 84 +3C5 : 84 +3D0 : 84 +3D1 : 84 +3D4 : 83 +3D5 : 83 +3D6 : 83 +3E0 : 84 +3F0 : 83 +3F1 : 82 +3F4 : 82 +3F5 : 82 +3F6 : 81 +3F8 : 82 +3FC : 81 +3FD : 80 +3FE : 80 diff --git a/tdc_releases/tdc_v2.0/tdc_components.vhd b/tdc_releases/tdc_v2.0/tdc_components.vhd new file mode 100644 index 0000000..a5b88a3 --- /dev/null +++ b/tdc_releases/tdc_v2.0/tdc_components.vhd @@ -0,0 +1,351 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.trb_net_std.all; + +package tdc_components is + component TDC is + generic ( + MODULE_NUMBER : integer range 1 to 4; + CHANNEL_NUMBER : integer range 2 to 65; + STATUS_REG_NR : integer range 0 to 31; + CONTROL_REG_NR : integer range 0 to 6; + TDC_VERSION : std_logic_vector(11 downto 0); + DEBUG : integer range 0 to 1 := c_YES; + SIMULATION : integer range 0 to 1 := c_NO); + port ( + RESET : in std_logic; + CLK_TDC : in std_logic; + CLK_READOUT : in std_logic; + REFERENCE_TIME : in std_logic; + HIT_IN : in std_logic_vector(CHANNEL_NUMBER downto 1); + HIT_CALIBRATION : in std_logic; + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); + TRG_DATA_VALID_IN : in std_logic := '0'; + VALID_TIMING_TRG_IN : in std_logic := '0'; + VALID_NOTIMING_TRG_IN : in std_logic := '0'; + INVALID_TRG_IN : in std_logic := '0'; + TMGTRG_TIMEOUT_IN : in std_logic := '0'; + SPIKE_DETECTED_IN : in std_logic := '0'; + MULTI_TMG_TRG_IN : in std_logic := '0'; + SPURIOUS_TRG_IN : in std_logic := '0'; + TRG_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0'); + TRG_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0'); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0) := (others => '0'); + TRG_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0'); + TRG_RELEASE_OUT : out std_logic_vector(MODULE_NUMBER downto 0); + TRG_STATUSBIT_OUT : out std_logic_vector_array_32(0 to MODULE_NUMBER); + DATA_OUT : out std_logic_vector_array_32(0 to MODULE_NUMBER); + DATA_WRITE_OUT : out std_logic_vector(MODULE_NUMBER downto 0); + DATA_FINISHED_OUT : out std_logic_vector(MODULE_NUMBER downto 0); + HCB_READ_EN_IN : in std_logic; + HCB_WRITE_EN_IN : in std_logic; + HCB_ADDR_IN : in std_logic_vector(6 downto 0); + HCB_DATA_OUT : out std_logic_vector(31 downto 0); + HCB_DATAREADY_OUT : out std_logic; + HCB_UNKNOWN_ADDR_OUT : out std_logic; + SRB_READ_EN_IN : in std_logic; + SRB_WRITE_EN_IN : in std_logic; + SRB_ADDR_IN : in std_logic_vector(6 downto 0); + SRB_DATA_OUT : out std_logic_vector(31 downto 0); + SRB_DATAREADY_OUT : out std_logic; + SRB_UNKNOWN_ADDR_OUT : out std_logic; + CDB_READ_EN_IN : in std_logic; + CDB_WRITE_EN_IN : in std_logic; + CDB_ADDR_IN : in std_logic_vector(6 downto 0); + CDB_DATA_OUT : out std_logic_vector(31 downto 0); + CDB_DATAREADY_OUT : out std_logic; + CDB_UNKNOWN_ADDR_OUT : out std_logic; + ESB_READ_EN_IN : in std_logic; + ESB_WRITE_EN_IN : in std_logic; + ESB_ADDR_IN : in std_logic_vector(6 downto 0); + ESB_DATA_OUT : out std_logic_vector(31 downto 0); + ESB_DATAREADY_OUT : out std_logic; + ESB_UNKNOWN_ADDR_OUT : out std_logic; + EFB_READ_EN_IN : in std_logic; + EFB_WRITE_EN_IN : in std_logic; + EFB_ADDR_IN : in std_logic_vector(6 downto 0); + EFB_DATA_OUT : out std_logic_vector(31 downto 0); + EFB_DATAREADY_OUT : out std_logic; + EFB_UNKNOWN_ADDR_OUT : out std_logic; + FWB_READ_EN_IN : in std_logic; -- not used after version 1.3 + FWB_WRITE_EN_IN : in std_logic; -- not used after version 1.3 + FWB_ADDR_IN : in std_logic_vector(6 downto 0); -- not used after version 1.3 + FWB_DATA_OUT : out std_logic_vector(31 downto 0); -- not used after version 1.3 + FWB_DATAREADY_OUT : out std_logic; -- not used after version 1.3 + FWB_UNKNOWN_ADDR_OUT : out std_logic; -- not used after version 1.3 + LHB_READ_EN_IN : in std_logic; + LHB_WRITE_EN_IN : in std_logic; + LHB_ADDR_IN : in std_logic_vector(6 downto 0); + LHB_DATA_OUT : out std_logic_vector(31 downto 0); + LHB_DATAREADY_OUT : out std_logic; + LHB_UNKNOWN_ADDR_OUT : out std_logic; + LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0); + CONTROL_REG_IN : in std_logic_vector(32*CONTROL_REG_NR-1 downto 0)); + end component TDC; + + component Channel + generic ( + CHANNEL_ID : integer range 0 to 64; + DEBUG : integer range 0 to 1; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); + port ( + RESET_200 : in std_logic; + RESET_100 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_200 : in std_logic; + CLK_100 : in std_logic; + HIT_IN : in std_logic; + HIT_EDGE_IN : in std_logic; + TRIGGER_WIN_END_TDC : in std_logic; + TRIGGER_WIN_END_RDO : in std_logic; + READ_EN_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_DATA_VALID_OUT : out std_logic; + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_EMPTY_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + EPOCH_WRITE_EN_IN : in std_logic; + LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); + HIT_DETECT_NUMBER : out std_logic_vector(30 downto 0); + ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); + ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); + FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0); + Channel_200_DEBUG : out std_logic_vector(31 downto 0); + Channel_DEBUG : out std_logic_vector(31 downto 0)); + end component; + + component Channel_200 + generic ( + CHANNEL_ID : integer range 0 to 64; + DEBUG : integer range 0 to 1; + SIMULATION : integer range 0 to 1; + REFERENCE : integer range 0 to 1); + port ( + CLK_200 : in std_logic; + RESET_200 : in std_logic; + CLK_100 : in std_logic; + RESET_100 : in std_logic; + HIT_IN : in std_logic; + HIT_EDGE_IN : in std_logic; + TRIGGER_WIN_END_TDC : in std_logic; + TRIGGER_WIN_END_RDO : in std_logic; + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + READ_EN_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(35 downto 0); + FIFO_DATA_VALID_OUT : out std_logic; + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + EPOCH_WRITE_EN_IN : in std_logic; + ENCODER_START_OUT : out std_logic; + ENCODER_FINISHED_OUT : out std_logic; + FIFO_WRITE_OUT : out std_logic; + Channel_200_DEBUG : out std_logic_vector(31 downto 0)); + end component; + + component Readout_Header is + port ( + RESET_100 : in std_logic; + CLK_100 : in std_logic; + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + INVALID_TRG_IN : in std_logic; + TRG_CODE_IN : in std_logic_vector(7 downto 0); + TRG_TYPE_IN : in std_logic_vector(3 downto 0); + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic); + end component Readout_Header; + + component Readout is + generic ( + MODULE_NUMBER : integer range 1 to 4; + CHANNEL_NUMBER : integer range 2 to 65; + STATUS_REG_NR : integer range 0 to 31; + TDC_VERSION : std_logic_vector(11 downto 0)); + port ( + RESET_100 : in std_logic; + RESET_200 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_100 : in std_logic; + CLK_200 : in std_logic; + CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); + CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_ALMOST_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + TRG_DATA_VALID_IN : in std_logic; + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + INVALID_TRG_IN : in std_logic; + TMGTRG_TIMEOUT_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + SPURIOUS_TRG_IN : in std_logic; + TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + TRG_CODE_IN : in std_logic_vector(7 downto 0); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + TRG_TYPE_IN : in std_logic_vector(3 downto 0); + DATA_LIMIT_IN : in unsigned(7 downto 0); + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; + READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); + TRG_WIN_PRE : in std_logic_vector(10 downto 0); + TRG_WIN_POST : in std_logic_vector(10 downto 0); + TRIGGER_WIN_EN_IN : in std_logic; + TRIG_WIN_END_TDC_IN : in std_logic; + TRIG_WIN_END_RDO_IN : in std_logic; + TRIG_TIME_IN : in std_logic_vector(38 downto 0); + TRIGGER_TDC_IN : in std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + DEBUG_MODE_EN_IN : in std_logic; + STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to STATUS_REG_NR-1); + READOUT_DEBUG : out std_logic_vector(31 downto 0); + REFERENCE_TIME : in std_logic + ); + end component Readout; + + + component TriggerHandler is + generic ( + TRIGGER_NUM : integer; + PHYSICAL_EVENT_TRG_NUM : integer); + port ( + CLK_TRG : in std_logic; + CLK_RDO : in std_logic; + CLK_TDC : in std_logic; + RESET_TRG : in std_logic; + RESET_RDO : in std_logic; + RESET_TDC : in std_logic; + TRIGGER_IN : in std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_RDO_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_TDC_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRIGGER_WIN_EN_IN : in std_logic; + TRIGGER_WIN_POST_IN : in unsigned(10 downto 0); + TRIGGER_WIN_END_RDO_OUT : out std_logic; + TRIGGER_WIN_END_TDC_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + TRIGGER_TIME_OUT : out std_logic_vector(38 downto 0) := (others => '0')); + end component TriggerHandler; + + component LogicAnalyser + generic ( + CHANNEL_NUMBER : integer range 2 to 65); + port ( + CLK : in std_logic; + RESET : in std_logic; + DATA_IN : in std_logic_vector(3*32-1 downto 0); + CONTROL_IN : in std_logic_vector(3 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0)); + end component; + + component BusHandler + generic ( + BUS_LENGTH : integer range 0 to 64 := 2); + port ( + RESET : in std_logic; + CLK : in std_logic; + DATA_IN : in std_logic_vector_array_32(0 to BUS_LENGTH); + READ_EN_IN : in std_logic; + WRITE_EN_IN : in std_logic; + ADDR_IN : in std_logic_vector(6 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATAREADY_OUT : out std_logic; + UNKNOWN_ADDR_OUT : out std_logic); + end component; + + component ROM_FIFO + port ( + Address : in std_logic_vector(7 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(3 downto 0)); + end component; + + component Stretcher is + port ( + PULSE_IN : in std_logic; + PULSE_OUT : out std_logic); + end component Stretcher; + + component up_counter + generic ( + NUMBER_OF_BITS : positive); + port ( + CLK : in std_logic; + RESET : in std_logic; + COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); + UP_IN : in std_logic); + end component; + + component Adder_304 + port ( + CLK : in std_logic; + RESET : in std_logic; + DataA : in std_logic_vector(303 downto 0); + DataB : in std_logic_vector(303 downto 0); + ClkEn : in std_logic; + Result : out std_logic_vector(303 downto 0)); + end component; + + component Encoder_304_Bit is + port ( + RESET : in std_logic; + CLK : in std_logic; + START_IN : in std_logic; + THERMOCODE_IN : in std_logic_vector(303 downto 0); + FINISHED_OUT : out std_logic; + BINARY_CODE_OUT : out std_logic_vector(9 downto 0); + ENCODER_INFO_OUT : out std_logic_vector(1 downto 0); + ENCODER_DEBUG : out std_logic_vector(31 downto 0)); + end component Encoder_304_Bit; + + component hit_mux is + port ( + CH_EN_IN : in std_logic; + CALIBRATION_EN_IN : in std_logic; + HIT_CALIBRATION_IN : in std_logic; + HIT_PHYSICAL_IN : in std_logic; + HIT_OUT : out std_logic); + end component hit_mux; + + component ROM_encoder_3 + port ( + Address : in std_logic_vector(9 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0)); + end component; + + component ROM4_Encoder is + port ( + Address : in std_logic_vector(9 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(7 downto 0)); + end component ROM4_Encoder; + + +end package; diff --git a/tdc_releases/tdc_v2.0/tdc_constraints_16.lpf b/tdc_releases/tdc_v2.0/tdc_constraints_16.lpf new file mode 100644 index 0000000..050158d --- /dev/null +++ b/tdc_releases/tdc_v2.0/tdc_constraints_16.lpf @@ -0,0 +1,309 @@ +################################################################# +# TDC Constraints +################################################################# +############################################################################## +## REFERENCE CHANNEL PLACEMENT ## +############################################################################## +UGROUP "Ref_Ch" BBOX 1 51 + BLKNAME THE_TDC/ReferenceChannel/Channel200/SimAdderNo_FC; +LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; +UGROUP "ref_hit" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/hit_buf_RNO; +LOCATE UGROUP "ref_hit" SITE "R9C133D" ; +UGROUP "Ref_ff_en" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; + +############################################################################## +## DELAY LINE and HIT BUFFER PLACEMENTS ## +############################################################################## +UGROUP "FC_1" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_1" SITE "R10C131D" ; +UGROUP "hit_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_1" SITE "R11C133D" ; +UGROUP "ff_en_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_1" SITE "R10C156D" ; +# +UGROUP "FC_2" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_2" SITE "R21C131D" ; +UGROUP "hit_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_2" SITE "R22C133D" ; +UGROUP "ff_en_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_2" SITE "R21C156D" ; +# +UGROUP "FC_3" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_3" SITE "R23C131D" ; +UGROUP "hit_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_3" SITE "R24C133D" ; +UGROUP "ff_en_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_3" SITE "R23C156D" ; +# +UGROUP "FC_4" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_4" SITE "R30C131D" ; +UGROUP "hit_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_4" SITE "R31C133D" ; +UGROUP "ff_en_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_4" SITE "R30C156D" ; +# +UGROUP "FC_5" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_5" SITE "R32C131D" ; +UGROUP "hit_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_5" SITE "R33C133D" ; +UGROUP "ff_en_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_5" SITE "R32C156D" ; +# +UGROUP "FC_6" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_6" SITE "R35C131D" ; +UGROUP "hit_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_6" SITE "R36C133D" ; +UGROUP "ff_en_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_6" SITE "R35C156D" ; +# +UGROUP "FC_7" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_7" SITE "R37C131D" ; +UGROUP "hit_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_7" SITE "R38C133D" ; +UGROUP "ff_en_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_7" SITE "R37C156D" ; +# +UGROUP "FC_8" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_8" SITE "R48C131D" ; +UGROUP "hit_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_8" SITE "R49C133D" ; +UGROUP "ff_en_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_8" SITE "R48C156D" ; +# +UGROUP "FC_9" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_9" SITE "R50C131D" ; +UGROUP "hit_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_9" SITE "R51C133D" ; +UGROUP "ff_en_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_9" SITE "R50C156D" ; +# +UGROUP "FC_10" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_10" SITE "R53C131D" ; +UGROUP "hit_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_10" SITE "R54C133D" ; +UGROUP "ff_en_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_10" SITE "R53C156D" ; +# +UGROUP "FC_11" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_11" SITE "R55C131D" ; +UGROUP "hit_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_11" SITE "R56C133D" ; +UGROUP "ff_en_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_11" SITE "R55C156D" ; +# +UGROUP "FC_12" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_12" SITE "R10C58D" ; +UGROUP "hit_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_12" SITE "R11C60D" ; +UGROUP "ff_en_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_12" SITE "R10C83D" ; +# +UGROUP "FC_13" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_13" SITE "R23C58D" ; +UGROUP "hit_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_13" SITE "R24C60D" ; +UGROUP "ff_en_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_13" SITE "R23C83D" ; +# +UGROUP "FC_14" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_14" SITE "R32C58D" ; +UGROUP "hit_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_14" SITE "R33C60D" ; +UGROUP "ff_en_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_14" SITE "R32C83D" ; +# +UGROUP "FC_15" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_15" SITE "R37C58D" ; +UGROUP "hit_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_15" SITE "R38C60D" ; +UGROUP "ff_en_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_15" SITE "R37C83D" ; +# +UGROUP "FC_16" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_16" SITE "R50C58D" ; +UGROUP "hit_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_16" SITE "R51C60D" ; +UGROUP "ff_en_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_16" SITE "R50C83D" ; + +############################################################################## +## CHANNEL PLACEMENTS ## +############################################################################## +UGROUP "EF_ref" BBOX 16 54 + BLKNAME THE_TDC/ReferenceChannel/Channel200 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200 + BLKNAME THE_TDC/ReferenceChannel/The_Buffer + BLKNAME THE_TDC/GEN_Channels_1_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_2_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_3_Channels/The_Buffer; +LOCATE UGROUP "EF_ref" SITE "R8C128D" ; + +UGROUP "EF_4" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_4_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_5_Channels/The_Buffer; +LOCATE UGROUP "EF_4" SITE "R24C128D" ; + +UGROUP "EF_6" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_6_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_7_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_8_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_9_Channels/The_Buffer; +LOCATE UGROUP "EF_6" SITE "R35C128D" ; + +UGROUP "EF_10" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_10_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_11_Channels/The_Buffer; +LOCATE UGROUP "EF_10" SITE "R53C128D" ; + +UGROUP "EF_12" BBOX 16 54 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_12_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_13_Channels/The_Buffer; +LOCATE UGROUP "EF_12" SITE "R8C56D" ; + +UGROUP "EF_14" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_14_Channels/The_Buffer; +LOCATE UGROUP "EF_14" SITE "R24C56D" ; + +UGROUP "EF_15" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_15_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_16_Channels/The_Buffer; +LOCATE UGROUP "EF_15" SITE "R35C56D" ; + +############################################################################# +## Coarse counter register placement +############################################################################# + +UGROUP "UR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_1_TheCoarseCounter; +LOCATE UGROUP "UR_Coarse_Counter" SITE R36C134D; +UGROUP "LR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_2_TheCoarseCounter; +LOCATE UGROUP "LR_Coarse_Counter" SITE R85C134D; +UGROUP "UL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_3_TheCoarseCounter; +LOCATE UGROUP "UL_Coarse_Counter" SITE R36C50D; +UGROUP "LL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_4_TheCoarseCounter; +LOCATE UGROUP "LL_Coarse_Counter" SITE R85C50D; +UGROUP "TheCounters" + BLKNAME THE_TDC/GenCoarseCounter_0_TheCoarseCounter + BLKNAME THE_TDC/TheEpochCounter; +#LOCATE UGROUP "TheCounters" REGION REGION_READOUT; + +############################################################################# +## Other Logic Placements +############################################################################# + +UGROUP "BusHandlers" + BLKNAME THE_TDC/TheHitCounterBus + BLKNAME THE_TDC/TheStatusRegistersBus +# BLKNAME THE_TDC/TheLostHitBus +# BLKNAME THE_TDC/TheEncoderStartBus +# BLKNAME THE_TDC/TheEncoderFinishedBus +; +LOCATE UGROUP "BusHandlers" REGION "REGION_TRBNET"; +LOCATE PGROUP "BusHandlers" REGION "REGION_TRBNET"; + +UGROUP "TheTdcReadout" #BBOX 35 57 + BLKNAME THE_TDC/TheReadout + ; +#LOCATE UGROUP "TheTdcReadout" SITE "R53C53D"; + +UGROUP "TheTriggerHandler" + BLKNAME THE_TDC/TheTriggerHandler + ; +LOCATE UGROUP "TheTriggerHandler" SITE "R65C80D"; + +############################################################################# +## Unimportant Data Lines ## +############################################################################# + +BLOCK NET "THE_TDC/reset_tdc*" ; +BLOCK NET "THE_TDC/reset_rdo*" ; +BLOCK NET "THE_TDC/hit_in_i_*" ; +BLOCK NET "THE_TDC/reset_counters_i*" ; +BLOCK PATH TO CELL "THE_TDC/GEN_Channels_*_Channels/sync_q_2*"; + + + +#BLOCK PATH TO CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/SimAdderNo_FC/FF_*" ; + + + +PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels_*_Channels/Channel200/ff_array_en_i"; + +MAXDELAY NET "THE_TDC/ReferenceChannel/hit_buf" 0.600000 nS DATAPATH_ONLY ; +MAXDELAY NET "THE_TDC/GEN_Channels_*_Channels/hit_buf" 0.600000 nS DATAPATH_ONLY ; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/GEN_Channels_*_Channels/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; diff --git a/tdc_releases/tdc_v2.0/tdc_constraints_32.lpf b/tdc_releases/tdc_v2.0/tdc_constraints_32.lpf new file mode 100644 index 0000000..d8c46bd --- /dev/null +++ b/tdc_releases/tdc_v2.0/tdc_constraints_32.lpf @@ -0,0 +1,492 @@ +################################################################# +# TDC Constraints +################################################################# +############################################################################## +## REFERENCE CHANNEL PLACEMENT ## +############################################################################## +UGROUP "Ref_Ch" BBOX 1 51 + BLKNAME THE_TDC/ReferenceChannel/Channel200/SimAdderNo_FC; +LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; +UGROUP "hitBuf_ref" BBOX 1 1 + BLKNAME THE_TDC/hit_mux_ref; +LOCATE UGROUP "hitBuf_ref" SITE "R9C133D" ; +UGROUP "Ref_ff_en" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; + +############################################################################## +## DELAY LINE and HIT BUFFER PLACEMENTS ## +############################################################################## +UGROUP "FC_1" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_1" SITE "R10C131D" ; +UGROUP "hitBuf_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_1_hit_mux_ch; +LOCATE UGROUP "hitBuf_1" SITE "R11C133D" ; +UGROUP "ff_en_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_1" SITE "R10C156D" ; +# +UGROUP "FC_2" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_2" SITE "R21C131D" ; +UGROUP "hitBuf_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_2_hit_mux_ch; +LOCATE UGROUP "hitBuf_2" SITE "R22C133D" ; +UGROUP "ff_en_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_2" SITE "R21C156D" ; +# +UGROUP "FC_3" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_3" SITE "R23C131D" ; +UGROUP "hitBuf_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_3_hit_mux_ch; +LOCATE UGROUP "hitBuf_3" SITE "R24C133D" ; +UGROUP "ff_en_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_3" SITE "R23C156D" ; +# +UGROUP "FC_4" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_4" SITE "R30C131D" ; +UGROUP "hitBuf_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_4_hit_mux_ch; +LOCATE UGROUP "hitBuf_4" SITE "R31C133D" ; +UGROUP "ff_en_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_4" SITE "R30C156D" ; +# +UGROUP "FC_5" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_5" SITE "R32C131D" ; +UGROUP "hitBuf_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_5_hit_mux_ch; +LOCATE UGROUP "hitBuf_5" SITE "R33C133D" ; +UGROUP "ff_en_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_5" SITE "R32C156D" ; +# +UGROUP "FC_6" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_6" SITE "R35C131D" ; +UGROUP "hitBuf_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_6_hit_mux_ch; +LOCATE UGROUP "hitBuf_6" SITE "R36C133D" ; +UGROUP "ff_en_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_6" SITE "R35C156D" ; +# +UGROUP "FC_7" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_7" SITE "R37C131D" ; +UGROUP "hitBuf_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_7_hit_mux_ch; +LOCATE UGROUP "hitBuf_7" SITE "R38C133D" ; +UGROUP "ff_en_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_7" SITE "R37C156D" ; +# +UGROUP "FC_8" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_8" SITE "R48C131D" ; +UGROUP "hitBuf_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_8_hit_mux_ch; +LOCATE UGROUP "hitBuf_8" SITE "R49C133D" ; +UGROUP "ff_en_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_8" SITE "R48C156D" ; +# +UGROUP "FC_9" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_9" SITE "R50C131D" ; +UGROUP "hitBuf_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_9_hit_mux_ch; +LOCATE UGROUP "hitBuf_9" SITE "R51C133D" ; +UGROUP "ff_en_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_9" SITE "R50C156D" ; +# +UGROUP "FC_10" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_10" SITE "R53C131D" ; +UGROUP "hitBuf_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_10_hit_mux_ch; +LOCATE UGROUP "hitBuf_10" SITE "R54C133D" ; +UGROUP "ff_en_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_10" SITE "R53C156D" ; +# +UGROUP "FC_11" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_11" SITE "R55C131D" ; +UGROUP "hitBuf_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_11_hit_mux_ch; +LOCATE UGROUP "hitBuf_11" SITE "R56C133D" ; +UGROUP "ff_en_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_11" SITE "R55C156D" ; +# +UGROUP "FC_12" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_12" SITE "R10C58D" ; +UGROUP "hitBuf_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_12_hit_mux_ch; +LOCATE UGROUP "hitBuf_12" SITE "R11C60D" ; +UGROUP "ff_en_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_12" SITE "R10C83D" ; +# +UGROUP "FC_13" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_13" SITE "R23C58D" ; +UGROUP "hitBuf_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_13_hit_mux_ch; +LOCATE UGROUP "hitBuf_13" SITE "R24C60D" ; +UGROUP "ff_en_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_13" SITE "R23C83D" ; +# +UGROUP "FC_14" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_14" SITE "R32C58D" ; +UGROUP "hitBuf_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_14_hit_mux_ch; +LOCATE UGROUP "hitBuf_14" SITE "R33C60D" ; +UGROUP "ff_en_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_14" SITE "R32C83D" ; +# +UGROUP "FC_15" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_15" SITE "R37C58D" ; +UGROUP "hitBuf_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_15_hit_mux_ch; +LOCATE UGROUP "hitBuf_15" SITE "R38C60D" ; +UGROUP "ff_en_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_15" SITE "R37C83D" ; +# +UGROUP "FC_16" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_16" SITE "R50C58D" ; +UGROUP "hitBuf_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_16_hit_mux_ch; +LOCATE UGROUP "hitBuf_16" SITE "R51C60D" ; +UGROUP "ff_en_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_16" SITE "R50C83D" ; +# +UGROUP "FC_17" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_17" SITE "R66C131D" ; +UGROUP "hitBuf_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_17_hit_mux_ch; +LOCATE UGROUP "hitBuf_17" SITE "R67C133D" ; +UGROUP "ff_en_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_17" SITE "R66C156D" ; +# +UGROUP "FC_18" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_18" SITE "R68C131D" ; +UGROUP "hitBuf_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_18_hit_mux_ch; +LOCATE UGROUP "hitBuf_18" SITE "R69C133D" ; +UGROUP "ff_en_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_18" SITE "R68C156D" ; +# +UGROUP "FC_19" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_19" SITE "R71C131D" ; +UGROUP "hitBuf_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_19_hit_mux_ch; +LOCATE UGROUP "hitBuf_19" SITE "R72C133D" ; +UGROUP "ff_en_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_19" SITE "R71C156D" ; +# +UGROUP "FC_20" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_20" SITE "R73C131D" ; +UGROUP "hitBuf_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_20_hit_mux_ch; +LOCATE UGROUP "hitBuf_20" SITE "R74C133D" ; +UGROUP "ff_en_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_20" SITE "R73C156D" ; +# +UGROUP "FC_21" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_21" SITE "R84C131D" ; +UGROUP "hitBuf_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_21_hit_mux_ch; +LOCATE UGROUP "hitBuf_21" SITE "R85C133D" ; +UGROUP "ff_en_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_21" SITE "R84C156D" ; +# +UGROUP "FC_22" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_22" SITE "R86C131D" ; +UGROUP "hitBuf_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_22_hit_mux_ch; +LOCATE UGROUP "hitBuf_22" SITE "R87C133D" ; +UGROUP "ff_en_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_22" SITE "R86C156D" ; +# +UGROUP "FC_23" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_23" SITE "R89C131D" ; +UGROUP "hitBuf_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_23_hit_mux_ch; +LOCATE UGROUP "hitBuf_23" SITE "R90C133D" ; +UGROUP "ff_en_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_23" SITE "R89C156D" ; +# +UGROUP "FC_24" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_24" SITE "R91C131D" ; +UGROUP "hitBuf_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_24_hit_mux_ch; +LOCATE UGROUP "hitBuf_24" SITE "R92C133D" ; +UGROUP "ff_en_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_24" SITE "R91C156D" ; +# +UGROUP "FC_25" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_25" SITE "R102C131D" ; +UGROUP "hitBuf_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_25_hit_mux_ch; +LOCATE UGROUP "hitBuf_25" SITE "R103C133D" ; +UGROUP "ff_en_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_25" SITE "R102C156D" ; +# +UGROUP "FC_26" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_26" SITE "R104C131D" ; +UGROUP "hitBuf_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_26_hit_mux_ch; +LOCATE UGROUP "hitBuf_26" SITE "R105C133D" ; +UGROUP "ff_en_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_26" SITE "R104C156D" ; +# +UGROUP "FC_27" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_27" SITE "R111C131D" ; +UGROUP "hitBuf_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_27_hit_mux_ch; +LOCATE UGROUP "hitBuf_27" SITE "R112C133D" ; +UGROUP "ff_en_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_27" SITE "R111C156D" ; +# +UGROUP "FC_28" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_28" SITE "R113C131D" ; +UGROUP "hitBuf_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_28_hit_mux_ch; +LOCATE UGROUP "hitBuf_28" SITE "R114C133D" ; +UGROUP "ff_en_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_28" SITE "R113C156D" ; +# +UGROUP "FC_29" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_29" SITE "R91C58D" ; +UGROUP "hitBuf_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_29_hit_mux_ch; +LOCATE UGROUP "hitBuf_29" SITE "R92C60D" ; +UGROUP "ff_en_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_29" SITE "R91C83D" ; +# +UGROUP "FC_30" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_30" SITE "R104C58D" ; +UGROUP "hitBuf_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_30_hit_mux_ch; +LOCATE UGROUP "hitBuf_30" SITE "R105C60D" ; +UGROUP "ff_en_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_30" SITE "R104C83D" ; +# +UGROUP "FC_31" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_31" SITE "R113C58D" ; +UGROUP "hitBuf_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_31_hit_mux_ch; +LOCATE UGROUP "hitBuf_31" SITE "R114C60D" ; +UGROUP "ff_en_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_31" SITE "R113C83D" ; +# +UGROUP "FC_32" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_32" SITE "R84C58D" ; +UGROUP "hitBuf_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_32_hit_mux_ch; +LOCATE UGROUP "hitBuf_32" SITE "R85C60D" ; +UGROUP "ff_en_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_32" SITE "R84C83D" ; + +############################################################################## +## CHANNEL PLACEMENTS ## +############################################################################## +UGROUP "EF_ref" BBOX 16 54 + BLKNAME THE_TDC/ReferenceChannel/Channel200 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200 + BLKNAME THE_TDC/ReferenceChannel/The_Buffer + BLKNAME THE_TDC/GEN_Channels_1_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_2_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_3_Channels/The_Buffer; +LOCATE UGROUP "EF_ref" SITE "R8C128D" ; + +UGROUP "EF_4" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_4_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_5_Channels/The_Buffer; +LOCATE UGROUP "EF_4" SITE "R24C128D" ; + +UGROUP "EF_6" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_6_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_7_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_8_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_9_Channels/The_Buffer; +LOCATE UGROUP "EF_6" SITE "R35C128D" ; + +UGROUP "EF_10" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_10_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_11_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_17_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_18_Channels/The_Buffer; +LOCATE UGROUP "EF_10" SITE "R53C128D" ; + +UGROUP "EF_12" BBOX 16 54 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_12_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_13_Channels/The_Buffer; +LOCATE UGROUP "EF_12" SITE "R8C56D" ; + +UGROUP "EF_14" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_14_Channels/The_Buffer; +LOCATE UGROUP "EF_14" SITE "R24C56D" ; + +UGROUP "EF_15" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_15_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_16_Channels/The_Buffer; +LOCATE UGROUP "EF_15" SITE "R35C56D" ; + +UGROUP "EF_19" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_19_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_20_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_21_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_22_Channels/The_Buffer; +LOCATE UGROUP "EF_19" SITE "R71C128D" ; + +UGROUP "EF_23" BBOX 16 54 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_23_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_24_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_25_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_26_Channels/The_Buffer; +LOCATE UGROUP "EF_23" SITE "R89C128D" ; + +UGROUP "EF_27" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_27_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_28_Channels/The_Buffer; +LOCATE UGROUP "EF_27" SITE "R105C128D" ; + +UGROUP "EF_29" BBOX 16 54 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_29_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_30_Channels/The_Buffer; +LOCATE UGROUP "EF_29" SITE "R89C56D" ; + +UGROUP "EF_31" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_31_Channels/The_Buffer; +LOCATE UGROUP "EF_31" SITE "R105C56D" ; + +UGROUP "EF_32" BBOX 10 24 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_32_Channels/The_Buffer; +LOCATE UGROUP "EF_32" SITE "R78C71D" ; + +############################################################################# +## Coarse counter register placement +############################################################################# + +UGROUP "UR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_1_TheCoarseCounter; +LOCATE UGROUP "UR_Coarse_Counter" SITE R36C134D; +UGROUP "LR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_2_TheCoarseCounter; +LOCATE UGROUP "LR_Coarse_Counter" SITE R85C134D; +UGROUP "UL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_3_TheCoarseCounter; +LOCATE UGROUP "UL_Coarse_Counter" SITE R36C50D; +UGROUP "LL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_4_TheCoarseCounter; +LOCATE UGROUP "LL_Coarse_Counter" SITE R85C50D; +UGROUP "TheCounters" + BLKNAME THE_TDC/GenCoarseCounter_0_TheCoarseCounter + BLKNAME THE_TDC/TheEpochCounter; +#LOCATE UGROUP "TheCounters" REGION REGION_READOUT; + +############################################################################# +## Other Logic Placements +############################################################################# + +UGROUP "BusHandlers" + BLKNAME THE_TDC/TheHitCounterBus + BLKNAME THE_TDC/TheStatusRegistersBus +# BLKNAME THE_TDC/TheLostHitBus +# BLKNAME THE_TDC/TheEncoderStartBus +# BLKNAME THE_TDC/TheEncoderFinishedBus +; +LOCATE UGROUP "BusHandlers" REGION "REGION_TRBNET"; +LOCATE PGROUP "BusHandlers" REGION "REGION_TRBNET"; + +UGROUP "TheTdcReadout" #BBOX 35 57 + BLKNAME THE_TDC/TheReadout + ; +#LOCATE UGROUP "TheTdcReadout" SITE "R53C53D"; + +UGROUP "TheTriggerHandler" + BLKNAME THE_TDC/TheTriggerHandler + ; +LOCATE UGROUP "TheTriggerHandler" SITE "R65C80D"; + diff --git a/tdc_releases/tdc_v2.0/tdc_constraints_4.lpf b/tdc_releases/tdc_v2.0/tdc_constraints_4.lpf new file mode 100644 index 0000000..4792f4b --- /dev/null +++ b/tdc_releases/tdc_v2.0/tdc_constraints_4.lpf @@ -0,0 +1,150 @@ +################################################################# +# TDC Constraints +################################################################# +############################################################################## +## REFERENCE CHANNEL PLACEMENT ## +############################################################################## +UGROUP "Ref_Ch" BBOX 1 51 + BLKNAME THE_TDC/ReferenceChannel/Channel200/SimAdderNo_FC; +LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; +UGROUP "ref_hit" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/hit_buf_RNO; +LOCATE UGROUP "ref_hit" SITE "R9C133D" ; +UGROUP "Ref_ff_en" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; + +############################################################################## +## DELAY LINE and HIT BUFFER PLACEMENTS ## +############################################################################## +UGROUP "FC_1" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_1" SITE "R10C131D" ; +UGROUP "hit_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_1" SITE "R11C133D" ; +UGROUP "ff_en_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_1" SITE "R10C156D" ; +# +UGROUP "FC_2" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_2" SITE "R21C131D" ; +UGROUP "hit_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_2" SITE "R22C133D" ; +UGROUP "ff_en_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_2" SITE "R21C156D" ; +# +UGROUP "FC_3" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_3" SITE "R23C131D" ; +UGROUP "hit_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_3" SITE "R24C133D" ; +UGROUP "ff_en_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_3" SITE "R23C156D" ; +# +UGROUP "FC_4" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_4" SITE "R30C131D" ; +UGROUP "hit_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_buf_RNO; +LOCATE UGROUP "hit_4" SITE "R31C133D" ; +UGROUP "ff_en_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_4" SITE "R30C156D" ; + +############################################################################## +## CHANNEL PLACEMENTS ## +############################################################################## +UGROUP "EF_ref" BBOX 16 54 + BLKNAME THE_TDC/ReferenceChannel/Channel200 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200 + BLKNAME THE_TDC/ReferenceChannel/The_Buffer + BLKNAME THE_TDC/GEN_Channels_1_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_2_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_3_Channels/The_Buffer; +LOCATE UGROUP "EF_ref" SITE "R8C128D" ; + +UGROUP "EF_4" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_4_Channels/The_Buffer; +LOCATE UGROUP "EF_4" SITE "R24C128D" ; + +############################################################################# +## Coarse counter register placement +############################################################################# + +UGROUP "UR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_1_TheCoarseCounter; +LOCATE UGROUP "UR_Coarse_Counter" SITE R36C134D; +UGROUP "LR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_2_TheCoarseCounter; +LOCATE UGROUP "LR_Coarse_Counter" SITE R85C134D; +UGROUP "UL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_3_TheCoarseCounter; +LOCATE UGROUP "UL_Coarse_Counter" SITE R36C50D; +UGROUP "LL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_4_TheCoarseCounter; +LOCATE UGROUP "LL_Coarse_Counter" SITE R85C50D; +UGROUP "TheCounters" + BLKNAME THE_TDC/GenCoarseCounter_0_TheCoarseCounter + BLKNAME THE_TDC/TheEpochCounter; +#LOCATE UGROUP "TheCounters" REGION REGION_READOUT; + +############################################################################# +## Other Logic Placements +############################################################################# + +UGROUP "BusHandlers" + BLKNAME THE_TDC/TheHitCounterBus + BLKNAME THE_TDC/TheStatusRegistersBus +# BLKNAME THE_TDC/TheLostHitBus +# BLKNAME THE_TDC/TheEncoderStartBus +# BLKNAME THE_TDC/TheEncoderFinishedBus +; +LOCATE UGROUP "BusHandlers" REGION "REGION_TRBNET"; +LOCATE PGROUP "BusHandlers" REGION "REGION_TRBNET"; + +UGROUP "TheTdcReadout" #BBOX 35 57 + BLKNAME THE_TDC/TheReadout + ; +#LOCATE UGROUP "TheTdcReadout" SITE "R53C53D"; + +UGROUP "TheTriggerHandler" + BLKNAME THE_TDC/TheTriggerHandler + ; +LOCATE UGROUP "TheTriggerHandler" SITE "R65C80D"; + +############################################################################# +## Unimportant Data Lines ## +############################################################################# + +BLOCK NET "THE_TDC/reset_tdc*" ; +BLOCK NET "THE_TDC/reset_rdo*" ; +BLOCK NET "THE_TDC/hit_in_i_*" ; +BLOCK NET "THE_TDC/reset_counters_i*" ; +BLOCK PATH TO CELL "THE_TDC/GEN_Channels_*_Channels/sync_q_2*"; + + + +#BLOCK PATH TO CELL "THE_TDC/GEN_Channels_*_Channels/Channel200/SimAdderNo_FC/FF_*" ; + + + +PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels_*_Channels/Channel200/ff_array_en_i"; + +MAXDELAY NET "THE_TDC/ReferenceChannel/hit_buf" 0.600000 nS DATAPATH_ONLY ; +MAXDELAY NET "THE_TDC/GEN_Channels_*_Channels/hit_buf" 0.600000 nS DATAPATH_ONLY ; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels_*_Channels/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/GEN_Channels_*_Channels/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter_*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; diff --git a/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf b/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf new file mode 100644 index 0000000..4419eb9 --- /dev/null +++ b/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf @@ -0,0 +1,1033 @@ +################################################################# +# TDC Constraints +################################################################# +############################################################################## +## REFERENCE CHANNEL PLACEMENT ## +############################################################################## +UGROUP "Ref_Ch" BBOX 1 51 + BLKNAME THE_TDC/ReferenceChannel/Channel200/SimAdderNo_FC; +LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; +UGROUP "hitBuf_ref" BBOX 1 1 + BLKNAME THE_TDC/hit_mux_ref; +LOCATE UGROUP "hitBuf_ref" SITE "R9C133D" ; +UGROUP "Ref_ff_en" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; + +############################################################################## +## DELAY LINE and HIT BUFFER PLACEMENTS ## +############################################################################## +UGROUP "FC_1" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_1" SITE "R10C131D" ; +UGROUP "hitBuf_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_1_hit_mux_ch; +LOCATE UGROUP "hitBuf_1" SITE "R11C133D" ; +UGROUP "ff_en_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_1" SITE "R10C156D" ; +# +UGROUP "FC_2" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_2" SITE "R21C131D" ; +UGROUP "hitBuf_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_2_hit_mux_ch; +LOCATE UGROUP "hitBuf_2" SITE "R22C133D" ; +UGROUP "ff_en_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_2" SITE "R21C156D" ; +# +UGROUP "FC_3" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_3" SITE "R23C131D" ; +UGROUP "hitBuf_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_3_hit_mux_ch; +LOCATE UGROUP "hitBuf_3" SITE "R24C133D" ; +UGROUP "ff_en_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_3" SITE "R23C156D" ; +# +UGROUP "FC_4" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_4" SITE "R30C131D" ; +UGROUP "hitBuf_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_4_hit_mux_ch; +LOCATE UGROUP "hitBuf_4" SITE "R31C133D" ; +UGROUP "ff_en_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_4" SITE "R30C156D" ; +# +UGROUP "FC_5" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_5" SITE "R32C131D" ; +UGROUP "hitBuf_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_5_hit_mux_ch; +LOCATE UGROUP "hitBuf_5" SITE "R33C133D" ; +UGROUP "ff_en_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_5" SITE "R32C156D" ; +# +UGROUP "FC_6" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_6" SITE "R35C131D" ; +UGROUP "hitBuf_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_6_hit_mux_ch; +LOCATE UGROUP "hitBuf_6" SITE "R36C133D" ; +UGROUP "ff_en_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_6" SITE "R35C156D" ; +# +UGROUP "FC_7" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_7" SITE "R37C131D" ; +UGROUP "hitBuf_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_7_hit_mux_ch; +LOCATE UGROUP "hitBuf_7" SITE "R38C133D" ; +UGROUP "ff_en_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_7" SITE "R37C156D" ; +# +UGROUP "FC_8" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_8" SITE "R48C131D" ; +UGROUP "hitBuf_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_8_hit_mux_ch; +LOCATE UGROUP "hitBuf_8" SITE "R49C133D" ; +UGROUP "ff_en_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_8" SITE "R48C156D" ; +# +UGROUP "FC_9" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_9" SITE "R50C131D" ; +UGROUP "hitBuf_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_9_hit_mux_ch; +LOCATE UGROUP "hitBuf_9" SITE "R51C133D" ; +UGROUP "ff_en_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_9" SITE "R50C156D" ; +# +UGROUP "FC_10" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_10" SITE "R53C131D" ; +UGROUP "hitBuf_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_10_hit_mux_ch; +LOCATE UGROUP "hitBuf_10" SITE "R54C133D" ; +UGROUP "ff_en_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_10" SITE "R53C156D" ; +# +UGROUP "FC_11" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_11" SITE "R55C131D" ; +UGROUP "hitBuf_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_11_hit_mux_ch; +LOCATE UGROUP "hitBuf_11" SITE "R56C133D" ; +UGROUP "ff_en_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_11" SITE "R55C156D" ; +# +UGROUP "FC_12" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_12" SITE "R10C58D" ; +UGROUP "hitBuf_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_12_hit_mux_ch; +LOCATE UGROUP "hitBuf_12" SITE "R11C60D" ; +UGROUP "ff_en_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_12" SITE "R10C83D" ; +# +UGROUP "FC_13" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_13" SITE "R23C58D" ; +UGROUP "hitBuf_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_13_hit_mux_ch; +LOCATE UGROUP "hitBuf_13" SITE "R24C60D" ; +UGROUP "ff_en_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_13" SITE "R23C83D" ; +# +UGROUP "FC_14" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_14" SITE "R32C58D" ; +UGROUP "hitBuf_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_14_hit_mux_ch; +LOCATE UGROUP "hitBuf_14" SITE "R33C60D" ; +UGROUP "ff_en_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_14" SITE "R32C83D" ; +# +UGROUP "FC_15" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_15" SITE "R37C58D" ; +UGROUP "hitBuf_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_15_hit_mux_ch; +LOCATE UGROUP "hitBuf_15" SITE "R38C60D" ; +UGROUP "ff_en_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_15" SITE "R37C83D" ; +# +UGROUP "FC_16" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_16" SITE "R50C58D" ; +UGROUP "hitBuf_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_16_hit_mux_ch; +LOCATE UGROUP "hitBuf_16" SITE "R51C60D" ; +UGROUP "ff_en_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_16" SITE "R50C83D" ; +# +UGROUP "FC_17" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_17" SITE "R66C131D" ; +UGROUP "hitBuf_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_17_hit_mux_ch; +LOCATE UGROUP "hitBuf_17" SITE "R67C133D" ; +UGROUP "ff_en_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_17" SITE "R66C156D" ; +# +UGROUP "FC_18" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_18" SITE "R68C131D" ; +UGROUP "hitBuf_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_18_hit_mux_ch; +LOCATE UGROUP "hitBuf_18" SITE "R69C133D" ; +UGROUP "ff_en_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_18" SITE "R68C156D" ; +# +UGROUP "FC_19" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_19" SITE "R71C131D" ; +UGROUP "hitBuf_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_19_hit_mux_ch; +LOCATE UGROUP "hitBuf_19" SITE "R72C133D" ; +UGROUP "ff_en_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_19" SITE "R71C156D" ; +# +UGROUP "FC_20" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_20" SITE "R73C131D" ; +UGROUP "hitBuf_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_20_hit_mux_ch; +LOCATE UGROUP "hitBuf_20" SITE "R74C133D" ; +UGROUP "ff_en_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_20" SITE "R73C156D" ; +# +UGROUP "FC_21" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_21" SITE "R84C131D" ; +UGROUP "hitBuf_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_21_hit_mux_ch; +LOCATE UGROUP "hitBuf_21" SITE "R85C133D" ; +UGROUP "ff_en_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_21" SITE "R84C156D" ; +# +UGROUP "FC_22" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_22" SITE "R86C131D" ; +UGROUP "hitBuf_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_22_hit_mux_ch; +LOCATE UGROUP "hitBuf_22" SITE "R87C133D" ; +UGROUP "ff_en_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_22" SITE "R86C156D" ; +# +UGROUP "FC_23" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_23" SITE "R89C131D" ; +UGROUP "hitBuf_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_23_hit_mux_ch; +LOCATE UGROUP "hitBuf_23" SITE "R90C133D" ; +UGROUP "ff_en_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_23" SITE "R89C156D" ; +# +UGROUP "FC_24" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_24" SITE "R91C131D" ; +UGROUP "hitBuf_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_24_hit_mux_ch; +LOCATE UGROUP "hitBuf_24" SITE "R92C133D" ; +UGROUP "ff_en_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_24" SITE "R91C156D" ; +# +UGROUP "FC_25" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_25" SITE "R102C131D" ; +UGROUP "hitBuf_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_25_hit_mux_ch; +LOCATE UGROUP "hitBuf_25" SITE "R103C133D" ; +UGROUP "ff_en_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_25" SITE "R102C156D" ; +# +UGROUP "FC_26" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_26" SITE "R104C131D" ; +UGROUP "hitBuf_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_26_hit_mux_ch; +LOCATE UGROUP "hitBuf_26" SITE "R105C133D" ; +UGROUP "ff_en_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_26" SITE "R104C156D" ; +# +UGROUP "FC_27" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_27" SITE "R111C131D" ; +UGROUP "hitBuf_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_27_hit_mux_ch; +LOCATE UGROUP "hitBuf_27" SITE "R112C133D" ; +UGROUP "ff_en_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_27" SITE "R111C156D" ; +# +UGROUP "FC_28" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_28" SITE "R113C131D" ; +UGROUP "hitBuf_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_28_hit_mux_ch; +LOCATE UGROUP "hitBuf_28" SITE "R114C133D" ; +UGROUP "ff_en_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_28" SITE "R113C156D" ; +# +UGROUP "FC_29" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_29" SITE "R91C58D" ; +UGROUP "hitBuf_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_29_hit_mux_ch; +LOCATE UGROUP "hitBuf_29" SITE "R92C60D" ; +UGROUP "ff_en_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_29" SITE "R91C83D" ; +# +UGROUP "FC_30" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_30" SITE "R104C58D" ; +UGROUP "hitBuf_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_30_hit_mux_ch; +LOCATE UGROUP "hitBuf_30" SITE "R105C60D" ; +UGROUP "ff_en_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_30" SITE "R104C83D" ; +# +UGROUP "FC_31" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_31" SITE "R113C58D" ; +UGROUP "hitBuf_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_31_hit_mux_ch; +LOCATE UGROUP "hitBuf_31" SITE "R114C60D" ; +UGROUP "ff_en_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_31" SITE "R113C83D" ; +# +UGROUP "FC_32" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_32" SITE "R84C58D" ; +UGROUP "hitBuf_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_32_hit_mux_ch; +LOCATE UGROUP "hitBuf_32" SITE "R85C60D" ; +UGROUP "ff_en_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_32" SITE "R84C83D" ; +# +UGROUP "FC_33" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_33" SITE "R8C58D" ; +UGROUP "hitBuf_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_33_hit_mux_ch; +LOCATE UGROUP "hitBuf_33" SITE "R9C60D" ; +UGROUP "ff_en_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_33" SITE "R8C83D" ; +# +UGROUP "FC_34" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_34" SITE "R21C58D" ; +UGROUP "hitBuf_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_34_hit_mux_ch; +LOCATE UGROUP "hitBuf_34" SITE "R22C60D" ; +UGROUP "ff_en_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_34" SITE "R21C83D" ; +# +UGROUP "FC_35" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_35" SITE "R30C58D" ; +UGROUP "hitBuf_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_35_hit_mux_ch; +LOCATE UGROUP "hitBuf_35" SITE "R31C60D" ; +UGROUP "ff_en_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_35" SITE "R30C83D" ; +# +UGROUP "FC_36" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_36" SITE "R35C58D" ; +UGROUP "hitBuf_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_36_hit_mux_ch; +LOCATE UGROUP "hitBuf_36" SITE "R36C60D" ; +UGROUP "ff_en_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_36" SITE "R35C83D" ; +# +UGROUP "FC_37" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_37" SITE "R48C58D" ; +UGROUP "hitBuf_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_37_hit_mux_ch; +LOCATE UGROUP "hitBuf_37" SITE "R49C60D" ; +UGROUP "ff_en_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_37" SITE "R48C83D" ; +# +UGROUP "FC_38" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_38" SITE "R8C2D" ; +UGROUP "hitBuf_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_38_hit_mux_ch; +LOCATE UGROUP "hitBuf_38" SITE "R9C4D" ; +UGROUP "ff_en_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_38" SITE "R8C27D" ; +# +UGROUP "FC_39" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_39" SITE "R10C2D" ; +UGROUP "hitBuf_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_39_hit_mux_ch; +LOCATE UGROUP "hitBuf_39" SITE "R11C4D" ; +UGROUP "ff_en_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_39" SITE "R10C27D" ; +# +UGROUP "FC_40" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_40" SITE "R21C2D" ; +UGROUP "hitBuf_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_40_hit_mux_ch; +LOCATE UGROUP "hitBuf_40" SITE "R22C4D" ; +UGROUP "ff_en_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_40" SITE "R21C27D" ; +# +UGROUP "FC_41" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_41" SITE "R23C2D" ; +UGROUP "hitBuf_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_41_hit_mux_ch; +LOCATE UGROUP "hitBuf_41" SITE "R24C4D" ; +UGROUP "ff_en_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_41" SITE "R23C27D" ; +# +UGROUP "FC_42" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_42" SITE "R30C2D" ; +UGROUP "hitBuf_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_42_hit_mux_ch; +LOCATE UGROUP "hitBuf_42" SITE "R31C4D" ; +UGROUP "ff_en_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_42" SITE "R30C27D" ; +# +UGROUP "FC_43" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_43" SITE "R32C2D" ; +UGROUP "hitBuf_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_43_hit_mux_ch; +LOCATE UGROUP "hitBuf_43" SITE "R33C4D" ; +UGROUP "ff_en_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_43" SITE "R32C27D" ; +# +UGROUP "FC_44" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_44" SITE "R35C2D" ; +UGROUP "hitBuf_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_44_hit_mux_ch; +LOCATE UGROUP "hitBuf_44" SITE "R36C4D" ; +UGROUP "ff_en_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_44" SITE "R35C27D" ; +# +UGROUP "FC_45" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_45" SITE "R37C2D" ; +UGROUP "hitBuf_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_45_hit_mux_ch; +LOCATE UGROUP "hitBuf_45" SITE "R38C4D" ; +UGROUP "ff_en_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_45" SITE "R37C27D" ; +# +UGROUP "FC_46" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_46" SITE "R48C2D" ; +UGROUP "hitBuf_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_46_hit_mux_ch; +LOCATE UGROUP "hitBuf_46" SITE "R49C4D" ; +UGROUP "ff_en_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_46" SITE "R48C27D" ; +# +UGROUP "FC_47" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_47" SITE "R50C2D" ; +UGROUP "hitBuf_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_47_hit_mux_ch; +LOCATE UGROUP "hitBuf_47" SITE "R51C4D" ; +UGROUP "ff_en_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_47" SITE "R50C27D" ; +# +UGROUP "FC_48" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_48" SITE "R53C2D" ; +UGROUP "hitBuf_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_48_hit_mux_ch; +LOCATE UGROUP "hitBuf_48" SITE "R54C4D" ; +UGROUP "ff_en_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_48" SITE "R53C27D" ; +# +UGROUP "FC_49" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_49" SITE "R55C2D" ; +UGROUP "hitBuf_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_49_hit_mux_ch; +LOCATE UGROUP "hitBuf_49" SITE "R56C4D" ; +UGROUP "ff_en_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_49" SITE "R55C27D" ; +# +UGROUP "FC_50" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_50" SITE "R89C58D" ; +UGROUP "hitBuf_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_50_hit_mux_ch; +LOCATE UGROUP "hitBuf_50" SITE "R90C60D" ; +UGROUP "ff_en_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_50" SITE "R89C83D" ; +# +UGROUP "FC_51" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_51" SITE "R102C58D" ; +UGROUP "hitBuf_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_51_hit_mux_ch; +LOCATE UGROUP "hitBuf_51" SITE "R103C60D" ; +UGROUP "ff_en_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_51" SITE "R102C83D" ; +# +UGROUP "FC_52" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_52" SITE "R111C58D" ; +UGROUP "hitBuf_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_52_hit_mux_ch; +LOCATE UGROUP "hitBuf_52" SITE "R112C60D" ; +UGROUP "ff_en_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_52" SITE "R111C83D" ; +# +UGROUP "FC_53" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_53" SITE "R66C2D" ; +UGROUP "hitBuf_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_53_hit_mux_ch; +LOCATE UGROUP "hitBuf_53" SITE "R67C4D" ; +UGROUP "ff_en_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_53" SITE "R66C27D" ; +# +UGROUP "FC_54" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_54" SITE "R68C2D" ; +UGROUP "hitBuf_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_54_hit_mux_ch; +LOCATE UGROUP "hitBuf_54" SITE "R69C4D" ; +UGROUP "ff_en_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_54" SITE "R68C27D" ; +# +UGROUP "FC_55" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_55" SITE "R71C2D" ; +UGROUP "hitBuf_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_55_hit_mux_ch; +LOCATE UGROUP "hitBuf_55" SITE "R72C4D" ; +UGROUP "ff_en_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_55" SITE "R71C27D" ; +# +UGROUP "FC_56" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_56" SITE "R73C2D" ; +UGROUP "hitBuf_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_56_hit_mux_ch; +LOCATE UGROUP "hitBuf_56" SITE "R74C4D" ; +UGROUP "ff_en_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_56" SITE "R73C27D" ; +# +UGROUP "FC_57" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_57" SITE "R84C2D" ; +UGROUP "hitBuf_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_57_hit_mux_ch; +LOCATE UGROUP "hitBuf_57" SITE "R85C4D" ; +UGROUP "ff_en_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_57" SITE "R84C27D" ; +# +UGROUP "FC_58" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_58" SITE "R86C2D" ; +UGROUP "hitBuf_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_58_hit_mux_ch; +LOCATE UGROUP "hitBuf_58" SITE "R87C4D" ; +UGROUP "ff_en_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_58" SITE "R86C27D" ; +# +UGROUP "FC_59" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_59" SITE "R89C2D" ; +UGROUP "hitBuf_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_59_hit_mux_ch; +LOCATE UGROUP "hitBuf_59" SITE "R90C4D" ; +UGROUP "ff_en_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_59" SITE "R89C27D" ; +# +UGROUP "FC_60" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_60" SITE "R91C2D" ; +UGROUP "hitBuf_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_60_hit_mux_ch; +LOCATE UGROUP "hitBuf_60" SITE "R92C4D" ; +UGROUP "ff_en_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_60" SITE "R91C27D" ; +# +UGROUP "FC_61" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_61" SITE "R102C2D" ; +UGROUP "hitBuf_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_61_hit_mux_ch; +LOCATE UGROUP "hitBuf_61" SITE "R103C4D" ; +UGROUP "ff_en_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_61" SITE "R102C27D" ; +# +UGROUP "FC_62" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_62" SITE "R104C2D" ; +UGROUP "hitBuf_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_62_hit_mux_ch; +LOCATE UGROUP "hitBuf_62" SITE "R105C4D" ; +UGROUP "ff_en_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_62" SITE "R104C27D" ; +# +UGROUP "FC_63" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_63" SITE "R111C2D" ; +UGROUP "hitBuf_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_63_hit_mux_ch; +LOCATE UGROUP "hitBuf_63" SITE "R112C4D" ; +UGROUP "ff_en_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_63" SITE "R111C27D" ; +# +UGROUP "FC_64" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_64" SITE "R113C2D" ; +UGROUP "hitBuf_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_64_hit_mux_ch; +LOCATE UGROUP "hitBuf_64" SITE "R114C4D" ; +UGROUP "ff_en_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_64" SITE "R113C27D" ; + + +############################################################################## +## CHANNEL PLACEMENTS ## +############################################################################## +UGROUP "EF_ref" BBOX 16 52 + BLKNAME THE_TDC/ReferenceChannel/Channel200 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200 + BLKNAME THE_TDC/ReferenceChannel/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_1_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_2_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_3_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[0] + BLKNAME THE_TDC/trig_win_end_tdc_i[1] + BLKNAME THE_TDC/trig_win_end_tdc_i[2] + BLKNAME THE_TDC/trig_win_end_tdc_i[3] +; +LOCATE UGROUP "EF_ref" SITE "R8C130D" ; + +UGROUP "EF_4" BBOX 10 52 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_5_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[4] + BLKNAME THE_TDC/trig_win_end_tdc_i[5] +; +LOCATE UGROUP "EF_4" SITE "R24C130D" ; + +UGROUP "EF_6" BBOX 17 52 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_7_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_8_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_9_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[6] + BLKNAME THE_TDC/trig_win_end_tdc_i[7] + BLKNAME THE_TDC/trig_win_end_tdc_i[8] + BLKNAME THE_TDC/trig_win_end_tdc_i[9] +; +LOCATE UGROUP "EF_6" SITE "R35C130D" ; + +UGROUP "EF_10" BBOX 17 52 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_11_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_17_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_18_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[10] + BLKNAME THE_TDC/trig_win_end_tdc_i[11] + BLKNAME THE_TDC/trig_win_end_tdc_i[17] + BLKNAME THE_TDC/trig_win_end_tdc_i[18] +; +LOCATE UGROUP "EF_10" SITE "R53C130D" ; + +UGROUP "EF_12" BBOX 16 52 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_13_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_33_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_34_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[12] + BLKNAME THE_TDC/trig_win_end_tdc_i[13] + BLKNAME THE_TDC/trig_win_end_tdc_i[33] + BLKNAME THE_TDC/trig_win_end_tdc_i[34] +; +LOCATE UGROUP "EF_12" SITE "R8C57D" ; + +UGROUP "EF_14" BBOX 10 52 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_35_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[14] + BLKNAME THE_TDC/trig_win_end_tdc_i[35] +; +LOCATE UGROUP "EF_14" SITE "R24C57D" ; + +UGROUP "EF_15" BBOX 17 52 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_16_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_36_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_37_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[15] + BLKNAME THE_TDC/trig_win_end_tdc_i[16] + BLKNAME THE_TDC/trig_win_end_tdc_i[36] + BLKNAME THE_TDC/trig_win_end_tdc_i[37] +; +LOCATE UGROUP "EF_15" SITE "R35C57D" ; + +UGROUP "EF_19" BBOX 17 52 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_20_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_21_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_22_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[19] + BLKNAME THE_TDC/trig_win_end_tdc_i[20] + BLKNAME THE_TDC/trig_win_end_tdc_i[21] + BLKNAME THE_TDC/trig_win_end_tdc_i[22] +; +LOCATE UGROUP "EF_19" SITE "R71C130D" ; + +UGROUP "EF_23" BBOX 16 52 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_24_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_25_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_26_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[23] + BLKNAME THE_TDC/trig_win_end_tdc_i[24] + BLKNAME THE_TDC/trig_win_end_tdc_i[25] + BLKNAME THE_TDC/trig_win_end_tdc_i[26] +; +LOCATE UGROUP "EF_23" SITE "R89C130D" ; + +UGROUP "EF_27" BBOX 10 52 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_28_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[27] + BLKNAME THE_TDC/trig_win_end_tdc_i[28] +; +LOCATE UGROUP "EF_27" SITE "R105C130D" ; + +UGROUP "EF_29" BBOX 16 52 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_30_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_50_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_51_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[29] + BLKNAME THE_TDC/trig_win_end_tdc_i[30] + BLKNAME THE_TDC/trig_win_end_tdc_i[50] + BLKNAME THE_TDC/trig_win_end_tdc_i[51]; +LOCATE UGROUP "EF_29" SITE "R89C57D" ; + +UGROUP "EF_31" BBOX 10 52 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_52_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[31] + BLKNAME THE_TDC/trig_win_end_tdc_i[52] +; +LOCATE UGROUP "EF_31" SITE "R105C57D" ; + +UGROUP "EF_32" BBOX 10 24 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[32] +; +LOCATE UGROUP "EF_32" SITE "R78C71D" ; + +UGROUP "EF_38" BBOX 16 52 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_39_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_40_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_41_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[38] + BLKNAME THE_TDC/trig_win_end_tdc_i[39] + BLKNAME THE_TDC/trig_win_end_tdc_i[40] + BLKNAME THE_TDC/trig_win_end_tdc_i[41] +; +LOCATE UGROUP "EF_38" SITE "R8C2D" ; + +UGROUP "EF_42" BBOX 10 52 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_43_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[42] + BLKNAME THE_TDC/trig_win_end_tdc_i[43] +; +LOCATE UGROUP "EF_42" SITE "R24C2D" ; + +UGROUP "EF_44" BBOX 17 52 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_45_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_46_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_47_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[44] + BLKNAME THE_TDC/trig_win_end_tdc_i[45] + BLKNAME THE_TDC/trig_win_end_tdc_i[46] + BLKNAME THE_TDC/trig_win_end_tdc_i[47] +; +LOCATE UGROUP "EF_44" SITE "R35C2D" ; + +UGROUP "EF_48" BBOX 17 52 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_49_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_53_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_54_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[48] + BLKNAME THE_TDC/trig_win_end_tdc_i[49] + BLKNAME THE_TDC/trig_win_end_tdc_i[53] + BLKNAME THE_TDC/trig_win_end_tdc_i[54] +; +LOCATE UGROUP "EF_48" SITE "R53C2D" ; + +UGROUP "EF_55" BBOX 17 52 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_56_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_57_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_58_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[55] + BLKNAME THE_TDC/trig_win_end_tdc_i[56] + BLKNAME THE_TDC/trig_win_end_tdc_i[57] + BLKNAME THE_TDC/trig_win_end_tdc_i[58] +; +LOCATE UGROUP "EF_55" SITE "R71C2D" ; + +UGROUP "EF_59" BBOX 16 52 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_60_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_61_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_62_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[59] + BLKNAME THE_TDC/trig_win_end_tdc_i[60] + BLKNAME THE_TDC/trig_win_end_tdc_i[61] + BLKNAME THE_TDC/trig_win_end_tdc_i[62] +; +LOCATE UGROUP "EF_59" SITE "R89C2D" ; + +UGROUP "EF_63" BBOX 10 52 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/GEN_Channels_64_Channels/Buffer_64_The_Buffer + BLKNAME THE_TDC/trig_win_end_tdc_i[63] + BLKNAME THE_TDC/trig_win_end_tdc_i[64] +; +LOCATE UGROUP "EF_63" SITE "R105C2D" ; + +############################################################################# +## Stretcher +############################################################################# +UGROUP "Stretcher_1_4_A" BBOX 2 2 + BLKNAME THE_TDC/GEN_HitBlock.1.gen_double.Stretcher_1/pulse_d1_RNO + BLKNAME THE_TDC/GEN_HitBlock.1.gen_double.Stretcher_1/pulse_d3_RNO + BLKNAME THE_TDC/GEN_HitBlock.2.gen_double.Stretcher_1/pulse_d1_RNO + BLKNAME THE_TDC/GEN_HitBlock.2.gen_double.Stretcher_1/pulse_d3_RNO + BLKNAME THE_TDC/GEN_HitBlock.3.gen_double.Stretcher_1/pulse_d1_RNO + BLKNAME THE_TDC/GEN_HitBlock.3.gen_double.Stretcher_1/pulse_d3_RNO + BLKNAME THE_TDC/GEN_HitBlock.4.gen_double.Stretcher_1/pulse_d1_RNO + BLKNAME THE_TDC/GEN_HitBlock.4.gen_double.Stretcher_1/pulse_d3_RNO +; +LOCATE UGROUP "Stretcher_1_4_A" SITE "R122C180D"; +UGROUP "Stretcher_1_4_B" BBOX 2 2 + BLKNAME THE_TDC/GEN_HitBlock.1.gen_double.Stretcher_1/pulse_d2_RNO + BLKNAME THE_TDC/GEN_HitBlock.1.gen_double.Stretcher_1/pulse_d4_RNO + BLKNAME THE_TDC/GEN_HitBlock.2.gen_double.Stretcher_1/pulse_d2_RNO + BLKNAME THE_TDC/GEN_HitBlock.2.gen_double.Stretcher_1/pulse_d4_RNO + BLKNAME THE_TDC/GEN_HitBlock.3.gen_double.Stretcher_1/pulse_d2_RNO + BLKNAME THE_TDC/GEN_HitBlock.3.gen_double.Stretcher_1/pulse_d4_RNO + BLKNAME THE_TDC/GEN_HitBlock.4.gen_double.Stretcher_1/pulse_d2_RNO + BLKNAME THE_TDC/GEN_HitBlock.4.gen_double.Stretcher_1/pulse_d4_RNO +; +LOCATE UGROUP "Stretcher_1_4_B" SITE "R2C2D"; + +UGROUP "Stretcher_5_8_A" BBOX 2 2 + BLKNAME THE_TDC/GEN_HitBlock.5.gen_double.Stretcher_1/pulse_d1_RNO + BLKNAME THE_TDC/GEN_HitBlock.5.gen_double.Stretcher_1/pulse_d3_RNO + BLKNAME THE_TDC/GEN_HitBlock.6.gen_double.Stretcher_1/pulse_d1_RNO + BLKNAME THE_TDC/GEN_HitBlock.6.gen_double.Stretcher_1/pulse_d3_RNO + BLKNAME THE_TDC/GEN_HitBlock.7.gen_double.Stretcher_1/pulse_d1_RNO + BLKNAME THE_TDC/GEN_HitBlock.7.gen_double.Stretcher_1/pulse_d3_RNO + BLKNAME THE_TDC/GEN_HitBlock.8.gen_double.Stretcher_1/pulse_d1_RNO + BLKNAME THE_TDC/GEN_HitBlock.8.gen_double.Stretcher_1/pulse_d3_RNO +; +LOCATE UGROUP "Stretcher_5_8_A" SITE "R122C180D"; +UGROUP "Stretcher_5_8_B" BBOX 2 2 + BLKNAME THE_TDC/GEN_HitBlock.5.gen_double.Stretcher_1/pulse_d2_RNO + BLKNAME THE_TDC/GEN_HitBlock.5.gen_double.Stretcher_1/pulse_d4_RNO + BLKNAME THE_TDC/GEN_HitBlock.6.gen_double.Stretcher_1/pulse_d2_RNO + BLKNAME THE_TDC/GEN_HitBlock.6.gen_double.Stretcher_1/pulse_d4_RNO + BLKNAME THE_TDC/GEN_HitBlock.7.gen_double.Stretcher_1/pulse_d2_RNO + BLKNAME THE_TDC/GEN_HitBlock.7.gen_double.Stretcher_1/pulse_d4_RNO + BLKNAME THE_TDC/GEN_HitBlock.8.gen_double.Stretcher_1/pulse_d2_RNO + BLKNAME THE_TDC/GEN_HitBlock.8.gen_double.Stretcher_1/pulse_d4_RNO +; +LOCATE UGROUP "Stretcher_5_8_B" SITE "R2C2D"; + +#PRIORITIZE NET "THE_TDC/GEN_HitBlock*gen_double.Stretcher_1/pulse_d*" 0; +############################################################################# +## Coarse counter register placement +############################################################################# + +UGROUP "UR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter.1.TheCoarseCounter; +LOCATE UGROUP "UR_Coarse_Counter" SITE "R36C134D" ; +UGROUP "LR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_2_TheCoarseCounter; +LOCATE UGROUP "LR_Coarse_Counter" SITE R85C134D; +UGROUP "UL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_3_TheCoarseCounter; +LOCATE UGROUP "UL_Coarse_Counter" SITE R36C50D; +UGROUP "LL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_4_TheCoarseCounter; +LOCATE UGROUP "LL_Coarse_Counter" SITE R85C50D; +UGROUP "TheCounters" + BLKNAME THE_TDC/GenCoarseCounter_0_TheCoarseCounter + BLKNAME THE_TDC/TheEpochCounter; +#LOCATE UGROUP "TheCounters" REGION REGION_READOUT; + + + +############################################################################# +## Other Logic Placements +############################################################################# + +UGROUP "BusHandlers" + BLKNAME THE_TDC/TheHitCounterBus + BLKNAME THE_TDC/TheStatusRegistersBus +# BLKNAME THE_TDC/TheLostHitBus +# BLKNAME THE_TDC/TheEncoderStartBus +# BLKNAME THE_TDC/TheEncoderFinishedBus +; +LOCATE UGROUP "BusHandlers" REGION "REGION_TRBNET"; +LOCATE PGROUP "BusHandlers" REGION "REGION_TRBNET"; + +UGROUP "TheTdcReadout" #BBOX 35 57 + BLKNAME THE_TDC/TheReadout + ; +#LOCATE UGROUP "TheTdcReadout" SITE "R53C53D"; + +UGROUP "TheTriggerHandler" + BLKNAME THE_TDC/TheTriggerHandler + ; +LOCATE UGROUP "TheTriggerHandler" SITE "R65C80D"; diff --git a/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf.nogroup b/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf.nogroup new file mode 100644 index 0000000..ac310c6 --- /dev/null +++ b/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf.nogroup @@ -0,0 +1,671 @@ +################################################################# +# TDC Constraints +################################################################# +############################################################################## +## REFERENCE CHANNEL PLACEMENT ## +############################################################################## +UGROUP "Ref_Ch" BBOX 1 51 + BLKNAME THE_TDC/ReferenceChannel/Channel200/SimAdderNo_FC; +LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; +UGROUP "hitBuf_ref" BBOX 1 1 + BLKNAME THE_TDC/hit_mux_ref; +LOCATE UGROUP "hitBuf_ref" SITE "R9C133D" ; +UGROUP "Ref_ff_en" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; + +############################################################################## +## DELAY LINE and HIT BUFFER PLACEMENTS ## +############################################################################## +UGROUP "FC_1" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_1" SITE "R10C131D" ; +UGROUP "hitBuf_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_1_hit_mux_ch; +LOCATE UGROUP "hitBuf_1" SITE "R11C133D" ; +UGROUP "ff_en_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_1" SITE "R10C156D" ; +# +UGROUP "FC_2" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_2" SITE "R21C131D" ; +UGROUP "hitBuf_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_2_hit_mux_ch; +LOCATE UGROUP "hitBuf_2" SITE "R22C133D" ; +UGROUP "ff_en_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_2" SITE "R21C156D" ; +# +UGROUP "FC_3" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_3" SITE "R23C131D" ; +UGROUP "hitBuf_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_3_hit_mux_ch; +LOCATE UGROUP "hitBuf_3" SITE "R24C133D" ; +UGROUP "ff_en_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_3" SITE "R23C156D" ; +# +UGROUP "FC_4" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_4" SITE "R30C131D" ; +UGROUP "hitBuf_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_4_hit_mux_ch; +LOCATE UGROUP "hitBuf_4" SITE "R31C133D" ; +UGROUP "ff_en_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_4" SITE "R30C156D" ; +# +UGROUP "FC_5" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_5" SITE "R32C131D" ; +UGROUP "hitBuf_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_5_hit_mux_ch; +LOCATE UGROUP "hitBuf_5" SITE "R33C133D" ; +UGROUP "ff_en_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_5" SITE "R32C156D" ; +# +UGROUP "FC_6" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_6" SITE "R35C131D" ; +UGROUP "hitBuf_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_6_hit_mux_ch; +LOCATE UGROUP "hitBuf_6" SITE "R36C133D" ; +UGROUP "ff_en_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_6" SITE "R35C156D" ; +# +UGROUP "FC_7" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_7" SITE "R37C131D" ; +UGROUP "hitBuf_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_7_hit_mux_ch; +LOCATE UGROUP "hitBuf_7" SITE "R38C133D" ; +UGROUP "ff_en_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_7" SITE "R37C156D" ; +# +UGROUP "FC_8" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_8" SITE "R48C131D" ; +UGROUP "hitBuf_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_8_hit_mux_ch; +LOCATE UGROUP "hitBuf_8" SITE "R49C133D" ; +UGROUP "ff_en_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_8" SITE "R48C156D" ; +# +UGROUP "FC_9" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_9" SITE "R50C131D" ; +UGROUP "hitBuf_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_9_hit_mux_ch; +LOCATE UGROUP "hitBuf_9" SITE "R51C133D" ; +UGROUP "ff_en_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_9" SITE "R50C156D" ; +# +UGROUP "FC_10" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_10" SITE "R53C131D" ; +UGROUP "hitBuf_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_10_hit_mux_ch; +LOCATE UGROUP "hitBuf_10" SITE "R54C133D" ; +UGROUP "ff_en_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_10" SITE "R53C156D" ; +# +UGROUP "FC_11" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_11" SITE "R55C131D" ; +UGROUP "hitBuf_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_11_hit_mux_ch; +LOCATE UGROUP "hitBuf_11" SITE "R56C133D" ; +UGROUP "ff_en_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_11" SITE "R55C156D" ; +# +UGROUP "FC_12" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_12" SITE "R10C58D" ; +UGROUP "hitBuf_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_12_hit_mux_ch; +LOCATE UGROUP "hitBuf_12" SITE "R11C60D" ; +UGROUP "ff_en_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_12" SITE "R10C83D" ; +# +UGROUP "FC_13" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_13" SITE "R23C58D" ; +UGROUP "hitBuf_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_13_hit_mux_ch; +LOCATE UGROUP "hitBuf_13" SITE "R24C60D" ; +UGROUP "ff_en_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_13" SITE "R23C83D" ; +# +UGROUP "FC_14" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_14" SITE "R32C58D" ; +UGROUP "hitBuf_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_14_hit_mux_ch; +LOCATE UGROUP "hitBuf_14" SITE "R33C60D" ; +UGROUP "ff_en_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_14" SITE "R32C83D" ; +# +UGROUP "FC_15" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_15" SITE "R37C58D" ; +UGROUP "hitBuf_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_15_hit_mux_ch; +LOCATE UGROUP "hitBuf_15" SITE "R38C60D" ; +UGROUP "ff_en_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_15" SITE "R37C83D" ; +# +UGROUP "FC_16" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_16" SITE "R50C58D" ; +UGROUP "hitBuf_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_16_hit_mux_ch; +LOCATE UGROUP "hitBuf_16" SITE "R51C60D" ; +UGROUP "ff_en_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_16" SITE "R50C83D" ; +# +UGROUP "FC_17" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_17" SITE "R66C131D" ; +UGROUP "hitBuf_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_17_hit_mux_ch; +LOCATE UGROUP "hitBuf_17" SITE "R67C133D" ; +UGROUP "ff_en_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_17" SITE "R66C156D" ; +# +UGROUP "FC_18" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_18" SITE "R68C131D" ; +UGROUP "hitBuf_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_18_hit_mux_ch; +LOCATE UGROUP "hitBuf_18" SITE "R69C133D" ; +UGROUP "ff_en_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_18" SITE "R68C156D" ; +# +UGROUP "FC_19" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_19" SITE "R71C131D" ; +UGROUP "hitBuf_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_19_hit_mux_ch; +LOCATE UGROUP "hitBuf_19" SITE "R72C133D" ; +UGROUP "ff_en_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_19" SITE "R71C156D" ; +# +UGROUP "FC_20" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_20" SITE "R73C131D" ; +UGROUP "hitBuf_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_20_hit_mux_ch; +LOCATE UGROUP "hitBuf_20" SITE "R74C133D" ; +UGROUP "ff_en_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_20" SITE "R73C156D" ; +# +UGROUP "FC_21" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_21" SITE "R84C131D" ; +UGROUP "hitBuf_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_21_hit_mux_ch; +LOCATE UGROUP "hitBuf_21" SITE "R85C133D" ; +UGROUP "ff_en_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_21" SITE "R84C156D" ; +# +UGROUP "FC_22" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_22" SITE "R86C131D" ; +UGROUP "hitBuf_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_22_hit_mux_ch; +LOCATE UGROUP "hitBuf_22" SITE "R87C133D" ; +UGROUP "ff_en_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_22" SITE "R86C156D" ; +# +UGROUP "FC_23" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_23" SITE "R89C131D" ; +UGROUP "hitBuf_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_23_hit_mux_ch; +LOCATE UGROUP "hitBuf_23" SITE "R90C133D" ; +UGROUP "ff_en_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_23" SITE "R89C156D" ; +# +UGROUP "FC_24" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_24" SITE "R91C131D" ; +UGROUP "hitBuf_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_24_hit_mux_ch; +LOCATE UGROUP "hitBuf_24" SITE "R92C133D" ; +UGROUP "ff_en_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_24" SITE "R91C156D" ; +# +UGROUP "FC_25" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_25" SITE "R102C131D" ; +UGROUP "hitBuf_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_25_hit_mux_ch; +LOCATE UGROUP "hitBuf_25" SITE "R103C133D" ; +UGROUP "ff_en_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_25" SITE "R102C156D" ; +# +UGROUP "FC_26" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_26" SITE "R104C131D" ; +UGROUP "hitBuf_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_26_hit_mux_ch; +LOCATE UGROUP "hitBuf_26" SITE "R105C133D" ; +UGROUP "ff_en_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_26" SITE "R104C156D" ; +# +UGROUP "FC_27" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_27" SITE "R111C131D" ; +UGROUP "hitBuf_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_27_hit_mux_ch; +LOCATE UGROUP "hitBuf_27" SITE "R112C133D" ; +UGROUP "ff_en_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_27" SITE "R111C156D" ; +# +UGROUP "FC_28" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_28" SITE "R113C131D" ; +UGROUP "hitBuf_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_28_hit_mux_ch; +LOCATE UGROUP "hitBuf_28" SITE "R114C133D" ; +UGROUP "ff_en_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_28" SITE "R113C156D" ; +# +UGROUP "FC_29" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_29" SITE "R91C58D" ; +UGROUP "hitBuf_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_29_hit_mux_ch; +LOCATE UGROUP "hitBuf_29" SITE "R92C60D" ; +UGROUP "ff_en_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_29" SITE "R91C83D" ; +# +UGROUP "FC_30" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_30" SITE "R104C58D" ; +UGROUP "hitBuf_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_30_hit_mux_ch; +LOCATE UGROUP "hitBuf_30" SITE "R105C60D" ; +UGROUP "ff_en_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_30" SITE "R104C83D" ; +# +UGROUP "FC_31" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_31" SITE "R113C58D" ; +UGROUP "hitBuf_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_31_hit_mux_ch; +LOCATE UGROUP "hitBuf_31" SITE "R114C60D" ; +UGROUP "ff_en_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_31" SITE "R113C83D" ; +# +UGROUP "FC_32" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_32" SITE "R84C58D" ; +UGROUP "hitBuf_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_32_hit_mux_ch; +LOCATE UGROUP "hitBuf_32" SITE "R85C60D" ; +UGROUP "ff_en_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_32" SITE "R84C83D" ; +# +UGROUP "FC_33" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_33" SITE "R8C58D" ; +UGROUP "hitBuf_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_33_hit_mux_ch; +LOCATE UGROUP "hitBuf_33" SITE "R9C60D" ; +UGROUP "ff_en_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_33" SITE "R8C83D" ; +# +UGROUP "FC_34" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_34" SITE "R21C58D" ; +UGROUP "hitBuf_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_34_hit_mux_ch; +LOCATE UGROUP "hitBuf_34" SITE "R22C60D" ; +UGROUP "ff_en_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_34" SITE "R21C83D" ; +# +UGROUP "FC_35" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_35" SITE "R30C58D" ; +UGROUP "hitBuf_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_35_hit_mux_ch; +LOCATE UGROUP "hitBuf_35" SITE "R31C60D" ; +UGROUP "ff_en_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_35" SITE "R30C83D" ; +# +UGROUP "FC_36" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_36" SITE "R35C58D" ; +UGROUP "hitBuf_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_36_hit_mux_ch; +LOCATE UGROUP "hitBuf_36" SITE "R36C60D" ; +UGROUP "ff_en_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_36" SITE "R35C83D" ; +# +UGROUP "FC_37" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_37" SITE "R48C58D" ; +UGROUP "hitBuf_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_37_hit_mux_ch; +LOCATE UGROUP "hitBuf_37" SITE "R49C60D" ; +UGROUP "ff_en_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_37" SITE "R48C83D" ; +# +UGROUP "FC_38" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_38" SITE "R8C2D" ; +UGROUP "hitBuf_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_38_hit_mux_ch; +LOCATE UGROUP "hitBuf_38" SITE "R9C4D" ; +UGROUP "ff_en_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_38" SITE "R8C27D" ; +# +UGROUP "FC_39" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_39" SITE "R10C2D" ; +UGROUP "hitBuf_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_39_hit_mux_ch; +LOCATE UGROUP "hitBuf_39" SITE "R11C4D" ; +UGROUP "ff_en_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_39" SITE "R10C27D" ; +# +UGROUP "FC_40" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_40" SITE "R21C2D" ; +UGROUP "hitBuf_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_40_hit_mux_ch; +LOCATE UGROUP "hitBuf_40" SITE "R22C4D" ; +UGROUP "ff_en_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_40" SITE "R21C27D" ; +# +UGROUP "FC_41" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_41" SITE "R23C2D" ; +UGROUP "hitBuf_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_41_hit_mux_ch; +LOCATE UGROUP "hitBuf_41" SITE "R24C4D" ; +UGROUP "ff_en_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_41" SITE "R23C27D" ; +# +UGROUP "FC_42" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_42" SITE "R30C2D" ; +UGROUP "hitBuf_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_42_hit_mux_ch; +LOCATE UGROUP "hitBuf_42" SITE "R31C4D" ; +UGROUP "ff_en_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_42" SITE "R30C27D" ; +# +UGROUP "FC_43" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_43" SITE "R32C2D" ; +UGROUP "hitBuf_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_43_hit_mux_ch; +LOCATE UGROUP "hitBuf_43" SITE "R33C4D" ; +UGROUP "ff_en_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_43" SITE "R32C27D" ; +# +UGROUP "FC_44" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_44" SITE "R35C2D" ; +UGROUP "hitBuf_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_44_hit_mux_ch; +LOCATE UGROUP "hitBuf_44" SITE "R36C4D" ; +UGROUP "ff_en_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_44" SITE "R35C27D" ; +# +UGROUP "FC_45" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_45" SITE "R37C2D" ; +UGROUP "hitBuf_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_45_hit_mux_ch; +LOCATE UGROUP "hitBuf_45" SITE "R38C4D" ; +UGROUP "ff_en_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_45" SITE "R37C27D" ; +# +UGROUP "FC_46" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_46" SITE "R48C2D" ; +UGROUP "hitBuf_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_46_hit_mux_ch; +LOCATE UGROUP "hitBuf_46" SITE "R49C4D" ; +UGROUP "ff_en_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_46" SITE "R48C27D" ; +# +UGROUP "FC_47" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_47" SITE "R50C2D" ; +UGROUP "hitBuf_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_47_hit_mux_ch; +LOCATE UGROUP "hitBuf_47" SITE "R51C4D" ; +UGROUP "ff_en_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_47" SITE "R50C27D" ; +# +UGROUP "FC_48" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_48" SITE "R53C2D" ; +UGROUP "hitBuf_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_48_hit_mux_ch; +LOCATE UGROUP "hitBuf_48" SITE "R54C4D" ; +UGROUP "ff_en_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_48" SITE "R53C27D" ; +# +UGROUP "FC_49" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_49" SITE "R55C2D" ; +UGROUP "hitBuf_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_49_hit_mux_ch; +LOCATE UGROUP "hitBuf_49" SITE "R56C4D" ; +UGROUP "ff_en_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_49" SITE "R55C27D" ; +# +UGROUP "FC_50" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_50" SITE "R89C58D" ; +UGROUP "hitBuf_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_50_hit_mux_ch; +LOCATE UGROUP "hitBuf_50" SITE "R90C60D" ; +UGROUP "ff_en_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_50" SITE "R89C83D" ; +# +UGROUP "FC_51" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_51" SITE "R102C58D" ; +UGROUP "hitBuf_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_51_hit_mux_ch; +LOCATE UGROUP "hitBuf_51" SITE "R103C60D" ; +UGROUP "ff_en_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_51" SITE "R102C83D" ; +# +UGROUP "FC_52" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_52" SITE "R111C58D" ; +UGROUP "hitBuf_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_52_hit_mux_ch; +LOCATE UGROUP "hitBuf_52" SITE "R112C60D" ; +UGROUP "ff_en_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_52" SITE "R111C83D" ; +# +UGROUP "FC_53" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_53" SITE "R66C2D" ; +UGROUP "hitBuf_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_53_hit_mux_ch; +LOCATE UGROUP "hitBuf_53" SITE "R67C4D" ; +UGROUP "ff_en_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_53" SITE "R66C27D" ; +# +UGROUP "FC_54" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_54" SITE "R68C2D" ; +UGROUP "hitBuf_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_54_hit_mux_ch; +LOCATE UGROUP "hitBuf_54" SITE "R69C4D" ; +UGROUP "ff_en_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_54" SITE "R68C27D" ; +# +UGROUP "FC_55" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_55" SITE "R71C2D" ; +UGROUP "hitBuf_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_55_hit_mux_ch; +LOCATE UGROUP "hitBuf_55" SITE "R72C4D" ; +UGROUP "ff_en_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_55" SITE "R71C27D" ; +# +UGROUP "FC_56" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_56" SITE "R73C2D" ; +UGROUP "hitBuf_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_56_hit_mux_ch; +LOCATE UGROUP "hitBuf_56" SITE "R74C4D" ; +UGROUP "ff_en_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_56" SITE "R73C27D" ; +# +UGROUP "FC_57" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_57" SITE "R84C2D" ; +UGROUP "hitBuf_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_57_hit_mux_ch; +LOCATE UGROUP "hitBuf_57" SITE "R85C4D" ; +UGROUP "ff_en_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_57" SITE "R84C27D" ; +# +UGROUP "FC_58" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_58" SITE "R86C2D" ; +UGROUP "hitBuf_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_58_hit_mux_ch; +LOCATE UGROUP "hitBuf_58" SITE "R87C4D" ; +UGROUP "ff_en_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_58" SITE "R86C27D" ; +# +UGROUP "FC_59" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_59" SITE "R89C2D" ; +UGROUP "hitBuf_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_59_hit_mux_ch; +LOCATE UGROUP "hitBuf_59" SITE "R90C4D" ; +UGROUP "ff_en_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_59" SITE "R89C27D" ; +# +UGROUP "FC_60" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_60" SITE "R91C2D" ; +UGROUP "hitBuf_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_60_hit_mux_ch; +LOCATE UGROUP "hitBuf_60" SITE "R92C4D" ; +UGROUP "ff_en_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_60" SITE "R91C27D" ; +# +UGROUP "FC_61" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_61" SITE "R102C2D" ; +UGROUP "hitBuf_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_61_hit_mux_ch; +LOCATE UGROUP "hitBuf_61" SITE "R103C4D" ; +UGROUP "ff_en_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_61" SITE "R102C27D" ; +# +UGROUP "FC_62" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_62" SITE "R104C2D" ; +UGROUP "hitBuf_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_62_hit_mux_ch; +LOCATE UGROUP "hitBuf_62" SITE "R105C4D" ; +UGROUP "ff_en_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_62" SITE "R104C27D" ; +# +UGROUP "FC_63" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_63" SITE "R111C2D" ; +UGROUP "hitBuf_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_63_hit_mux_ch; +LOCATE UGROUP "hitBuf_63" SITE "R112C4D" ; +UGROUP "ff_en_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_63" SITE "R111C27D" ; +# +UGROUP "FC_64" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_64" SITE "R113C2D" ; +UGROUP "hitBuf_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_64_hit_mux_ch; +LOCATE UGROUP "hitBuf_64" SITE "R114C4D" ; +UGROUP "ff_en_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_64" SITE "R113C27D" ; + + +############################################################################## +## CHANNEL PLACEMENTS ## +############################################################################## + +############################################################################# +## Coarse counter register placement +############################################################################# + +############################################################################# +## Other Logic Placements +############################################################################# diff --git a/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf.orig b/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf.orig new file mode 100644 index 0000000..c338ff1 --- /dev/null +++ b/tdc_releases/tdc_v2.0/tdc_constraints_64.lpf.orig @@ -0,0 +1,945 @@ +################################################################# +# TDC Constraints +################################################################# +############################################################################## +## REFERENCE CHANNEL PLACEMENT ## +############################################################################## +UGROUP "Ref_Ch" BBOX 1 51 + BLKNAME THE_TDC/ReferenceChannel/Channel200/SimAdderNo_FC; +LOCATE UGROUP "Ref_Ch" SITE "R8C131D" ; +UGROUP "hitBuf_ref" BBOX 1 1 + BLKNAME THE_TDC/hit_mux_ref; +LOCATE UGROUP "hitBuf_ref" SITE "R9C133D" ; +UGROUP "Ref_ff_en" BBOX 1 1 + BLKNAME THE_TDC/ReferenceChannel/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; + +############################################################################## +## DELAY LINE and HIT BUFFER PLACEMENTS ## +############################################################################## +UGROUP "FC_1" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_1" SITE "R10C131D" ; +UGROUP "hitBuf_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_1_hit_mux_ch; +LOCATE UGROUP "hitBuf_1" SITE "R11C133D" ; +UGROUP "ff_en_1" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_1" SITE "R10C156D" ; +# +UGROUP "FC_2" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_2" SITE "R21C131D" ; +UGROUP "hitBuf_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_2_hit_mux_ch; +LOCATE UGROUP "hitBuf_2" SITE "R22C133D" ; +UGROUP "ff_en_2" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_2" SITE "R21C156D" ; +# +UGROUP "FC_3" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_3" SITE "R23C131D" ; +UGROUP "hitBuf_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_3_hit_mux_ch; +LOCATE UGROUP "hitBuf_3" SITE "R24C133D" ; +UGROUP "ff_en_3" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_3" SITE "R23C156D" ; +# +UGROUP "FC_4" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_4" SITE "R30C131D" ; +UGROUP "hitBuf_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_4_hit_mux_ch; +LOCATE UGROUP "hitBuf_4" SITE "R31C133D" ; +UGROUP "ff_en_4" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_4" SITE "R30C156D" ; +# +UGROUP "FC_5" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_5" SITE "R32C131D" ; +UGROUP "hitBuf_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_5_hit_mux_ch; +LOCATE UGROUP "hitBuf_5" SITE "R33C133D" ; +UGROUP "ff_en_5" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_5" SITE "R32C156D" ; +# +UGROUP "FC_6" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_6" SITE "R35C131D" ; +UGROUP "hitBuf_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_6_hit_mux_ch; +LOCATE UGROUP "hitBuf_6" SITE "R36C133D" ; +UGROUP "ff_en_6" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_6" SITE "R35C156D" ; +# +UGROUP "FC_7" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_7" SITE "R37C131D" ; +UGROUP "hitBuf_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_7_hit_mux_ch; +LOCATE UGROUP "hitBuf_7" SITE "R38C133D" ; +UGROUP "ff_en_7" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_7" SITE "R37C156D" ; +# +UGROUP "FC_8" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_8" SITE "R48C131D" ; +UGROUP "hitBuf_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_8_hit_mux_ch; +LOCATE UGROUP "hitBuf_8" SITE "R49C133D" ; +UGROUP "ff_en_8" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_8" SITE "R48C156D" ; +# +UGROUP "FC_9" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_9" SITE "R50C131D" ; +UGROUP "hitBuf_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_9_hit_mux_ch; +LOCATE UGROUP "hitBuf_9" SITE "R51C133D" ; +UGROUP "ff_en_9" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_9" SITE "R50C156D" ; +# +UGROUP "FC_10" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_10" SITE "R53C131D" ; +UGROUP "hitBuf_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_10_hit_mux_ch; +LOCATE UGROUP "hitBuf_10" SITE "R54C133D" ; +UGROUP "ff_en_10" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_10" SITE "R53C156D" ; +# +UGROUP "FC_11" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_11" SITE "R55C131D" ; +UGROUP "hitBuf_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_11_hit_mux_ch; +LOCATE UGROUP "hitBuf_11" SITE "R56C133D" ; +UGROUP "ff_en_11" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_11" SITE "R55C156D" ; +# +UGROUP "FC_12" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_12" SITE "R10C58D" ; +UGROUP "hitBuf_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_12_hit_mux_ch; +LOCATE UGROUP "hitBuf_12" SITE "R11C60D" ; +UGROUP "ff_en_12" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_12" SITE "R10C83D" ; +# +UGROUP "FC_13" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_13" SITE "R23C58D" ; +UGROUP "hitBuf_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_13_hit_mux_ch; +LOCATE UGROUP "hitBuf_13" SITE "R24C60D" ; +UGROUP "ff_en_13" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_13" SITE "R23C83D" ; +# +UGROUP "FC_14" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_14" SITE "R32C58D" ; +UGROUP "hitBuf_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_14_hit_mux_ch; +LOCATE UGROUP "hitBuf_14" SITE "R33C60D" ; +UGROUP "ff_en_14" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_14" SITE "R32C83D" ; +# +UGROUP "FC_15" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_15" SITE "R37C58D" ; +UGROUP "hitBuf_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_15_hit_mux_ch; +LOCATE UGROUP "hitBuf_15" SITE "R38C60D" ; +UGROUP "ff_en_15" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_15" SITE "R37C83D" ; +# +UGROUP "FC_16" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_16" SITE "R50C58D" ; +UGROUP "hitBuf_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_16_hit_mux_ch; +LOCATE UGROUP "hitBuf_16" SITE "R51C60D" ; +UGROUP "ff_en_16" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_16" SITE "R50C83D" ; +# +UGROUP "FC_17" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_17" SITE "R66C131D" ; +UGROUP "hitBuf_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_17_hit_mux_ch; +LOCATE UGROUP "hitBuf_17" SITE "R67C133D" ; +UGROUP "ff_en_17" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_17" SITE "R66C156D" ; +# +UGROUP "FC_18" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_18" SITE "R68C131D" ; +UGROUP "hitBuf_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_18_hit_mux_ch; +LOCATE UGROUP "hitBuf_18" SITE "R69C133D" ; +UGROUP "ff_en_18" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_18" SITE "R68C156D" ; +# +UGROUP "FC_19" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_19" SITE "R71C131D" ; +UGROUP "hitBuf_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_19_hit_mux_ch; +LOCATE UGROUP "hitBuf_19" SITE "R72C133D" ; +UGROUP "ff_en_19" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_19" SITE "R71C156D" ; +# +UGROUP "FC_20" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_20" SITE "R73C131D" ; +UGROUP "hitBuf_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_20_hit_mux_ch; +LOCATE UGROUP "hitBuf_20" SITE "R74C133D" ; +UGROUP "ff_en_20" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_20" SITE "R73C156D" ; +# +UGROUP "FC_21" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_21" SITE "R84C131D" ; +UGROUP "hitBuf_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_21_hit_mux_ch; +LOCATE UGROUP "hitBuf_21" SITE "R85C133D" ; +UGROUP "ff_en_21" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_21" SITE "R84C156D" ; +# +UGROUP "FC_22" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_22" SITE "R86C131D" ; +UGROUP "hitBuf_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_22_hit_mux_ch; +LOCATE UGROUP "hitBuf_22" SITE "R87C133D" ; +UGROUP "ff_en_22" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_22" SITE "R86C156D" ; +# +UGROUP "FC_23" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_23" SITE "R89C131D" ; +UGROUP "hitBuf_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_23_hit_mux_ch; +LOCATE UGROUP "hitBuf_23" SITE "R90C133D" ; +UGROUP "ff_en_23" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_23" SITE "R89C156D" ; +# +UGROUP "FC_24" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_24" SITE "R91C131D" ; +UGROUP "hitBuf_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_24_hit_mux_ch; +LOCATE UGROUP "hitBuf_24" SITE "R92C133D" ; +UGROUP "ff_en_24" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_24" SITE "R91C156D" ; +# +UGROUP "FC_25" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_25" SITE "R102C131D" ; +UGROUP "hitBuf_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_25_hit_mux_ch; +LOCATE UGROUP "hitBuf_25" SITE "R103C133D" ; +UGROUP "ff_en_25" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_25" SITE "R102C156D" ; +# +UGROUP "FC_26" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_26" SITE "R104C131D" ; +UGROUP "hitBuf_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_26_hit_mux_ch; +LOCATE UGROUP "hitBuf_26" SITE "R105C133D" ; +UGROUP "ff_en_26" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_26" SITE "R104C156D" ; +# +UGROUP "FC_27" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_27" SITE "R111C131D" ; +UGROUP "hitBuf_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_27_hit_mux_ch; +LOCATE UGROUP "hitBuf_27" SITE "R112C133D" ; +UGROUP "ff_en_27" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_27" SITE "R111C156D" ; +# +UGROUP "FC_28" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_28" SITE "R113C131D" ; +UGROUP "hitBuf_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_28_hit_mux_ch; +LOCATE UGROUP "hitBuf_28" SITE "R114C133D" ; +UGROUP "ff_en_28" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_28" SITE "R113C156D" ; +# +UGROUP "FC_29" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_29" SITE "R91C58D" ; +UGROUP "hitBuf_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_29_hit_mux_ch; +LOCATE UGROUP "hitBuf_29" SITE "R92C60D" ; +UGROUP "ff_en_29" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_29" SITE "R91C83D" ; +# +UGROUP "FC_30" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_30" SITE "R104C58D" ; +UGROUP "hitBuf_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_30_hit_mux_ch; +LOCATE UGROUP "hitBuf_30" SITE "R105C60D" ; +UGROUP "ff_en_30" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_30" SITE "R104C83D" ; +# +UGROUP "FC_31" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_31" SITE "R113C58D" ; +UGROUP "hitBuf_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_31_hit_mux_ch; +LOCATE UGROUP "hitBuf_31" SITE "R114C60D" ; +UGROUP "ff_en_31" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_31" SITE "R113C83D" ; +# +UGROUP "FC_32" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_32" SITE "R84C58D" ; +UGROUP "hitBuf_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_32_hit_mux_ch; +LOCATE UGROUP "hitBuf_32" SITE "R85C60D" ; +UGROUP "ff_en_32" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_32" SITE "R84C83D" ; +# +UGROUP "FC_33" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_33" SITE "R8C58D" ; +UGROUP "hitBuf_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_33_hit_mux_ch; +LOCATE UGROUP "hitBuf_33" SITE "R9C60D" ; +UGROUP "ff_en_33" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_33" SITE "R8C83D" ; +# +UGROUP "FC_34" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_34" SITE "R21C58D" ; +UGROUP "hitBuf_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_34_hit_mux_ch; +LOCATE UGROUP "hitBuf_34" SITE "R22C60D" ; +UGROUP "ff_en_34" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_34" SITE "R21C83D" ; +# +UGROUP "FC_35" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_35" SITE "R30C58D" ; +UGROUP "hitBuf_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_35_hit_mux_ch; +LOCATE UGROUP "hitBuf_35" SITE "R31C60D" ; +UGROUP "ff_en_35" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_35" SITE "R30C83D" ; +# +UGROUP "FC_36" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_36" SITE "R35C58D" ; +UGROUP "hitBuf_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_36_hit_mux_ch; +LOCATE UGROUP "hitBuf_36" SITE "R36C60D" ; +UGROUP "ff_en_36" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_36" SITE "R35C83D" ; +# +UGROUP "FC_37" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_37" SITE "R48C58D" ; +UGROUP "hitBuf_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_37_hit_mux_ch; +LOCATE UGROUP "hitBuf_37" SITE "R49C60D" ; +UGROUP "ff_en_37" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_37" SITE "R48C83D" ; +# +UGROUP "FC_38" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_38" SITE "R8C2D" ; +UGROUP "hitBuf_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_38_hit_mux_ch; +LOCATE UGROUP "hitBuf_38" SITE "R9C4D" ; +UGROUP "ff_en_38" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_38" SITE "R8C27D" ; +# +UGROUP "FC_39" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_39" SITE "R10C2D" ; +UGROUP "hitBuf_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_39_hit_mux_ch; +LOCATE UGROUP "hitBuf_39" SITE "R11C4D" ; +UGROUP "ff_en_39" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_39" SITE "R10C27D" ; +# +UGROUP "FC_40" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_40" SITE "R21C2D" ; +UGROUP "hitBuf_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_40_hit_mux_ch; +LOCATE UGROUP "hitBuf_40" SITE "R22C4D" ; +UGROUP "ff_en_40" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_40" SITE "R21C27D" ; +# +UGROUP "FC_41" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_41" SITE "R23C2D" ; +UGROUP "hitBuf_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_41_hit_mux_ch; +LOCATE UGROUP "hitBuf_41" SITE "R24C4D" ; +UGROUP "ff_en_41" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_41" SITE "R23C27D" ; +# +UGROUP "FC_42" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_42" SITE "R30C2D" ; +UGROUP "hitBuf_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_42_hit_mux_ch; +LOCATE UGROUP "hitBuf_42" SITE "R31C4D" ; +UGROUP "ff_en_42" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_42" SITE "R30C27D" ; +# +UGROUP "FC_43" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_43" SITE "R32C2D" ; +UGROUP "hitBuf_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_43_hit_mux_ch; +LOCATE UGROUP "hitBuf_43" SITE "R33C4D" ; +UGROUP "ff_en_43" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_43" SITE "R32C27D" ; +# +UGROUP "FC_44" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_44" SITE "R35C2D" ; +UGROUP "hitBuf_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_44_hit_mux_ch; +LOCATE UGROUP "hitBuf_44" SITE "R36C4D" ; +UGROUP "ff_en_44" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_44" SITE "R35C27D" ; +# +UGROUP "FC_45" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_45" SITE "R37C2D" ; +UGROUP "hitBuf_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_45_hit_mux_ch; +LOCATE UGROUP "hitBuf_45" SITE "R38C4D" ; +UGROUP "ff_en_45" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_45" SITE "R37C27D" ; +# +UGROUP "FC_46" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_46" SITE "R48C2D" ; +UGROUP "hitBuf_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_46_hit_mux_ch; +LOCATE UGROUP "hitBuf_46" SITE "R49C4D" ; +UGROUP "ff_en_46" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_46" SITE "R48C27D" ; +# +UGROUP "FC_47" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_47" SITE "R50C2D" ; +UGROUP "hitBuf_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_47_hit_mux_ch; +LOCATE UGROUP "hitBuf_47" SITE "R51C4D" ; +UGROUP "ff_en_47" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_47" SITE "R50C27D" ; +# +UGROUP "FC_48" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_48" SITE "R53C2D" ; +UGROUP "hitBuf_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_48_hit_mux_ch; +LOCATE UGROUP "hitBuf_48" SITE "R54C4D" ; +UGROUP "ff_en_48" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_48" SITE "R53C27D" ; +# +UGROUP "FC_49" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_49" SITE "R55C2D" ; +UGROUP "hitBuf_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_49_hit_mux_ch; +LOCATE UGROUP "hitBuf_49" SITE "R56C4D" ; +UGROUP "ff_en_49" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_49" SITE "R55C27D" ; +# +UGROUP "FC_50" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_50" SITE "R89C58D" ; +UGROUP "hitBuf_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_50_hit_mux_ch; +LOCATE UGROUP "hitBuf_50" SITE "R90C60D" ; +UGROUP "ff_en_50" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_50" SITE "R89C83D" ; +# +UGROUP "FC_51" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_51" SITE "R102C58D" ; +UGROUP "hitBuf_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_51_hit_mux_ch; +LOCATE UGROUP "hitBuf_51" SITE "R103C60D" ; +UGROUP "ff_en_51" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_51" SITE "R102C83D" ; +# +UGROUP "FC_52" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_52" SITE "R111C58D" ; +UGROUP "hitBuf_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_52_hit_mux_ch; +LOCATE UGROUP "hitBuf_52" SITE "R112C60D" ; +UGROUP "ff_en_52" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_52" SITE "R111C83D" ; +# +UGROUP "FC_53" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_53" SITE "R66C2D" ; +UGROUP "hitBuf_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_53_hit_mux_ch; +LOCATE UGROUP "hitBuf_53" SITE "R67C4D" ; +UGROUP "ff_en_53" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_53" SITE "R66C27D" ; +# +UGROUP "FC_54" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_54" SITE "R68C2D" ; +UGROUP "hitBuf_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_54_hit_mux_ch; +LOCATE UGROUP "hitBuf_54" SITE "R69C4D" ; +UGROUP "ff_en_54" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_54" SITE "R68C27D" ; +# +UGROUP "FC_55" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_55" SITE "R71C2D" ; +UGROUP "hitBuf_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_55_hit_mux_ch; +LOCATE UGROUP "hitBuf_55" SITE "R72C4D" ; +UGROUP "ff_en_55" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_55" SITE "R71C27D" ; +# +UGROUP "FC_56" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_56" SITE "R73C2D" ; +UGROUP "hitBuf_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_56_hit_mux_ch; +LOCATE UGROUP "hitBuf_56" SITE "R74C4D" ; +UGROUP "ff_en_56" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_56" SITE "R73C27D" ; +# +UGROUP "FC_57" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_57" SITE "R84C2D" ; +UGROUP "hitBuf_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_57_hit_mux_ch; +LOCATE UGROUP "hitBuf_57" SITE "R85C4D" ; +UGROUP "ff_en_57" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_57" SITE "R84C27D" ; +# +UGROUP "FC_58" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_58" SITE "R86C2D" ; +UGROUP "hitBuf_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_58_hit_mux_ch; +LOCATE UGROUP "hitBuf_58" SITE "R87C4D" ; +UGROUP "ff_en_58" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_58" SITE "R86C27D" ; +# +UGROUP "FC_59" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_59" SITE "R89C2D" ; +UGROUP "hitBuf_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_59_hit_mux_ch; +LOCATE UGROUP "hitBuf_59" SITE "R90C4D" ; +UGROUP "ff_en_59" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_59" SITE "R89C27D" ; +# +UGROUP "FC_60" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_60" SITE "R91C2D" ; +UGROUP "hitBuf_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_60_hit_mux_ch; +LOCATE UGROUP "hitBuf_60" SITE "R92C4D" ; +UGROUP "ff_en_60" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_60" SITE "R91C27D" ; +# +UGROUP "FC_61" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_61" SITE "R102C2D" ; +UGROUP "hitBuf_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_61_hit_mux_ch; +LOCATE UGROUP "hitBuf_61" SITE "R103C4D" ; +UGROUP "ff_en_61" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_61" SITE "R102C27D" ; +# +UGROUP "FC_62" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_62" SITE "R104C2D" ; +UGROUP "hitBuf_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_62_hit_mux_ch; +LOCATE UGROUP "hitBuf_62" SITE "R105C4D" ; +UGROUP "ff_en_62" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_62" SITE "R104C27D" ; +# +UGROUP "FC_63" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_63" SITE "R111C2D" ; +UGROUP "hitBuf_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_63_hit_mux_ch; +LOCATE UGROUP "hitBuf_63" SITE "R112C4D" ; +UGROUP "ff_en_63" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_63" SITE "R111C27D" ; +# +UGROUP "FC_64" BBOX 1 51 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200/SimAdderNo_FC; +LOCATE UGROUP "FC_64" SITE "R113C2D" ; +UGROUP "hitBuf_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_hit_mux_64_hit_mux_ch; +LOCATE UGROUP "hitBuf_64" SITE "R114C4D" ; +UGROUP "ff_en_64" BBOX 1 1 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200/ff_array_en_i_1_i; +LOCATE UGROUP "ff_en_64" SITE "R113C27D" ; + + +############################################################################## +## CHANNEL PLACEMENTS ## +############################################################################## +UGROUP "EF_ref" BBOX 16 54 + BLKNAME THE_TDC/ReferenceChannel/Channel200 + BLKNAME THE_TDC/GEN_Channels_1_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_2_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_3_Channels/Channel200 + BLKNAME THE_TDC/ReferenceChannel/The_Buffer + BLKNAME THE_TDC/GEN_Channels_1_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_2_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_3_Channels/The_Buffer; +LOCATE UGROUP "EF_ref" SITE "R8C128D" ; + +UGROUP "EF_4" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_4_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_5_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_4_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_5_Channels/The_Buffer; +LOCATE UGROUP "EF_4" SITE "R24C128D" ; + +UGROUP "EF_6" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_6_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_7_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_8_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_9_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_6_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_7_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_8_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_9_Channels/The_Buffer; +LOCATE UGROUP "EF_6" SITE "R35C128D" ; + +UGROUP "EF_10" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_10_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_11_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_17_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_18_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_10_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_11_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_17_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_18_Channels/The_Buffer; +LOCATE UGROUP "EF_10" SITE "R53C128D" ; + +UGROUP "EF_12" BBOX 16 54 + BLKNAME THE_TDC/GEN_Channels_12_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_13_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_33_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_34_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_12_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_13_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_33_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_34_Channels/The_Buffer; +LOCATE UGROUP "EF_12" SITE "R8C56D" ; + +UGROUP "EF_14" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_14_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_35_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_14_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_35_Channels/The_Buffer; +LOCATE UGROUP "EF_14" SITE "R24C56D" ; + +UGROUP "EF_15" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_15_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_16_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_36_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_37_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_15_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_16_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_36_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_37_Channels/The_Buffer; +LOCATE UGROUP "EF_15" SITE "R35C56D" ; + +UGROUP "EF_19" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_19_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_20_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_21_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_22_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_19_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_20_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_21_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_22_Channels/The_Buffer; +LOCATE UGROUP "EF_19" SITE "R71C128D" ; + +UGROUP "EF_23" BBOX 16 54 + BLKNAME THE_TDC/GEN_Channels_23_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_24_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_25_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_26_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_23_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_24_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_25_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_26_Channels/The_Buffer; +LOCATE UGROUP "EF_23" SITE "R89C128D" ; + +UGROUP "EF_27" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_27_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_28_Channels/The_Buffer; +LOCATE UGROUP "EF_27" SITE "R105C128D" ; + +UGROUP "EF_29" BBOX 16 54 + BLKNAME THE_TDC/GEN_Channels_29_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_30_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_50_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_51_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_29_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_30_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_50_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_51_Channels/The_Buffer; +LOCATE UGROUP "EF_29" SITE "R89C56D" ; + +UGROUP "EF_31" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_31_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_52_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_31_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_52_Channels/The_Buffer; +LOCATE UGROUP "EF_31" SITE "R105C56D" ; + +UGROUP "EF_32" BBOX 10 24 + BLKNAME THE_TDC/GEN_Channels_32_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_32_Channels/The_Buffer; +LOCATE UGROUP "EF_32" SITE "R78C71D" ; + +UGROUP "EF_38" BBOX 16 54 + BLKNAME THE_TDC/GEN_Channels_38_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_39_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_40_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_41_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_38_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_39_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_40_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_41_Channels/The_Buffer; +LOCATE UGROUP "EF_38" SITE "R8C2D" ; + +UGROUP "EF_42" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_42_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_43_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_42_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_43_Channels/The_Buffer; +LOCATE UGROUP "EF_42" SITE "R24C2D" ; + +UGROUP "EF_44" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_44_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_45_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_46_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_47_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_44_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_45_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_46_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_47_Channels/The_Buffer; +LOCATE UGROUP "EF_44" SITE "R35C2D" ; + +UGROUP "EF_48" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_48_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_49_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_53_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_54_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_48_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_49_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_53_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_54_Channels/The_Buffer; +LOCATE UGROUP "EF_48" SITE "R53C2D" ; + +UGROUP "EF_55" BBOX 17 54 + BLKNAME THE_TDC/GEN_Channels_55_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_56_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_57_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_58_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_55_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_56_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_57_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_58_Channels/The_Buffer; +LOCATE UGROUP "EF_55" SITE "R71C2D" ; + +UGROUP "EF_59" BBOX 16 54 + BLKNAME THE_TDC/GEN_Channels_59_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_60_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_61_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_62_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_59_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_60_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_61_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_62_Channels/The_Buffer; +LOCATE UGROUP "EF_59" SITE "R89C2D" ; + +UGROUP "EF_63" BBOX 10 54 + BLKNAME THE_TDC/GEN_Channels_63_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_64_Channels/Channel200 + BLKNAME THE_TDC/GEN_Channels_63_Channels/The_Buffer + BLKNAME THE_TDC/GEN_Channels_64_Channels/The_Buffer; +LOCATE UGROUP "EF_63" SITE "R105C2D" ; + +############################################################################# +## Coarse counter register placement +############################################################################# + +UGROUP "UR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_1_TheCoarseCounter; +LOCATE UGROUP "UR_Coarse_Counter" SITE R36C134D; +UGROUP "LR_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_2_TheCoarseCounter; +LOCATE UGROUP "LR_Coarse_Counter" SITE R85C134D; +UGROUP "UL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_3_TheCoarseCounter; +LOCATE UGROUP "UL_Coarse_Counter" SITE R36C50D; +UGROUP "LL_Coarse_Counter" + BLKNAME THE_TDC/GenCoarseCounter_4_TheCoarseCounter; +LOCATE UGROUP "LL_Coarse_Counter" SITE R85C50D; +UGROUP "TheCounters" + BLKNAME THE_TDC/GenCoarseCounter_0_TheCoarseCounter + BLKNAME THE_TDC/TheEpochCounter; +#LOCATE UGROUP "TheCounters" REGION REGION_READOUT; + +############################################################################# +## Other Logic Placements +############################################################################# + +UGROUP "BusHandlers" + BLKNAME THE_TDC/TheHitCounterBus + BLKNAME THE_TDC/TheStatusRegistersBus +# BLKNAME THE_TDC/TheLostHitBus +# BLKNAME THE_TDC/TheEncoderStartBus +# BLKNAME THE_TDC/TheEncoderFinishedBus +; +LOCATE UGROUP "BusHandlers" REGION "REGION_TRBNET"; +LOCATE PGROUP "BusHandlers" REGION "REGION_TRBNET"; + +UGROUP "TheTdcReadout" #BBOX 35 57 + BLKNAME THE_TDC/TheReadout + ; +#LOCATE UGROUP "TheTdcReadout" SITE "R53C53D"; + +UGROUP "TheTriggerHandler" + BLKNAME THE_TDC/TheTriggerHandler + ; +LOCATE UGROUP "TheTriggerHandler" SITE "R65C80D"; + +############################################################################# +## Unimportant Data Lines ## +############################################################################# +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 4x; +MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; +MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/FIFO/*" CLKNET CLK_EXT TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/FIFO/*" CLKNET CLK_EXT TO CELL "THE_TDC/ReferenceChannel/Channel200/FIFO/*" CLKNET clk_100_i_c 2x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; + +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5 X; + +MAXDELAY NET "THE_TDC/hit_in_i[*]" 0.600000 nS; #DATAPATH_ONLY ; + +## Maybe effective + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; + + + + + + +# BLOCK NET "THE_TDC/reset_tdc*" ; +# BLOCK NET "THE_TDC/reset_rdo*" ; +# #BLOCK NET "THE_TDC/hit_in_i_*" ; +# BLOCK NET "THE_TDC/hit_latch*" ; +# BLOCK NET "THE_TDC/reset_counters_i*" ; + + + +# PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +# PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels*Channels/Channel200/ff_array_en_i"; + +# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; +# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; diff --git a/tdc_releases/tdc_v2.0/tdc_version.vhd b/tdc_releases/tdc_v2.0/tdc_version.vhd new file mode 100644 index 0000000..63b4d8e --- /dev/null +++ b/tdc_releases/tdc_v2.0/tdc_version.vhd @@ -0,0 +1,9 @@ +library ieee; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +package tdc_version is + + constant TDC_VERSION : std_logic_vector(11 downto 0) := x"200"; + +end; diff --git a/tdc_releases/tdc_v2.0/trb3_periph.vhd b/tdc_releases/tdc_v2.0/trb3_periph.vhd index 9e2ff52..e074371 100644 --- a/tdc_releases/tdc_v2.0/trb3_periph.vhd +++ b/tdc_releases/tdc_v2.0/trb3_periph.vhd @@ -34,9 +34,9 @@ entity trb3_periph is SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only INP : in std_logic_vector(63 downto 0); --DAC_SDO : in std_logic; - --DAC_SDI : out std_logic; - --DAC_SCK : out std_logic; - --DAC_CS : out std_logic_vector(3 downto 0); + DAC_SDI : out std_logic; + DAC_SCK : out std_logic; + DAC_CS : out std_logic_vector(4 downto 1); --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; @@ -71,13 +71,13 @@ entity trb3_periph is attribute syn_useioff of FLASH_DIN : signal is true; attribute syn_useioff of FLASH_DOUT : signal is true; attribute syn_useioff of FPGA5_COMM : signal is true; - attribute syn_useioff of TEST_LINE : signal is false; --true; + attribute syn_useioff of TEST_LINE : signal is true; attribute syn_useioff of INP : signal is false; attribute syn_useioff of SPARE_LINE : signal is true; --attribute syn_useioff of DAC_SDO : signal is true; - --attribute syn_useioff of DAC_SDI : signal is true; - --attribute syn_useioff of DAC_SCK : signal is true; - --attribute syn_useioff of DAC_CS : signal is true; + attribute syn_useioff of DAC_SDI : signal is true; + attribute syn_useioff of DAC_SCK : signal is true; + attribute syn_useioff of DAC_CS : signal is true; end entity; @@ -93,6 +93,8 @@ architecture trb3_periph_arch of trb3_periph is --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal clk_125_i : std_logic; -- 125 MHz, via Clock Manager and bypassed PLL + signal clk_20_i : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -220,21 +222,26 @@ architecture trb3_periph_arch of trb3_periph is signal esb_data_ready : std_logic; signal esb_invalid : std_logic; - signal fwb_read_en : std_logic; - signal fwb_write_en : std_logic; - signal fwb_addr : std_logic_vector(6 downto 0); - signal fwb_data_out : std_logic_vector(31 downto 0); - signal fwb_data_ready : std_logic; - signal fwb_invalid : std_logic; + signal efb_read_en : std_logic; + signal efb_write_en : std_logic; + signal efb_addr : std_logic_vector(6 downto 0); + signal efb_data_out : std_logic_vector(31 downto 0); + signal efb_data_ready : std_logic; + signal efb_invalid : std_logic; + + signal tdc_ctrl_read : std_logic; + signal last_tdc_ctrl_read : std_logic; + signal tdc_ctrl_write : std_logic; + signal tdc_ctrl_addr : std_logic_vector(2 downto 0); + signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); + signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); + signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0); signal spi_bram_addr : std_logic_vector(7 downto 0); signal spi_bram_wr_d : std_logic_vector(7 downto 0); signal spi_bram_rd_d : std_logic_vector(7 downto 0); signal spi_bram_we : std_logic; - --FPGA Test --- signal time_counter : unsigned(31 downto 0); - --TDC signal hit_in_i : std_logic_vector(64 downto 1); signal logic_analyser_i : std_logic_vector(15 downto 0); @@ -275,6 +282,13 @@ begin LOCK => pll_lock ); + -- generates hits for calibration uncorrelated with tdc clk + THE_CALIBRATION_PLL : pll_in125_out20 + port map ( + CLK => CLK_GPLL_LEFT, + CLKOP => clk_20_i, + CLKOK => clk_125_i, + LOCK => open); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) @@ -323,6 +337,19 @@ begin --------------------------------------------------------------------------- -- Endpoint --------------------------------------------------------------------------- + --regio_hardware_version_i <= x"9100" & addOn_type_i & edge_type_i & tdc_channel_no_i & x"0"; + + --addOn_type_i <= x"0"; -- x"0" - ADA AddOn version 1 + -- -- x"1" - ADA AddOn version 2 + -- -- x"2" - multi purpose test AddOn + -- -- x"3" - SFP hub AddOn + -- -- x"4" - Wasa AddOn + --edge_type_i <= x"0"; -- x"0" - single edge + -- -- x"1" - double edge + -- -- x"4" - has spi interface + -- -- x"8" - double edge on consecutive channels + --tdc_channel_no_i <= x"6"; -- 2^n channels + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler generic map( REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg @@ -331,20 +358,16 @@ begin BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91000000", --regio_hardware_version_i(31 downto 16) <= x"9100"; - --regio_hardware_version_i(15 downto 12) <= x"0"; --addOn_type_i; - --regio_hardware_version_i(11 downto 8) <= x"0"; --edge_type_i; - --regio_hardware_version_i(7 downto 4) <= x"6"; --tdc_channel_no_i; - --regio_hardware_version_i(3 downto 0) <= x"0"; + REGIO_HARDWARE_VERSION => x"91000460", -- regio_hardware_version_i, REGIO_INIT_ADDRESS => x"f305", REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => 125, + CLOCK_FREQUENCY => 100, TIMING_TRIGGER_RAW => c_YES, --Configure data handler DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => 13, --13 + DATA_BUFFER_DEPTH => 13, --13 DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024 + DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-(maximal 2**12) TRG_RELEASE_AFTER_DATA => c_YES, HEADER_BUFFER_DEPTH => 9, HEADER_BUFFER_FULL_THRESH => 2**9-16 @@ -436,8 +459,9 @@ begin DEBUG_LVL1_HANDLER_OUT => open ); - timing_trg_received_i <= TRIGGER_LEFT; + timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; -- common_stat_reg <= (others => '0'); + stat_reg <= (others => '0'); --------------------------------------------------------------------------- -- AddOn @@ -448,9 +472,9 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 8, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, others => 0) + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, others => 0) ) port map( CLK => clk_100_i, @@ -540,17 +564,17 @@ begin BUS_NO_MORE_DATA_IN(5) => '0', BUS_UNKNOWN_ADDR_IN(5) => esb_invalid, --Fifo Write Registers - BUS_READ_ENABLE_OUT(6) => fwb_read_en, - BUS_WRITE_ENABLE_OUT(6) => fwb_write_en, + BUS_READ_ENABLE_OUT(6) => efb_read_en, + BUS_WRITE_ENABLE_OUT(6) => efb_write_en, BUS_DATA_OUT(6*32+31 downto 6*32) => open, - BUS_ADDR_OUT(6*16+6 downto 6*16) => fwb_addr, + BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr, BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, BUS_TIMEOUT_OUT(6) => open, - BUS_DATA_IN(6*32+31 downto 6*32) => fwb_data_out, - BUS_DATAREADY_IN(6) => fwb_data_ready, + BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out, + BUS_DATAREADY_IN(6) => efb_data_ready, BUS_WRITE_ACK_IN(6) => '0', BUS_NO_MORE_DATA_IN(6) => '0', - BUS_UNKNOWN_ADDR_IN(6) => fwb_invalid, + BUS_UNKNOWN_ADDR_IN(6) => efb_invalid, --Lost Hit Registers BUS_READ_ENABLE_OUT(7) => lhb_read_en, BUS_WRITE_ENABLE_OUT(7) => lhb_write_en, @@ -563,11 +587,34 @@ begin BUS_WRITE_ACK_IN(7) => '0', BUS_NO_MORE_DATA_IN(7) => '0', BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid, - + --TDC config registers + BUS_READ_ENABLE_OUT(8) => tdc_ctrl_read, + BUS_WRITE_ENABLE_OUT(8) => tdc_ctrl_write, + BUS_DATA_OUT(8*32+31 downto 8*32) => tdc_ctrl_data_in, + BUS_ADDR_OUT(8*16+2 downto 8*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+3) => open, + BUS_TIMEOUT_OUT(8) => open, + BUS_DATA_IN(8*32+31 downto 8*32) => tdc_ctrl_data_out, + BUS_DATAREADY_IN(8) => last_tdc_ctrl_read, + BUS_WRITE_ACK_IN(8) => tdc_ctrl_write, + BUS_NO_MORE_DATA_IN(8) => '0', + BUS_UNKNOWN_ADDR_IN(8) => '0', STAT_DEBUG => open ); + PROC_TDC_CTRL_REG : process + variable pos : integer; + begin + wait until rising_edge(clk_100_i); + pos := to_integer(unsigned(tdc_ctrl_addr))*32; + tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos); + last_tdc_ctrl_read <= tdc_ctrl_read; + if tdc_ctrl_write = '1' then + tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in; + end if; + end process; + --------------------------------------------------------------------------- -- SPI / Flash --------------------------------------------------------------------------- @@ -635,13 +682,13 @@ begin -- SPI connections SPI_CS_OUT(15 downto 4) => open, SPI_CS_OUT(3 downto 0) => dac_cs_i, - SPI_SDI_IN => open, + SPI_SDI_IN => '0', SPI_SDO_OUT => dac_sdi_i, SPI_SCK_OUT => dac_sck_i); - --DAC_CS <= open; --dac_cs_i; - --DAC_SDI <= open; --dac_sdi_i; - --DAC_SCK <= open; --dac_sck_i; + DAC_CS <= dac_cs_i; + DAC_SDI <= dac_sdi_i; + DAC_SCK <= dac_sck_i; --------------------------------------------------------------------------- -- Reboot FPGA @@ -659,14 +706,14 @@ begin --------------------------------------------------------------------------- LED_GREEN <= not med_stat_op(9); LED_ORANGE <= not med_stat_op(10); - LED_RED <= not TRIGGER_LEFT; + LED_RED <= not INP(0); LED_YELLOW <= not med_stat_op(11); --------------------------------------------------------------------------- -- Test Connector - Logic Analyser --------------------------------------------------------------------------- --- TEST_LINE <= logic_analyser_i; + TEST_LINE <= logic_analyser_i; ------------------------------------------------------------------------------- -- TDC @@ -674,17 +721,18 @@ begin THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 4, -- Number of TDC channels - STATUS_REG_NR => REGIO_NUM_STAT_REGS, - CONTROL_REG_NR => REGIO_NUM_CTRL_REGS) + CHANNEL_NUMBER => 65, -- Number of TDC channels + CONTROL_REG_NR => 5, -- Number of control regs - higher than 8 check tdc_ctrl_addr + TDC_VERSION => "001" & x"51") -- TDC version number port map ( RESET => reset_i, CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout - REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(3 downto 1), -- Channel start signals - TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width - TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(64 downto 1), -- Channel start signals + HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC + TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width + TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width -- -- Trigger signals from handler TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet @@ -730,12 +778,12 @@ begin ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr --Fifo Write Registers Bus - FWB_READ_EN_IN => fwb_read_en, -- bus read en strobe - FWB_WRITE_EN_IN => fwb_write_en, -- bus write en strobe - FWB_ADDR_IN => fwb_addr, -- bus address - FWB_DATA_OUT => fwb_data_out, -- bus data - FWB_DATAREADY_OUT => fwb_data_ready, -- bus data ready strobe - FWB_UNKNOWN_ADDR_OUT => fwb_invalid, -- bus invalid addr + EFB_READ_EN_IN => efb_read_en, -- bus read en strobe + EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe + EFB_ADDR_IN => efb_addr, -- bus address + EFB_DATA_OUT => efb_data_out, -- bus data + EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe + EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr --Lost Hit Registers Bus LHB_READ_EN_IN => lhb_read_en, -- bus read en strobe LHB_WRITE_EN_IN => lhb_write_en, -- bus write en strobe @@ -744,40 +792,18 @@ begin LHB_DATAREADY_OUT => lhb_data_ready, -- bus data ready strobe LHB_UNKNOWN_ADDR_OUT => lhb_invalid, -- bus invalid addr -- - SLOW_CONTROL_REG_OUT => stat_reg, LOGIC_ANALYSER_OUT => logic_analyser_i, - CONTROL_REG_IN => ctrl_reg); - - ---- For single edge measurements - - - hit_in_i <= INP; + CONTROL_REG_IN => tdc_ctrl_reg); - Stretcher_1 : Stretcher - port map ( - PULSE_IN => hit_in_i(1), - PULSE_OUT => TEST_LINE(0)); - - Stretcher_2 : Stretcher - port map ( - PULSE_IN => hit_in_i(2), - PULSE_OUT => TEST_LINE(1)); - - Stretcher_3 : Stretcher - port map ( - PULSE_IN => hit_in_i(3), - PULSE_OUT => TEST_LINE(2)); - - Stretcher_4 : Stretcher - port map ( - PULSE_IN => hit_in_i(4), - PULSE_OUT => TEST_LINE(3)); + -- For single edge measurements + hit_in_i <= INP; + --hit_in_i <= (others => timing_trg_received_i); ---- For ToT Measurements - --hit_in_i(1) <= not timing_trg_received_i; - --Gen_Hit_In_Signals : for i in 1 to 16 generate - -- hit_in_i(i*2) <= INP(i-1); - -- hit_in_i(i*2+1) <= not INP(i-1); + --Gen_Hit_In_Signals : for i in 1 to 32 generate + -- hit_in_i(i*2-1) <= INP(i-1); + -- hit_in_i(i*2) <= not INP(i-1); --end generate Gen_Hit_In_Signals; +-- !!!!! IMPORTANT !!!!! Don't forget to set the REGIO_HARDWARE_VERSION !!!!! end architecture; diff --git a/tdc_releases/tdc_v2.0/trbnet_constraints.lpf b/tdc_releases/tdc_v2.0/trbnet_constraints.lpf new file mode 100644 index 0000000..2e8b1a7 --- /dev/null +++ b/tdc_releases/tdc_v2.0/trbnet_constraints.lpf @@ -0,0 +1,73 @@ +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "reset_i"; + +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; + +REGION "MEDIA_UPLINK" "R105C110D" 10 18; +REGION "REGION_SPI" "R2C110D" 15 18 DEVSIZE; +REGION "REGION_TRBNET" "R17C110D" 95 18 DEVSIZE; + +#LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +#LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/trb_reset_*" 20 ns; +MULTICYCLE TO CELL "gen_SPI_DAC_SPI_*io*" 20 ns; +MULTICYCLE TO CELL "THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; + +BLOCK PATH TO CELL "gen_TRIGGER_LOGIC_THE_TRIG_LOGIC/out_*"; + +#Jan: Placement of TrbNet components (at least, most of them) + +#UGROUP "TrbNet" BBOX 77 27 +# BLKNAME THE_ENDPOINT +# BLKNAME THE_ENDPOINT/THE_ENDPOINT +#LOCATE UGROUP "TrbNet" REGION "REGION_TRBNET"; + +#LOCATE UGROUP "THE_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +#LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group" REGION "REGION_TRBNET"; + + +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +#LOCATE UGROUP "THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET"; + +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; + +UGROUP "ENDPOINT" + BLKNAME THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl +; +LOCATE UGROUP "ENDPOINT" REGION "REGION_TRBNET"; + +UGROUP "SctrlGroup" + BLKNAME THE_BUS_HANDLER + BLKNAME THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER + ; +LOCATE UGROUP "SctrlGroup" REGION "REGION_TRBNET"; + + +UGROUP "ResetHandler" + BLKNAME THE_RESET_HANDLER +; + + + diff --git a/tdc_releases/tdc_v2.0/trbnet_constraints.lpf.nogroup b/tdc_releases/tdc_v2.0/trbnet_constraints.lpf.nogroup new file mode 100644 index 0000000..bdeb4ec --- /dev/null +++ b/tdc_releases/tdc_v2.0/trbnet_constraints.lpf.nogroup @@ -0,0 +1,22 @@ +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "reset_i"; + +################################################################# +# Locate Serdes and media interfaces +################################################################# + +MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/trb_reset_*" 20 ns; +MULTICYCLE TO CELL "gen_SPI_DAC_SPI_*io*" 20 ns; +MULTICYCLE TO CELL "THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; + +BLOCK PATH TO CELL "gen_TRIGGER_LOGIC_THE_TRIG_LOGIC/out_*"; + +#Jan: Placement of TrbNet components (at least, most of them) + + +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns; diff --git a/tdc_releases/tdc_v2.0/trbnet_constraints.lpf.orig b/tdc_releases/tdc_v2.0/trbnet_constraints.lpf.orig new file mode 100644 index 0000000..2e8b1a7 --- /dev/null +++ b/tdc_releases/tdc_v2.0/trbnet_constraints.lpf.orig @@ -0,0 +1,73 @@ +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "reset_i"; + +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; + +REGION "MEDIA_UPLINK" "R105C110D" 10 18; +REGION "REGION_SPI" "R2C110D" 15 18 DEVSIZE; +REGION "REGION_TRBNET" "R17C110D" 95 18 DEVSIZE; + +#LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +#LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/trb_reset_*" 20 ns; +MULTICYCLE TO CELL "gen_SPI_DAC_SPI_*io*" 20 ns; +MULTICYCLE TO CELL "THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; + +BLOCK PATH TO CELL "gen_TRIGGER_LOGIC_THE_TRIG_LOGIC/out_*"; + +#Jan: Placement of TrbNet components (at least, most of them) + +#UGROUP "TrbNet" BBOX 77 27 +# BLKNAME THE_ENDPOINT +# BLKNAME THE_ENDPOINT/THE_ENDPOINT +#LOCATE UGROUP "TrbNet" REGION "REGION_TRBNET"; + +#LOCATE UGROUP "THE_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +#LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group" REGION "REGION_TRBNET"; + + +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +#LOCATE UGROUP "THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET"; + +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; + +UGROUP "ENDPOINT" + BLKNAME THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl +; +LOCATE UGROUP "ENDPOINT" REGION "REGION_TRBNET"; + +UGROUP "SctrlGroup" + BLKNAME THE_BUS_HANDLER + BLKNAME THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER + ; +LOCATE UGROUP "SctrlGroup" REGION "REGION_TRBNET"; + + +UGROUP "ResetHandler" + BLKNAME THE_RESET_HANDLER +; + + + diff --git a/tdc_releases/tdc_v2.0/unimportant_lines_constraints.lpf b/tdc_releases/tdc_v2.0/unimportant_lines_constraints.lpf new file mode 100644 index 0000000..bb35e0d --- /dev/null +++ b/tdc_releases/tdc_v2.0/unimportant_lines_constraints.lpf @@ -0,0 +1,57 @@ +############################################################################# +## Unimportant Data Lines ## +############################################################################# +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_LEFT_c 2x; + +MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; +# MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; + +# MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; +# MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/ReferenceChannel/Channel200/ringBuffer_almost_full_sync*" 2x; + +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 3 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 3 X; + +MULTICYCLE TO CELL "THE_TDC/TheFirstReadout/TW_pre*" 4 x; +MULTICYCLE TO CELL "THE_TDC/TheFirstReadout/TW_post*" 4 x; +MULTICYCLE TO CELL "THE_TDC/Gen_Readout*Module*TheReadout/TW_pre*" 4 x; +MULTICYCLE TO CELL "THE_TDC/Gen_Readout*Module*TheReadout/TW_post*" 4 x; + +MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/data_out_reg*" 4 x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo.FC/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/Encoder/interval_reg*" 2 x; + + + + +# #MAXDELAY FROM GROUP "hitBuf*" TO GROUP "FC*" 0.600000 nS; +# #MAXDELAY FROM GROUP "hitBuf_ref*" TO GROUP "Ref_Ch" 0.600000 nS; + +MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ; + + +## Maybe effective + +# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheFirstReadout/rd_en*" 2 X; +# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/Gen_Readout*Module*TheReadout/rd_en*" 2 X; + + + + + +# # BLOCK NET "THE_TDC/reset_tdc*" ; +# # BLOCK NET "THE_TDC/reset_rdo*" ; +# # #BLOCK NET "THE_TDC/hit_in_i_*" ; +# # BLOCK NET "THE_TDC/hit_latch*" ; +# # BLOCK NET "THE_TDC/reset_counters_i*" ; + + + +# # PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +# # PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels*Channels/Channel200/ff_array_en_i";