From: Jan Michel Date: Thu, 6 Aug 2015 10:31:37 +0000 (+0200) Subject: update X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=fec3cdfd3c83414df4665310d41055e1395d9ba9;p=trbnet.git update --- diff --git a/gbe_trb/top/trb3_central.lpf b/gbe_trb/top/trb3_central.lpf new file mode 100644 index 0000000..392e012 --- /dev/null +++ b/gbe_trb/top/trb3_central.lpf @@ -0,0 +1,789 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +# ################################################################# +# # Basic Settings +# ################################################################# +# +# SYSCONFIG MCCLK_FREQ = 2.5; +# +# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +# FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz; +# FREQUENCY PORT CLK_GPLL_LEFT 200 MHz; +# FREQUENCY PORT CLK_EXT_3 10 MHz; +# FREQUENCY PORT CLK_EXT_4 10 MHz; + + +################################################################# +# Clock I/O +################################################################# + +#Additional signals from Clock-RJ-45 +LOCATE COMP "CLK_EXT_3" SITE "U9"; #was SPARE_LINE_2 +LOCATE COMP "CLK_EXT_4" SITE "Y34"; #was SPARE_LINE_4 +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AH22"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AH12"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "Y28"; +LOCATE COMP "CLK_GPLL_LEFT" SITE "Y9"; +LOCATE COMP "CLK_PCLK_LEFT" SITE "V9"; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U28"; + +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25; + +LOCATE COMP "ENPIRION_CLOCK" SITE "G18"; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4; + +################################################################# +# Trigger I/O +################################################################# + +#Trigger from fan-out +LOCATE COMP "TRIGGER_RIGHT" SITE "W30"; +IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; +LOCATE COMP "TRIGGER_LEFT" SITE "Y2"; +IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; + +#To fan-out to all FPGA +LOCATE COMP "TRIGGER_OUT" SITE "V7"; +IOBUF PORT "TRIGGER_OUT" IO_TYPE=LVDS25 ; + +LOCATE COMP "TRIGGER_OUT2" SITE "W8"; #was EXT_TRIG_4 +IOBUF PORT "TRIGGER_OUT2" IO_TYPE=LVDS25 ; + + +#Additional lines on Trigger-RJ-45 +LOCATE COMP "TRIGGER_EXT_2" SITE "W2"; +LOCATE COMP "TRIGGER_EXT_3" SITE "W4"; #was EXT_TRIG_2 +#LOCATE COMP "TRIGGER_EXT_4" SITE "W8"; #was EXT_TRIG_4 +DEFINE PORT GROUP "TRIGGER_EXT_group" "TRIGGER_EXT*" ; +IOBUF GROUP "TRIGGER_EXT_group" IO_TYPE=LVDS25; + +LOCATE COMP "CLK_TEST_OUT_2" SITE "Y34"; +IOBUF PORT "CLK_TEST_OUT_2" IO_TYPE=LVDS25 ; +LOCATE COMP "CLK_TEST_OUT_1" SITE "W4"; +IOBUF PORT "CLK_TEST_OUT_1" IO_TYPE=LVDS25 ; +LOCATE COMP "CLK_TEST_OUT_0" SITE "U9"; +IOBUF PORT "CLK_TEST_OUT_0" IO_TYPE=LVDS25 ; + + +LOCATE COMP "CLKRJ_0" SITE "U9"; +LOCATE COMP "CLKRJ_1" SITE "U8"; +LOCATE COMP "CLKRJ_2" SITE "Y34"; +LOCATE COMP "CLKRJ_3" SITE "Y33"; +DEFINE PORT GROUP "CLKRJ_group" "CLKRJ*" ; +IOBUF GROUP "CLKRJ_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=12; + +################################################################# +# Clock and Trigger Select +################################################################# +#Trigger select for fan-out. 0: external trigger. 1: TRIGGER_OUT +LOCATE COMP "TRIGGER_SELECT" SITE "AA31"; +IOBUF PORT "TRIGGER_SELECT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4 ; + +LOCATE COMP "CLK_MNGR1_USER_0" SITE "AA28"; +LOCATE COMP "CLK_MNGR1_USER_1" SITE "AA27"; +LOCATE COMP "CLK_MNGR1_USER_2" SITE "AB32"; +LOCATE COMP "CLK_MNGR1_USER_3" SITE "AB31"; +LOCATE COMP "CLK_MNGR2_USER_0" SITE "AE34"; +LOCATE COMP "CLK_MNGR2_USER_1" SITE "AE33"; +LOCATE COMP "CLK_MNGR2_USER_2" SITE "AB26"; +LOCATE COMP "CLK_MNGR2_USER_3" SITE "AB25"; +DEFINE PORT GROUP "CLK_MNGR_group" "CLK_MNGR*" ; +IOBUF GROUP "CLK_MNGR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; + +LOCATE COMP "CLOCK_SELECT" SITE "AA30"; +IOBUF PORT "CLOCK_SELECT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4 ; + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "A17"; +LOCATE COMP "LED_ORANGE" SITE "B17"; +LOCATE COMP "LED_RED" SITE "E19"; +LOCATE COMP "LED_YELLOW" SITE "E20"; +IOBUF PORT "LED_GREEN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_ORANGE" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_RED" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_YELLOW" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8; + +LOCATE COMP "LED_TRIGGER_GREEN" SITE "AP5"; +LOCATE COMP "LED_TRIGGER_RED" SITE "AP6"; +LOCATE COMP "LED_CLOCK_GREEN" SITE "AL4"; +LOCATE COMP "LED_CLOCK_RED" SITE "AM4"; +IOBUF PORT "LED_TRIGGER_GREEN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_TRIGGER_RED" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_CLOCK_GREEN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; +IOBUF PORT "LED_CLOCK_RED" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; + +################################################################# +# Inter-FPGA Connection +################################################################# +LOCATE COMP "FPGA1_COMM_0" SITE "AC9"; +LOCATE COMP "FPGA1_COMM_10" SITE "AJ1"; +LOCATE COMP "FPGA1_COMM_11" SITE "AK1"; +LOCATE COMP "FPGA1_COMM_1" SITE "AC8"; +LOCATE COMP "FPGA1_COMM_2" SITE "AE2"; +LOCATE COMP "FPGA1_COMM_3" SITE "AE1"; +LOCATE COMP "FPGA1_COMM_4" SITE "AE4"; +LOCATE COMP "FPGA1_COMM_5" SITE "AE3"; +LOCATE COMP "FPGA1_COMM_6" SITE "AB10"; +LOCATE COMP "FPGA1_COMM_7" SITE "AC10"; +LOCATE COMP "FPGA1_COMM_8" SITE "AD4"; +LOCATE COMP "FPGA1_COMM_9" SITE "AD3"; + +LOCATE COMP "FPGA2_COMM_0" SITE "P5"; +LOCATE COMP "FPGA2_COMM_10" SITE "M10"; +LOCATE COMP "FPGA2_COMM_11" SITE "N10"; +LOCATE COMP "FPGA2_COMM_1" SITE "P4"; +LOCATE COMP "FPGA2_COMM_2" SITE "N8"; +LOCATE COMP "FPGA2_COMM_3" SITE "P8"; +LOCATE COMP "FPGA2_COMM_4" SITE "M5"; +LOCATE COMP "FPGA2_COMM_5" SITE "N5"; +LOCATE COMP "FPGA2_COMM_6" SITE "R7"; +LOCATE COMP "FPGA2_COMM_7" SITE "R5"; +LOCATE COMP "FPGA2_COMM_8" SITE "N2"; +LOCATE COMP "FPGA2_COMM_9" SITE "N1"; + +LOCATE COMP "FPGA3_COMM_0" SITE "AC28"; +LOCATE COMP "FPGA3_COMM_10" SITE "AF32"; +LOCATE COMP "FPGA3_COMM_11" SITE "AF31"; +LOCATE COMP "FPGA3_COMM_1" SITE "AB27"; +LOCATE COMP "FPGA3_COMM_2" SITE "AE32"; +LOCATE COMP "FPGA3_COMM_3" SITE "AE31"; +LOCATE COMP "FPGA3_COMM_4" SITE "AE30"; +LOCATE COMP "FPGA3_COMM_5" SITE "AE29"; +LOCATE COMP "FPGA3_COMM_6" SITE "AC25"; +LOCATE COMP "FPGA3_COMM_7" SITE "AC26"; +LOCATE COMP "FPGA3_COMM_8" SITE "AD26"; +LOCATE COMP "FPGA3_COMM_9" SITE "AD25"; + +LOCATE COMP "FPGA4_COMM_0" SITE "AN32"; +LOCATE COMP "FPGA4_COMM_10" SITE "AM29"; +LOCATE COMP "FPGA4_COMM_11" SITE "AN29"; +LOCATE COMP "FPGA4_COMM_1" SITE "AM32"; +LOCATE COMP "FPGA4_COMM_2" SITE "AP29"; +LOCATE COMP "FPGA4_COMM_3" SITE "AP30"; +LOCATE COMP "FPGA4_COMM_4" SITE "AL30"; +LOCATE COMP "FPGA4_COMM_5" SITE "AM30"; +LOCATE COMP "FPGA4_COMM_6" SITE "AL31"; +LOCATE COMP "FPGA4_COMM_7" SITE "AM31"; +LOCATE COMP "FPGA4_COMM_8" SITE "AP31"; +LOCATE COMP "FPGA4_COMM_9" SITE "AN31"; + + +################################################################# +# Connection to small AddOns +################################################################# +LOCATE COMP "FPGA1_CONNECTOR_0" SITE "AN1"; +LOCATE COMP "FPGA1_CONNECTOR_1" SITE "AN2"; +LOCATE COMP "FPGA1_CONNECTOR_2" SITE "AD9"; +LOCATE COMP "FPGA1_CONNECTOR_3" SITE "AD8"; +LOCATE COMP "FPGA1_CONNECTOR_4" SITE "AP2"; +LOCATE COMP "FPGA1_CONNECTOR_5" SITE "AP3"; +LOCATE COMP "FPGA1_CONNECTOR_6" SITE "AJ2"; +LOCATE COMP "FPGA1_CONNECTOR_7" SITE "AJ3"; + +LOCATE COMP "FPGA2_CONNECTOR_0" SITE "P9"; +LOCATE COMP "FPGA2_CONNECTOR_1" SITE "P10"; +LOCATE COMP "FPGA2_CONNECTOR_2" SITE "R2"; +LOCATE COMP "FPGA2_CONNECTOR_3" SITE "R1"; +LOCATE COMP "FPGA2_CONNECTOR_4" SITE "P7"; +LOCATE COMP "FPGA2_CONNECTOR_5" SITE "P6"; +LOCATE COMP "FPGA2_CONNECTOR_6" SITE "R4"; +LOCATE COMP "FPGA2_CONNECTOR_7" SITE "R3"; + +LOCATE COMP "FPGA3_CONNECTOR_0" SITE "AN34"; +LOCATE COMP "FPGA3_CONNECTOR_1" SITE "AN33"; +LOCATE COMP "FPGA3_CONNECTOR_2" SITE "AH33"; +LOCATE COMP "FPGA3_CONNECTOR_3" SITE "AJ33"; +LOCATE COMP "FPGA3_CONNECTOR_4" SITE "AP33"; +LOCATE COMP "FPGA3_CONNECTOR_5" SITE "AP32"; +LOCATE COMP "FPGA3_CONNECTOR_6" SITE "AL34"; +LOCATE COMP "FPGA3_CONNECTOR_7" SITE "AL33"; + +LOCATE COMP "FPGA4_CONNECTOR_0" SITE "AK27"; +LOCATE COMP "FPGA4_CONNECTOR_1" SITE "AJ27"; +LOCATE COMP "FPGA4_CONNECTOR_2" SITE "AK28"; +LOCATE COMP "FPGA4_CONNECTOR_3" SITE "AJ28"; +LOCATE COMP "FPGA4_CONNECTOR_4" SITE "AH27"; +LOCATE COMP "FPGA4_CONNECTOR_5" SITE "AH28"; +LOCATE COMP "FPGA4_CONNECTOR_6" SITE "AL29"; +LOCATE COMP "FPGA4_CONNECTOR_7" SITE "AK29"; + +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +LOCATE COMP "FPGA1_TTL_0" SITE "J21"; #202 #was F1_3V3_LINE etc. +LOCATE COMP "FPGA1_TTL_1" SITE "H22"; #204 +LOCATE COMP "FPGA1_TTL_2" SITE "A23"; #206 +LOCATE COMP "FPGA1_TTL_3" SITE "B23"; #208 +LOCATE COMP "FPGA2_TTL_0" SITE "E22"; #202 +LOCATE COMP "FPGA2_TTL_1" SITE "E23"; #204 +LOCATE COMP "FPGA2_TTL_2" SITE "C23"; #206 +LOCATE COMP "FPGA2_TTL_3" SITE "D23"; #208 +LOCATE COMP "FPGA3_TTL_0" SITE "K22"; #202 +LOCATE COMP "FPGA3_TTL_1" SITE "K21"; #204 +LOCATE COMP "FPGA3_TTL_2" SITE "A24"; #206 +LOCATE COMP "FPGA3_TTL_3" SITE "B24"; #208 +LOCATE COMP "FPGA4_TTL_0" SITE "G23"; #202 +LOCATE COMP "FPGA4_TTL_1" SITE "H23"; #204 +LOCATE COMP "FPGA4_TTL_2" SITE "D24"; #206 +LOCATE COMP "FPGA4_TTL_3" SITE "E24"; #208 +DEFINE PORT GROUP "FPGATTL_group" "*TTL*" ; +IOBUF GROUP "FPGATTL_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=8; + +################################################################# +# SFP Control / Status +################################################################# +LOCATE COMP "SFP_TX_FAULT_1" SITE "K23"; +LOCATE COMP "SFP_TX_FAULT_2" SITE "D21"; +LOCATE COMP "SFP_TX_FAULT_3" SITE "H19"; +LOCATE COMP "SFP_TX_FAULT_4" SITE "A18"; +LOCATE COMP "SFP_TX_FAULT_5" SITE "D25"; +LOCATE COMP "SFP_TX_FAULT_6" SITE "D27"; +LOCATE COMP "SFP_TX_FAULT_7" SITE "D20"; +LOCATE COMP "SFP_TX_FAULT_8" SITE "J19"; +LOCATE COMP "SFP_RATE_SEL_1" SITE "C25"; +LOCATE COMP "SFP_RATE_SEL_2" SITE "J22"; +LOCATE COMP "SFP_RATE_SEL_3" SITE "D19"; +LOCATE COMP "SFP_RATE_SEL_4" SITE "G19"; +LOCATE COMP "SFP_RATE_SEL_5" SITE "C27"; +LOCATE COMP "SFP_RATE_SEL_6" SITE "A29"; +LOCATE COMP "SFP_RATE_SEL_7" SITE "E16"; +LOCATE COMP "SFP_RATE_SEL_8" SITE "C20"; +LOCATE COMP "SFP_LOS_1" SITE "K24"; +LOCATE COMP "SFP_LOS_2" SITE "E21"; +LOCATE COMP "SFP_LOS_3" SITE "A19"; +LOCATE COMP "SFP_LOS_4" SITE "B18"; +LOCATE COMP "SFP_LOS_5" SITE "G26"; +LOCATE COMP "SFP_LOS_6" SITE "E27"; +LOCATE COMP "SFP_LOS_7" SITE "F21"; +LOCATE COMP "SFP_LOS_8" SITE "K19"; +LOCATE COMP "SFP_TXDIS_1" SITE "A25"; +LOCATE COMP "SFP_TXDIS_2" SITE "H20"; +LOCATE COMP "SFP_TXDIS_3" SITE "B19"; +LOCATE COMP "SFP_TXDIS_4" SITE "J18"; +LOCATE COMP "SFP_TXDIS_5" SITE "G25"; +LOCATE COMP "SFP_TXDIS_6" SITE "B28"; +LOCATE COMP "SFP_TXDIS_7" SITE "F22"; +LOCATE COMP "SFP_TXDIS_8" SITE "A20"; +LOCATE COMP "SFP_MOD0_1" SITE "B25"; +LOCATE COMP "SFP_MOD0_2" SITE "J20"; +LOCATE COMP "SFP_MOD0_3" SITE "K20"; +LOCATE COMP "SFP_MOD0_4" SITE "H18"; +LOCATE COMP "SFP_MOD0_5" SITE "C26"; +LOCATE COMP "SFP_MOD0_6" SITE "A28"; +LOCATE COMP "SFP_MOD0_7" SITE "A21"; +LOCATE COMP "SFP_MOD0_8" SITE "B20"; +LOCATE COMP "SFP_MOD1_1" SITE "C28"; +LOCATE COMP "SFP_MOD1_2" SITE "A22"; +LOCATE COMP "SFP_MOD1_3" SITE "L19"; +LOCATE COMP "SFP_MOD1_4" SITE "D18"; +LOCATE COMP "SFP_MOD1_5" SITE "D26"; +LOCATE COMP "SFP_MOD1_6" SITE "A26"; +LOCATE COMP "SFP_MOD1_7" SITE "B21"; +LOCATE COMP "SFP_MOD1_8" SITE "G20"; +LOCATE COMP "SFP_MOD2_1" SITE "D28"; +LOCATE COMP "SFP_MOD2_2" SITE "B22"; +LOCATE COMP "SFP_MOD2_3" SITE "C19"; +LOCATE COMP "SFP_MOD2_4" SITE "E18"; +LOCATE COMP "SFP_MOD2_5" SITE "B27"; +LOCATE COMP "SFP_MOD2_6" SITE "A27"; +LOCATE COMP "SFP_MOD2_7" SITE "F16"; +LOCATE COMP "SFP_MOD2_8" SITE "G21"; + +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 PULLMODE=UP; + +################################################################# +# Main AddOn Connector +################################################################# + +LOCATE COMP "ECL_IN_0" SITE "M25"; +LOCATE COMP "ECL_IN_1" SITE "M26"; +LOCATE COMP "ECL_IN_2" SITE "L26"; +LOCATE COMP "ECL_IN_3" SITE "N28"; +DEFINE PORT GROUP "ECL_IN_group" "ECL_IN*" ; +IOBUF GROUP "ECL_IN_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; + +LOCATE COMP "JIN1_0" SITE "R26"; +LOCATE COMP "JIN1_1" SITE "N26"; # was P26 +LOCATE COMP "JIN1_2" SITE "P28"; +LOCATE COMP "JIN1_3" SITE "K29"; +DEFINE PORT GROUP "JIN1_group" "JIN1*" ; +IOBUF GROUP "JIN1_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +LOCATE COMP "JIN2_0" SITE "R28"; # was R27 +LOCATE COMP "JIN2_1" SITE "R31"; # was R30 +LOCATE COMP "JIN2_2" SITE "U34"; +LOCATE COMP "JIN2_3" SITE "K34"; +DEFINE PORT GROUP "JIN2_group" "JIN2*" ; +IOBUF GROUP "JIN2_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +LOCATE COMP "JINLVDS_0" SITE "L32"; +LOCATE COMP "JINLVDS_1" SITE "L33"; +LOCATE COMP "JINLVDS_2" SITE "N32"; +LOCATE COMP "JINLVDS_3" SITE "M30"; +LOCATE COMP "JINLVDS_4" SITE "P32"; +LOCATE COMP "JINLVDS_5" SITE "R29"; +LOCATE COMP "JINLVDS_6" SITE "N31"; +LOCATE COMP "JINLVDS_7" SITE "P30"; +LOCATE COMP "JINLVDS_8" SITE "M31"; +LOCATE COMP "JINLVDS_9" SITE "P31"; +LOCATE COMP "JINLVDS_10" SITE "L31"; +LOCATE COMP "JINLVDS_11" SITE "L34"; +LOCATE COMP "JINLVDS_12" SITE "K31"; +LOCATE COMP "JINLVDS_13" SITE "K32"; +LOCATE COMP "JINLVDS_14" SITE "N30"; +LOCATE COMP "JINLVDS_15" SITE "N29"; +DEFINE PORT GROUP "JINLVDS_group" "JINLVDS*" ; +IOBUF GROUP "JINLVDS_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; + +LOCATE COMP "DISCRIMINATOR_IN_0" SITE "T32"; +LOCATE COMP "DISCRIMINATOR_IN_1" SITE "T30"; +DEFINE PORT GROUP "DISCRIMINATOR_group" "DISCRIMINATOR*" ; +IOBUF GROUP "DISCRIMINATOR_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF; + +LOCATE COMP "JOUT1_0" SITE "B4"; +LOCATE COMP "JOUT1_1" SITE "B3"; +LOCATE COMP "JOUT1_2" SITE "B1"; +LOCATE COMP "JOUT1_3" SITE "C3"; +DEFINE PORT GROUP "JOUT1_group" "JOUT1*" ; +IOBUF GROUP "JOUT1_group" IO_TYPE=LVDS25E; + +LOCATE COMP "JOUT2_0" SITE "D3"; +LOCATE COMP "JOUT2_1" SITE "E4"; +LOCATE COMP "JOUT2_2" SITE "D6"; +LOCATE COMP "JOUT2_3" SITE "B6"; +DEFINE PORT GROUP "JOUT2_group" "JOUT2*" ; +IOBUF GROUP "JOUT2_group" IO_TYPE=LVDS25E; + + +LOCATE COMP "JOUTLVDS_0" SITE "C11"; +LOCATE COMP "JOUTLVDS_1" SITE "D9"; +LOCATE COMP "JOUTLVDS_2" SITE "E11"; +LOCATE COMP "JOUTLVDS_3" SITE "F10"; +LOCATE COMP "JOUTLVDS_4" SITE "G11"; +LOCATE COMP "JOUTLVDS_5" SITE "H11"; +LOCATE COMP "JOUTLVDS_6" SITE "J14"; +LOCATE COMP "JOUTLVDS_7" SITE "J12"; +DEFINE PORT GROUP "JOUTLVDS_group" "JOUTLVDS*" ; +IOBUF GROUP "JOUTLVDS_group" IO_TYPE=LVDS25E ; + +LOCATE COMP "JTTL_0" SITE "D12"; +LOCATE COMP "JTTL_1" SITE "E12"; +LOCATE COMP "JTTL_2" SITE "A12"; +LOCATE COMP "JTTL_3" SITE "B12"; +LOCATE COMP "JTTL_4" SITE "A11"; +LOCATE COMP "JTTL_5" SITE "B11"; +LOCATE COMP "JTTL_6" SITE "A10"; +LOCATE COMP "JTTL_7" SITE "B10"; +LOCATE COMP "JTTL_8" SITE "B7"; +LOCATE COMP "JTTL_9" SITE "A7"; +LOCATE COMP "JTTL_10" SITE "B8"; +LOCATE COMP "JTTL_11" SITE "C8"; +LOCATE COMP "JTTL_12" SITE "A8"; +LOCATE COMP "JTTL_13" SITE "A9"; +LOCATE COMP "JTTL_14" SITE "K11"; +LOCATE COMP "JTTL_15" SITE "J11"; +DEFINE PORT GROUP "JTTL_group" "JTTL_{0:14}" ; +IOBUF GROUP "JTTL_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; +IOBUF PORT "JTTL_15" IO_TYPE=LVCMOS25 PULLMODE=DOWN; + +LOCATE COMP "LED_BANK_0" SITE "E13"; +LOCATE COMP "LED_BANK_1" SITE "F13"; +LOCATE COMP "LED_BANK_2" SITE "G13"; +LOCATE COMP "LED_BANK_3" SITE "H14"; +LOCATE COMP "LED_BANK_4" SITE "A13"; +LOCATE COMP "LED_BANK_5" SITE "B13"; +LOCATE COMP "LED_BANK_6" SITE "K16"; +LOCATE COMP "LED_BANK_7" SITE "L16"; +DEFINE PORT GROUP "LED_BANK_group" "LED_BANK*" ; +IOBUF GROUP "LED_BANK_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8; + +LOCATE COMP "LED_FAN_GREEN" SITE "T29"; +LOCATE COMP "LED_FAN_ORANGE" SITE "T34"; +LOCATE COMP "LED_FAN_RED" SITE "T28"; +LOCATE COMP "LED_FAN_YELLOW" SITE "U32"; +DEFINE PORT GROUP "LED_FAN_group" "LED_FAN*" ; +IOBUF GROUP "LED_FAN_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8; + +LOCATE COMP "LED_RJ_GREEN_0" SITE "M27"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "P33"; +LOCATE COMP "LED_RJ_GREEN_2" SITE "M34"; +LOCATE COMP "LED_RJ_GREEN_3" SITE "P34"; +LOCATE COMP "LED_RJ_GREEN_4" SITE "J17"; +LOCATE COMP "LED_RJ_GREEN_5" SITE "M28"; +LOCATE COMP "LED_RJ_RED_0" SITE "N27"; +LOCATE COMP "LED_RJ_RED_1" SITE "R34"; +LOCATE COMP "LED_RJ_RED_2" SITE "N34"; +LOCATE COMP "LED_RJ_RED_3" SITE "L28"; +LOCATE COMP "LED_RJ_RED_4" SITE "H17"; +LOCATE COMP "LED_RJ_RED_5" SITE "M29"; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVTTL33 DRIVE=8 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVTTL33 DRIVE=8 ; +IOBUF PORT "LED_RJ_GREEN_2" IO_TYPE=LVTTL33 DRIVE=8 ; +IOBUF PORT "LED_RJ_GREEN_3" IO_TYPE=LVTTL33 DRIVE=8 ; +IOBUF PORT "LED_RJ_GREEN_4" IO_TYPE=LVCMOS25 DRIVE=8 ; +IOBUF PORT "LED_RJ_GREEN_5" IO_TYPE=LVTTL33 DRIVE=8 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVTTL33 DRIVE=8 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVTTL33 DRIVE=8 ; +IOBUF PORT "LED_RJ_RED_2" IO_TYPE=LVTTL33 DRIVE=8 ; +IOBUF PORT "LED_RJ_RED_3" IO_TYPE=LVTTL33 DRIVE=8 ; +IOBUF PORT "LED_RJ_RED_4" IO_TYPE=LVCMOS25 DRIVE=8 ; +IOBUF PORT "LED_RJ_RED_5" IO_TYPE=LVTTL33 DRIVE=8 ; + +LOCATE COMP "NIM_IN_0" SITE "T26"; +LOCATE COMP "NIM_IN_1" SITE "U26"; +DEFINE PORT GROUP "NIM_group" "NIM*" ; +IOBUF GROUP "NIM_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; + +LOCATE COMP "PWM_OUT_0" SITE "U27"; +LOCATE COMP "PWM_OUT_1" SITE "U31"; +DEFINE PORT GROUP "PWM_group" "PWM*" ; +IOBUF GROUP "PWM_group" IO_TYPE=LVTTL33 DRIVE=8; + + +LOCATE COMP "TRG_FANOUT_ADDON" SITE "D5"; +IOBUF PORT "TRG_FANOUT_ADDON" IO_TYPE=LVDS25E ; + +# DEFINE PORT GROUP "ADO_LV_group" "ADO_LV*" ; +# IOBUF GROUP "ADO_LV_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8; +# DEFINE PORT GROUP "FS_PE_group" "FS_PE*" ; +# IOBUF GROUP "FS_PE_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8; +# DEFINE PORT GROUP "ADO_TTL_group" "ADO_TTL*" ; +# IOBUF GROUP "ADO_TTL_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8; +# IOBUF PORT "LED_RJ_RED_4" IO_TYPE=LVDS25 ; +# IOBUF PORT "TRB_TO_ADDON_CLK" IO_TYPE=LVCMOS25 ; +# IOBUF PORT "ADDON_RESET" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; + + +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "C30"; +LOCATE COMP "FLASH_CS" SITE "A31"; +LOCATE COMP "FLASH_DIN" SITE "B31"; +LOCATE COMP "FLASH_DOUT" SITE "C29"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "H25"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Test Connector (Order corrected to match pin-out of connector!) +################################################################# +LOCATE COMP "TEST_LINE_4" SITE "G4"; # "TEST_LINE_0" +LOCATE COMP "TEST_LINE_5" SITE "G5"; # "TEST_LINE_1" +LOCATE COMP "TEST_LINE_2" SITE "H5"; # "TEST_LINE_2" +LOCATE COMP "TEST_LINE_3" SITE "H4"; # "TEST_LINE_3" +LOCATE COMP "TEST_LINE_10" SITE "F2"; # "TEST_LINE_4" +LOCATE COMP "TEST_LINE_11" SITE "F1"; # "TEST_LINE_5" +LOCATE COMP "TEST_LINE_6" SITE "F3"; # "TEST_LINE_6" +LOCATE COMP "TEST_LINE_7" SITE "E3"; # "TEST_LINE_7" +LOCATE COMP "TEST_LINE_12" SITE "G2"; # "TEST_LINE_8" +LOCATE COMP "TEST_LINE_13" SITE "G1"; # "TEST_LINE_9" +LOCATE COMP "TEST_LINE_8" SITE "G3"; # "TEST_LINE_10" +LOCATE COMP "TEST_LINE_9" SITE "H3"; # "TEST_LINE_11" +LOCATE COMP "TEST_LINE_14" SITE "H1"; # "TEST_LINE_12" +LOCATE COMP "TEST_LINE_15" SITE "J1"; # "TEST_LINE_13" +LOCATE COMP "TEST_LINE_0" SITE "J3"; # "TEST_LINE_14" +LOCATE COMP "TEST_LINE_1" SITE "H2"; # "TEST_LINE_15" + +LOCATE COMP "TEST_LINE_20" SITE "K4"; # "TEST_LINE_16" +LOCATE COMP "TEST_LINE_21" SITE "K3"; # "TEST_LINE_17" +LOCATE COMP "TEST_LINE_26" SITE "K7"; # "TEST_LINE_18" +LOCATE COMP "TEST_LINE_27" SITE "J6"; # "TEST_LINE_19" +LOCATE COMP "TEST_LINE_16" SITE "K2"; # "TEST_LINE_20" +LOCATE COMP "TEST_LINE_17" SITE "K1"; # "TEST_LINE_21" +LOCATE COMP "TEST_LINE_30" SITE "L10"; # "TEST_LINE_22" +LOCATE COMP "TEST_LINE_31" SITE "L9"; # "TEST_LINE_23" +LOCATE COMP "TEST_LINE_18" SITE "L2"; # "TEST_LINE_24" +LOCATE COMP "TEST_LINE_19" SITE "L1"; # "TEST_LINE_25" +LOCATE COMP "TEST_LINE_28" SITE "M8"; # "TEST_LINE_26" +LOCATE COMP "TEST_LINE_29" SITE "L7"; # "TEST_LINE_27" +LOCATE COMP "TEST_LINE_22" SITE "L5"; # "TEST_LINE_28" +LOCATE COMP "TEST_LINE_23" SITE "L4"; # "TEST_LINE_29" +LOCATE COMP "TEST_LINE_24" SITE "K6"; # "TEST_LINE_30" +LOCATE COMP "TEST_LINE_25" SITE "K5"; # "TEST_LINE_31" + +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "D22"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + + + + + +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# +SYSCONFIG MCCLK_FREQ=20 ; + +FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ; +# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +#FREQUENCY PORT "CLK_GPLL_RIGHT" 125.000000 MHz ; +#FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ; +# FREQUENCY PORT CLK_EXT_3 10 MHz; +# FREQUENCY PORT CLK_EXT_4 10 MHz; + +FREQUENCY PORT "CLK_GPLL_RIGHT" 125.0 MHz; +FREQUENCY PORT "CLK_PCLK_RIGHT" 200.0 MHz; +FREQUENCY PORT "JINLVDS[0]" 200.0 MHz; +FREQUENCY NET "GEN_CTS.THE_CTS/cts_trigger_out" 100.0 MHz; +FREQUENCY NET "THE_MAIN_PLL/clk_200_i" 200.0 MHz; +FREQUENCY NET "THE_MAIN_PLL/clk_100_i_c" 100.0 MHz; +FREQUENCY NET "GEN_CBMNET.GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/clk_tx_full_i" 250.0 MHz; +FREQUENCY NET "GEN_CBMNET.GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR/CLK_RX_HALF_OUT_c" 125.0 MHz; +FREQUENCY NET "GEN_CBMNET.GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/CLK_RX_FULL_OUTz" 250.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch0" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch1" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch2" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch3" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_tx_ch" 100.0 MHz; +FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; +FREQUENCY NET "osc_int" 200.0 MHz; +FREQUENCY NET "GEN_TDC.GEN_TDC.THE_TDC/GEN_Channels.1.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; +FREQUENCY NET "GEN_TDC.GEN_TDC.THE_TDC/GEN_Channels.2.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; +FREQUENCY NET "GEN_TDC.GEN_TDC.THE_TDC/GEN_Channels.3.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; +FREQUENCY NET "GEN_TDC.GEN_TDC.THE_TDC/GEN_Channels.4.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; +FREQUENCY NET "GEN_TDC.GEN_TDC.THE_TDC/ReferenceChannel/Channel200/FSM_RD_STATE[2]" 100.0 MHz; + +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "GSR_N"; + +################################################################# +# Locate Serdes and media interfaces +################################################################# +#LOCATE COMP "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSB"; +LOCATE COMP "gen_single_sfp_THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_four_sfp_THE_MEDIA_UPLINK/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/PCSD_INST" SITE "PCSC" ; +LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ; + +UGROUP "THE_RESET_HANDLER_GRP" BLKNAME THE_RESET_HANDLER; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset[*]" 30.000000 ns ; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30.000000 ns ; + +#MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30.000000 ns ; + +#REGION "MEDIA_UPLINK" "R100C115D" 20 60 DEVSIZE; +#LOCATE UGROUP "gen_four_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +#LOCATE UGROUP "gen_single_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +#LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ; + + + + + + +#REGION "MEDIA_ONBOARD" "R90C122" 20 40; +#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "gen_single_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; +MULTICYCLE TO CELL "gen_four_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; +#SPI Interface + +REGION "REGION_SPI" "R9C95D" 20 20 DEVSIZE; +LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +#LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; +#REGION "REGION_CTS" "R42C2D" 37 57 DEVSIZE; +# UGROUP "cts_group" +# BLKNAME THE_CTS; +# LOCATE UGROUP "cts_group" REGION "REGION_CTS"; + +MULTICYCLE TO CELL "gen_mbs_vulom_as_etm.THE_MBS/trg_sync" 20.000000 ns ; +MULTICYCLE TO CELL "gen_mbs_vulom_as_etm.THE_MBS/error_reg" 20.000000 ns ; + +#TrbNet Hub +REGION "REGION_IOBUF" "R35C20D" 65 85 DEVSIZE; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; + +#GbE Part +UGROUP "tsmac" + BLKNAME GBE/imp_gen.MAC + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SGMII_GBE_PCS + BLKNAME GBE/rx_enable_gen.FRAME_RECEIVER + BLKNAME GBE/FRAME_TRANSMITTER; +UGROUP "controllers" + BLKNAME GBE/main_gen.MAIN_CONTROL + BLKNAME GBE/rx_enable_gen.RECEIVE_CONTROLLER + BLKNAME GBE/transmit_gen.TRANSMIT_CONTROLLER; +UGROUP "gbe_rx_tx" + BLKNAME GBE/FRAME_CONSTRUCTOR + BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG + BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR + BLKNAME GBE/setup_imp_gen.SETUP; + +#REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE; +#REGION "MED0" "R81C30D" 34 40 DEVSIZE; +#LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ; +#REGION "GBE_MAIN_REGION" "R50C64C" 65 64 DEVSIZE; +#LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ; +#LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ; + +UGROUP "sd_tx_to_pcs" + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[0] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[1] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[2] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[3] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[4] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[5] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[6] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[7] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q; +UGROUP "sd_rx_to_pcs" + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[0] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[1] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[2] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[3] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[4] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[5] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[6] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[7] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q; +UGROUP "pcs_tx_to_mac" + BLKNAME GBE/pcs_tx_en_q + BLKNAME GBE/pcs_tx_en_qq + BLKNAME GBE/pcs_tx_er_q + BLKNAME GBE/pcs_tx_er_qq + BLKNAME GBE/pcs_txd_q[0] + BLKNAME GBE/pcs_txd_q[1] + BLKNAME GBE/pcs_txd_q[2] + BLKNAME GBE/pcs_txd_q[3] + BLKNAME GBE/pcs_txd_q[4] + BLKNAME GBE/pcs_txd_q[5] + BLKNAME GBE/pcs_txd_q[6] + BLKNAME GBE/pcs_txd_q[7] + BLKNAME GBE/pcs_txd_qq[0] + BLKNAME GBE/pcs_txd_qq[1] + BLKNAME GBE/pcs_txd_qq[2] + BLKNAME GBE/pcs_txd_qq[3] + BLKNAME GBE/pcs_txd_qq[4] + BLKNAME GBE/pcs_txd_qq[5] + BLKNAME GBE/pcs_txd_qq[6] + BLKNAME GBE/pcs_txd_qq[7]; +UGROUP "pcs_rx_to_mac" + BLKNAME GBE/pcs_rx_en_q + BLKNAME GBE/pcs_rx_en_qq + BLKNAME GBE/pcs_rx_er_q + BLKNAME GBE/pcs_rx_er_qq + BLKNAME GBE/pcs_rxd_q[0] + BLKNAME GBE/pcs_rxd_q[1] + BLKNAME GBE/pcs_rxd_q[2] + BLKNAME GBE/pcs_rxd_q[3] + BLKNAME GBE/pcs_rxd_q[4] + BLKNAME GBE/pcs_rxd_q[5] + BLKNAME GBE/pcs_rxd_q[6] + BLKNAME GBE/pcs_rxd_q[7] + BLKNAME GBE/pcs_rxd_qq[0] + BLKNAME GBE/pcs_rxd_qq[1] + BLKNAME GBE/pcs_rxd_qq[2] + BLKNAME GBE/pcs_rxd_qq[3] + BLKNAME GBE/pcs_rxd_qq[4] + BLKNAME GBE/pcs_rxd_qq[5] + BLKNAME GBE/pcs_rxd_qq[6] + BLKNAME GBE/pcs_rxd_qq[7]; + +UGROUP "GBE_SERDES_group" BBOX 10 67 + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES; +LOCATE UGROUP "GBE_SERDES_group" SITE "R105C17D" ; + +MAXDELAY NET "GBE/pcs_rx_e?_q" 1.500000 nS ; +MAXDELAY NET "GBE/pcs_rxd_q[?]" 1.500000 nS ; + +DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q" + "GBE/pcs_rx_er_q" + "GBE/pcs_rxd_q*"; +INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ; + +PRIORITIZE NET "GBE/pcs_rx_en_q" 100 ; +PRIORITIZE NET "GBE/pcs_rx_er_q" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[1]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[2]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[3]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[4]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[5]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; +PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ; + +#BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_tx_mac*" ; +#BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_rx_mac*" ; + +LOCATE UGROUP "CBMNET_PHY_GROUP" SITE "R100C118D"; +LOCATE UGROUP "CBMNET_BRIDGE_GROUP" SITE "R42C106D"; +LOCATE COMP "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSA" ; + + +UGROUP "THE_MEDIA_ONBOARD_GROUP" BBOX 25 45 + BLKNAME THE_MEDIA_ONBOARD; +LOCATE UGROUP "THE_MEDIA_ONBOARD_GROUP" SITE "R98C75D" ; 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