From: Your Name <you@example.com>
Date: Tue, 29 Jun 2021 04:36:18 +0000 (+0200)
Subject: xfer_clk
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=refs%2Fheads%2Fcracow_devel;p=clocked_tdc.git

xfer_clk
---

diff --git a/release.v b/release.v
index 56699fc..79c7cff 100644
--- a/release.v
+++ b/release.v
@@ -2,11 +2,14 @@
 COMPONENT ctdc_channel_raw_out is PORT
 										(
 										reset_in: 	IN STD_LOGIC;	--active high
-										pll_clks_in: IN STD_LOGIC_VECTOR(3 downto 0);	-- 0, 45, 90, 135 phase shifted
+										pll_clks_in: IN STD_LOGIC_VECTOR(3 downto 0);	-- 0, 45, 90, 135 phase shifted
+										xfer_clk_in: 	IN STD_LOGIC;
 										coarse_reset_in: 	IN STD_LOGIC;	--active rising edge 
 										signal_in:	IN STD_LOGIC;				--idle low
 										data_out:	OUT STD_LOGIC_VECTOR(23 downto 0);	--output on rising edge of pll_clks_in[0] 
-										data_valid_out:	OUT STD_LOGIC	--active high; output on rising edge of pll_clks_in[0] 
+										data_valid_out:	OUT STD_LOGIC	--active high; using rising edge of pll_clks_in[0] 
+										xfer_data_out:	OUT STD_LOGIC_VECTOR(23 downto 0);	--output on rising edge of xfer_clk
+										xfer_data_valid_out:	OUT STD_LOGIC	--active high; using rising edge of xfer_clk
 										pos_ready:	OUT STD_LOGIC;				--debug; leave open
 										neg_ready:	OUT STD_LOGIC;				--debug; leave open
 										coarse:	OUT STD_LOGIC_VECTOR(8 downto 0);	--debug; leave open
@@ -22,11 +25,14 @@ END COMPONENT;
 
 module ctdc_channel_raw_out (
 										reset_in, 
-										pll_clks_in, 
+										pll_clks_in, 
+										xfer_clk_in,
 										coarse_reset_in, 
 										signal_in,
 										data_out,
 										data_valid_out,
+										xfer_data_out,
+										xfer_data_valid_out,
 										pos_ready,
 										neg_ready,
 										coarse,
@@ -38,7 +44,8 @@ module ctdc_channel_raw_out (
 	parameter TDC_WIDTH = 3;
 
 	input wire reset_in;
-	input wire [3:0]pll_clks_in;
+	input wire [3:0]pll_clks_in;
+	input wire xfer_clk_in;
 	input wire signal_in;
 	input wire coarse_reset_in;
 	output wire pos_ready;
@@ -52,7 +59,9 @@ module ctdc_channel_raw_out (
 	wire [7:0]tdc_single;
 	wire tdc_single_valid;
 	output reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]data_out;
-	output reg data_valid_out;
+	output reg data_valid_out;
+	output reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]xfer_data_out;
+	output reg xfer_data_valid_out;
 	wire [1:0]raw_valid_vect;
 	
 	wire signal_gate /* synthesis syn_preserve= 1*/;
@@ -157,7 +166,34 @@ ctdc_enc_pos ctdc_enc_pos_inst(
 				data_valid_out <= 'b0;
 			end
 		end
-end
+	end
+	
+	reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]slow_buf;
+	reg [3:0] slow_valid_dl;
+	wire slow_valid;
+	assign slow_valid = |slow_valid_dl[3:2];
+	
+	always @(posedge xfer_clk_in)begin
+		if(slow_valid)begin
+			xfer_data_out <= slow_buf;
+			xfer_data_valid_out <= 1'b1;
+		end else begin
+			xfer_data_valid_out <= 1'b0;
+		end
+	end
+	
+	always @(posedge pll_clks_in[0])begin
+		if(data_valid_out & !(|slow_valid_dl))begin
+			slow_buf <= data_out;
+			slow_valid_dl[0] <= 1'b1;
+		end else begin
+			slow_valid_dl[0] <= 1'b0;
+		end
+	end
+
+	always @(posedge pll_clks_in[0])begin
+		slow_valid_dl[3:1] <= slow_valid_dl[2:0];
+	end
 
 endmodule