From: Benedikt Gutsche <b.gutsche@gsi.de>
Date: Mon, 2 Jun 2025 12:20:26 +0000 (+0200)
Subject: updated lattice pahts
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=refs%2Fheads%2Fmaster;p=logicbox.git

updated lattice pahts
---

diff --git a/default/config_compile_frankfurt.pl b/default/config_compile_frankfurt.pl
old mode 100644
new mode 100755
index deab44c..05cc9f5
--- a/default/config_compile_frankfurt.pl
+++ b/default/config_compile_frankfurt.pl
@@ -6,8 +6,8 @@ Speedgrade  => '5',
 TOPNAME                      => "logicbox",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.12',
-synplify_path                => '/d/jspc29/lattice/synplify/S-2021.09-SP2/',
+lattice_path                 => '/d/jspc29/lattice/diamond/3.14',
+synplify_path                => '/d/jspc29/lattice/synplify/W-2024.09',
 # synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
 # synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 # synplify_command             => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
diff --git a/default/logicbox.lpf b/default/logicbox.lpf
new file mode 100644
index 0000000..4b51d4b
--- /dev/null
+++ b/default/logicbox.lpf
@@ -0,0 +1,48 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+SYSCONFIG MCCLK_FREQ=133 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE JTAG_PORT=DISABLE MUX_CONFIGURATION_PORTS=ENABLE ;
+LOCATE COMP "OUTPUT[2]" SITE "A6" ;
+LOCATE COMP "OUTPUT[3]" SITE "C5" ;
+LOCATE COMP "OUTPUT[0]" SITE "B4" ;
+LOCATE COMP "OUTPUT[1]" SITE "B5" ;
+LOCATE COMP "CONTROLI" SITE "B1" ;
+LOCATE COMP "CONTROLO" SITE "A1" ;
+LOCATE COMP "LED[0]" SITE "A7" ;
+LOCATE COMP "LED[1]" SITE "E5" ;
+LOCATE COMP "LED[2]" SITE "C1" ;
+LOCATE COMP "LED[3]" SITE "B2" ;
+LOCATE COMP "INPUT[0]" SITE "F7" ;
+LOCATE COMP "INPUT[2]" SITE "G7" ;
+LOCATE COMP "INPUT[3]" SITE "F4" ;
+LOCATE COMP "INPUT[1]" SITE "F3" ;
+LOCATE COMP "RX_OUT" SITE "F1" ;
+LOCATE COMP "TX_IN" SITE "C4" ;
+LOCATE COMP "CBUS" SITE "C3" ;
+LOCATE COMP "CLK" SITE "G4" ;
+LOCATE COMP "STATUSO" SITE "G2" ;
+LOCATE COMP "STATUSI" SITE "G1" ;
+IOBUF PORT "INPUT[0]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[1]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[2]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[3]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "CONTROLI" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CONTROLO" IO_TYPE=LVTTL33 ;
+IOBUF PORT "LED[0]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[1]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[2]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[3]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "OUTPUT[0]" IO_TYPE=LVTTL33 SLEWRATE=FAST DRIVE=16 ;
+IOBUF PORT "OUTPUT[1]" IO_TYPE=LVTTL33 SLEWRATE=FAST DRIVE=16 ;
+IOBUF PORT "OUTPUT[2]" IO_TYPE=LVTTL33 SLEWRATE=FAST DRIVE=16 ;
+IOBUF PORT "OUTPUT[3]" IO_TYPE=LVTTL33 SLEWRATE=FAST DRIVE=16 ;
+IOBUF PORT "RX_OUT" IO_TYPE=LVTTL33 ;
+IOBUF PORT "TX_IN" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CBUS" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CLK" IO_TYPE=LVDS25 ;
+IOBUF PORT "STATUSO" IO_TYPE=LVTTL33 ;
+IOBUF PORT "STATUSI" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+BANK 0 VCCIO 3.3 V;
+BANK 5 VCCIO 3.3 V;
+BANK 2 VCCIO 3.3 V;
+FREQUENCY PORT "CLK" 100.000000 MHz ;
+FREQUENCY NET "clk_osc" 133.000000 MHz ;
diff --git a/default/logicbox.prj b/default/logicbox.prj
index 00785f8..2d7a6f9 100644
--- a/default/logicbox.prj
+++ b/default/logicbox.prj
@@ -4,7 +4,7 @@
 
 #project files
 
-add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.12/cae_library/synthesis/vhdl/machxo3lf.vhd"
+add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.14/cae_library/synthesis/vhdl/machxo3lf.vhd"
 
 #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"