From: Jan Michel Date: Tue, 24 Jan 2017 17:21:58 +0000 (+0100) Subject: Update repository with older changes to ASD8 read-out X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;p=mdcfee.git Update repository with older changes to ASD8 read-out --- diff --git a/code/ffarray.vhd b/code/ffarray.vhd index a121f5f..d662a46 100644 --- a/code/ffarray.vhd +++ b/code/ffarray.vhd @@ -15,7 +15,6 @@ entity ffarray is RESET_IN : in std_logic; SIGNAL_IN : in std_logic_vector(CHANNELS-1 downto 0); - SELECT_IN : in std_logic_vector(3 downto 0); DATA_OUT : out std_logic_vector(31 downto 0); READ_IN : in std_logic := '0'; EMPTY_OUT : out std_logic := '0' @@ -150,14 +149,15 @@ PROC_BUFFER : process begin buffer_empty_0(c) <= '0'; end if; end if; + if buffer_read(c) = '1' then + buffer_empty_1(c) <= '1'; + end if; if buffer_empty_0(c) = '0' and buffer_empty_1(c) = '1' then buffer_data(c)(1) <= buffer_data(c)(0); buffer_empty_0(c) <= '1'; buffer_empty_1(c) <= '0'; end if; - if buffer_read(c) = '1' then - buffer_empty_1(c) <= '1'; - end if; + end process; @@ -167,7 +167,6 @@ process variable chan : integer range 0 to 16 := 0; begin wait until rising_edge(CLK); --- chan := to_integer(unsigned(SELECT_IN)); fifo_real_write <= '0'; buffer_read <= (others => '0'); if buffer_empty_1(chan) = '0' then diff --git a/code/uart_sctrl.vhd b/code/uart_sctrl.vhd index 1f0ff38..8cc20bb 100644 --- a/code/uart_sctrl.vhd +++ b/code/uart_sctrl.vhd @@ -184,13 +184,13 @@ PROC_TX : process begin when SEND_TERM=> if tx_ready = '1' then tx_send <= '1'; - txbuf <= x"0a"; + txbuf <= x"0d"; txstate <= SEND_FINISH; end if; when SEND_FINISH=> if tx_ready = '1' then tx_send <= '1'; - txbuf <= x"0d"; + txbuf <= x"0a"; txstate <= SEND_WAIT; end if; when SEND_WAIT => diff --git a/mboasd8/mbo.lpf b/mboasd8/mbo.lpf index 461cad7..8167296 100644 --- a/mboasd8/mbo.lpf +++ b/mboasd8/mbo.lpf @@ -314,7 +314,7 @@ LOCATE UGROUP "ffarrTgroupA" REGION "FFARRTA"; LOCATE UGROUP "ffarrTgroupB" REGION "FFARRTB"; - +BLOCK PATH FROM CELL "PROC_REGS.input_disable[*]"; USE PRIMARY NET "THE_TDC/CLKa*"; USE PRIMARY NET "THE_TDC_CLKa*"; diff --git a/mboasd8/mbo.vhd b/mboasd8/mbo.vhd index aa6fd3b..3bf62e4 100644 --- a/mboasd8/mbo.vhd +++ b/mboasd8/mbo.vhd @@ -63,7 +63,7 @@ architecture arch of mbo is signal pwm_addr_i : std_logic_vector(4 downto 0); signal input_hold : std_logic_vector(7 downto 0); - signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(7 downto 0); + signal input_reg_0, input_reg_1, input_reg_2, input_i : std_logic_vector(7 downto 0); -- signal edge_rising, edge_falling : std_logic_vector(3 downto 0); -- signal pulser : std_logic; @@ -72,7 +72,7 @@ architecture arch of mbo is signal timer_i : unsigned(31 downto 0) := (others => '0'); signal led_highz : std_logic; - type led_timer_t is array(0 to 3) of unsigned(5 downto 0); + type led_timer_t is array(0 to 3) of unsigned(7 downto 0); signal led_timer : led_timer_t; signal led_state : std_logic_vector(3 downto 0); signal led_clk_en : std_logic; @@ -82,6 +82,8 @@ architecture arch of mbo is signal select_i : std_logic_vector(3 downto 0); signal readcounter : unsigned(15 downto 0); signal uart_debug : std_logic_vector(15 downto 0); + signal input_disable : std_logic_vector(7 downto 0); + begin clk_i <= CLK; @@ -126,7 +128,8 @@ PROC_REGS : process begin case uart_addr is when x"00" => uart_tx_data <= x"000000" & config & config_reg; when x"01" => uart_tx_data <= x"00000" & "00" & CBUS & TRG & input_reg_2; --- when x"10" => uart_tx_data <= reg; + when x"11" => + uart_tx_data <= x"000000" & input_disable; when x"d0" => f_read <= '1'; bus_ready <= '0'; @@ -142,8 +145,8 @@ PROC_REGS : process begin case uart_addr is when x"00" => config_reg <= uart_rx_data(3 downto 0); - when x"10" => - select_i <= uart_rx_data(3 downto 0); + when x"11" => + input_disable <= uart_rx_data(7 downto 0); when x"80" => pwm_write_i <= '1'; pwm_data_i <= uart_rx_data(15 downto 0); @@ -209,7 +212,7 @@ input_reg_2 <= input_reg_1 when rising_edge(clk_i); input_hold <= INPUT or (input_hold and not input_reg_0); - +input_i <= INPUT and not input_disable; --------------------------------------------------------------------------- -- Input Counter @@ -234,17 +237,14 @@ THE_TDC : entity work.ffarray port map( CLK => clk_i, RESET_IN => '0', - SIGNAL_IN(7 downto 0) => INPUT(7 downto 0), + SIGNAL_IN(7 downto 0) => input_i(7 downto 0), SIGNAL_IN(8) => TRG, - SELECT_IN => select_i, DATA_OUT => f_data, READ_IN => f_read, EMPTY_OUT => f_empty ); - - --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- @@ -259,17 +259,17 @@ THE_TDC : entity work.ffarray PROC_LED_STATE : process begin wait until rising_edge(clk_i); - if timer_i(18 downto 0) = 0 then + if timer_i(15 downto 0) = 0 then led_clk_en <= '1'; else led_clk_en <= '0'; end if; for i in 0 to 3 loop - if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(4 downto 2) > 0) then + if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(7 downto 5) > 0) then led_state(i) <= not led_state(i); led_timer(i) <= 0; - elsif led_timer(i)(4) = '1' then + elsif led_timer(i)(7) = '1' then led_state(i) <= input_reg_1(i); elsif led_clk_en = '1' then led_timer(i) <= led_timer(i) + 1; @@ -300,7 +300,7 @@ LED <= led_i when led_highz = '0' else - +-- -- THE_SED : entity work.sedcheck -- port map( -- CLK => clk_i, diff --git a/mboasd8/par.p2t b/mboasd8/par.p2t index 39a0684..9386a1c 100644 --- a/mboasd8/par.p2t +++ b/mboasd8/par.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 1 +-t 3 -c 1 -e 2 #-g guidefile.ncd