From: Jan Michel <j.michel@gsi.de>
Date: Wed, 5 Sep 2018 15:59:49 +0000 (+0200)
Subject: fix syntax for LEDs in padiwa amps 2
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;p=padiwa.git

fix syntax for LEDs in padiwa amps 2
---

diff --git a/amps2/padiwa_amps2.vhd b/amps2/padiwa_amps2.vhd
index 7a4a4a9..2d58c64 100644
--- a/amps2/padiwa_amps2.vhd
+++ b/amps2/padiwa_amps2.vhd
@@ -362,7 +362,7 @@ THE_PWM_GEN : entity work.pwm_generator
 --    wait until rising_edge(clk_i);
     wait until rising_edge(clk_66);
     for i in 1 to 8 loop
-      if (last_inp((i-1)*2) xor inp_status((i-1)*2) = '1' and (led_timer(i)(23 downto 21) > 0) then
+      if (last_inp((i-1)*2) xor inp_status((i-1)*2)) = '1' and (led_timer(i)(23 downto 21) > 0) then
         led_state(i) <= not led_state(i);
         led_timer(i) <= 0;
       elsif led_timer(i)(23) = '1' then
@@ -374,7 +374,7 @@ THE_PWM_GEN : entity work.pwm_generator
   end process;  
 
 gen_leds : for i in 1 to 8 generate
-  LED(i) <= not leds((i-1)*2) when led_status(8) = '1' else not led_status(i-1);
+  LED(i) <= not led_state(i) when led_status(8) = '1' else not led_status(i-1);
 end generate;
 
   
@@ -453,9 +453,9 @@ last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);
 -- Test Output
 ---------------------------------------------------------------------------  
   --TEST_LINE(7 downto 0)  <= selected_delay;
-  TEST_LINE(13) <= SPI_CLK;
-  TEST_LINE(12) <= SPI_out;
-  TEST_LINE(11) <= SPI_in;
+--   TEST_LINE(13) <= SPI_CLK;
+--   TEST_LINE(12) <= SPI_out;
+--   TEST_LINE(11) <= SPI_in;
   
   TEST_LINE(10 downto 8) <= (others => '0');
 end architecture;