From: Jan Michel <michel@physik.uni-frankfurt.de>
Date: Thu, 4 Apr 2024 13:48:48 +0000 (+0200)
Subject: add reload port to SEDcheck
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;p=vhdlbasics.git

add reload port to SEDcheck
---

diff --git a/ecp5/sedcheck.vhd b/ecp5/sedcheck.vhd
index 46f6b9d..062a1f1 100644
--- a/ecp5/sedcheck.vhd
+++ b/ecp5/sedcheck.vhd
@@ -13,6 +13,7 @@ entity sedcheck is
   port(
     CLK        : in std_logic;
     ERROR_OUT  : out std_logic;
+    RELOAD_OUT : out std_logic := '0';
     
     BUS_RX     : in  CTRLBUS_RX;
     BUS_TX     : out CTRLBUS_TX;
@@ -23,26 +24,9 @@ end entity;
 
 architecture sed_arch of sedcheck is
  
-  component SEDCA
-    generic (
-      OSC_DIV : integer :=4 ;
-      CHECKALWAYS : string :="DISABLED";
-      AUTORECONFIG: string :="OFF" ;
-      MCCLK_FREQ : string :="20" ;
-      DEV_DENSITY : string :="150K" 
-      );
-    port (
-      SEDENABLE : in std_logic;
-      SEDSTART : in std_logic;
-      SEDFRCERR : in std_logic;
-      SEDERR : out std_logic;
-      SEDDONE : out std_logic;
-      SEDINPROG : out std_logic;
-      SEDCLKOUT : out std_logic
-      );
-  end component;  
+
  
-  type state_t is (IDLE, INIT_1, INIT_2, INIT_3, START_1, START_2, WAITACTIVE, WAITDONE);
+  type state_t is (IDLE, INIT_1, INIT_2, INIT_3, START_1, START_2, WAITACTIVE, WAITDONE, SLEEP_FOR_REBOOT);
   signal state          : state_t;
   signal state_bits     : std_logic_vector(3 downto 0);
 
@@ -61,12 +45,13 @@ architecture sed_arch of sedcheck is
   signal sed_error_q      : std_logic;
   signal sed_inprogress_q : std_logic;
 
-  signal control_i      : std_logic_vector(31 downto 0) := (others => '0');
+  signal control_i      : std_logic_vector(7 downto 0) := (others => '0');
   signal status_i       : std_logic_vector(31 downto 0);
   
   signal run_counter    : unsigned(7 downto 0) := (others => '0');
   signal error_counter  : unsigned(7 downto 0) := (others => '0');
   signal timer          : unsigned(5 downto 0);
+  signal longtimer      : unsigned(20  downto 0);
   
 begin
 
@@ -91,13 +76,13 @@ proc_reg : process begin
   if BUS_RX.write = '1' then
     BUS_TX.ack <= '1';
     case BUS_RX.addr(1 downto 0) is
-      when "00"   => control_i <= BUS_RX.data;
+      when "00"   => control_i <= BUS_RX.data(7 downto 0);
       when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
     end case;
   elsif BUS_RX.read = '1' then
     BUS_TX.ack <= '1';
     case BUS_RX.addr(1 downto 0) is
-      when "00"   => BUS_TX.data <= control_i;
+      when "00"   => BUS_TX.data <= x"000000" & control_i;
       when "01"   => BUS_TX.data <= status_i;
       when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
     end case;
@@ -110,6 +95,9 @@ end process;
 proc_ctrl : process begin
   wait until rising_edge(CLK);
   timer <= timer + 1;
+  longtimer <= (others => '0');
+  RELOAD_OUT <= '0';
+  
   case state is
     when IDLE =>
       sed_enable   <= '0';
@@ -141,6 +129,7 @@ proc_ctrl : process begin
       sed_start    <= '0';
       if sed_edge = '1' then
         state      <= START_2;
+        timer <= (0 => '1', others => '0');
       end if;
     when START_2 =>      
       sed_enable   <= '1';
@@ -148,6 +137,9 @@ proc_ctrl : process begin
       if sed_edge = '1' and sed_inprogress_q = '1' then
         state      <= WAITACTIVE;
       end if;
+      if timer = 0 then  --force restart if fails to start
+        state      <= IDLE;
+      end if;
     when WAITACTIVE =>
       sed_enable   <= '1';
       sed_start    <= '0';
@@ -162,8 +154,23 @@ proc_ctrl : process begin
         run_counter <= run_counter + 1;
         if sed_error_q = '1' then
           error_counter <= error_counter + 1;
+          if control_i(1) = '1' then
+            state      <= SLEEP_FOR_REBOOT;
+            RELOAD_OUT <= sed_error_q;
+          end if;  
         end if;
       end if;
+    when SLEEP_FOR_REBOOT =>
+      sed_enable   <= '0';
+      sed_start    <= '0';
+      if timer = 0 then
+        longtimer <= longtimer + 1;
+      else
+        longtimer <= longtimer;
+      end if;
+      if longtimer(longtimer'left) = '1' then
+        state       <= INIT_1;
+      end if;
   end case;
   
   if control_i(0) = '0' then
@@ -199,7 +206,7 @@ status_i(15 downto 11) <= (others => '0');
 status_i(23 downto 16) <= std_logic_vector(run_counter);
 status_i(31 downto 24) <= std_logic_vector(error_counter);
               
-ERROR_OUT <= sed_error;              
+ERROR_OUT <= sed_error_q;              
 DEBUG     <= status_i when rising_edge(CLK);
 
 ---------------------------------------------------------------------------
@@ -208,7 +215,7 @@ DEBUG     <= status_i when rising_edge(CLK);
 THE_SED : SEDGA
   generic map(
       CHECKALWAYS  => "DISABLED",
-      SED_CLK_FREQ   => "38.8",
+      SED_CLK_FREQ   => "19.4",
       DEV_DENSITY  => FPGA_SIZE --"85KUM" 
       )
   port map(