]>
jspc29.x-matter.uni-frankfurt.de Git - trb3.git/log
Andreas Neiser [Mon, 22 Apr 2013 17:11:46 +0000 (19:11 +0200)]
Switch to Mainz A2 as ETM
Andreas Neiser [Mon, 22 Apr 2013 17:04:34 +0000 (19:04 +0200)]
Integrate another trigger recv, but still use MBS VULOM by default
Andreas Neiser [Mon, 22 Apr 2013 16:03:34 +0000 (18:03 +0200)]
Fixed correct timeout, should be 50000 cycles=500us
Andreas Neiser [Mon, 22 Apr 2013 11:46:31 +0000 (13:46 +0200)]
Added compile script which seems to work on lxhadeb07
Andreas Neiser [Mon, 22 Apr 2013 09:01:13 +0000 (11:01 +0200)]
Added trigger receiver for Mainz A2
Cahit [Mon, 22 Apr 2013 14:27:55 +0000 (16:27 +0200)]
added some pins for the sfp - cu
Jan Michel [Mon, 22 Apr 2013 12:24:33 +0000 (14:24 +0200)]
changed CTS TDC to version 1.4
Cahit [Mon, 22 Apr 2013 12:03:09 +0000 (14:03 +0200)]
providing compatibility for previous designs - cu
Cahit [Thu, 18 Apr 2013 14:22:56 +0000 (16:22 +0200)]
edited for the tdc_v1.4 - cu
Cahit [Thu, 18 Apr 2013 14:22:14 +0000 (16:22 +0200)]
constraints script is added - cu
Cahit [Thu, 18 Apr 2013 12:49:22 +0000 (14:49 +0200)]
Merge branch release 'tdc_v1.4'
Cahit [Thu, 18 Apr 2013 12:48:01 +0000 (14:48 +0200)]
tdc_v1.4 is released. For details see tdc_releases/ReleaseNotes.txt - cu
Cahit [Thu, 18 Apr 2013 07:17:18 +0000 (09:17 +0200)]
compile_constraints.pl scripts are added - cu
Cahit [Thu, 18 Apr 2013 07:15:45 +0000 (09:15 +0200)]
data trasfer limit is implemented - cu
Cahit [Wed, 17 Apr 2013 09:36:48 +0000 (11:36 +0200)]
Work on release v1.4 has started - cu
Jan Michel [Tue, 16 Apr 2013 09:49:44 +0000 (11:49 +0200)]
Merge branch 'master' of jspc29:trb3
Jan Michel [Tue, 16 Apr 2013 09:49:38 +0000 (11:49 +0200)]
moved CTS module to CTS directory
Ludwig Maier [Mon, 15 Apr 2013 21:44:44 +0000 (23:44 +0200)]
update
Ludwig Maier [Mon, 15 Apr 2013 21:40:55 +0000 (23:40 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Ludwig Maier [Mon, 15 Apr 2013 21:40:39 +0000 (23:40 +0200)]
nxyter adc is delivering data so far
Hadaq in Frankfurt [Wed, 10 Apr 2013 13:24:05 +0000 (15:24 +0200)]
Merge branch 'master' of jspc29:trb3
Hadaq in Frankfurt [Wed, 10 Apr 2013 13:23:57 +0000 (15:23 +0200)]
removed soda files from TRB3 repository
Ludwig Maier [Tue, 9 Apr 2013 12:43:05 +0000 (14:43 +0200)]
no more fifo9to36 stuff in nx_timestamp_fifo_read, updates...
Hadaq in Frankfurt [Mon, 8 Apr 2013 16:05:10 +0000 (18:05 +0200)]
Merge branch 'master' of jspc29:trb3
Conflicts:
Hadaq in Frankfurt [Mon, 8 Apr 2013 16:02:36 +0000 (18:02 +0200)]
almost final version of soda_source, JM
Manuel Penschuck [Fri, 5 Apr 2013 11:49:32 +0000 (13:49 +0200)]
Symbolic links required to embed gbe
Hadaq in Frankfurt [Thu, 4 Apr 2013 21:24:08 +0000 (23:24 +0200)]
Bugfix: Reset of signal in wrong process causes multiple drivers
Hadaq in Frankfurt [Thu, 4 Apr 2013 21:23:11 +0000 (23:23 +0200)]
Added FF to time-reference signal
Cahit [Thu, 4 Apr 2013 12:32:55 +0000 (14:32 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Thu, 4 Apr 2013 12:32:20 +0000 (14:32 +0200)]
pin assignment correction - cu
Cahit [Thu, 4 Apr 2013 09:23:02 +0000 (11:23 +0200)]
New front end porject for the cbmtof detector designed by Jochen Fruehauf - cu
Ludwig Maier [Thu, 4 Apr 2013 02:00:39 +0000 (04:00 +0200)]
migrated nxyter to git
hadeshyp [Thu, 28 Mar 2013 18:08:07 +0000 (18:08 +0000)]
latest changes, JM
hadeshyp [Wed, 27 Mar 2013 23:34:21 +0000 (23:34 +0000)]
new nxyter data input stage, JM
hadeshyp [Wed, 27 Mar 2013 23:31:35 +0000 (23:31 +0000)]
new nxyter data input stage, JM
hadaq [Wed, 27 Mar 2013 22:24:40 +0000 (22:24 +0000)]
update
hadeshyp [Wed, 27 Mar 2013 19:09:03 +0000 (19:09 +0000)]
new DQS block, ADC changed
hadeshyp [Wed, 27 Mar 2013 19:08:37 +0000 (19:08 +0000)]
*** empty log message ***
hadeshyp [Wed, 27 Mar 2013 19:08:26 +0000 (19:08 +0000)]
*** empty log message ***
hadaq [Wed, 27 Mar 2013 17:57:38 +0000 (17:57 +0000)]
hmmm
hadaq [Wed, 27 Mar 2013 17:56:38 +0000 (17:56 +0000)]
hmmmm
hadaq [Wed, 27 Mar 2013 17:56:15 +0000 (17:56 +0000)]
hmmmm
hadeshyp [Wed, 27 Mar 2013 17:38:31 +0000 (17:38 +0000)]
*** empty log message ***
hadaq [Wed, 27 Mar 2013 17:34:24 +0000 (17:34 +0000)]
update
hadeshyp [Wed, 27 Mar 2013 17:26:33 +0000 (17:26 +0000)]
*** empty log message ***
hadeshyp [Wed, 27 Mar 2013 17:22:36 +0000 (17:22 +0000)]
*** empty log message ***
hadeshyp [Wed, 27 Mar 2013 13:33:13 +0000 (13:33 +0000)]
added clockmanager.
hadeshyp [Wed, 27 Mar 2013 13:32:38 +0000 (13:32 +0000)]
added mvd lpf.
hadaq [Wed, 27 Mar 2013 08:51:49 +0000 (08:51 +0000)]
bitfiles - cu
hadaq [Wed, 27 Mar 2013 08:23:52 +0000 (08:23 +0000)]
debug bus addresses are added - cu
hadaq [Wed, 27 Mar 2013 08:21:35 +0000 (08:21 +0000)]
unnecessary - cu
hadaq [Wed, 27 Mar 2013 08:17:32 +0000 (08:17 +0000)]
control registers are moved to the bus address 0xc800 - cu
hadaq [Wed, 27 Mar 2013 08:14:50 +0000 (08:14 +0000)]
allignment - cu
hadaq [Wed, 27 Mar 2013 08:09:27 +0000 (08:09 +0000)]
allignment - cu
hadaq [Wed, 27 Mar 2013 08:08:49 +0000 (08:08 +0000)]
toggle time between the hit pulse edges is made shorter - cu
hadaq [Wed, 27 Mar 2013 08:06:57 +0000 (08:06 +0000)]
new entity for rising edge detection - cu
hadaq [Wed, 27 Mar 2013 08:06:04 +0000 (08:06 +0000)]
unnecessary reset signals are removed - cu
hadaq [Wed, 27 Mar 2013 08:05:08 +0000 (08:05 +0000)]
port interface is updated - cu
hadaq [Wed, 27 Mar 2013 08:04:42 +0000 (08:04 +0000)]
port interface is updated - cu
hadaq [Wed, 27 Mar 2013 08:03:43 +0000 (08:03 +0000)]
unnecessary signals are removed - cu
hadaq [Wed, 27 Mar 2013 08:02:06 +0000 (08:02 +0000)]
reset signal is removed - cu
hadaq [Wed, 27 Mar 2013 08:00:48 +0000 (08:00 +0000)]
port interface is updated - cu
hadaq [Wed, 27 Mar 2013 07:58:49 +0000 (07:58 +0000)]
constraints are updated with the new syntax - cu
hadaq [Wed, 27 Mar 2013 07:57:47 +0000 (07:57 +0000)]
control registers are moved to 0xc800 bus address - cu
hadaq [Wed, 27 Mar 2013 07:55:26 +0000 (07:55 +0000)]
hit and debug counters are decreased to 100MHz clock domain to ease the timing constraints - cu
hadaq [Mon, 25 Mar 2013 07:45:56 +0000 (07:45 +0000)]
correct constraints are added - cu
hadaq [Mon, 25 Mar 2013 01:17:27 +0000 (01:17 +0000)]
geht nicht mit adc2
hadaq [Sun, 24 Mar 2013 22:53:14 +0000 (22:53 +0000)]
geht nicht mit adc
hadeshyp [Fri, 22 Mar 2013 14:16:48 +0000 (14:16 +0000)]
added link for txt files
hadeshyp [Fri, 22 Mar 2013 12:37:05 +0000 (12:37 +0000)]
added new IP cores
hadeshyp [Fri, 22 Mar 2013 12:28:43 +0000 (12:28 +0000)]
new source file added to project. bn.
hadeshyp [Thu, 21 Mar 2013 10:55:17 +0000 (10:55 +0000)]
added config.vhd for gbe hub, JM
hadaq [Wed, 20 Mar 2013 19:43:35 +0000 (19:43 +0000)]
nx timestamp window filter added
hadaq [Wed, 20 Mar 2013 19:42:45 +0000 (19:42 +0000)]
running so far, now implement TrbNet ch1 and ch2
hadaq [Wed, 20 Mar 2013 10:12:52 +0000 (10:12 +0000)]
performance increase for 200MHz - cu
hadaq [Tue, 19 Mar 2013 14:36:46 +0000 (14:36 +0000)]
*** empty log message ***
hadaq [Tue, 19 Mar 2013 10:17:09 +0000 (10:17 +0000)]
updated for the tdc_v1.3 - cu
hadaq [Tue, 19 Mar 2013 10:04:31 +0000 (10:04 +0000)]
debugged - cu
hadaq [Mon, 18 Mar 2013 10:46:19 +0000 (10:46 +0000)]
performance upgrade for 200MHz - cu
hadeshyp [Fri, 15 Mar 2013 17:22:40 +0000 (17:22 +0000)]
latest mvd JTAG version, JM
hadeshyp [Fri, 15 Mar 2013 16:06:11 +0000 (16:06 +0000)]
added config for CTS, JM
hadaq [Fri, 15 Mar 2013 16:01:48 +0000 (16:01 +0000)]
debugged - cu
hadaq [Fri, 15 Mar 2013 15:59:30 +0000 (15:59 +0000)]
debugged -cu
hadeshyp [Thu, 14 Mar 2013 18:16:55 +0000 (18:16 +0000)]
furhter steps toward MVD JTAG, JM
hadaq [Thu, 14 Mar 2013 11:18:19 +0000 (11:18 +0000)]
typo correction - cu
hadeshyp [Wed, 13 Mar 2013 18:41:13 +0000 (18:41 +0000)]
added MVD JTAG project
hadaq [Wed, 13 Mar 2013 07:29:00 +0000 (07:29 +0000)]
The responsivness of the encoder is increased to 100%
hadeshyp [Wed, 6 Mar 2013 11:32:10 +0000 (11:32 +0000)]
*** empty log message ***
hadaq [Tue, 5 Mar 2013 10:25:58 +0000 (10:25 +0000)]
removed unused entity - cu
hadaq [Tue, 5 Mar 2013 10:23:02 +0000 (10:23 +0000)]
edge detection logic - cu
hadaq [Tue, 5 Mar 2013 10:05:45 +0000 (10:05 +0000)]
not used - cu
hadaq [Tue, 5 Mar 2013 10:01:09 +0000 (10:01 +0000)]
cu
hadaq [Tue, 5 Mar 2013 10:00:07 +0000 (10:00 +0000)]
Interconnections are changed for the tdc_v1.3 -cu
hadaq [Tue, 5 Mar 2013 09:53:10 +0000 (09:53 +0000)]
removal of unnecessary parts - cu
hadaq [Tue, 5 Mar 2013 09:38:32 +0000 (09:38 +0000)]
tdc_v1.3 added. For more details see the ReleaseNotes.txt - cu
hadeshyp [Thu, 28 Feb 2013 14:54:05 +0000 (14:54 +0000)]
*** empty log message ***
hadaq [Tue, 26 Feb 2013 09:51:02 +0000 (09:51 +0000)]
excess signal removal - cu
hadeshyp [Fri, 22 Feb 2013 14:35:24 +0000 (14:35 +0000)]
small updates
hadeshyp [Wed, 20 Feb 2013 18:36:36 +0000 (18:36 +0000)]
syncmode test design
hadeshyp [Mon, 18 Feb 2013 17:21:11 +0000 (17:21 +0000)]
prepared soda test design
jspc29 / trb3.git / log