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jspc29.x-matter.uni-frankfurt.de Git - trb3.git/log
Ludwig Maier [Tue, 5 Aug 2014 11:46:13 +0000 (13:46 +0200)]
cleanup adc handler
Ludwig Maier [Mon, 4 Aug 2014 13:52:59 +0000 (15:52 +0200)]
try new clock domains in nx_data_receiver
Manuel Penschuck [Sun, 10 Aug 2014 19:09:36 +0000 (21:09 +0200)]
Readout seems to work with TrbNet test-pattern generator
Manuel Penschuck [Thu, 7 Aug 2014 17:33:32 +0000 (19:33 +0200)]
CBMNet: data_stop-related timing problem in combination with slow fifo required additional output-buffer - now implemented. New simulation includes two lp_top's for an end-to-end coverage of the readout path. Simulation look promising
Manuel Penschuck [Tue, 5 Aug 2014 18:08:35 +0000 (20:08 +0200)]
CBMNet readout: Debug-Design for Periph-FPGA with Test-Pattern generator. Simulation proven. Scripts to verify data received by FLIB. Seems to work fine as long as there's no back-pressure
Jan Michel [Mon, 4 Aug 2014 11:34:01 +0000 (13:34 +0200)]
added entities for proper ADC readout, reorganized ADC code slightly, moved ADC registers from 0xe000 to 0xa000.
Cahit [Thu, 31 Jul 2014 07:49:48 +0000 (09:49 +0200)]
tdc v1.6.3 compatibility with the tdc v1.7.1
Cahit [Tue, 29 Jul 2014 13:10:34 +0000 (15:10 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Tue, 29 Jul 2014 13:10:22 +0000 (15:10 +0200)]
32PinAddOn design is brought up-to-date with tdc v1.7.1
Cahit [Tue, 29 Jul 2014 13:09:28 +0000 (15:09 +0200)]
tdc v1.7 and v1.7.1 release
Jan Michel [Tue, 29 Jul 2014 09:02:21 +0000 (11:02 +0200)]
created two CTS constraints files for compatibilty with Diamond 2
Manuel Penschuck [Mon, 28 Jul 2014 09:55:07 +0000 (11:55 +0200)]
Migrated CTS constraints to Diamond 3.2 (Synplify I), Added FDC for synplify, added CBMNet constraints, relaxed Reset Path (Retiming), debug tools for cbmnet stack
Manuel Penschuck [Mon, 28 Jul 2014 09:50:39 +0000 (11:50 +0200)]
Monitoring and Debug features added to CBM-Readout Chain
Jan Michel [Fri, 25 Jul 2014 16:16:28 +0000 (18:16 +0200)]
few more debugging regs for ADC
Jan Michel [Thu, 24 Jul 2014 16:00:51 +0000 (18:00 +0200)]
some additional registers for ADC control
Jan Michel [Wed, 23 Jul 2014 17:41:43 +0000 (19:41 +0200)]
first running ADC AddOn version
Jan Michel [Tue, 22 Jul 2014 12:05:03 +0000 (14:05 +0200)]
next step towards running ADC board
Manuel Penschuck [Fri, 18 Jul 2014 19:05:20 +0000 (21:05 +0200)]
CBMNet: Simulation of TrbNet -> CBMNet readout path seems to work
Cahit [Fri, 18 Jul 2014 08:39:24 +0000 (10:39 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Fri, 18 Jul 2014 08:39:18 +0000 (10:39 +0200)]
tidy up
Ludwig Maier [Thu, 17 Jul 2014 22:04:12 +0000 (00:04 +0200)]
nxyter ts/adc timestamp delay auto adjust entity implemented, works now
Manuel Penschuck [Thu, 17 Jul 2014 20:55:34 +0000 (22:55 +0200)]
CBMNet readout backup
Cahit [Thu, 17 Jul 2014 07:34:57 +0000 (09:34 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Thu, 17 Jul 2014 07:32:31 +0000 (09:32 +0200)]
TDC version v1.6.3 brought uptodate with the new config file
Cahit [Thu, 17 Jul 2014 07:31:55 +0000 (09:31 +0200)]
General Purpose project brought uptodate with tdc core v1.6.3
Ludwig Maier [Wed, 16 Jul 2014 22:52:26 +0000 (00:52 +0200)]
nxyter ts/adc timestamp delay auto adjust entity implemented
Ludwig Maier [Mon, 7 Jul 2014 08:41:34 +0000 (10:41 +0200)]
nxyter: bug fix in slow control
Andreas Neiser [Wed, 16 Jul 2014 08:04:01 +0000 (10:04 +0200)]
ADC: Keeping the ADC SPI pins low (also PULLMODE=DOWN), prevent entering power on test mode
Jan Michel [Mon, 7 Jul 2014 16:51:11 +0000 (18:51 +0200)]
added flexible UART to all 4conn AddOns via FPGA5_3V3 lines
Andreas Neiser [Mon, 7 Jul 2014 16:08:39 +0000 (18:08 +0200)]
ADC: Adding many missing things to LPF files...how stupid!
Andreas Neiser [Mon, 7 Jul 2014 15:29:54 +0000 (17:29 +0200)]
ADC: More nxyter like CLK usage...not tested yet
Andreas Neiser [Mon, 7 Jul 2014 15:20:06 +0000 (17:20 +0200)]
ADC: Switching to other CLK also does not help...
Andreas Neiser [Mon, 7 Jul 2014 09:04:26 +0000 (11:04 +0200)]
ADC Addon: Fix CS numbering
Jan Michel [Wed, 2 Jul 2014 17:00:42 +0000 (19:00 +0200)]
update to CTS project file for TDCs
Jan Michel [Wed, 2 Jul 2014 17:00:07 +0000 (19:00 +0200)]
removed fast signals from debug word
Jan Michel [Wed, 2 Jul 2014 16:58:37 +0000 (18:58 +0200)]
added UART to trb3_gbe design
Manuel Penschuck [Mon, 30 Jun 2014 14:24:10 +0000 (16:24 +0200)]
Added CBMNet support to CTS - not working yet
Manuel Penschuck [Mon, 30 Jun 2014 14:22:55 +0000 (16:22 +0200)]
added module configuration to CTS prj-file: All include-statements from config.vhd are converted into tcl code and thus can be used to include only necessary hdl-files. for example, TDC and CBMNET are only loaded when needed
Manuel Penschuck [Mon, 30 Jun 2014 14:19:59 +0000 (16:19 +0200)]
initial version of the (yet incomplete) read-out handler for cbmnet
Manuel Penschuck [Mon, 30 Jun 2014 14:19:18 +0000 (16:19 +0200)]
cbmnet phy: additional debug tools .. data transport works ... sometimes
Manuel Penschuck [Mon, 30 Jun 2014 14:17:58 +0000 (16:17 +0200)]
moved CBMNet SFP to base
Manuel Penschuck [Wed, 25 Jun 2014 17:46:19 +0000 (19:46 +0200)]
CBMNet: Relaxed Timing Constraints - Seems to work
Manuel Penschuck [Wed, 25 Jun 2014 08:57:05 +0000 (10:57 +0200)]
CBMNet: Relaxed some time critical components. Design currently broken; back-up
Ludwig Maier [Tue, 24 Jun 2014 22:26:20 +0000 (00:26 +0200)]
nxyter: additional debug line out for new addon board
Ludwig Maier [Tue, 10 Jun 2014 18:51:45 +0000 (20:51 +0200)]
nxyter update
Ludwig Maier [Wed, 28 May 2014 20:17:15 +0000 (22:17 +0200)]
nxyter update
Cahit [Tue, 24 Jun 2014 08:44:50 +0000 (10:44 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Tue, 24 Jun 2014 08:44:47 +0000 (10:44 +0200)]
tdc release 1.6.3
Jan Michel [Mon, 23 Jun 2014 09:46:03 +0000 (11:46 +0200)]
changed enable handling in trigger logic
Jan Michel [Mon, 23 Jun 2014 09:43:20 +0000 (11:43 +0200)]
changed enable handling in trigger logic
Cahit [Sat, 21 Jun 2014 06:28:48 +0000 (08:28 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Manuel Penschuck [Wed, 18 Jun 2014 16:41:01 +0000 (18:41 +0200)]
Data transport works in the straight-forward case
Jan Michel [Fri, 13 Jun 2014 12:42:09 +0000 (14:42 +0200)]
updated coincidence logic
Cahit [Fri, 13 Jun 2014 08:10:34 +0000 (10:10 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Fri, 13 Jun 2014 08:08:05 +0000 (10:08 +0200)]
Standard AddOn Project is brought up to date with tdc_v1.6.2
Manuel Penschuck [Fri, 13 Jun 2014 07:25:03 +0000 (09:25 +0200)]
Synthesisable with new CBMNet, however initialisation of link fails
Jan Michel [Thu, 12 Jun 2014 16:35:00 +0000 (18:35 +0200)]
very simple coincidence logic for trigger logic
Manuel Penschuck [Wed, 4 Jun 2014 15:45:14 +0000 (17:45 +0200)]
Changes before adopting to new CBMNet version
Manuel Penschuck [Wed, 4 Jun 2014 15:44:38 +0000 (17:44 +0200)]
create_project: more helpful error messages & bug-fix
Manuel Penschuck [Wed, 4 Jun 2014 15:43:27 +0000 (17:43 +0200)]
Changes before adopting to new CBMNet version
Jan Michel [Tue, 27 May 2014 10:55:35 +0000 (12:55 +0200)]
added included features map to trb3_gbe design
Jan Michel [Fri, 23 May 2014 09:06:01 +0000 (11:06 +0200)]
small change in definition of included features tables
Ludwig Maier [Mon, 26 May 2014 18:37:47 +0000 (20:37 +0200)]
nxyter update
Ludwig Maier [Sun, 25 May 2014 15:41:53 +0000 (17:41 +0200)]
nxyter trb3_periph.prj update
Ludwig Maier [Sun, 25 May 2014 12:07:07 +0000 (14:07 +0200)]
nxyter timestamp histogram added
Andreas Neiser [Fri, 23 May 2014 13:27:10 +0000 (15:27 +0200)]
ADC Addon: Better CS mapping, probably...
Manuel Penschuck [Fri, 23 May 2014 14:00:36 +0000 (16:00 +0200)]
CTS typo
Manuel Penschuck [Fri, 23 May 2014 14:00:13 +0000 (16:00 +0200)]
CBMNet before refactoring to slave-only version
Manuel Penschuck [Fri, 23 May 2014 13:57:51 +0000 (15:57 +0200)]
Typo
Andreas Neiser [Fri, 23 May 2014 13:06:10 +0000 (15:06 +0200)]
ADC Addon: Fix SPI connections to FPGA (single ended!)
Andreas Neiser [Fri, 23 May 2014 13:03:49 +0000 (15:03 +0200)]
Fixing group name clash in LPF for ADC addon
Andreas Neiser [Fri, 23 May 2014 09:12:56 +0000 (11:12 +0200)]
Multiplex the SPI communication for the ADC addon
Andreas Neiser [Fri, 23 May 2014 09:12:23 +0000 (11:12 +0200)]
Somewhat better grepping for errors in compile script
Andreas Neiser [Fri, 23 May 2014 07:20:56 +0000 (09:20 +0200)]
Adding GSI compile script for ADC addon
Andreas Neiser [Thu, 22 May 2014 16:05:07 +0000 (18:05 +0200)]
Adding bus_register_handler.vhd to the project files
Manuel Penschuck [Thu, 22 May 2014 11:38:11 +0000 (13:38 +0200)]
Diamond project creation tool. See daqdocu
Andreas Neiser [Thu, 22 May 2014 07:22:57 +0000 (09:22 +0200)]
Commenting duplicate declaration of FIFO_DC_36x32_OutReg/FIFO_DC_36x16_OutReg
Jan Michel [Wed, 21 May 2014 09:40:04 +0000 (11:40 +0200)]
added included features bitmap to hadesstart design
Ludwig Maier [Tue, 20 May 2014 09:38:33 +0000 (11:38 +0200)]
nxyter all working, seems to be at least
Ludwig Maier [Sun, 11 May 2014 21:54:21 +0000 (23:54 +0200)]
updated adc handler, improved timing
Ludwig Maier [Thu, 1 May 2014 13:52:53 +0000 (15:52 +0200)]
nxyter working design, adc still slightly buggy...
Ludwig Maier [Tue, 29 Apr 2014 08:53:47 +0000 (10:53 +0200)]
nxyter tmp
Manuel Penschuck [Mon, 19 May 2014 14:12:07 +0000 (16:12 +0200)]
Bug-Fix: Slow-control timing problem when no TDC included. Peripheral Trigger input mapping now (10 downto 6)
Jan Michel [Thu, 15 May 2014 15:11:48 +0000 (17:11 +0200)]
fixing trb3_components after two people changing the same thing
Cahit [Thu, 15 May 2014 15:04:20 +0000 (17:04 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Thu, 15 May 2014 15:04:12 +0000 (17:04 +0200)]
different FIFOs for different ring buffer sizes
Jan Michel [Thu, 15 May 2014 13:35:54 +0000 (15:35 +0200)]
Fixing the hadesstart to compile again with updated TDC
Manuel Penschuck [Thu, 15 May 2014 08:58:58 +0000 (10:58 +0200)]
Sequential EB selection
Jan Michel [Thu, 15 May 2014 08:40:39 +0000 (10:40 +0200)]
updated Cts for tdc v1.6.1
Jan Michel [Wed, 14 May 2014 16:44:48 +0000 (18:44 +0200)]
added default values for slow control inputs
Cahit [Wed, 14 May 2014 11:13:16 +0000 (13:13 +0200)]
conflict fix
Jan Michel [Mon, 12 May 2014 14:58:29 +0000 (16:58 +0200)]
updated input monitor, single FIFO mode available
Jan Michel [Mon, 12 May 2014 14:11:13 +0000 (16:11 +0200)]
updated TDC version and added default values on slow control bus
Jan Michel [Mon, 12 May 2014 14:09:49 +0000 (16:09 +0200)]
removed old debug stuff
Jan Michel [Mon, 12 May 2014 14:09:19 +0000 (16:09 +0200)]
added input statistics and trigger
Jan Michel [Mon, 12 May 2014 14:08:06 +0000 (16:08 +0200)]
updated trb3_gbe config files
Jan Michel [Mon, 12 May 2014 14:06:53 +0000 (16:06 +0200)]
fixed trigger logic generator with stretcher for short pulses
Jan Michel [Mon, 12 May 2014 14:05:13 +0000 (16:05 +0200)]
added new constraints file for diamond 3
Cahit [Fri, 9 May 2014 12:42:10 +0000 (14:42 +0200)]
tdc version 1.6.2 is added with option of different ringbuffer size.
Cahit [Tue, 6 May 2014 12:53:58 +0000 (14:53 +0200)]
constraint files are individual for each design