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hadeshyp [Thu, 2 Sep 2010 21:36:27 +0000 (21:36 +0000)]
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hadeshyp [Thu, 19 Aug 2010 09:27:49 +0000 (09:27 +0000)]
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14 years agowrong depth on 16k and 32k fifos
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hadaq [Thu, 19 Aug 2010 08:34:02 +0000 (08:34 +0000)]
wrong depth on 16k and 32k fifos

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hadaq [Fri, 9 Jul 2010 08:32:48 +0000 (08:32 +0000)]
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14 years agochanged LINK_BROKEN_OUT to one cycle pulse, according to Master Jan's wish :-)
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hadaq [Fri, 9 Jul 2010 08:32:34 +0000 (08:32 +0000)]
changed LINK_BROKEN_OUT to one cycle pulse, according to Master Jan's wish :-)

14 years agoNew entity for forwarding only full packets from SerDes to media interface.
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hadaq [Fri, 9 Jul 2010 07:51:59 +0000 (07:51 +0000)]
New entity for forwarding only full packets from SerDes to media interface.
Written to workaround the "MDC I sparking kills da optical link" problem.
Not suitable for real fibre links (2GB), as it also does 25MHz/100MHz conversion
as well as 8b/16b by FIFO.

14 years agoPrepared for new "receive only full packets" stuff.
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hadaq [Fri, 9 Jul 2010 07:49:48 +0000 (07:49 +0000)]
Prepared for new "receive only full packets" stuff.

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hadaq [Thu, 1 Jul 2010 09:46:56 +0000 (09:46 +0000)]
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14 years agofor LVL1 handler, taken from ADCMv3
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hadaq [Thu, 1 Jul 2010 09:18:26 +0000 (09:18 +0000)]
for LVL1 handler, taken from ADCMv3

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hadeshyp [Wed, 30 Jun 2010 22:22:58 +0000 (22:22 +0000)]
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14 years agoTypos corrected, doubles removed, now loads in ispLever8.1 Windows without spellcheck...
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hadaq [Wed, 30 Jun 2010 16:17:35 +0000 (16:17 +0000)]
Typos corrected, doubles removed, now loads in ispLever8.1 Windows without spellcheck errors.

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hadaq [Wed, 30 Jun 2010 16:08:15 +0000 (16:08 +0000)]
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14 years agoFirst try, will most likely not compile.
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hadaq [Wed, 30 Jun 2010 15:50:00 +0000 (15:50 +0000)]
First try, will most likely not compile.
Clock domains must be checked completely.
Reset sequence most likely not suitable.
RX delay registers between SerDes and byte swapper removed.
Too many bullshit comments in.

14 years agofirst try (no warranty!) after studying some of the 344 pages of SCM SerDes documenta...
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hadaq [Wed, 30 Jun 2010 15:48:18 +0000 (15:48 +0000)]
first try (no warranty!) after studying some of the 344 pages of SCM SerDes documentation:
SerDes is operated in G8B10B mode, with GbE LSM enabled, and CTC mode switched on.
Latter two points must be done "by hand" inside the *.txt config file.
Important: hands off the quad_rst input!

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hadaq [Tue, 29 Jun 2010 08:46:18 +0000 (08:46 +0000)]
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14 years agoregenerated modules for SCM chip (CTS).
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hadaq [Tue, 29 Jun 2010 08:33:24 +0000 (08:33 +0000)]
regenerated modules for SCM chip (CTS).
not tested.

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hadeshyp [Tue, 29 Jun 2010 00:48:37 +0000 (00:48 +0000)]
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14 years ago29_06_10
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hadeshyp [Tue, 29 Jun 2010 00:44:09 +0000 (00:44 +0000)]
29_06_10

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hadeshyp [Fri, 25 Jun 2010 16:16:52 +0000 (16:16 +0000)]
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14 years agobug fixed version of sbuf5: new statemachine handles (hopefully, keep fingers crossed)
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hadaq [Fri, 25 Jun 2010 15:36:33 +0000 (15:36 +0000)]
bug fixed version of sbuf5: new statemachine handles (hopefully, keep fingers crossed)
all FIFO fill levels correctly now, independent of the data stream timing on the input.

14 years agostate machine completely reworked. new bugs inserted.
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hadaq [Fri, 25 Jun 2010 10:04:36 +0000 (10:04 +0000)]
state machine completely reworked. new bugs inserted.

14 years agohopefully fixed bug in sbuf5
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hadaq [Thu, 24 Jun 2010 15:41:08 +0000 (15:41 +0000)]
hopefully fixed bug in sbuf5

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hadeshyp [Mon, 21 Jun 2010 15:37:30 +0000 (15:37 +0000)]
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14 years agotrb_net_sbuf5.vhd
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hadaq [Mon, 21 Jun 2010 08:42:51 +0000 (08:42 +0000)]
trb_net_sbuf5.vhd

14 years agotrb_net_sbuf5.vhd
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hadaq [Mon, 21 Jun 2010 08:04:30 +0000 (08:04 +0000)]
trb_net_sbuf5.vhd

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14 years ago26_05
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hadeshyp [Wed, 26 May 2010 13:51:40 +0000 (13:51 +0000)]
26_05

14 years agochanged fifo_rx_rd_en to be not static anymore.
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hadaq [Fri, 21 May 2010 11:25:59 +0000 (11:25 +0000)]
changed fifo_rx_rd_en to be not static anymore.

14 years agoFirst version in official TRBnet.
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hadaq [Fri, 21 May 2010 11:21:59 +0000 (11:21 +0000)]
First version in official TRBnet.

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TrbNet VHDL code