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jspc29.x-matter.uni-frankfurt.de Git - dirich.git/log
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Jan Michel [Tue, 18 Jul 2017 16:37:42 +0000 (18:37 +0200)]
Move some MachXO3 files to new repository 'vhdlbasics'
local account [Thu, 22 Jun 2017 08:31:20 +0000 (10:31 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:dirich
local account [Thu, 22 Jun 2017 08:30:12 +0000 (10:30 +0200)]
latest Version of threshold FPGA - FLASH included
Jan Michel [Wed, 31 May 2017 16:49:12 +0000 (18:49 +0200)]
Change reset to include clear on reset.
Change PLL LOL settings for Serdes
local account [Thu, 18 May 2017 08:37:59 +0000 (10:37 +0200)]
Addes Flash support and minor fixes for MachXO34300E
local account [Thu, 18 May 2017 08:23:17 +0000 (10:23 +0200)]
Addes Flash support and minor fixes for MachXO34300E
Jan Michel [Sun, 14 May 2017 21:12:49 +0000 (23:12 +0200)]
one lpf file for each Dirich version because current Diamond doesnt like double assigend pins
Jan Michel [Sun, 14 May 2017 20:24:28 +0000 (22:24 +0200)]
count SPI pins from 0 to 1, not 1 to 2
Jan Michel [Wed, 10 May 2017 12:47:17 +0000 (14:47 +0200)]
fix names of SPI ports
fix mapping of PWM outputs on DAC FPGAs
Cahit [Tue, 25 Apr 2017 19:35:27 +0000 (21:35 +0200)]
solved conflicts
Cahit [Tue, 25 Apr 2017 19:30:34 +0000 (21:30 +0200)]
uploaded extre files
local account [Mon, 24 Apr 2017 13:33:56 +0000 (15:33 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:dirich
local account [Mon, 24 Apr 2017 13:32:28 +0000 (15:32 +0200)]
threshold-fpga design with spi connection and preparation for FLASH connection
Jan Michel [Mon, 24 Apr 2017 09:31:12 +0000 (11:31 +0200)]
Update Dirich design with new SPI port and option to disable PWM
Jan Michel [Mon, 24 Apr 2017 09:00:49 +0000 (11:00 +0200)]
Update pinout files for all FPGA
Jan Michel [Mon, 24 Apr 2017 09:00:09 +0000 (11:00 +0200)]
Update placement of serdes in combiner
Jan Michel [Tue, 24 Jan 2017 17:12:37 +0000 (18:12 +0100)]
Update dirich with minor changes
Jan Michel [Tue, 24 Jan 2017 17:08:40 +0000 (18:08 +0100)]
Update threshold FPGA code
Jan Michel [Tue, 24 Jan 2017 17:00:13 +0000 (18:00 +0100)]
Combiner: default trigger input selection corrected
Jan Michel [Tue, 24 Jan 2017 16:59:45 +0000 (17:59 +0100)]
Add adapted version of PWM for external threshold FPGA
local account [Thu, 27 Oct 2016 15:13:12 +0000 (17:13 +0200)]
Implemented SPI and changed to testboard
Jan Michel [Thu, 25 Aug 2016 15:09:46 +0000 (17:09 +0200)]
Fixing conflicts due to reformatting of code
Jan Michel [Thu, 25 Aug 2016 15:05:12 +0000 (17:05 +0200)]
add pulldown to control pins
Jan Michel [Thu, 25 Aug 2016 15:04:33 +0000 (17:04 +0200)]
Few minor changes to combiner
Cahit [Mon, 22 Aug 2016 19:41:51 +0000 (21:41 +0200)]
corrected databuffer threshold calculation for the endpoint
Cahit [Mon, 22 Aug 2016 17:27:39 +0000 (19:27 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:dirich
Jan Michel [Fri, 19 Aug 2016 09:48:13 +0000 (11:48 +0200)]
Add current serdes cores to git
Jan Michel [Thu, 18 Aug 2016 10:59:35 +0000 (12:59 +0200)]
Adding necessary changes to allow reading of ADC on Power board
Jan Michel [Tue, 26 Jul 2016 14:36:13 +0000 (16:36 +0200)]
Update dirich with LED for PLL lock
Jan Michel [Tue, 26 Jul 2016 14:34:59 +0000 (16:34 +0200)]
change media interface clocks for non-synchronous clock w.r.t uplink
Jan Michel [Tue, 26 Jul 2016 14:34:14 +0000 (16:34 +0200)]
Update pinout files
Jan Michel [Tue, 26 Jul 2016 14:33:49 +0000 (16:33 +0200)]
Add design skeleton for PWM FPGAs
Cahit [Fri, 15 Jul 2016 20:37:55 +0000 (22:37 +0200)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:dirich
Cahit [Fri, 15 Jul 2016 20:35:54 +0000 (22:35 +0200)]
edited compile config for ecp5 compilation
Jan Michel [Mon, 11 Jul 2016 16:55:56 +0000 (18:55 +0200)]
changed feedback in pll, lower frequency pwm, flash working
Jan Michel [Wed, 6 Jul 2016 12:51:58 +0000 (14:51 +0200)]
Update dirich files
Cahit [Sun, 26 Jun 2016 12:04:27 +0000 (14:04 +0200)]
added link to the tdc repo for dirich top module
Jan Michel [Fri, 1 Apr 2016 08:44:18 +0000 (10:44 +0200)]
Committing missing changes from depc363
Cahit [Mon, 21 Mar 2016 13:47:26 +0000 (14:47 +0100)]
corrected merge
Cahit [Mon, 21 Mar 2016 13:44:14 +0000 (14:44 +0100)]
updated project file, config compile file, tdc version number for the project
Jan Michel [Fri, 18 Mar 2016 15:44:03 +0000 (16:44 +0100)]
Dirich update: input clock 200 MHz, flash connected to clock signal
Jan Michel [Fri, 18 Mar 2016 14:32:14 +0000 (15:32 +0100)]
Minor updates to dirich design and lpf
Jan Michel [Fri, 18 Mar 2016 14:31:54 +0000 (15:31 +0100)]
Adding lpf and design for combiner board
Jan Michel [Fri, 4 Mar 2016 17:42:45 +0000 (18:42 +0100)]
Adding first files for DiRich combiner module. Not finished yet.
Jan Michel [Fri, 22 Jan 2016 12:37:51 +0000 (13:37 +0100)]
Fixing some mistakes in the DiRich lpf
Jan Michel [Fri, 22 Jan 2016 11:18:18 +0000 (12:18 +0100)]
Updating dirich lpf
Jan Michel [Thu, 21 Jan 2016 14:29:08 +0000 (15:29 +0100)]
Adding PWM generator incl. temperature compensation for Dirich
Jan Michel [Wed, 6 Jan 2016 18:23:41 +0000 (19:23 +0100)]
Adding preliminary pinout and device config for dirich
Jan Michel [Wed, 6 Jan 2016 17:18:22 +0000 (18:18 +0100)]
Moving Diamond Project
Jan Michel [Wed, 6 Jan 2016 17:13:07 +0000 (18:13 +0100)]
File update, compiling, but media interface missing
Jan Michel [Wed, 6 Jan 2016 15:59:44 +0000 (16:59 +0100)]
Adding ecp5 libs
Jan Michel [Wed, 6 Jan 2016 15:55:55 +0000 (16:55 +0100)]
More DiRich files
Jan Michel [Tue, 22 Dec 2015 16:11:19 +0000 (17:11 +0100)]
Adding first files for dirich project. Not compiling yet just the files.