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jspc29.x-matter.uni-frankfurt.de Git - vhdlbasics.git/log
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Ingo Froehlich [Tue, 6 Mar 2018 21:20:50 +0000 (22:20 +0100)]
spi interface with 2 clocks, IF
Ingo Froehlich [Tue, 6 Mar 2018 21:19:39 +0000 (22:19 +0100)]
small fixes, IF
Ingo Froehlich [Tue, 27 Feb 2018 12:26:13 +0000 (13:26 +0100)]
timing optimization, IF
Ingo Froehlich [Tue, 30 Jan 2018 14:39:17 +0000 (15:39 +0100)]
new 16 bit scheme for flash, IF
Ingo Froehlich [Tue, 30 Jan 2018 11:21:17 +0000 (12:21 +0100)]
bug fix in flash master, IF
Ingo Froehlich [Thu, 25 Jan 2018 15:03:22 +0000 (16:03 +0100)]
unix format, IF
Ingo Froehlich [Thu, 25 Jan 2018 15:02:59 +0000 (16:02 +0100)]
async ram, IF
Ingo Froehlich [Thu, 21 Sep 2017 15:56:15 +0000 (17:56 +0200)]
flash disabled after boot, IF
Ingo Froehlich [Tue, 5 Sep 2017 12:31:15 +0000 (14:31 +0200)]
32 bit master debugged, IF
Ingo Froehlich [Wed, 30 Aug 2017 14:49:26 +0000 (16:49 +0200)]
burst option for flash, IF
Ingo Froehlich [Wed, 30 Aug 2017 12:48:28 +0000 (14:48 +0200)]
32bit flash read and endian option, IF
Ingo Froehlich [Fri, 25 Aug 2017 14:57:37 +0000 (16:57 +0200)]
added 32-bit burst, IF
Ingo Froehlich [Fri, 25 Aug 2017 12:44:01 +0000 (14:44 +0200)]
asynchronous uart, IF
Ingo Froehlich [Thu, 24 Aug 2017 16:14:26 +0000 (18:14 +0200)]
generic flash ctrl with generic bus width, IF
Ingo Froehlich [Tue, 22 Aug 2017 14:09:15 +0000 (16:09 +0200)]
finished master in generic flash ctrl, IF
Ingo Froehlich [Mon, 24 Jul 2017 16:24:34 +0000 (18:24 +0200)]
fixed missing wait for ready when reading, IF
Ingo Froehlich [Mon, 24 Jul 2017 16:00:23 +0000 (18:00 +0200)]
added flash ctrl, IF
Jan Michel [Thu, 20 Jul 2017 12:32:50 +0000 (14:32 +0200)]
add .gitignore
Jan Michel [Thu, 20 Jul 2017 12:32:10 +0000 (14:32 +0200)]
Add MachXO3 Flash files
Jan Michel [Thu, 20 Jul 2017 12:22:02 +0000 (14:22 +0200)]
add downsampling option to PWM module
Jan Michel [Tue, 18 Jul 2017 16:45:00 +0000 (18:45 +0200)]
include change of SPI from Dirich
Jan Michel [Tue, 18 Jul 2017 16:35:13 +0000 (18:35 +0200)]
add first files to generic VHDL repo
jspc29 / vhdlbasics.git / log