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jspc29.x-matter.uni-frankfurt.de Git - trb3.git/log
Cahit [Fri, 13 Mar 2015 16:21:48 +0000 (17:21 +0100)]
release table written in org mode. Also a script exists for exporting the table to latex
Cahit [Sat, 14 Feb 2015 09:57:08 +0000 (10:57 +0100)]
tdc_v2.1.2 version release
Jan Michel [Fri, 13 Feb 2015 14:37:25 +0000 (15:37 +0100)]
correcting changes in lpf files
Jan Michel [Fri, 13 Feb 2015 14:12:57 +0000 (15:12 +0100)]
updated central hub with new uart
Cahit [Wed, 4 Feb 2015 09:00:38 +0000 (10:00 +0100)]
projects brought up-to-date with tdc_v2.1.1
Cahit [Tue, 3 Feb 2015 11:21:06 +0000 (12:21 +0100)]
periph_padiwa is brought up-to-date with tdc_v2.1.1
Cahit [Mon, 2 Feb 2015 14:24:19 +0000 (15:24 +0100)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Mon, 2 Feb 2015 14:24:15 +0000 (15:24 +0100)]
ring buffer full threshold register moved to 0xc804
Cahit [Mon, 2 Feb 2015 14:22:20 +0000 (15:22 +0100)]
cbmtof is brought up-to-date with tdc_v2.1.1
Cahit [Mon, 2 Feb 2015 14:20:53 +0000 (15:20 +0100)]
tdc version 2.1.1 is released
Cahit [Mon, 2 Feb 2015 14:18:37 +0000 (15:18 +0100)]
edge type correction for single edge designs
Jan Michel [Wed, 28 Jan 2015 17:04:21 +0000 (18:04 +0100)]
changed pulser project compile script
Cahit [Fri, 23 Jan 2015 09:17:43 +0000 (10:17 +0100)]
new fifo core with dynamic threshold
Cahit [Fri, 23 Jan 2015 09:16:39 +0000 (10:16 +0100)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Fri, 23 Jan 2015 09:16:34 +0000 (10:16 +0100)]
tdc version 2.1 is released
Jan Michel [Wed, 21 Jan 2015 16:49:05 +0000 (17:49 +0100)]
updated pulser design
Jan Michel [Thu, 15 Jan 2015 17:33:06 +0000 (18:33 +0100)]
prepared design for pulser
Andreas Neiser [Wed, 14 Jan 2015 10:26:34 +0000 (11:26 +0100)]
ADC: convert explicitly to std_logic_vector
Andreas Neiser [Mon, 12 Jan 2015 16:45:33 +0000 (17:45 +0100)]
Base: create_project: allow whitespace in prj statements at end of line...
Andreas Neiser [Mon, 12 Jan 2015 16:39:10 +0000 (17:39 +0100)]
ADC: Make compile_constraints.pl work with base/create_project.pl
Jan Michel [Fri, 9 Jan 2015 18:36:54 +0000 (19:36 +0100)]
using trb_net16_endpoint_hades_full_handler_record with a record for the slow control bus
Andreas Neiser [Thu, 8 Jan 2015 15:00:47 +0000 (16:00 +0100)]
ADC: Make sim work on non-Frankfurt systems, dont forget to actually create the vsim library inside the lattice diamond installation
Jan Michel [Wed, 17 Dec 2014 18:27:08 +0000 (19:27 +0100)]
updated ADC with new pulse shape processing. Simulation ok, par works fine, but not tested in hardware yet
Jan Michel [Wed, 17 Dec 2014 15:55:07 +0000 (16:55 +0100)]
added MAC component
Manuel Penschuck [Mon, 15 Dec 2014 21:31:10 +0000 (22:31 +0100)]
CTS: Moved selection of trigger module into config file; added config for tof
Cahit [Thu, 11 Dec 2014 14:15:11 +0000 (15:15 +0100)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Thu, 11 Dec 2014 14:13:35 +0000 (15:13 +0100)]
light mode tdc is implemented
Cahit [Thu, 11 Dec 2014 14:08:06 +0000 (15:08 +0100)]
tp modules are linked to the current release directory
Cahit [Thu, 11 Dec 2014 13:39:24 +0000 (14:39 +0100)]
cbmtof design brought up to tdc_v2.0
Andreas Neiser [Mon, 8 Dec 2014 15:47:56 +0000 (16:47 +0100)]
ADC: Sim: Cosmetic fixes
Andreas Neiser [Mon, 8 Dec 2014 15:39:13 +0000 (16:39 +0100)]
ADC: Sim: Correct compile order for VHDL files
Andreas Neiser [Mon, 8 Dec 2014 13:31:29 +0000 (14:31 +0100)]
ADC: Sim: Add dummy version.vhd for simulation
Andreas Neiser [Mon, 8 Dec 2014 13:28:15 +0000 (14:28 +0100)]
ADC: Sim: use relative path names, work library still needs to be recreated
Cahit [Fri, 5 Dec 2014 14:59:49 +0000 (15:59 +0100)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Fri, 5 Dec 2014 14:59:04 +0000 (15:59 +0100)]
calibration and data trigger switching problem is fixed
Jan Michel [Fri, 5 Dec 2014 13:44:27 +0000 (14:44 +0100)]
added buffer size setting to config file of 32pin AddOn
Jan Michel [Fri, 5 Dec 2014 12:49:35 +0000 (13:49 +0100)]
added included features to ADC config file
Jan Michel [Fri, 5 Dec 2014 12:32:05 +0000 (13:32 +0100)]
added few more control registers for ADC
Andreas Neiser [Thu, 4 Dec 2014 12:48:19 +0000 (13:48 +0100)]
CTS: map needs correct arguments...args
Cahit [Thu, 4 Dec 2014 09:10:12 +0000 (10:10 +0100)]
projects made compatible with tdc_v2.0.0
Cahit [Thu, 4 Dec 2014 09:08:12 +0000 (10:08 +0100)]
trigger window bug fix and constraints update for v2.0.0
Cahit [Wed, 3 Dec 2014 08:25:49 +0000 (09:25 +0100)]
conflict fix
Cahit [Wed, 3 Dec 2014 08:22:43 +0000 (09:22 +0100)]
tdc_v1.6.3 is made back compatible
Cahit [Wed, 3 Dec 2014 08:20:53 +0000 (09:20 +0100)]
encoder name correctiongit add Channel.vhd Channel_200.vhd Encoder_304_Bit.vhd Readout.vhd TDC.vhd tdc_components.vhd
Andreas Neiser [Wed, 3 Dec 2014 08:02:09 +0000 (09:02 +0100)]
CTS: Minor compile scripts fixes
Manuel Penschuck [Tue, 2 Dec 2014 21:37:51 +0000 (22:37 +0100)]
CTS: Clock select based on config-constant
Manuel Penschuck [Tue, 2 Dec 2014 21:37:21 +0000 (22:37 +0100)]
CTS: ITC on input mux
Manuel Penschuck [Tue, 2 Dec 2014 21:37:04 +0000 (22:37 +0100)]
CTS: Total dead time counter
Andreas Neiser [Tue, 2 Dec 2014 14:57:33 +0000 (15:57 +0100)]
CTS: Compile script uses single core par, fix bitgen call
Andreas Neiser [Tue, 2 Dec 2014 14:37:26 +0000 (15:37 +0100)]
CTS: Remove DRIVE for JTTL ports
Andreas Neiser [Tue, 2 Dec 2014 12:48:32 +0000 (13:48 +0100)]
Should be rom_encoder_3...
Andreas Neiser [Tue, 2 Dec 2014 12:00:01 +0000 (13:00 +0100)]
CTS: Make it work if no CBM but TDC is enabled
Andreas Neiser [Tue, 2 Dec 2014 11:59:15 +0000 (12:59 +0100)]
CTS compile script fixes to make it work for Manuel...
Andreas Neiser [Tue, 2 Dec 2014 11:58:39 +0000 (12:58 +0100)]
CTS changes to make 1.7.x / 1.6.3 TDC switch easier
Andreas Neiser [Tue, 2 Dec 2014 11:57:47 +0000 (12:57 +0100)]
TDC 1.6.3 changes to conform with 1.7.x component handling
Cahit [Tue, 2 Dec 2014 10:41:50 +0000 (11:41 +0100)]
rom encoder update for tdc 1.6.3
Cahit [Tue, 2 Dec 2014 10:27:17 +0000 (11:27 +0100)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Tue, 2 Dec 2014 10:27:11 +0000 (11:27 +0100)]
tdc_components.vhd for tdc version 1.6.x
Andreas Neiser [Tue, 2 Dec 2014 09:28:41 +0000 (10:28 +0100)]
CTS: Compile on lxhadeb07 does not work...Synplify cant handle missing component declaration?
Andreas Neiser [Tue, 2 Dec 2014 08:24:07 +0000 (09:24 +0100)]
CTS: Compile scripts updated, syncing config.vhd
Jan Michel [Mon, 1 Dec 2014 18:41:24 +0000 (19:41 +0100)]
update ADC code
Cahit [Mon, 1 Dec 2014 15:18:21 +0000 (16:18 +0100)]
32PinAddOn Design updated for tdc_v2.0
Cahit [Mon, 1 Dec 2014 15:10:04 +0000 (16:10 +0100)]
tdc release notes update
Cahit [Mon, 1 Dec 2014 15:07:33 +0000 (16:07 +0100)]
Merge branch 'master' of jspc29.x-matter.uni-frankfurt.de:trb3
Cahit [Mon, 1 Dec 2014 15:07:21 +0000 (16:07 +0100)]
GPIN addon design pin correction
Cahit [Mon, 1 Dec 2014 14:29:14 +0000 (15:29 +0100)]
top files and component files for the tdc version 2.0
Cahit [Mon, 1 Dec 2014 11:35:14 +0000 (12:35 +0100)]
unnecessary files are removed from tdc test folder
Cahit [Mon, 1 Dec 2014 11:33:19 +0000 (12:33 +0100)]
constraints update for version 1.6.3
Cahit [Mon, 1 Dec 2014 11:32:23 +0000 (12:32 +0100)]
tdc_v2.0 release
Andreas Neiser [Fri, 28 Nov 2014 15:28:29 +0000 (16:28 +0100)]
ADC: correct address range to include invalid words as well
Jan Michel [Fri, 28 Nov 2014 14:25:46 +0000 (15:25 +0100)]
one more attribute to get timing right
Jan Michel [Fri, 21 Nov 2014 15:17:24 +0000 (16:17 +0100)]
fixed timeout on sctrl bus in hub without gbe
Manuel Penschuck [Thu, 6 Nov 2014 08:10:48 +0000 (09:10 +0100)]
CBMNet: Reboot DLM availabe (send 3 DLMS: 0xd, 0x1, 0xe). Optional GBE disable
Manuel Penschuck [Thu, 6 Nov 2014 08:09:40 +0000 (09:09 +0100)]
CTS: JTTL(15) functions as reboot input (provide 1.28us high-pulse)
Manuel Penschuck [Mon, 3 Nov 2014 09:37:31 +0000 (10:37 +0100)]
CBMNet: Reminder to myself: Don't connect the Reset-Input of a synchroniser to the very reset-signal you want to synchronise ;)
Manuel Penschuck [Mon, 3 Nov 2014 09:09:35 +0000 (10:09 +0100)]
CTS: Back up TDC 1.6.3, Better constraints for design
Manuel Penschuck [Mon, 3 Nov 2014 09:06:24 +0000 (10:06 +0100)]
CBMNet: Test design compatible to bridge, test-lines added, clean-up, constraints
Manuel Penschuck [Mon, 3 Nov 2014 09:02:24 +0000 (10:02 +0100)]
MBS-Recv(+Billboard): Introduced optional Timestamps and Regio-Master
Manuel Penschuck [Mon, 3 Nov 2014 09:00:24 +0000 (10:00 +0100)]
CBMNet: Misc. Clean-Up
Manuel Penschuck [Mon, 3 Nov 2014 08:50:52 +0000 (09:50 +0100)]
CBMNet: Remove OBuf as not required anymore
Manuel Penschuck [Mon, 3 Nov 2014 08:49:33 +0000 (09:49 +0100)]
CBMNet: Undo new-style CTRLBUS as incompatible with ChipScope. Migrated to new new CBMNet PCS-Init-Module, Added some synchroniser (that should not be vital), code clean-up
Manuel Penschuck [Sun, 26 Oct 2014 20:25:06 +0000 (21:25 +0100)]
CTS: Migrated back to TDC 1.6.3 and code clean up
Manuel Penschuck [Sun, 26 Oct 2014 20:24:37 +0000 (21:24 +0100)]
CTS: Migrated back to TDC 1.6.3 and code clean up
Manuel Penschuck [Sun, 26 Oct 2014 20:22:30 +0000 (21:22 +0100)]
CBMNet: PCS-Reset issued when receive a Link-Reinit, Generic signal_sync in contrast to manual syncs, code clean-up
Manuel Penschuck [Sun, 26 Oct 2014 20:20:32 +0000 (21:20 +0100)]
Billboard: Corrected HW-ID
Manuel Penschuck [Sun, 26 Oct 2014 20:18:29 +0000 (21:18 +0100)]
Merge conflict
Jan Michel [Sun, 26 Oct 2014 18:28:14 +0000 (19:28 +0100)]
added checker for ADC words
Manuel Penschuck [Sat, 25 Oct 2014 19:33:20 +0000 (21:33 +0200)]
CBMNET: TX-GEAR back-up
Manuel Penschuck [Fri, 24 Oct 2014 20:38:38 +0000 (22:38 +0200)]
Add Billboard design (includes storage billboard and MBS receiver)
Jan Michel [Thu, 23 Oct 2014 17:11:38 +0000 (19:11 +0200)]
added sed checker to ADC design
Manuel Penschuck [Thu, 23 Oct 2014 14:59:36 +0000 (16:59 +0200)]
CTS: Backup before migrating to TDC v1.6.3 and MBS
Cahit [Mon, 20 Oct 2014 14:38:33 +0000 (16:38 +0200)]
symbolic links for the top entities
Cahit [Mon, 20 Oct 2014 14:33:44 +0000 (16:33 +0200)]
conflict fix
Cahit [Mon, 20 Oct 2014 14:13:50 +0000 (16:13 +0200)]
tdc release 2.0.xx
Cahit [Mon, 20 Oct 2014 14:12:55 +0000 (16:12 +0200)]
tdc release 1.7.xx
Cahit [Mon, 20 Oct 2014 14:10:06 +0000 (16:10 +0200)]
top file update for designs
Cahit [Mon, 20 Oct 2014 14:08:37 +0000 (16:08 +0200)]
base folder update
Cahit [Mon, 20 Oct 2014 14:07:29 +0000 (16:07 +0200)]
wasa design update
Cahit [Mon, 20 Oct 2014 14:06:40 +0000 (16:06 +0200)]
ADA Addon design update
Cahit [Mon, 20 Oct 2014 14:06:08 +0000 (16:06 +0200)]
32PinAddOn design update
jspc29 / trb3.git / log