jspc29.x-matter.uni-frankfurt.de Git

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hadeshyp [Fri, 22 Oct 2010 08:59:03 +0000 (08:59 +0000)]

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hadeshyp [Tue, 19 Oct 2010 16:45:42 +0000 (16:45 +0000)]

The xilinx fifo 19x16 for the lvl1 handler of the Full Endpoint Handler
Boris

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hadeshyp [Tue, 19 Oct 2010 16:43:16 +0000 (16:43 +0000)]

The ddr_off entity (DDR OBUF) for the med_IC component
Boris

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hadeshyp [Tue, 19 Oct 2010 15:09:00 +0000 (15:09 +0000)]

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hadeshyp [Thu, 14 Oct 2010 18:55:24 +0000 (18:55 +0000)]

the med_IC was removed.
A new ddr_off will be added soon to the xilinx/virtex4
Boris :)

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hadeshyp [Tue, 12 Oct 2010 13:52:56 +0000 (13:52 +0000)]

Added trb_net16_med_16_IC.vhd for Xilinix to the xilinx/ directory.
This entity uses a Virtex4 output buffer ODDR to provide the clock signal
to the external entity.

Boris

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hadeshyp [Mon, 11 Oct 2010 11:42:51 +0000 (11:42 +0000)]

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hadeshyp [Fri, 8 Oct 2010 14:09:11 +0000 (14:09 +0000)]

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hadaq [Thu, 19 Aug 2010 08:34:02 +0000 (08:34 +0000)]

wrong depth on 16k and 32k fifos

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hadeshyp [Tue, 17 Aug 2010 13:35:57 +0000 (13:35 +0000)]

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hadeshyp [Thu, 22 Jul 2010 14:48:22 +0000 (14:48 +0000)]

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hadaq [Thu, 15 Jul 2010 15:32:13 +0000 (15:32 +0000)]

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hadaq [Thu, 15 Jul 2010 15:29:38 +0000 (15:29 +0000)]

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hadaq [Mon, 12 Jul 2010 16:05:31 +0000 (16:05 +0000)]

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hadeshyp [Fri, 9 Jul 2010 13:04:43 +0000 (13:04 +0000)]

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hadaq [Fri, 9 Jul 2010 08:32:48 +0000 (08:32 +0000)]

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hadaq [Fri, 9 Jul 2010 08:32:34 +0000 (08:32 +0000)]

changed LINK_BROKEN_OUT to one cycle pulse, according to Master Jan's wish :-)

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hadaq [Fri, 9 Jul 2010 07:51:59 +0000 (07:51 +0000)]

New entity for forwarding only full packets from SerDes to media interface.
Written to workaround the "MDC I sparking kills da optical link" problem.
Not suitable for real fibre links (2GB), as it also does 25MHz/100MHz conversion
as well as 8b/16b by FIFO.

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hadaq [Fri, 9 Jul 2010 07:49:48 +0000 (07:49 +0000)]

Prepared for new "receive only full packets" stuff.

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hadaq [Fri, 9 Jul 2010 07:45:30 +0000 (07:45 +0000)]

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hadaq [Fri, 9 Jul 2010 07:43:17 +0000 (07:43 +0000)]

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hadaq [Thu, 1 Jul 2010 09:46:56 +0000 (09:46 +0000)]

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hadaq [Thu, 1 Jul 2010 09:18:26 +0000 (09:18 +0000)]

for LVL1 handler, taken from ADCMv3

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hadeshyp [Thu, 1 Jul 2010 08:08:01 +0000 (08:08 +0000)]

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hadeshyp [Thu, 1 Jul 2010 08:07:18 +0000 (08:07 +0000)]

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hadeshyp [Wed, 30 Jun 2010 22:22:58 +0000 (22:22 +0000)]

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hadaq [Wed, 30 Jun 2010 16:17:35 +0000 (16:17 +0000)]

Typos corrected, doubles removed, now loads in ispLever8.1 Windows without spellcheck errors.

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hadaq [Wed, 30 Jun 2010 16:08:15 +0000 (16:08 +0000)]

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hadaq [Wed, 30 Jun 2010 15:50:00 +0000 (15:50 +0000)]

First try, will most likely not compile.
Clock domains must be checked completely.
Reset sequence most likely not suitable.
RX delay registers between SerDes and byte swapper removed.
Too many bullshit comments in.

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hadaq [Wed, 30 Jun 2010 15:48:18 +0000 (15:48 +0000)]

first try (no warranty!) after studying some of the 344 pages of SCM SerDes documentation:
SerDes is operated in G8B10B mode, with GbE LSM enabled, and CTC mode switched on.
Latter two points must be done "by hand" inside the *.txt config file.
Important: hands off the quad_rst input!

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hadaq [Tue, 29 Jun 2010 09:29:16 +0000 (09:29 +0000)]