From 00b7de12c1e7d27bcebb3887fc14a529e89ae82d Mon Sep 17 00:00:00 2001 From: Hadaq in Frankfurt Date: Fri, 15 Mar 2013 14:45:33 +0100 Subject: [PATCH] changed chain trbnet addresses to new version, for which vhdl is in development bn --- soft/README.txt | 2 + soft/toolbox/jtag_atomic/boards.ini | 21 +- soft/toolbox/jtag_atomic/chains.ini | 142 +++--- soft/toolbox/jtag_atomic/chains.ini.chain0 | 52 +-- soft/toolbox/jtag_atomic/chains.ini.chain1 | 46 +- soft/toolbox/jtag_atomic/chains.ini.chain2 | 44 +- .../jtag_atomic/generate_chainorder.pl | 2 +- soft/toolbox/jtag_atomic/the_gui.pl | 353 +-------------- soft/toolbox/jtag_atomic/ui.pl | 413 +----------------- soft/toolbox/jtag_atomic/ui_generators.pl | 375 ++++++++++++++++ soft/toolbox/jtag_atomic/ui_writeram.pl | 2 +- 11 files changed, 537 insertions(+), 915 deletions(-) create mode 100644 soft/toolbox/jtag_atomic/ui_generators.pl diff --git a/soft/README.txt b/soft/README.txt index 720e22f..ce92c35 100644 --- a/soft/README.txt +++ b/soft/README.txt @@ -90,6 +90,8 @@ ui_trigger_all_chains.sh: and after this sending of the START-Signal on all 3 chains simultaneously. ************************************************ +ui_generators.pl: + Generates the routines for ui.pl and the_gui.pl ui_writeram.pl: Is executed as part of ui.pl. This script writes the RAM1a (of the selected chain). diff --git a/soft/toolbox/jtag_atomic/boards.ini b/soft/toolbox/jtag_atomic/boards.ini index fc2e68b..def4577 100644 --- a/soft/toolbox/jtag_atomic/boards.ini +++ b/soft/toolbox/jtag_atomic/boards.ini @@ -5,17 +5,16 @@ FPGAboard_staplfilename=jcb_trb_009.stapl FPGAboard_staplfilename_delay1=jcb_trb_008.stapl FPGAboard_addonortrb=trb FPGAtrbnetAddr=0xf013 -CONFperiod_trbnetAddr=0xc001 -CONFoffspillcounter_trbnetAddr=0xc002 -CONFwaitstart_trbnetAddr=0xc007 -CONFtriginitseq_trbnetAddr=0xc003 -CONFtrigmapsstart_trbnetAddr=0xc00b -CONFtrigmapsreset_trbnetAddr=0xc00a -CONFtrigrunjtag_trbnetAddr=0xc00f -CONFtrigwriteonce_trbnetAddr=0xc014 -;gui_defaults is a comma-separated list of the following strings representing buttons in the gui: -;'h_prog_fpga','h_start_trbnetd','h_period_0_15s','h_period_1s','h_period_10s', 'h_no_period' +CONFwaitstart_trbnetAddr=0xb007 +CONFtriginitseq_trbnetAddr=0xb003 +CONFtrigmapsstart_trbnetAddr=0xb00b +CONFtrigmapsreset_trbnetAddr=0xb00a +CONFtrigrunjtag_trbnetAddr=0xb00f +CONFtrigwriteonce_trbnetAddr=0xb014 +;guiBM_NP_defaults is a comma-separated list of the following strings representing buttons in the gui: +;'h_prog_fpga','h_start_trbnetd','h_period_0_15s', 'h_waitbeforestart_6us', 'h_waitbeforestart_1ms' , +;'h_waitbeforestart_1s', 'h_trigger_init_sequence', 'h_maps_reset', 'h_run_jtag', 'h_write_once', +;'h_maps_start' ;be aware that h_prog_fpga doesn't wait until the optical link is up on the Trb -gui_defaults=h_period_0_15s guiBM_NP_defaults=h_waitbeforestart_6us diff --git a/soft/toolbox/jtag_atomic/chains.ini b/soft/toolbox/jtag_atomic/chains.ini index 1a44926..072ee22 100644 --- a/soft/toolbox/jtag_atomic/chains.ini +++ b/soft/toolbox/jtag_atomic/chains.ini @@ -2,42 +2,38 @@ [chain1] FPGAtrbnetAddr=0xf013 -RAMtrbnetAddr=0xb000 -CMDreg_trbnetAddr=0xb120 -RAMbase_trbnetAddr=0xb121 -DATAreg_trbnetAddr=0xb122 -STATUS2RAM3BBASEADDRREGtrbnetAddr=0xb163 -STATUS2RAM3BtrbnetAddr=0xb170 -CONFsignals_trbnetAddr=0xc006 -CONFresetafterfirstwrite_trbnetAddr=0xc011 -CONFresetbeforeinit_trbnetAddr=0xc010 -CONFtrigmapsstart_trbnetAddr=0xc00e -CONFtrigmapsreset_trbnetAddr=0xc00d -CONFtrigrunjtag_trbnetAddr=0xc00f -CONFtrigwriteonce_trbnetAddr=0xc014 -CONFtriginitseq_trbnetAddr=0xc00c +RAMtrbnetAddr=0xa000 +CMDreg_trbnetAddr=0xa120 +RAMbase_trbnetAddr=0xa121 +DATAreg_trbnetAddr=0xa122 +STATUS2RAM3BBASEADDRREGtrbnetAddr=0xa163 +STATUS2RAM3BtrbnetAddr=0xa170 +CONFsignals_trbnetAddr=0xb020 +CONFresetafterfirstwrite_trbnetAddr=0xb011 +CONFresetbeforeinit_trbnetAddr=0xb010 +CONFtrigmapsstart_trbnetAddr=0xb00e +CONFtrigmapsreset_trbnetAddr=0xb00d +CONFtrigrunjtag_trbnetAddr=0xb00f +CONFtrigwriteonce_trbnetAddr=0xb014 +CONFtriginitseq_trbnetAddr=0xb00c chainnr=0 -DEBUGram1baddr=0xb147 -DEBUGram1bdata=0xb148 -DEBUGram1caddr=0xb149 -DEBUGram1cdata=0xb14a -DEBUGram1crun=0xb14b -;CONFperiod_trbnetAddr=0xc001 -;CONFoffspillcounter_trbnetAddr=0xc002 -;CONFwaitstart_trbnetAddr=0xc007 +DEBUGram1baddr=0xa147 +DEBUGram1bdata=0xa148 +DEBUGram1caddr=0xa149 +DEBUGram1cdata=0xa14a +DEBUGram1crun=0xa14b +;CONFwaitstart_trbnetAddr=0xb007 FPGAboard_hostname=trb126 ;FPGAboard_staplfilename=jcb_trb_007.stapl FPGAboard_staplfilename=jcb_trb_009.stapl FPGAboard_staplfilename_delay1=jcb_trb_008.stapl FPGAboard_addonortrb=trb -; gui_defaults1/gui_defaults2 is a comma separated list of the following strings representing buttons in the gui: -;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz', -;'h_start', 'h_stop', 'h_set_inout', 'h_maps_reset_on', 'h_maps_reset_off', 'h_maps_start_on', 'h_maps_start_off', -;'h_maps_clk_on', 'h_maps_clk_off' +; guiBM_NP_defaults1/guiBM_NP_defaults2 is a comma separated list of the following strings representing buttons in the gui: +;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz', 'h_set_timing_100khz', +; 'h_set_inout', 'h_maps_reset_before_on', 'h_maps_reset_after_on', 'h_maps_reset_before_off', 'h_maps_reset_after_off', +;'h_maps_clk_on', 'h_maps_clk_off', 'h_trig_init_seq', 'h_maps_reset', 'h_run_jtag', 'h_write_once', 'h_maps_start' ; gui_defaults1: executed in this order, before board defaults -gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on ; gui_defaults2: executed in this order, after board defaults -gui_defaults2=h_start guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on guiBM_NP_defaults2="" @@ -51,30 +47,32 @@ JNR3_sensor1=sensor1.ini [chain2] FPGAtrbnetAddr=0xf013 -RAMtrbnetAddr=0xd000 -CMDreg_trbnetAddr=0xd120 -RAMbase_trbnetAddr=0xd121 -DATAreg_trbnetAddr=0xd122 -STATUS2RAM3BBASEADDRREGtrbnetAddr=0xd163 -STATUS2RAM3BtrbnetAddr=0xd170 -CONFsignals_trbnetAddr=0xc008 -CONFresetafterfirstwrite_trbnetAddr=0xc011 -CONFresetbeforeinit_trbnetAddr=0xc010 -CONFtrigmapsstart_trbnetAddr=0xc00e -CONFtrigmapsreset_trbnetAddr=0xc00d -CONFtrigrunjtag_trbnetAddr=0xc00f -CONFtrigwriteonce_trbnetAddr=0xc014 -CONFtriginitseq_trbnetAddr=0xc00c +RAMtrbnetAddr=0xa000 +CMDreg_trbnetAddr=0xa320 +RAMbase_trbnetAddr=0xa321 +DATAreg_trbnetAddr=0xa322 +STATUS2RAM3BBASEADDRREGtrbnetAddr=0xa363 +STATUS2RAM3BtrbnetAddr=0xa370 +CONFsignals_trbnetAddr=0xb021 +CONFresetafterfirstwrite_trbnetAddr=0xb011 +CONFresetbeforeinit_trbnetAddr=0xb010 +CONFtrigmapsstart_trbnetAddr=0xb00e +CONFtrigmapsreset_trbnetAddr=0xb00d +CONFtrigrunjtag_trbnetAddr=0xb00f +CONFtrigwriteonce_trbnetAddr=0xb014 +CONFtriginitseq_trbnetAddr=0xb00c chainnr=1 -DEBUGram1baddr=0xd147 -DEBUGram1bdata=0xd148 -DEBUGram1caddr=0xd149 -DEBUGram1cdata=0xd14a -DEBUGram1crun=0xd14b -;CONFperiod_trbnetAddr=0xc001 -gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on +DEBUGram1baddr=0xa347 +DEBUGram1bdata=0xa348 +DEBUGram1caddr=0xa349 +DEBUGram1cdata=0xa34a +DEBUGram1crun=0xa34b +; guiBM_NP_defaults1/guiBM_NP_defaults2 is a comma separated list of the following strings representing buttons in the gui: +;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz', 'h_set_timing_100khz', +; 'h_set_inout', 'h_maps_reset_before_on', 'h_maps_reset_after_on', 'h_maps_reset_before_off', 'h_maps_reset_after_off', +;'h_maps_clk_on', 'h_maps_clk_off', 'h_trig_init_seq', 'h_maps_reset', 'h_run_jtag', 'h_write_once', 'h_maps_start' +; gui_defaults1: executed in this order, before board defaults ; gui_defaults2: executed in this order, after board defaults -gui_defaults2=h_start guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on guiBM_NP_defaults2="" @@ -88,30 +86,32 @@ JNR3_sensor5=sensor5.ini [chain3] FPGAtrbnetAddr=0xf013 -RAMtrbnetAddr=0xe000 -CMDreg_trbnetAddr=0xe120 -RAMbase_trbnetAddr=0xe121 -DATAreg_trbnetAddr=0xe122 +RAMtrbnetAddr=0xa400 +CMDreg_trbnetAddr=0xa520 +RAMbase_trbnetAddr=0xa521 +DATAreg_trbnetAddr=0xa522 STATUS2RAM3BBASEADDRREGtrbnetAddr=0xe163 -STATUS2RAM3BtrbnetAddr=0xe170 -CONFsignals_trbnetAddr=0xc009 -CONFresetafterfirstwrite_trbnetAddr=0xc011 -CONFresetbeforeinit_trbnetAddr=0xc010 -CONFtrigmapsstart_trbnetAddr=0xc00e -CONFtrigmapsreset_trbnetAddr=0xc00d -CONFtrigrunjtag_trbnetAddr=0xc00f -CONFtrigwriteonce_trbnetAddr=0xc014 -CONFtriginitseq_trbnetAddr=0xc00c +STATUS2RAM3BtrbnetAddr=0xa570 +CONFsignals_trbnetAddr=0xb022 +CONFresetafterfirstwrite_trbnetAddr=0xb011 +CONFresetbeforeinit_trbnetAddr=0xb010 +CONFtrigmapsstart_trbnetAddr=0xb00e +CONFtrigmapsreset_trbnetAddr=0xb00d +CONFtrigrunjtag_trbnetAddr=0xb00f +CONFtrigwriteonce_trbnetAddr=0xb014 +CONFtriginitseq_trbnetAddr=0xb00c chainnr=2 -DEBUGram1baddr=0xe147 -DEBUGram1bdata=0xe148 -DEBUGram1caddr=0xe149 -DEBUGram1cdata=0xe14a -DEBUGram1crun=0xe14b -;CONFperiod_trbnetAddr=0xc001 -gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on +DEBUGram1baddr=0xa547 +DEBUGram1bdata=0xa548 +DEBUGram1caddr=0xa549 +DEBUGram1cdata=0xa54a +DEBUGram1crun=0xa54b +; guiBM_NP_defaults1/guiBM_NP_defaults2 is a comma separated list of the following strings representing buttons in the gui: +;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz', 'h_set_timing_100khz', +; 'h_set_inout', 'h_maps_reset_before_on', 'h_maps_reset_after_on', 'h_maps_reset_before_off', 'h_maps_reset_after_off', +;'h_maps_clk_on', 'h_maps_clk_off', 'h_trig_init_seq', 'h_maps_reset', 'h_run_jtag', 'h_write_once', 'h_maps_start' +; gui_defaults1: executed in this order, before board defaults ; gui_defaults2: executed in this order, after board defaults -gui_defaults2=h_start guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on guiBM_NP_defaults2="" diff --git a/soft/toolbox/jtag_atomic/chains.ini.chain0 b/soft/toolbox/jtag_atomic/chains.ini.chain0 index 7d5aaba..585713f 100644 --- a/soft/toolbox/jtag_atomic/chains.ini.chain0 +++ b/soft/toolbox/jtag_atomic/chains.ini.chain0 @@ -1,40 +1,36 @@ FPGAtrbnetAddr=0xf013 -RAMtrbnetAddr=0xb000 -CMDreg_trbnetAddr=0xb120 -RAMbase_trbnetAddr=0xb121 -DATAreg_trbnetAddr=0xb122 -STATUS2RAM3BBASEADDRREGtrbnetAddr=0xb163 -STATUS2RAM3BtrbnetAddr=0xb170 -CONFsignals_trbnetAddr=0xc006 -CONFresetafterfirstwrite_trbnetAddr=0xc011 -CONFresetbeforeinit_trbnetAddr=0xc010 -CONFtrigmapsstart_trbnetAddr=0xc00e -CONFtrigmapsreset_trbnetAddr=0xc00d -CONFtrigrunjtag_trbnetAddr=0xc00f -CONFtrigwriteonce_trbnetAddr=0xc014 -CONFtriginitseq_trbnetAddr=0xc00c +RAMtrbnetAddr=0xa000 +CMDreg_trbnetAddr=0xa120 +RAMbase_trbnetAddr=0xa121 +DATAreg_trbnetAddr=0xa122 +STATUS2RAM3BBASEADDRREGtrbnetAddr=0xa163 +STATUS2RAM3BtrbnetAddr=0xa170 +CONFsignals_trbnetAddr=0xb020 +CONFresetafterfirstwrite_trbnetAddr=0xb011 +CONFresetbeforeinit_trbnetAddr=0xb010 +CONFtrigmapsstart_trbnetAddr=0xb00e +CONFtrigmapsreset_trbnetAddr=0xb00d +CONFtrigrunjtag_trbnetAddr=0xb00f +CONFtrigwriteonce_trbnetAddr=0xb014 +CONFtriginitseq_trbnetAddr=0xb00c chainnr=0 -DEBUGram1baddr=0xb147 -DEBUGram1bdata=0xb148 -DEBUGram1caddr=0xb149 -DEBUGram1cdata=0xb14a -DEBUGram1crun=0xb14b -;CONFperiod_trbnetAddr=0xc001 -;CONFoffspillcounter_trbnetAddr=0xc002 -;CONFwaitstart_trbnetAddr=0xc007 +DEBUGram1baddr=0xa147 +DEBUGram1bdata=0xa148 +DEBUGram1caddr=0xa149 +DEBUGram1cdata=0xa14a +DEBUGram1crun=0xa14b +;CONFwaitstart_trbnetAddr=0xb007 FPGAboard_hostname=trb126 ;FPGAboard_staplfilename=jcb_trb_007.stapl FPGAboard_staplfilename=jcb_trb_009.stapl FPGAboard_staplfilename_delay1=jcb_trb_008.stapl FPGAboard_addonortrb=trb -; gui_defaults1/gui_defaults2 is a comma separated list of the following strings representing buttons in the gui: -;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz', -;'h_start', 'h_stop', 'h_set_inout', 'h_maps_reset_on', 'h_maps_reset_off', 'h_maps_start_on', 'h_maps_start_off', -;'h_maps_clk_on', 'h_maps_clk_off' +; guiBM_NP_defaults1/guiBM_NP_defaults2 is a comma separated list of the following strings representing buttons in the gui: +;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz', 'h_set_timing_100khz', +; 'h_set_inout', 'h_maps_reset_before_on', 'h_maps_reset_after_on', 'h_maps_reset_before_off', 'h_maps_reset_after_off', +;'h_maps_clk_on', 'h_maps_clk_off', 'h_trig_init_seq', 'h_maps_reset', 'h_run_jtag', 'h_write_once', 'h_maps_start' ; gui_defaults1: executed in this order, before board defaults -gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on ; gui_defaults2: executed in this order, after board defaults -gui_defaults2=h_start guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on guiBM_NP_defaults2="" diff --git a/soft/toolbox/jtag_atomic/chains.ini.chain1 b/soft/toolbox/jtag_atomic/chains.ini.chain1 index 2d652dd..4d1866d 100644 --- a/soft/toolbox/jtag_atomic/chains.ini.chain1 +++ b/soft/toolbox/jtag_atomic/chains.ini.chain1 @@ -1,28 +1,30 @@ FPGAtrbnetAddr=0xf013 -RAMtrbnetAddr=0xd000 -CMDreg_trbnetAddr=0xd120 -RAMbase_trbnetAddr=0xd121 -DATAreg_trbnetAddr=0xd122 -STATUS2RAM3BBASEADDRREGtrbnetAddr=0xd163 -STATUS2RAM3BtrbnetAddr=0xd170 -CONFsignals_trbnetAddr=0xc008 -CONFresetafterfirstwrite_trbnetAddr=0xc011 -CONFresetbeforeinit_trbnetAddr=0xc010 -CONFtrigmapsstart_trbnetAddr=0xc00e -CONFtrigmapsreset_trbnetAddr=0xc00d -CONFtrigrunjtag_trbnetAddr=0xc00f -CONFtrigwriteonce_trbnetAddr=0xc014 -CONFtriginitseq_trbnetAddr=0xc00c +RAMtrbnetAddr=0xa000 +CMDreg_trbnetAddr=0xa320 +RAMbase_trbnetAddr=0xa321 +DATAreg_trbnetAddr=0xa322 +STATUS2RAM3BBASEADDRREGtrbnetAddr=0xa363 +STATUS2RAM3BtrbnetAddr=0xa370 +CONFsignals_trbnetAddr=0xb021 +CONFresetafterfirstwrite_trbnetAddr=0xb011 +CONFresetbeforeinit_trbnetAddr=0xb010 +CONFtrigmapsstart_trbnetAddr=0xb00e +CONFtrigmapsreset_trbnetAddr=0xb00d +CONFtrigrunjtag_trbnetAddr=0xb00f +CONFtrigwriteonce_trbnetAddr=0xb014 +CONFtriginitseq_trbnetAddr=0xb00c chainnr=1 -DEBUGram1baddr=0xd147 -DEBUGram1bdata=0xd148 -DEBUGram1caddr=0xd149 -DEBUGram1cdata=0xd14a -DEBUGram1crun=0xd14b -;CONFperiod_trbnetAddr=0xc001 -gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on +DEBUGram1baddr=0xa347 +DEBUGram1bdata=0xa348 +DEBUGram1caddr=0xa349 +DEBUGram1cdata=0xa34a +DEBUGram1crun=0xa34b +; guiBM_NP_defaults1/guiBM_NP_defaults2 is a comma separated list of the following strings representing buttons in the gui: +;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz', 'h_set_timing_100khz', +; 'h_set_inout', 'h_maps_reset_before_on', 'h_maps_reset_after_on', 'h_maps_reset_before_off', 'h_maps_reset_after_off', +;'h_maps_clk_on', 'h_maps_clk_off', 'h_trig_init_seq', 'h_maps_reset', 'h_run_jtag', 'h_write_once', 'h_maps_start' +; gui_defaults1: executed in this order, before board defaults ; gui_defaults2: executed in this order, after board defaults -gui_defaults2=h_start guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on guiBM_NP_defaults2="" diff --git a/soft/toolbox/jtag_atomic/chains.ini.chain2 b/soft/toolbox/jtag_atomic/chains.ini.chain2 index f285980..2b7f6bb 100644 --- a/soft/toolbox/jtag_atomic/chains.ini.chain2 +++ b/soft/toolbox/jtag_atomic/chains.ini.chain2 @@ -1,28 +1,30 @@ FPGAtrbnetAddr=0xf013 -RAMtrbnetAddr=0xe000 -CMDreg_trbnetAddr=0xe120 -RAMbase_trbnetAddr=0xe121 -DATAreg_trbnetAddr=0xe122 +RAMtrbnetAddr=0xa400 +CMDreg_trbnetAddr=0xa520 +RAMbase_trbnetAddr=0xa521 +DATAreg_trbnetAddr=0xa522 STATUS2RAM3BBASEADDRREGtrbnetAddr=0xe163 -STATUS2RAM3BtrbnetAddr=0xe170 -CONFsignals_trbnetAddr=0xc009 -CONFresetafterfirstwrite_trbnetAddr=0xc011 -CONFresetbeforeinit_trbnetAddr=0xc010 -CONFtrigmapsstart_trbnetAddr=0xc00e -CONFtrigmapsreset_trbnetAddr=0xc00d -CONFtrigrunjtag_trbnetAddr=0xc00f -CONFtrigwriteonce_trbnetAddr=0xc014 -CONFtriginitseq_trbnetAddr=0xc00c +STATUS2RAM3BtrbnetAddr=0xa570 +CONFsignals_trbnetAddr=0xb022 +CONFresetafterfirstwrite_trbnetAddr=0xb011 +CONFresetbeforeinit_trbnetAddr=0xb010 +CONFtrigmapsstart_trbnetAddr=0xb00e +CONFtrigmapsreset_trbnetAddr=0xb00d +CONFtrigrunjtag_trbnetAddr=0xb00f +CONFtrigwriteonce_trbnetAddr=0xb014 +CONFtriginitseq_trbnetAddr=0xb00c chainnr=2 -DEBUGram1baddr=0xe147 -DEBUGram1bdata=0xe148 -DEBUGram1caddr=0xe149 -DEBUGram1cdata=0xe14a -DEBUGram1crun=0xe14b -;CONFperiod_trbnetAddr=0xc001 -gui_defaults1=h_stop,h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_on +DEBUGram1baddr=0xa547 +DEBUGram1bdata=0xa548 +DEBUGram1caddr=0xa549 +DEBUGram1cdata=0xa54a +DEBUGram1crun=0xa54b +; guiBM_NP_defaults1/guiBM_NP_defaults2 is a comma separated list of the following strings representing buttons in the gui: +;'h_man_maps_reset', 'h_delay0', 'h_delay1', 'h_delay2', 'h_delay3', 'h_prog_ram', 'h_set_timing_10mhz', 'h_set_timing_1mhz', 'h_set_timing_100khz', +; 'h_set_inout', 'h_maps_reset_before_on', 'h_maps_reset_after_on', 'h_maps_reset_before_off', 'h_maps_reset_after_off', +;'h_maps_clk_on', 'h_maps_clk_off', 'h_trig_init_seq', 'h_maps_reset', 'h_run_jtag', 'h_write_once', 'h_maps_start' +; gui_defaults1: executed in this order, before board defaults ; gui_defaults2: executed in this order, after board defaults -gui_defaults2=h_start guiBM_NP_defaults1=h_delay1,h_prog_ram,h_set_timing_10mhz,h_set_inout,h_maps_reset_before_off,h_maps_reset_after_on guiBM_NP_defaults2="" diff --git a/soft/toolbox/jtag_atomic/generate_chainorder.pl b/soft/toolbox/jtag_atomic/generate_chainorder.pl index c87ac62..f6c683a 100755 --- a/soft/toolbox/jtag_atomic/generate_chainorder.pl +++ b/soft/toolbox/jtag_atomic/generate_chainorder.pl @@ -8,7 +8,7 @@ my $chaincol = 1; # column of chain name, column counting from zero my $jnrcol = 2; # column of JNR for sorting, column counting from zero my $minnumcols = 4; -open(PROTOTYPEDBFILE,"/daq/toolbox/prototype_setup.db") || die("Cannot open file chains.ini!"); +open(PROTOTYPEDBFILE,"../prototype_setup.db") || die("Cannot open file chains.ini!"); my @lines_db = ; close(PROTOTYPEDBFILE); my $keydesc = 0; diff --git a/soft/toolbox/jtag_atomic/the_gui.pl b/soft/toolbox/jtag_atomic/the_gui.pl index eac3a6f..b602b82 100755 --- a/soft/toolbox/jtag_atomic/the_gui.pl +++ b/soft/toolbox/jtag_atomic/the_gui.pl @@ -5,6 +5,7 @@ use lib "./libs/"; use Config::Abstract::Ini; use POSIX qw(strftime); use FileHandle; +require "./ui_generators.pl"; $ENV{DAQOPSERVER}='trb124'; if(not( -e "/tmp/jtag_initmem")) { @@ -199,356 +200,6 @@ sub execute_shell_command_return { } -sub generate_h_man_maps_reset { - my ($chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg( "manual reset chain " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $resetnormal = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $resetinv = int_to_32bit_hex((~(1 << 10 )) & hex($resetnormal)); - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$resetinv 2>&1 && sleep 1 && trbcmd w $fpga_addr $conf_signals_addr $resetnormal 2>&1", ""); - } -} - -sub generate_h_maps_start_signal { - my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg( "generate MAPS start $onoroff " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $before = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $newval; - if($onoroff == 0) { - #off - $newval = int_to_32bit_hex((~(1<<9)) & hex($before)); - } - else { - #on - $newval = int_to_32bit_hex(((1<<9)) | hex($before)); - } - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", ""); - } -} -sub generate_h_maps_reset_signal { - my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg("MAPS reset signal $onoroff " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $before = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $newval; - if($onoroff == 0) { - #off - $newval = int_to_32bit_hex((~(1<< 11)) & hex($before)); - } - else { - #on - $newval = int_to_32bit_hex(((1<< 11)) | hex($before)); - } - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval", ""); - } -} -sub generate_h_maps_clk_signal { - my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg("generate MAPS clk $onoroff " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); - - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $before = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $newval; - if($onoroff == 0) { - #off - $newval = int_to_32bit_hex((~(1<< 13)) & hex($before)); - } - else { - #on - $newval = int_to_32bit_hex(((1<< 13)) | hex($before)); - } - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", ""); - } -} -sub generate_h_prog_ram { - my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, $numsensors, $memfilenames_ref) = @_; - my @memfilenames = @{$memfilenames_ref}; - return sub { - init_msg("program RAM $chain."); - execute_shell_command("./ui_writeram.pl -c $chain -q", "$chain: done.\n"); # load sensor*.ini - } -} - -sub generate_h_set_timing_10mhz { - my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_; - return sub { - init_msg("timing 10 MHz $chain."); - my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP -trbcmd w $fpga_addr $data_reg_addr 0x0000000A 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH -trbcmd w $fpga_addr $data_reg_addr 0x00000003 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1 -trbcmd w $fpga_addr $data_reg_addr 0x00000008 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2 -trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1 -trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2 -trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3 -trbcmd w $fpga_addr $data_reg_addr 0x00000009 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME -trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START"; - #reportd $cmdline; - #system($cmdline); - execute_shell_command($cmdline, ""); - } -} - -sub generate_h_set_timing_1mhz { - my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_; - return sub { - init_msg("timing 1 MHz $chain."); - my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP -trbcmd w $fpga_addr $data_reg_addr 0x00000064 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH -trbcmd w $fpga_addr $data_reg_addr 0x00000031 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1 -trbcmd w $fpga_addr $data_reg_addr 0x00000062 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2 -trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1 -trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2 -trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3 -trbcmd w $fpga_addr $data_reg_addr 0x00000063 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME -trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START"; - execute_shell_command($cmdline, ""); - } -} - -sub generate_h_set_timing_100khz { - my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_; - return sub { - init_msg("timing 100 kHz $chain."); - my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP -trbcmd w $fpga_addr $data_reg_addr 0x000003E8 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH -trbcmd w $fpga_addr $data_reg_addr 0x000001CC 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1 -trbcmd w $fpga_addr $data_reg_addr 0x000003C0 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2 -trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1 -trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2 -trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3 -trbcmd w $fpga_addr $data_reg_addr 0x000003E7 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME -trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START"; - execute_shell_command($cmdline, ""); - } -} - - - -sub generate_h_delay { - my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $delay) = @_; - return sub { - init_msg("Delay $delay $chain."); - my $cmdline = "trbcmd w $fpga_addr $data_reg_addr 0x".int_to_32bit_hex($delay)." 2>&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000067 2>&1 # COMMAND: M26C_CMD_SET_DELAY_EXPECTED_VALUES"; - execute_shell_command($cmdline, ""); - } -} - -sub generate_h_waitbeforestart_6us { - - my($board, $fpga_addr, $conf_waitstart_addr) = @_; - return sub { - init_msg("Wait before start $board 6us."); - if(!defined($conf_waitstart_addr)) { - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - # Set time to wait after finished programming before sending MAPS_start - execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00000200", ""); # wait before start (counted with 80 MHz) - - } -} -sub generate_h_waitbeforestart_1ms { - - my($board, $fpga_addr, $conf_waitstart_addr) = @_; - return sub { - init_msg("Wait before start $board 1ms."); - if(!defined($conf_waitstart_addr)) { - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - # Set time to wait after finished programming before sending MAPS_start - execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00013880", ""); # wait before start (counted with 80 MHz) - - } -} - -sub generate_h_waitbeforestart_1s { - - my($board, $fpga_addr, $conf_waitstart_addr) = @_; - return sub { - init_msg("Wait before start $board 1s."); - if(!defined($conf_waitstart_addr)) { - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - # Set time to wait after finished programming before sending MAPS_start - execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x04C4B400", ""); # wait before start (counted with 80 MHz) - - } -} - -sub generate_h_maps_reset { - my ($onoroff, $chain, $chainnr, $fpga_addr, $conf_resets_addr) = @_; - return sub { - init_msg("initseq setting: MAPS reset addr $conf_resets_addr $onoroff " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_resets_addr"); - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $before = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $newval; - if($onoroff == 0) { - #off - $newval = int_to_32bit_hex((~(1<<$chainnr)) & hex($before)); - } - else { - #on - $newval = int_to_32bit_hex(((1<<$chainnr)) | hex($before)); - } - execute_shell_command("trbcmd w $fpga_addr $conf_resets_addr 0x$newval", ""); - } -} - - -sub generate_h_trig { - my ($board, $fpga_addr, $conf_trigger_addr) = @_; - return sub { - init_msg("generate trigger addr $conf_trigger_addr " . $board); - # hack: for runjtag trigger single trigger address is used, otherwise setting LSB would be sufficient - execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0xFFFFFFFF", ""); - } -} -sub generate_h_chain_trig { - my ($chain, $chainnr, $fpga_addr, $conf_trigger_addr) = @_; - return sub { - init_msg("generate trigger addr $conf_trigger_addr chainnr:$chainnr " . $chain); - # set bit in trigger register correspondig to chain-# $chainnr - my $newval; - $newval = int_to_32bit_hex(((1<<$chainnr))); - execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0x$newval", ""); - } -} - - - -sub generate_h_trigger_init_sequence { - my($board, $fpga_addr, $conf_fet_trigger_addr, $conf_period_addr) = @_; - return sub { - init_msg("Send Trigger $board."); - if(!defined($conf_fet_trigger_addr)) { - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - # generate trigger - execute_shell_command("trbcmd w $fpga_addr $conf_fet_trigger_addr 0x00000001", ""); # generate fet_trigger via trbnet - } -} - - -sub generate_h_set_inout { - my($chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg("Set IN/OUT $chain."); - if(!defined($conf_signals_addr)){ - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x000002EAA", "");# outputs/inputs not inverted, but activated, RESET activated and inverted (high) - } -} - -sub generate_h_prog_fpga { - my($board, $trbhostname, $addonortrb, $staplfilename) = @_; - return sub { - init_msg("Prog FPGA $board."); - if(!defined($trbhostname)||!defined($addonortrb)||!defined($staplfilename)){ - report('report_general', "Settings missing. Doing nothing.\n"); - return; - } - execute_shell_command("command_client.pl -e $trbhostname -c \"jam_trbv2_ao --$addonortrb -aRUN_XILINX_PROC /home/hadaq/bneumann/$staplfilename\"", - "------------- Connection accepted ------------- -> return value of command: 0 -> stdout: -Successful File Execution. -------------- END OF OUTPUT ------------ -"); - } -} -sub generate_h_start_trbnetd { - my($board, $trbhostname) = @_; - return sub { - init_msg("Start trbnetd $board."); - if(!defined($trbhostname)){ - report('report_general',"Settings missing. Doing nothing.\n"); - return; - } - execute_shell_command("command_client.pl -e $trbhostname -c \"trbnetd\"","------------- Connection accepted ------------- -> return value of command: 0 -------------- END OF OUTPUT ------------ -"); - } -} - -sub generate_h_set_standard { - my %boards_handlers = %{$_[0]}; - my %chains_handlers = %{$_[1]}; - return sub { - foreach my $board (reverse sort keys %chains_handlers) { - my %chains_handlers2 = %{$chains_handlers{$board}}; - foreach my $chain (reverse sort keys %chains_handlers2) { - my %chain_handlers = %{$chains_handlers2{$chain}}; - foreach my $handler_name (@{$chain_defaults{$board}{$chain}}) { - &{$chain_handlers{$handler_name}}; # run subroutine saved in hash - } - } - } - foreach my $board (reverse sort keys %boards_handlers) { - my %board_handlers = %{$boards_handlers{$board}}; - foreach my $handler_name (@{$board_defaults{$board}}) { - &{$board_handlers{$handler_name}}; # run subroutine saved in hash - } - } - foreach my $board (reverse sort keys %chains_handlers) { - my %chains_handlers2 = %{$chains_handlers{$board}}; - foreach my $chain (reverse sort keys %chains_handlers2) { - my %chain_handlers = %{$chains_handlers2{$chain}}; - foreach my $handler_name (@{$chain_defaults2{$board}{$chain}}) { - &{$chain_handlers{$handler_name}}; # run subroutine saved in hash - } - } - } - } -} - # outputs/inputs not inverted, but activated, RESET deactivated and inverted (high) sub h_reload_boardsini { my ($widget, $data) = @_; @@ -827,7 +478,7 @@ sub reload_chainsini { } } - my $ref_h_prog_ram = generate_h_prog_ram($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, scalar @sensors, \@memfilenames); + my $ref_h_prog_ram = generate_h_prog_ram($chain); my %handlers_hash = ('h_man_maps_reset'=>generate_h_man_maps_reset($chain, $fpga_addr, $conf_signals_addr), #'h_prog_fpga_delay1' => generate_h_prog_fpga($chain, $trbhostname, $addonortrb, $staplfilename_delay1), 'h_delay0' => generate_h_delay ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, 0), diff --git a/soft/toolbox/jtag_atomic/ui.pl b/soft/toolbox/jtag_atomic/ui.pl index e09e959..b692f33 100755 --- a/soft/toolbox/jtag_atomic/ui.pl +++ b/soft/toolbox/jtag_atomic/ui.pl @@ -7,6 +7,8 @@ use POSIX qw(strftime); use FileHandle; use Getopt::Long; use Sys::Syslog; +require "./ui_generators.pl"; + $ENV{DAQOPSERVER}='trb124'; @@ -37,7 +39,7 @@ if($opt_help or not defined $opt_board) { sub help(){ syslog("debug", "showing usage information."); - print "Usage: ui.pl [-c ] [-o ] [-a
] + print "Usage: ui.pl -b [-c ] [-o ] [-a
] required: [-c|--chain ] : Select the JTAG chain (controller) whose RAM should be written. @@ -166,413 +168,6 @@ sub execute_shell_command_return { } -sub generate_h_read_ram1b_word { - my ($chain, $fpga_addr, $debug_ram1baddr, $debug_ram1bdata, $addr) = @_; - return sub { - init_msg( "read ram1b word " . $chain); - execute_shell_command("trbcmd w $fpga_addr $debug_ram1baddr $addr", ""); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1bdata"); - report('report_general', "regval: ". substr($regval, 8, 10). "\n"); - report('data', substr($regval, 8, 10)); - } -} -sub generate_h_read_ram1c_word { - my ($chain, $fpga_addr, $debug_ram1caddr, $debug_ram1cdata, $addr) = @_; - return sub { - init_msg( "read ram1b word " . $chain); - execute_shell_command("trbcmd w $fpga_addr $debug_ram1caddr $addr", ""); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1cdata"); - report('report_general', "regval: ". substr($regval, 8, 10). "\n"); - report('data', substr($regval, 8, 10)); - } -} - - -sub generate_h_copy_ram1b1c { - my ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $addr) = @_; - return sub { - init_msg( "read ram1b word " . $chain); - execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x00000008", ""); # unconditional trigger - execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000064", ""); # M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER - } -} - - -sub generate_h_man_maps_reset { - my ($chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg( "manual reset chain " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $resetnormal = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $resetinv = int_to_32bit_hex((~(1<<10)) & hex($resetnormal)); - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$resetinv 2>&1 && sleep 1 && trbcmd w $fpga_addr $conf_signals_addr $resetnormal 2>&1", ""); - } -} - -sub generate_h_maps_start_signal { - my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg( "generate MAPS start $onoroff " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $before = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $newval; - if($onoroff == 0) { - #off - $newval = int_to_32bit_hex((~(1<<9)) & hex($before)); - } - else { - #on - $newval = int_to_32bit_hex(((1<<9)) | hex($before)); - } - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", ""); - } -} -sub generate_h_maps_reset_signal { - my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg("MAPS reset signal $onoroff " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $before = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $newval; - if($onoroff == 0) { - #off - $newval = int_to_32bit_hex((~(1<<11)) & hex($before)); - } - else { - #on - $newval = int_to_32bit_hex(((1<<11)) | hex($before)); - } - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval", ""); - } -} -sub generate_h_maps_clk_signal { - my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg("generate MAPS clk $onoroff " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); - - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $before = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $newval; - if($onoroff == 0) { - #off - $newval = int_to_32bit_hex((~(1<<13)) & hex($before)); - } - else { - #on - $newval = int_to_32bit_hex(((1<<13)) | hex($before)); - } - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", ""); - } -} -sub generate_h_prog_ram { - my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $ram_base_addr, $ram_addr, $numsensors, $memfilenames_ref) = @_; - my @memfilenames = @{$memfilenames_ref}; - return sub { - init_msg("program RAM $chain."); - my $numchips_hex = int_to_32bit_hex($numsensors); - execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A", ""); # CMD_STOP - execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x$numchips_hex", ""); # ADDR_CONTROL_DATA_REGISTER - execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000033", ""); # COMMAND: M26C_CMD_SET_NUMCHIPS_CONFIGURED - for(my $i=0;$i&1 # ADDR_CONTROL_DATA_REGISTER -trbcmd w $fpga_addr $cmd_reg_addr 0x00000067 2>&1 # COMMAND: M26C_CMD_SET_DELAY_EXPECTED_VALUES"; - execute_shell_command($cmdline, ""); - } -} - -sub generate_h_waitbeforestart_6us { - - my($board, $fpga_addr, $conf_waitstart_addr) = @_; - return sub { - init_msg("Wait before start $board 6us."); - if(!defined($conf_waitstart_addr)) { - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - # Set time to wait after finished programming before sending MAPS_start - execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00000200", ""); # wait before start (counted with 80 MHz) - - } -} -sub generate_h_waitbeforestart_1ms { - - my($board, $fpga_addr, $conf_waitstart_addr) = @_; - return sub { - init_msg("Wait before start $board 1ms."); - if(!defined($conf_waitstart_addr)) { - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - # Set time to wait after finished programming before sending MAPS_start - execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00013880", ""); # wait before start (counted with 80 MHz) - - } -} - -sub generate_h_waitbeforestart_1s { - - my($board, $fpga_addr, $conf_waitstart_addr) = @_; - return sub { - init_msg("Wait before start $board 1s."); - if(!defined($conf_waitstart_addr)) { - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - # Set time to wait after finished programming before sending MAPS_start - execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x04C4B400", ""); # wait before start (counted with 80 MHz) - - } -} - -sub generate_h_maps_reset { - my ($onoroff, $chain, $chainnr, $fpga_addr, $conf_resets_addr) = @_; - return sub { - init_msg("initseq setting: MAPS reset addr $conf_resets_addr $onoroff " . $chain); - # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset - my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_resets_addr"); - reportd "regval: ". substr($regval, 8, 10). "\n"; - my $before = substr($regval, 8, 10); -# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); - my $newval; - if($onoroff == 0) { - #off - $newval = int_to_32bit_hex((~(1<<$chainnr)) & hex($before)); - } - else { - #on - $newval = int_to_32bit_hex(((1<<$chainnr)) | hex($before)); - } - execute_shell_command("trbcmd w $fpga_addr $conf_resets_addr 0x$newval", ""); - } -} - - -sub generate_h_trig { - my ($board, $fpga_addr, $conf_trigger_addr) = @_; - return sub { - init_msg("generate trigger addr $conf_trigger_addr " . $board); - # hack: for runjtag trigger single trigger address is used, otherwise setting LSB would be sufficient - execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0xFFFFFFFF", ""); - } -} -sub generate_h_chain_trig { - my ($chain, $chainnr, $fpga_addr, $conf_trigger_addr) = @_; - return sub { - init_msg("generate trigger addr $conf_trigger_addr chainnr:$chainnr " . $chain); - # set bit in trigger register correspondig to chain-# $chainnr - my $newval; - $newval = int_to_32bit_hex(((1<<$chainnr))); - execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0x$newval", ""); - } -} - - - -sub generate_h_trigger_init_sequence { - my($board, $fpga_addr, $conf_fet_trigger_addr, $conf_period_addr) = @_; - return sub { - init_msg("Send Trigger $board."); - if(!defined($conf_fet_trigger_addr)) { - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - # generate trigger - execute_shell_command("trbcmd w $fpga_addr $conf_fet_trigger_addr 0x00000001", ""); # generate fet_trigger via trbnet - } -} - - -sub generate_h_set_inout { - my($chain, $fpga_addr, $conf_signals_addr) = @_; - return sub { - init_msg("Set IN/OUT $chain."); - if(!defined($conf_signals_addr)){ - report('report_general', "TrbNet address missing. Doing nothing.\n"); - return; - } - execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x000002EAA", "");# outputs/inputs not inverted, but activated, RESET activated and inverted (high) - } -} - -sub generate_h_prog_fpga { - my($board, $trbhostname, $addonortrb, $staplfilename) = @_; - return sub { - init_msg("Prog FPGA $board."); - if(!defined($trbhostname)||!defined($addonortrb)||!defined($staplfilename)){ - report('report_general', "Settings missing. Doing nothing.\n"); - return; - } - execute_shell_command("command_client.pl -e $trbhostname -c \"jam_trbv2_ao --$addonortrb -aRUN_XILINX_PROC /home/hadaq/bneumann/$staplfilename\"", - "------------- Connection accepted ------------- -> return value of command: 0 -> stdout: -Successful File Execution. -------------- END OF OUTPUT ------------ -"); - } -} -sub generate_h_prog_ram_external { - my ($chain) = @_; - return sub { - my $output = execute_shell_command_return("./ui_writeram.pl -c $chain"); - #reportd $output; - } -} - - -sub generate_h_start_trbnetd { - my($board, $trbhostname) = @_; - return sub { - init_msg("Start trbnetd $board."); - if(!defined($trbhostname)){ - report('report_general',"Settings missing. Doing nothing.\n"); - return; - } - execute_shell_command("command_client.pl -e $trbhostname -c \"trbnetd\"","------------- Connection accepted ------------- -> return value of command: 0 -------------- END OF OUTPUT ------------ -"); - } -} - -# sub generate_h_set_standard { -# my %boards_handlers = %{$_[0]}; -# my %chains_handlers = %{$_[1]}; -# return sub { -# foreach my $board (reverse sort keys %chains_handlers) { -# my %chains_handlers2 = %{$chains_handlers{$board}}; -# foreach my $chain (reverse sort keys %chains_handlers2) { -# my %chain_handlers = %{$chains_handlers2{$chain}}; -# foreach my $handler_name (@{$chain_defaults{$board}{$chain}}) { -# &{$chain_handlers{$handler_name}}; # run subroutine saved in hash -# } -# } -# } -# foreach my $board (reverse sort keys %boards_handlers) { -# my %board_handlers = %{$boards_handlers{$board}}; -# foreach my $handler_name (@{$board_defaults{$board}}) { -# &{$board_handlers{$handler_name}}; # run subroutine saved in hash -# } -# } -# foreach my $board (reverse sort keys %chains_handlers) { -# my %chains_handlers2 = %{$chains_handlers{$board}}; -# foreach my $chain (reverse sort keys %chains_handlers2) { -# my %chain_handlers = %{$chains_handlers2{$chain}}; -# foreach my $handler_name (@{$chain_defaults2{$board}{$chain}}) { -# &{$chain_handlers{$handler_name}}; # run subroutine saved in hash -# } -# } -# } -# } -# } - my $boardsfile= 'boards.ini'; my $boardsSettings = new Config::Abstract::Ini($boardsfile); my %allboards = $boardsSettings->get_all_settings; @@ -673,7 +268,7 @@ foreach my $board (keys %allboards) { $subr = generate_h_delay ($chain, $chain_fpga_addr, $cmd_reg_addr, $data_reg_addr, 3); } elsif(("h_".$opt_operation) eq 'h_prog_ram' ) { - $subr = generate_h_prog_ram_external($chain); + $subr = generate_h_prog_ram($chain); } elsif(("h_".$opt_operation) eq 'h_set_timing_10mhz' ) { $subr = generate_h_set_timing_10mhz($chain, $chain_fpga_addr,$cmd_reg_addr, $data_reg_addr); diff --git a/soft/toolbox/jtag_atomic/ui_generators.pl b/soft/toolbox/jtag_atomic/ui_generators.pl new file mode 100644 index 0000000..026e7c1 --- /dev/null +++ b/soft/toolbox/jtag_atomic/ui_generators.pl @@ -0,0 +1,375 @@ + +sub generate_h_read_ram1b_word { + my ($chain, $fpga_addr, $debug_ram1baddr, $debug_ram1bdata, $addr) = @_; + return sub { + init_msg( "read ram1b word " . $chain); + execute_shell_command("trbcmd w $fpga_addr $debug_ram1baddr $addr", ""); + # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset + my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1bdata"); + report('report_general', "regval: ". substr($regval, 8, 10). "\n"); + report('data', substr($regval, 8, 10)); + } +} +sub generate_h_read_ram1c_word { + my ($chain, $fpga_addr, $debug_ram1caddr, $debug_ram1cdata, $addr) = @_; + return sub { + init_msg( "read ram1b word " . $chain); + execute_shell_command("trbcmd w $fpga_addr $debug_ram1caddr $addr", ""); + # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset + my $regval = execute_shell_command_return("trbcmd r $fpga_addr $debug_ram1cdata"); + report('report_general', "regval: ". substr($regval, 8, 10). "\n"); + report('data', substr($regval, 8, 10)); + } +} + + +sub generate_h_copy_ram1b1c { + my ($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $addr) = @_; + return sub { + init_msg( "read ram1b word " . $chain); + execute_shell_command("trbcmd w $fpga_addr $data_reg_addr 0x00000008", ""); # unconditional trigger + execute_shell_command("trbcmd w $fpga_addr $cmd_reg_addr 0x00000064", ""); # M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER + } +} + + +sub generate_h_man_maps_reset { + my ($chain, $fpga_addr, $conf_signals_addr) = @_; + return sub { + init_msg( "manual reset chain " . $chain); + # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset + my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); + reportd "regval: ". substr($regval, 8, 10). "\n"; + my $resetnormal = substr($regval, 8, 10); +# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); + my $resetinv = int_to_32bit_hex((~(1<< 10)) & hex($resetnormal)); + execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$resetinv 2>&1 && sleep 1 && trbcmd w $fpga_addr $conf_signals_addr $resetnormal 2>&1", ""); + } +} + +sub generate_h_maps_start_signal { + my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_; + return sub { + init_msg( "generate MAPS start $onoroff " . $chain); + # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset + my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); + reportd "regval: ". substr($regval, 8, 10). "\n"; + my $before = substr($regval, 8, 10); +# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); + my $newval; + if($onoroff == 0) { + #off + $newval = int_to_32bit_hex((~(1<< 9)) & hex($before)); + } + else { + #on + $newval = int_to_32bit_hex(((1<< 9)) | hex($before)); + } + execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", ""); + } +} +sub generate_h_maps_reset_signal { + my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_; + return sub { + init_msg("MAPS reset signal $onoroff " . $chain); + # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset + my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); + reportd "regval: ". substr($regval, 8, 10). "\n"; + my $before = substr($regval, 8, 10); +# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); + my $newval; + if($onoroff == 0) { + #off + $newval = int_to_32bit_hex((~(1<< 11)) & hex($before)); + } + else { + #on + $newval = int_to_32bit_hex(((1<< 11)) | hex($before)); + } + execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval", ""); + } +} +sub generate_h_maps_clk_signal { + my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_; + return sub { + init_msg("generate MAPS clk $onoroff " . $chain); + # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset + my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr"); + + reportd "regval: ". substr($regval, 8, 10). "\n"; + my $before = substr($regval, 8, 10); +# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); + my $newval; + if($onoroff == 0) { + #off + $newval = int_to_32bit_hex((~(1<< 13)) & hex($before)); + } + else { + #on + $newval = int_to_32bit_hex(((1<< 13)) | hex($before)); + } + execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", ""); + } +} + +sub generate_h_prog_ram { + my($chain) = @_; + return sub { + init_msg("program RAM $chain."); + execute_shell_command("./ui_writeram.pl -c $chain -q", "$chain: done.\n"); # load sensor*.ini + } +} + +sub generate_h_set_timing_10mhz { + my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_; + return sub { + init_msg("timing 10 MHz $chain."); + my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP +trbcmd w $fpga_addr $data_reg_addr 0x0000000A 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH +trbcmd w $fpga_addr $data_reg_addr 0x00000003 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1 +trbcmd w $fpga_addr $data_reg_addr 0x00000008 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2 +trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1 +trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2 +trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3 +trbcmd w $fpga_addr $data_reg_addr 0x00000009 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME +trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START"; + #reportd $cmdline; + #system($cmdline); + execute_shell_command($cmdline, ""); + } +} + +sub generate_h_set_timing_1mhz { + my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_; + return sub { + init_msg("timing 1 MHz $chain."); + my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP +trbcmd w $fpga_addr $data_reg_addr 0x00000064 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH +trbcmd w $fpga_addr $data_reg_addr 0x00000031 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1 +trbcmd w $fpga_addr $data_reg_addr 0x00000062 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2 +trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1 +trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2 +trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3 +trbcmd w $fpga_addr $data_reg_addr 0x00000063 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME +trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START"; + execute_shell_command($cmdline, ""); + } +} + +sub generate_h_set_timing_100khz { + my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_; + return sub { + init_msg("timing 100 kHz $chain."); + my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP +trbcmd w $fpga_addr $data_reg_addr 0x000003E8 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH +trbcmd w $fpga_addr $data_reg_addr 0x000001CC 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1 +trbcmd w $fpga_addr $data_reg_addr 0x000003C0 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2 +trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1 +trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2 +trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3 +trbcmd w $fpga_addr $data_reg_addr 0x000003E7 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME +trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START"; + execute_shell_command($cmdline, ""); + } +} + + + +sub generate_h_delay { + my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $delay) = @_; + return sub { + init_msg("Delay $delay $chain."); + my $cmdline = "trbcmd w $fpga_addr $data_reg_addr 0x".int_to_32bit_hex($delay)." 2>&1 # ADDR_CONTROL_DATA_REGISTER +trbcmd w $fpga_addr $cmd_reg_addr 0x00000067 2>&1 # COMMAND: M26C_CMD_SET_DELAY_EXPECTED_VALUES"; + execute_shell_command($cmdline, ""); + } +} + +sub generate_h_waitbeforestart_6us { + + my($board, $fpga_addr, $conf_waitstart_addr) = @_; + return sub { + init_msg("Wait before start $board 6us."); + if(!defined($conf_waitstart_addr)) { + report('report_general', "TrbNet address missing. Doing nothing.\n"); + return; + } + # Set time to wait after finished programming before sending MAPS_start + execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00000200", ""); # wait before start (counted with 80 MHz) + + } +} + +sub generate_h_waitbeforestart_1ms { + + my($board, $fpga_addr, $conf_waitstart_addr) = @_; + return sub { + init_msg("Wait before start $board 1ms."); + if(!defined($conf_waitstart_addr)) { + report('report_general', "TrbNet address missing. Doing nothing.\n"); + return; + } + # Set time to wait after finished programming before sending MAPS_start + execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00013880", ""); # wait before start (counted with 80 MHz) + + } +} + +sub generate_h_waitbeforestart_1s { + + my($board, $fpga_addr, $conf_waitstart_addr) = @_; + return sub { + init_msg("Wait before start $board 1s."); + if(!defined($conf_waitstart_addr)) { + report('report_general', "TrbNet address missing. Doing nothing.\n"); + return; + } + # Set time to wait after finished programming before sending MAPS_start + execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x04C4B400", ""); # wait before start (counted with 80 MHz) + + } +} + +sub generate_h_maps_reset { + my ($onoroff, $chain, $chainnr, $fpga_addr, $conf_resets_addr) = @_; + return sub { + init_msg("initseq setting: MAPS reset addr $conf_resets_addr $onoroff " . $chain); + # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset + my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_resets_addr"); + reportd "regval: ". substr($regval, 8, 10). "\n"; + my $before = substr($regval, 8, 10); +# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal)); + my $newval; + if($onoroff == 0) { + #off + $newval = int_to_32bit_hex((~(1<<$chainnr)) & hex($before)); + } + else { + #on + $newval = int_to_32bit_hex(((1<<$chainnr)) | hex($before)); + } + execute_shell_command("trbcmd w $fpga_addr $conf_resets_addr 0x$newval", ""); + } +} + + +sub generate_h_trig { + my ($board, $fpga_addr, $conf_trigger_addr) = @_; + return sub { + init_msg("generate trigger addr $conf_trigger_addr " . $board); + # hack: for runjtag trigger single trigger address is used, otherwise setting LSB would be sufficient + execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0xFFFFFFFF", ""); + } +} +sub generate_h_chain_trig { + my ($chain, $chainnr, $fpga_addr, $conf_trigger_addr) = @_; + return sub { + init_msg("generate trigger addr $conf_trigger_addr chainnr:$chainnr " . $chain); + # set bit in trigger register correspondig to chain-# $chainnr + my $newval; + $newval = int_to_32bit_hex(((1<<$chainnr))); + execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0x$newval", ""); + } +} + + + + +sub generate_h_set_inout { + my($chain, $fpga_addr, $conf_signals_addr) = @_; + return sub { + init_msg("Set IN/OUT $chain."); + if(!defined($conf_signals_addr)){ + report('report_general', "TrbNet address missing. Doing nothing.\n"); + return; + } + execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x000002EAA", "");# outputs/inputs not inverted, but activated, RESET activated and inverted (high) + } +} + +sub generate_h_prog_fpga { + my($board, $trbhostname, $addonortrb, $staplfilename) = @_; + return sub { + init_msg("Prog FPGA $board."); + if(!defined($trbhostname)||!defined($addonortrb)||!defined($staplfilename)){ + report('report_general', "Settings missing. Doing nothing.\n"); + return; + } + execute_shell_command("command_client.pl -e $trbhostname -c \"jam_trbv2_ao --$addonortrb -aRUN_XILINX_PROC /home/hadaq/bneumann/$staplfilename\"", + "------------- Connection accepted ------------- +> return value of command: 0 +> stdout: +Successful File Execution. +------------- END OF OUTPUT ------------ +"); + } +} + +sub generate_h_start_trbnetd { + my($board, $trbhostname) = @_; + return sub { + init_msg("Start trbnetd $board."); + if(!defined($trbhostname)){ + report('report_general',"Settings missing. Doing nothing.\n"); + return; + } + execute_shell_command("command_client.pl -e $trbhostname -c \"trbnetd\"","------------- Connection accepted ------------- +> return value of command: 0 +------------- END OF OUTPUT ------------ +"); + } +} + +sub generate_h_set_standard { + my %boards_handlers = %{$_[0]}; + my %chains_handlers = %{$_[1]}; + return sub { + foreach my $board (reverse sort keys %chains_handlers) { + my %chains_handlers2 = %{$chains_handlers{$board}}; + foreach my $chain (reverse sort keys %chains_handlers2) { + my %chain_handlers = %{$chains_handlers2{$chain}}; + foreach my $handler_name (@{$chain_defaults{$board}{$chain}}) { + &{$chain_handlers{$handler_name}}; # run subroutine saved in hash + } + } + } + foreach my $board (reverse sort keys %boards_handlers) { + my %board_handlers = %{$boards_handlers{$board}}; + foreach my $handler_name (@{$board_defaults{$board}}) { + &{$board_handlers{$handler_name}}; # run subroutine saved in hash + } + } + foreach my $board (reverse sort keys %chains_handlers) { + my %chains_handlers2 = %{$chains_handlers{$board}}; + foreach my $chain (reverse sort keys %chains_handlers2) { + my %chain_handlers = %{$chains_handlers2{$chain}}; + foreach my $handler_name (@{$chain_defaults2{$board}{$chain}}) { + &{$chain_handlers{$handler_name}}; # run subroutine saved in hash + } + } + } + } +} + +1; # need to end with a true value diff --git a/soft/toolbox/jtag_atomic/ui_writeram.pl b/soft/toolbox/jtag_atomic/ui_writeram.pl index f240012..a71c7e1 100755 --- a/soft/toolbox/jtag_atomic/ui_writeram.pl +++ b/soft/toolbox/jtag_atomic/ui_writeram.pl @@ -41,7 +41,7 @@ required: #use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/"; #use lib "/d/sugar/bneumann/vhdl/jtag_proj/trb_maps_jtag2/ui/BN/blib/arch"; -use lib "BN/blib/arch"; +use lib "libs/BN/blib/arch"; use BN::CRC32; #use String::CRC32; -- 2.43.0