From 015aebcc3d16f902bbf3e549d3474548424075f2 Mon Sep 17 00:00:00 2001 From: Cahit Date: Mon, 24 Feb 2014 14:56:30 +0100 Subject: [PATCH] Information for calibration hit divider is included. --- trb3/TdcSlowControl.tex | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex index 6b1d94f..5fe68a3 100644 --- a/trb3/TdcSlowControl.tex +++ b/trb3/TdcSlowControl.tex @@ -8,13 +8,19 @@ the control registers are given in Table \ref{tab:tdcControlReg}. \hline Address & \multicolumn{1}{c|}{Name} & Bits & \multicolumn{1}{c|}{Explanation}\\ \hline \hline - \multirow{13}{*}{0xc800} & \multirow{13}{*}{Basic controls} & 3-0 & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\ + \multirow{14}{*}{0xc800} & \multirow{14}{*}{Basic controls} & 3-0 +& Enables different signals to the HPLA* output for debugging with logic +analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\ & & 4 & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\ & & 7-5 & reserved.\\ & & 8 & Resets the internal counters (active high).\\ & & 11-9 & reserved.\\ & & 12 & Used to select the trigger mode. 0 - with trigger mode; 1 - trigger-less mode (For more details see \ref{sec:tdcTrigWin}).\\ - & & 31-13 & reserved.\\ + & & 27-13 & reserved.\\ + & & 31-28 +& Used to divide the calibration hit frequency.\\&&& $Freq_{hit}=1.6~MHz/2^n$\\ + + \hline \multirow{10}{*}{0xc801} & \multirow{10}{*}{Trigger window} & 10-0 & Defines the trigger window width before the trigger with granularity of 5~ns. Minimum value is x"000".\\ & & 15-11 & reserved.\\ -- 2.43.0