From 02a4c65c43f7aa783622039657cbcb130e603ae5 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 25 Mar 2022 17:38:52 +0100 Subject: [PATCH] recompilation works --- backplanemaster/config.vhd | 3 ++ backplanemaster/trb3sc_master.lpf | 12 +++---- backplanemaster/trb3sc_master.prj | 6 ++-- backplanemaster/trb3sc_master.vhd | 24 ++++++++------ code/clock_reset_handler.vhd | 35 +++----------------- cts/config_simple.vhd | 13 +++++--- cts/trb3sc_cts.lpf | 6 ++-- cts/trb3sc_cts.prj | 6 ++-- cts/trb3sc_cts.vhd | 29 +++++++++------- hub/config.vhd | 7 ++-- hub/trb3sc_hub.lpf | 35 +++++++++----------- hub/trb3sc_hub.prj | 6 ++-- hub/trb3sc_hub.vhd | 35 ++++++++++---------- tdctemplate/config_16_sfp_kel.vhd | 6 ++-- tdctemplate/trb3sc_tdctemplate.lpf | 6 ++-- tdctemplate/trb3sc_tdctemplate.prj | 6 ++-- tdctemplate/trb3sc_tdctemplate.vhd | 53 ++++++++++++++++-------------- 17 files changed, 137 insertions(+), 151 deletions(-) diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd index 2b3c20e..84f1eac 100644 --- a/backplanemaster/config.vhd +++ b/backplanemaster/config.vhd @@ -13,6 +13,9 @@ package config is --We use an ECP3 constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 +-- Link speed + constant LINK_SPEED : integer := 200; -- 125: 1.25Gbps, 200: 2.00Gbps + --Gbe included? constant INCLUDE_GBE : integer := c_NO; diff --git a/backplanemaster/trb3sc_master.lpf b/backplanemaster/trb3sc_master.lpf index 74b13d7..f5bef81 100644 --- a/backplanemaster/trb3sc_master.lpf +++ b/backplanemaster/trb3sc_master.lpf @@ -1,6 +1,6 @@ # locate the PCS blocks -LOCATE COMP "THE_MEDIA_INT_MIXED/THE_SERDES/PCSD_INST" SITE "PCSB" ; -LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_MEDIA_INT_MIXED/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "THE_MEDIA_4_DOWN/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; # locate the media interfaces inside fabric @@ -10,12 +10,12 @@ LOCATE UGROUP "THE_MEDIA_INT_MIXED/media_interface_group" REGION "MEDIA_LEFT" ; LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_RIGHT" ; # read from SCI can be delayed due to long read strobe -MULTICYCLE FROM ASIC THE_MEDIA_INT_MIXED/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE FROM ASIC THE_MEDIA_INT_MIXED/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; # write strobe can be delayed due to A/D being stable after access -MULTICYCLE TO ASIC THE_MEDIA_INT_MIXED/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE TO ASIC THE_MEDIA_INT_MIXED/gen.SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; # read from SCI can be delayed due to long read strobe -MULTICYCLE FROM ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE FROM ASIC THE_MEDIA_4_DOWN/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; # write strobe can be delayed due to A/D being stable after access -MULTICYCLE TO ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE TO ASIC THE_MEDIA_4_DOWN/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj index f10f3cb..1437831 100644 --- a/backplanemaster/trb3sc_master.prj +++ b/backplanemaster/trb3sc_master.prj @@ -133,11 +133,9 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vh add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" - +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd index 9213c98..d8c8b1d 100644 --- a/backplanemaster/trb3sc_master.vhd +++ b/backplanemaster/trb3sc_master.vhd @@ -198,7 +198,8 @@ architecture trb3sc_arch of trb3sc_master is signal send_rst_word_i : std_logic_vector(7 downto 0); signal send_dlm_word_i : std_logic_vector(7 downto 0); - signal init_quad : std_logic; + signal init_quad : std_logic; + signal link_clock : std_logic; begin @@ -206,7 +207,7 @@ begin -- Clock & Reset Handling --------------------------------------------------------------------------- THE_CLOCK_RESET : entity work.clock_reset_handler - port map( + port map(-- Link speed INT_CLK_IN => CLK_CORE_PCLK, EXT_CLK_IN => CLK_EXT_PLL_LEFT, NET_CLK_FULL_IN => med2int(4).clk_full, @@ -228,17 +229,22 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ); init_quad <= not GSR_N; - + + -- select link speed, wrong values are catched in media interface + link_clock <= CLK_SUPPL_PCLK when (LINK_SPEED = 125) else + clk_full_osc when (LINK_SPEED = 200) else + '0'; + --------------------------------------------------------------------------- -- PCBSB: TrbNet Uplink --------------------------------------------------------------------------- -THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_125M_RS +THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE) ) port map( -- Clocks and reset - CLK_REF_FULL => CLK_SUPPL_PCLK, + CLK_REF_FULL => link_clock, SYSCLK => clk_sys, RESET => reset_i, CLEAR => init_quad, @@ -263,7 +269,6 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_125M_RS WORD_SYNC_OUT => word_sync_i, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => master_clk_i, - QUAD_RST_IN => '0', LINK_TX_NULL_IN => global_reset_i, LINK_RX_NULL_OUT => global_reset_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, @@ -311,7 +316,7 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_125M_RS THE_MAIN_TX_RST: main_tx_reset_RS port map ( CLEAR => init_quad, - CLK_REF => CLK_SUPPL_PCLK, + CLK_REF => link_clock, TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i, TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, TX_PLL_LOL_QD_C_IN => '0', @@ -326,13 +331,13 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_125M_RS --------------------------------------------------------------------------- -- PCSA: TrbNet Downlink --------------------------------------------------------------------------- -THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_125M_RS +THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER) ) port map( -- Clocks and reset - CLK_REF_FULL => CLK_SUPPL_PCLK, + CLK_REF_FULL => link_clock, SYSCLK => clk_sys, RESET => reset_i, CLEAR => init_quad, @@ -359,7 +364,6 @@ THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_125M_RS WORD_SYNC_OUT => open, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => open, - QUAD_RST_IN => '0', LINK_TX_NULL_IN => global_reset_i, LINK_RX_NULL_OUT => open, TX_PLL_LOL_OUT => tx_pll_lol_qd_a_i, diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index dc98b35..9f8b39d 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -8,7 +8,6 @@ library work; use work.trb3_components.all; use work.config.all; --- REMARK: USE_RXCLOCK doesnt't make sense here, can be removed -- REMARK: USE_EXTERNAL_CLOCK seems to be mandatory, can be simplified entity clock_reset_handler is @@ -23,9 +22,9 @@ entity clock_reset_handler is BUS_RX : in CTRLBUS_RX; -- NOT USED BUS_TX : out CTRLBUS_TX; -- NOT USED - RESET_OUT : out std_logic; - CLEAR_OUT : out std_logic; - GSR_OUT : out std_logic; + RESET_OUT : out std_logic; -- active high + CLEAR_OUT : out std_logic; -- active high + GSR_OUT : out std_logic; -- active low FULL_CLK_OUT : out std_logic; -- 200/240 MHz for FPGA fabric SYS_CLK_OUT : out std_logic; -- 100/120 MHz for FPGA fabric @@ -76,33 +75,7 @@ LED_GREEN_OUT(0) <= '0' when USE_RXCLOCK = c_NO else '1'; LED_RED_OUT(1) <= clock_select; LED_GREEN_OUT(1) <= '0'; -GSR_OUT <= not pll_int_lock or clear_n_i; -- keeps everything in reset until a valid FPGA fabric clock is available - ---------------------------------------------------------------------------- --- if RX clock is used, just forward what is provided, adjust internal as reference ---------------------------------------------------------------------------- -gen_recov_clock : if USE_RXCLOCK = c_YES generate --- clk_selected_full <= NET_CLK_FULL_IN; --- clk_selected_half <= NET_CLK_HALF_IN; --- --- timer <= (others => '1'); --- --- gen_200rec : if USE_120_MHZ = c_NO generate --- THE_INT_PLL : entity work.pll_in240_out200 --- port map( --- CLK => INT_CLK_IN, --- CLKOP => clk_int_full, --- CLKOK => clk_int_half, --- LOCK => pll_int_lock --- ); --- clk_selected_ref <= clk_int_full; --- end generate; --- --- gen_240rec : if USE_120_MHZ = c_YES generate --- clk_selected_ref <= INT_CLK_IN; --- pll_int_lock <= '1'; --- end generate; -end generate; +GSR_OUT <= pll_int_lock and clear_n_i; -- keeps everything in reset until a valid FPGA fabric clock is available --------------------------------------------------------------------------- -- No recovered clock diff --git a/cts/config_simple.vhd b/cts/config_simple.vhd index 27ea225..b00a260 100644 --- a/cts/config_simple.vhd +++ b/cts/config_simple.vhd @@ -13,11 +13,14 @@ package config is -- FPGA type constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 +-- Link speed + constant LINK_SPEED : integer := 200; -- 125: 1.25Gbps, 200: 2.00Gbps + --design options: backplane or front SFP, with or without GBE - constant USE_BACKPLANE : integer := c_NO; --c_YES doesn't work - constant USE_ADDON : integer := c_NO; - constant USE_RJADAPT : integer := c_NO; --!!! Change pin-out file! - constant INCLUDE_GBE : integer := c_YES; --c_NO doesn't work + constant USE_BACKPLANE : integer := c_NO; --c_YES doesn't work + constant USE_ADDON : integer := c_NO; + constant USE_RJADAPT : integer := c_NO; --!!! Change pin-out file! + constant INCLUDE_GBE : integer := c_YES; --c_NO doesn't work --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; @@ -26,7 +29,7 @@ package config is constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA - constant USE_RXCLOCK : integer := c_NO; + constant USE_RXCLOCK : integer := c_NO; -- DEPRECIATED --Address settings constant INIT_ADDRESS : std_logic_vector := x"F3C0"; diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf index 5deaf52..cf7a95e 100644 --- a/cts/trb3sc_cts.lpf +++ b/cts/trb3sc_cts.lpf @@ -1,5 +1,5 @@ # locate the PCS blocks -LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB"; +LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSB"; LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; # locate the media interfaces inside fabric @@ -8,9 +8,9 @@ REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_LEFT"; # read from SCI can be delayed due to long read strobe -MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; # write strobe can be delayed due to A/D being stable after access -MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; ################################################################################################################### ################################################################################################################### diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index a7a805f..ef6c9ad 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -136,11 +136,9 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vh add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" - +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index eebd87c..52750ce 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -258,8 +258,9 @@ architecture trb3sc_arch of trb3sc_cts is signal slave_active_fake : std_logic; signal send_reset_i : std_logic; - signal init_quad : std_logic; - + signal init_quad : std_logic; + signal link_clock : std_logic; + begin THE_TIME_COUNTER_PROC: process( clk_full_osc ) @@ -296,6 +297,11 @@ begin init_quad <= not GSR_N; + -- select link speed, wrong values are catched in media interface + link_clock <= CLK_SUPPL_PCLK when (LINK_SPEED = 125) else + clk_full_osc when (LINK_SPEED = 200) else + '0'; + -- Reset by GbE: a minimum delay of 1us is kept before the reset -- pulse is injected into the reset handler. PROC_MAKE_RESET : process @@ -352,13 +358,13 @@ begin -- PCSB: Downlink without backplane is SFP --------------------------------------------------------------------------- gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate - THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_125M_RS + THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER) ) port map( -- Clocks and reset - CLK_REF_FULL => CLK_SUPPL_PCLK, + CLK_REF_FULL => link_clock, SYSCLK => clk_sys, CLEAR => init_quad, RESET => reset_i, @@ -382,7 +388,6 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate WORD_SYNC_OUT => word_sync_i, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => open, - QUAD_RST_IN => '0', LINK_TX_NULL_IN => send_reset_i, LINK_RX_NULL_OUT => open, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, @@ -409,12 +414,12 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate DEBUG_OUT => debug_i ); - master_clk_i <= CLK_SUPPL_PCLK; + master_clk_i <= link_clock; THE_MAIN_TX_RST: main_tx_reset_RS port map ( CLEAR => init_quad, - CLK_REF => CLK_SUPPL_PCLK, + CLK_REF => link_clock, TX_PLL_LOL_QD_A_IN => '0', TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, TX_PLL_LOL_QD_C_IN => '0', @@ -430,18 +435,18 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate -- just for testing enable_dlm_i <= test_reg(31); + tx_dlm_i <= dlm_send_qq; + send_dlm_word_i <= std_logic_vector(dlm_tag_ctr); send_rst_i <= test_reg(30); - destroy_link_i <= test_reg(24); - send_dlm_word_i <= std_logic_vector(dlm_tag_ctr); --test_reg(15 downto 8); send_rst_word_i <= test_reg(15 downto 8); - wap_requested_i <= test_reg(3 downto 0); + destroy_link_i <= test_reg(24); -- ONLY FOR TESTING + wap_requested_i <= test_reg(3 downto 0); -- ONLY FOR TESTING - tx_dlm_i <= dlm_send_qq; - -- LED feedback LED_WHITE(1) <= not std_logic(dlm_tag_ctr(7)); LED_WHITE(0) <= not send_rst_word_i(0); + -- DO NOT MESS WITH TIMING HERE! -- DLM timing generator THE_DLM_SEND_PROC: process( master_clk_i ) begin diff --git a/hub/config.vhd b/hub/config.vhd index 7220cbc..07d3d01 100644 --- a/hub/config.vhd +++ b/hub/config.vhd @@ -16,7 +16,10 @@ package config is constant INCLUDE_GBE : integer := c_NO; --We want an ECP3 - constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 + constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 + +-- Link speed + constant LINK_SPEED : integer := 125; -- 125: 1.25Gbps, 200: 2.00Gbps --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; @@ -25,7 +28,7 @@ package config is constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA - constant USE_RXCLOCK : integer := c_NO; + constant USE_RXCLOCK : integer := c_NO; -- DEPRECIATED --Address settings constant INIT_ADDRESS : std_logic_vector := x"F3CD"; diff --git a/hub/trb3sc_hub.lpf b/hub/trb3sc_hub.lpf index fc82013..c08b9c4 100644 --- a/hub/trb3sc_hub.lpf +++ b/hub/trb3sc_hub.lpf @@ -1,9 +1,9 @@ # locate the PCS blocks -LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST" SITE "PCSA"; -LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB"; -LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB"; -LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC"; -LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD"; +LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSA"; +LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSB"; +LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSB"; +LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/gen_SERDES.PCSD_INST" SITE "PCSC"; +LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSD"; LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; # locate the media interfaces inside fabric @@ -31,21 +31,16 @@ USE SECONDARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[1]"; # read from SCI can be delayed due to long read strobe # write strobe can be delayed due to A/D being stable after access -MULTICYCLE FROM ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; -MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; -MULTICYCLE FROM ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; -MULTICYCLE TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; -MULTICYCLE FROM ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; -MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; -MULTICYCLE FROM ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; -MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; -MULTICYCLE FROM ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; -MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; - - -# SCI write signal problem... -#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i; -#BLOCK INTERCLOCKDOMAIN PATHS; +MULTICYCLE FROM ASIC gen_PCSA.THE_MEDIA_PCSA/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE FROM ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE FROM ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE FROM ASIC THE_MEDIA_4_PCSC/THE_SERDES/gen_SERDES.PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/gen_SERDES.PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE FROM ASIC gen_PCSD.THE_MEDIA_4_PCSD/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; ################################ diff --git a/hub/trb3sc_hub.prj b/hub/trb3sc_hub.prj index df39ee8..21a2538 100644 --- a/hub/trb3sc_hub.prj +++ b/hub/trb3sc_hub.prj @@ -137,11 +137,9 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vh add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" - +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd index d2189a8..dc7b3b7 100644 --- a/hub/trb3sc_hub.vhd +++ b/hub/trb3sc_hub.vhd @@ -181,7 +181,8 @@ architecture trb3sc_arch of trb3sc_hub is signal send_rst_word_i : std_logic_vector(7 downto 0); signal send_dlm_word_i : std_logic_vector(7 downto 0); - signal init_quad : std_logic; + signal init_quad : std_logic; + signal link_clock : std_logic; begin --------------------------------------------------------------------------- @@ -210,12 +211,17 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ); init_quad <= not GSR_N; - + + -- select link speed, wrong values are catched in media interface + link_clock <= CLK_SUPPL_PCLK when (LINK_SPEED = 125) else + clk_full_osc when (LINK_SPEED = 200) else + '0'; + --------------------------------------------------------------------------- -- PCSA: Uplink when backplane is used --------------------------------------------------------------------------- gen_PCSA : if USE_BACKPLANE = c_YES generate - THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync_all_125M_RS + THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_SLAVE, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED) ) @@ -246,7 +252,6 @@ gen_PCSA : if USE_BACKPLANE = c_YES generate WORD_SYNC_OUT => word_sync_i, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => master_clk_i, - QUAD_RST_IN => '0', LINK_TX_NULL_IN => global_reset_i, LINK_RX_NULL_OUT => global_reset_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_a_i, @@ -277,13 +282,13 @@ end generate; -- PCSB: TrbNet downlinks (backplane) --------------------------------------------------------------------------- gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate - THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_125M_RS + THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER) ) port map( -- Clocks and reset - CLK_REF_FULL => CLK_SUPPL_PCLK, + CLK_REF_FULL => link_clock, SYSCLK => clk_sys, RESET => reset_i, CLEAR => init_quad, @@ -313,7 +318,6 @@ gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate WORD_SYNC_OUT => open, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => open, - QUAD_RST_IN => '0', LINK_TX_NULL_IN => global_reset_i, LINK_RX_NULL_OUT => open, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, @@ -350,13 +354,13 @@ end generate; -- PCSB: TrbNet one uplink and three downlinks (no backplane) --------------------------------------------------------------------------- gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate - THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_125M_RS + THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_SLAVE) ) port map( -- Clocks and reset - CLK_REF_FULL => CLK_SUPPL_PCLK, + CLK_REF_FULL => link_clock, SYSCLK => clk_sys, RESET => reset_i, CLEAR => init_quad, @@ -387,7 +391,6 @@ gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate WORD_SYNC_OUT => word_sync_i, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => master_clk_i, - QUAD_RST_IN => '0', LINK_TX_NULL_IN => global_reset_i, LINK_RX_NULL_OUT => global_reset_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, @@ -426,7 +429,7 @@ end generate; THE_MAIN_TX_RST: main_tx_reset_RS port map ( CLEAR => init_quad, - CLK_REF => CLK_SUPPL_PCLK, + CLK_REF => link_clock, TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i, TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, TX_PLL_LOL_QD_C_IN => tx_pll_lol_qd_c_i, @@ -441,13 +444,13 @@ end generate; --------------------------------------------------------------------------- -- PCSC: 4 downlinks --------------------------------------------------------------------------- - THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_125M_RS + THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER) ) port map( -- Clocks and reset - CLK_REF_FULL => CLK_SUPPL_PCLK, + CLK_REF_FULL => link_clock, SYSCLK => clk_sys, RESET => reset_i, CLEAR => init_quad, @@ -474,7 +477,6 @@ end generate; WORD_SYNC_OUT => open, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => open, - QUAD_RST_IN => '0', LINK_TX_NULL_IN => global_reset_i, LINK_RX_NULL_OUT => open, TX_PLL_LOL_OUT => tx_pll_lol_qd_c_i, @@ -510,13 +512,13 @@ end generate; -- PCSD: 2 downlinks (no GbE) --------------------------------------------------------------------------- gen_PCSD : if INCLUDE_GBE = c_NO generate - THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_125M_RS + THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_UNUSED, c_IS_UNUSED) ) port map( -- Clocks and reset - CLK_REF_FULL => CLK_SUPPL_PCLK, + CLK_REF_FULL => link_clock, SYSCLK => clk_sys, RESET => reset_i, CLEAR => init_quad, @@ -543,7 +545,6 @@ gen_PCSD : if INCLUDE_GBE = c_NO generate WORD_SYNC_OUT => open, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => open, - QUAD_RST_IN => '0', LINK_TX_NULL_IN => global_reset_i, LINK_RX_NULL_OUT => open, TX_PLL_LOL_OUT => tx_pll_lol_qd_d_i, diff --git a/tdctemplate/config_16_sfp_kel.vhd b/tdctemplate/config_16_sfp_kel.vhd index 06a4626..cfec05e 100644 --- a/tdctemplate/config_16_sfp_kel.vhd +++ b/tdctemplate/config_16_sfp_kel.vhd @@ -10,9 +10,11 @@ package config is --Begin of design configuration ------------------------------------------------------------------------------ +-- FPGA type constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 - - constant USE_RETRANSMISSION : integer := c_NO; + +-- Link speed + constant LINK_SPEED : integer := 200; -- 125: 1.25Gbps, 200: 2.00Gbps --pinout to be used - don't forget to change config_compile.pl as well -- 0: 32 Pin AddOn diff --git a/tdctemplate/trb3sc_tdctemplate.lpf b/tdctemplate/trb3sc_tdctemplate.lpf index 7ffe490..8572145 100644 --- a/tdctemplate/trb3sc_tdctemplate.lpf +++ b/tdctemplate/trb3sc_tdctemplate.lpf @@ -1,5 +1,5 @@ # locate the PCS blocks -LOCATE COMP "THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST" SITE "PCSB"; +LOCATE COMP "THE_MEDIA_INTERFACE/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSB"; # locate the media interfaces inside fabric REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB @@ -18,6 +18,6 @@ LOCATE COMP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe # read from SCI can be delayed due to long read strobe # write strobe can be delayed due to A/D being stable after access -MULTICYCLE FROM ASIC THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; -MULTICYCLE TO ASIC THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE FROM ASIC THE_MEDIA_INTERFACE/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC THE_MEDIA_INTERFACE/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj index 470dd9b..7163161 100644 --- a/tdctemplate/trb3sc_tdctemplate.prj +++ b/tdctemplate/trb3sc_tdctemplate.prj @@ -184,11 +184,9 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vh add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" - +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 73a35e4..a2f7232 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -145,25 +145,26 @@ architecture trb3sc_arch of trb3sc_tdctemplate is attribute syn_keep of bustc_rx : signal is true; attribute syn_preserve of bustc_rx : signal is true; - signal tx_pll_lol_qd_b_i : std_logic; - signal sync_tx_quad_i : std_logic; - signal tx_clk_avail_i : std_logic; - signal link_tx_ready_i : std_logic; - signal tx_pcs_rst_i : std_logic; - signal debug_i : std_logic_vector(31 downto 0); - signal rx_dlm_i : std_logic; - signal word_sync_i : std_logic; - signal master_clk_i : std_logic; - - signal tx_reset_state : std_logic_vector(3 downto 0); - signal global_reset_i : std_logic; - - signal send_rst_i : std_logic; - signal send_rst_word_i : std_logic_vector(7 downto 0); - signal send_dlm_word_i : std_logic_vector(7 downto 0); - - signal init_quad : std_logic; - + signal tx_pll_lol_qd_b_i : std_logic; + signal sync_tx_quad_i : std_logic; + signal tx_clk_avail_i : std_logic; + signal link_tx_ready_i : std_logic; + signal tx_pcs_rst_i : std_logic; + signal debug_i : std_logic_vector(31 downto 0); + signal rx_dlm_i : std_logic; + signal word_sync_i : std_logic; + signal master_clk_i : std_logic; + + signal tx_reset_state : std_logic_vector(3 downto 0); + signal global_reset_i : std_logic; + + signal send_rst_i : std_logic; + signal send_rst_word_i : std_logic_vector(7 downto 0); + signal send_dlm_word_i : std_logic_vector(7 downto 0); + + signal init_quad : std_logic; + signal link_clock : std_logic; + begin --------------------------------------------------------------------------- @@ -192,7 +193,12 @@ begin ); init_quad <= not GSR_N; - + + -- select link speed, wrong values are catched in media interface + link_clock <= CLK_SUPPL_PCLK when (LINK_SPEED = 125) else + clk_full_osc when (LINK_SPEED = 200) else + '0'; + gen_cal125 : if (USE_CALIBRATION_200MHZ = c_NO) generate pll_calibration : entity work.pll_in125_out33 port map ( @@ -214,13 +220,13 @@ end generate; --------------------------------------------------------------------------- -- TrbNet Uplink --------------------------------------------------------------------------- - THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_125M_RS + THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_RS generic map( IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE) ) port map( -- Clocks and reset - CLK_REF_FULL => CLK_SUPPL_PCLK, + CLK_REF_FULL => link_clock, SYSCLK => clk_sys, CLEAR => init_quad, RESET => reset_i, @@ -251,7 +257,6 @@ end generate; WORD_SYNC_OUT => word_sync_i, MASTER_CLK_IN => master_clk_i, MASTER_CLK_OUT => master_clk_i, - QUAD_RST_IN => '0', LINK_TX_NULL_IN => global_reset_i, LINK_RX_NULL_OUT => global_reset_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, @@ -286,7 +291,7 @@ end generate; THE_MAIN_TX_RST: main_tx_reset_RS port map ( CLEAR => init_quad, - CLK_REF => CLK_SUPPL_PCLK, + CLK_REF => link_clock, TX_PLL_LOL_QD_A_IN => '0', TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, TX_PLL_LOL_QD_C_IN => '0', -- 2.43.0