From 03439fe29803969d514794abadd83bd959d517a8 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 19 Feb 2009 12:30:34 +0000 Subject: [PATCH] *** empty log message *** --- testbenches/pseudo_random_stream_checker.vhd | 34 ++- .../pseudo_random_stream_generator.vhd | 6 +- testbenches/testbench_all_channels_p2p.prj | 3 + testbenches/testbench_all_channels_p2p.vhd | 131 +++++++++++- trb_net16_endpoint_hades_full.vhd | 10 +- trb_net16_med_16_CC.vhd | 200 +++++++++++------- trb_net_CRC.vhd | 20 +- 7 files changed, 292 insertions(+), 112 deletions(-) diff --git a/testbenches/pseudo_random_stream_checker.vhd b/testbenches/pseudo_random_stream_checker.vhd index 9b35aa5..417a5da 100644 --- a/testbenches/pseudo_random_stream_checker.vhd +++ b/testbenches/pseudo_random_stream_checker.vhd @@ -41,13 +41,15 @@ architecture arch of pseudo_random_stream_checker is ); end component; - signal test_counter : unsigned(15 downto 0); + signal test_counter : unsigned(15 downto 0) := x"0000"; signal CRC_reset : std_logic; signal last_D_EN : std_logic; signal last_D_RST : std_logic; signal last_D_IN : std_logic_vector(15 downto 0); signal CRC_out : std_logic_vector(15 downto 0); - + signal detected_RST : std_logic := '1'; + signal rst_counter : unsigned(3 downto 0) := x"0"; + signal tmp_DATA_IN : std_logic_vector(15 downto 0); begin THE_CRC : trb_net_CRC @@ -55,12 +57,12 @@ begin CLK => CLK, RESET => CRC_reset, CLK_EN => D_EN, - DATA_IN => std_logic_vector(test_counter)(15 downto 0), + DATA_IN => tmp_DATA_IN(15 downto 0), CRC_OUT => CRC_out, CRC_match => open ); - - CRC_reset <= RESET or D_RST; + tmp_DATA_IN <= std_logic_vector(test_counter); + CRC_reset <= RESET or D_RST or detected_RST; MY_CRC_OUT <= CRC_out; process(CLK) @@ -78,7 +80,7 @@ begin end if; end if; - if last_D_RST = '1' then + if last_D_RST = '1' or detected_RST = '1' then test_counter <= (others => '0'); else test_counter <= test_counter + 1; @@ -86,4 +88,24 @@ begin end if; end process; + PROC_detect_reset : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + detected_RST <= '1'; + else + if rst_counter = x"8" then + detected_RST <= '1'; + end if; + if D_IN = x"0000" and D_EN = '1' and rst_counter < x"8" then + rst_counter <= rst_counter + to_unsigned(1,1); + elsif D_IN /= x"0000" and D_EN = '1' then + rst_counter <= (others => '0'); + detected_RST <= '0'; + end if; + end if; + end if; + end process; + + end architecture; \ No newline at end of file diff --git a/testbenches/pseudo_random_stream_generator.vhd b/testbenches/pseudo_random_stream_generator.vhd index ee89176..8533a15 100644 --- a/testbenches/pseudo_random_stream_generator.vhd +++ b/testbenches/pseudo_random_stream_generator.vhd @@ -36,7 +36,7 @@ architecture arch of pseudo_random_stream_generator is end component; - signal test_counter : unsigned(20 downto 0); + signal test_counter : unsigned(20 downto 0) := '1' & x"FFF30"; signal CRC_reset : std_logic; signal CRC_enable : std_logic; signal last_CRC_enable : std_logic; @@ -81,7 +81,7 @@ begin begin if rising_edge(CLK) then if RESET = '1' then - test_counter <= (others => '0'); + test_counter <= '1' & x"FFFF0"; CRC_enable <= '0'; D_EN <= '0'; D_RST <= '1'; @@ -90,7 +90,7 @@ begin D_OUT <= next_D_OUT; D_EN <= next_D_EN; D_RST <= next_D_RST; - CRC_enable <= ((CRC2_out(5) or CRC2_out(14))); + CRC_enable <= ((CRC2_out(5) or CRC2_out(14))) or CRC_reset; last_CRC_enable <= CRC_enable; end if; end if; diff --git a/testbenches/testbench_all_channels_p2p.prj b/testbenches/testbench_all_channels_p2p.prj index 4d897be..7342ebf 100644 --- a/testbenches/testbench_all_channels_p2p.prj +++ b/testbenches/testbench_all_channels_p2p.prj @@ -10,6 +10,8 @@ vhdl work "../basics/rom_16x8.vhd" vhdl work "../basics/ram.vhd" vhdl work "../basics/ram_16x8_dp.vhd" vhdl work "../basics/ram_16x16_dp.vhd" +vhdl work "../basics/signal_sync.vhd" + vhdl work "../trb_net16_addresses.vhd" vhdl work "../basics/ram_dp.vhd" vhdl work "../trb_net16_term.vhd" @@ -38,4 +40,5 @@ vhdl work "../trb_net16_endpoint_active_4_channel.vhd" -- vhdl work "../trb_net16_hub_func.vhd" -- vhdl work "../trb_net16_hub_base.vhd" -- vhdl work "../trb_net16_hub_logic.vhd" +vhdl work "../trb_net16_med_16_CC.vhd" vhdl work "testbench_all_channels_p2p.vhd" \ No newline at end of file diff --git a/testbenches/testbench_all_channels_p2p.vhd b/testbenches/testbench_all_channels_p2p.vhd index 2456d9a..b00e3cd 100644 --- a/testbenches/testbench_all_channels_p2p.vhd +++ b/testbenches/testbench_all_channels_p2p.vhd @@ -87,9 +87,9 @@ architecture testbench_arch of testbench is API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; - INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_YES); USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; @@ -234,6 +234,35 @@ architecture testbench_arch of testbench is ); end component; + component trb_net16_med_16_CC is + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_VALID_OUT : out std_logic; + DATA_CTRL_OUT : out std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + DATA_VALID_IN : in std_logic; + DATA_CTRL_IN : in std_logic; + + STAT_OP : out std_logic_vector(15 downto 0); + CTRL_OP : in std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(63 downto 0) + ); + end component; + signal CLK : std_logic := '1'; signal RESET : std_logic := '1'; signal CLK_EN : std_logic := '1'; @@ -246,6 +275,14 @@ architecture testbench_arch of testbench is signal MED_PACKET_NUM_IN : std_logic_vector(2 downto 0); signal MED_DATA_IN : std_logic_vector(15 downto 0); signal MED_DATA_OUT : std_logic_vector(15 downto 0); + signal MED_R_DATAREADY_IN : std_logic; + signal MED_R_READ_IN : std_logic; + signal MED_R_DATAREADY_OUT : std_logic; + signal MED_R_READ_OUT : std_logic; + signal MED_R_PACKET_NUM_OUT : std_logic_vector(2 downto 0); + signal MED_R_PACKET_NUM_IN : std_logic_vector(2 downto 0); + signal MED_R_DATA_IN : std_logic_vector(15 downto 0); + signal MED_R_DATA_OUT : std_logic_vector(15 downto 0); signal MED_STAT_OP : std_logic_vector(31 downto 0); signal MED_CTRL_OP : std_logic_vector(31 downto 0); @@ -313,6 +350,10 @@ architecture testbench_arch of testbench is signal MPLEX_CTRL : std_logic_vector(31 downto 0); + signal DATA_LINK1 : std_logic_vector(17 downto 0); + signal DATA_LINK2 : std_logic_vector(17 downto 0); + + begin CLK <= not CLK after 5 ns; RESET <= '0' after 50 ns; @@ -476,6 +517,76 @@ APL_LENGTH_IN <= (others => '0'); ); +--Connecting both parts +----------------------- + + +-- MED_R_READ_IN <= transport MED_READ_OUT after 0 ns; +-- MED_R_DATAREADY_IN <= transport MED_DATAREADY_OUT after 499 ns ; +-- MED_R_DATA_IN <= transport MED_DATA_OUT after 499 ns ; +-- MED_R_PACKET_NUM_IN <= transport MED_PACKET_NUM_OUT after 499 ns ; +-- +-- MED_READ_IN <= transport MED_R_READ_OUT after 0 ns; +-- MED_DATAREADY_IN <= transport MED_R_DATAREADY_OUT after 499 ns ; +-- MED_DATA_IN <= transport MED_R_DATA_OUT after 499 ns ; +-- MED_PACKET_NUM_IN <= transport MED_R_PACKET_NUM_OUT after 499 ns ; +-- MED_STAT_OP <= (others => '0'); + + THE_SENDER_MED : trb_net16_med_16_CC + port map( + CLK => CLK, + CLK_EN => CLK_EN, + RESET => RESET, + + --Internal Connection + MED_DATA_IN => MED_DATA_OUT, + MED_PACKET_NUM_IN => MED_PACKET_NUM_OUT, + MED_DATAREADY_IN => MED_DATAREADY_OUT, + MED_READ_OUT => MED_READ_IN, + MED_DATA_OUT => MED_DATA_IN, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN, + MED_DATAREADY_OUT => MED_DATAREADY_IN, + MED_READ_IN => MED_READ_OUT, + + DATA_OUT => DATA_LINK1(15 downto 0), + DATA_VALID_OUT => DATA_LINK1(16), + DATA_CTRL_OUT => DATA_LINK1(17), + DATA_IN => DATA_LINK2(15 downto 0), + DATA_VALID_IN => DATA_LINK2(16), + DATA_CTRL_IN => DATA_LINK2(17), + + STAT_OP => MED_STAT_OP(15 downto 0), + CTRL_OP => MED_CTRL_OP(15 downto 0), + STAT_DEBUG => open + ); + + THE_RECEIVER_MED : trb_net16_med_16_CC + port map( + CLK => CLK, + CLK_EN => CLK_EN, + RESET => RESET, + + --Internal Connection + MED_DATA_IN => MED_R_DATA_OUT, + MED_PACKET_NUM_IN => MED_R_PACKET_NUM_OUT, + MED_DATAREADY_IN => MED_R_DATAREADY_OUT, + MED_READ_OUT => MED_R_READ_IN, + MED_DATA_OUT => MED_R_DATA_IN, + MED_PACKET_NUM_OUT => MED_R_PACKET_NUM_IN, + MED_DATAREADY_OUT => MED_R_DATAREADY_IN, + MED_READ_IN => MED_R_READ_OUT, + + DATA_OUT => DATA_LINK2(15 downto 0), + DATA_VALID_OUT => DATA_LINK2(16), + DATA_CTRL_OUT => DATA_LINK2(17), + DATA_IN => DATA_LINK1(15 downto 0), + DATA_VALID_IN => DATA_LINK1(16), + DATA_CTRL_IN => DATA_LINK1(17), + + STAT_OP => MED_STAT_OP(31 downto 16), + CTRL_OP => MED_CTRL_OP(31 downto 16), + STAT_DEBUG => open + ); --Receiver @@ -487,15 +598,15 @@ APL_LENGTH_IN <= (others => '0'); RESET => RESET, CLK_EN => CLK_EN, - MED_DATAREADY_OUT => MED_DATAREADY_IN, - MED_DATA_OUT => MED_DATA_IN, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN, - MED_READ_IN => MED_READ_OUT, + MED_DATAREADY_OUT => MED_R_DATAREADY_OUT, + MED_DATA_OUT => MED_R_DATA_OUT, + MED_PACKET_NUM_OUT => MED_R_PACKET_NUM_OUT, + MED_READ_IN => MED_R_READ_IN, - MED_DATAREADY_IN => MED_DATAREADY_OUT, - MED_DATA_IN => MED_DATA_OUT, - MED_PACKET_NUM_IN => MED_PACKET_NUM_OUT, - MED_READ_OUT => MED_READ_IN, + MED_DATAREADY_IN => MED_R_DATAREADY_IN, + MED_DATA_IN => MED_R_DATA_IN, + MED_PACKET_NUM_IN => MED_R_PACKET_NUM_IN, + MED_READ_OUT => MED_R_READ_OUT, MED_STAT_OP_IN => MED_STAT_OP(31 downto 16), MED_CTRL_OP_OUT => MED_CTRL_OP(31 downto 16), diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index edc9beb..1c7487e 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -1016,13 +1016,19 @@ begin INT_DATA_IN => MED_IO_DATA_OUT, INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT, INT_READ_OUT => MED_IO_READ_IN, + STAT => STAT_DEBUG_1, CTRL => CTRL_MPLEX ); buf_CTRL_GEN <= IOBUF_CTRL_GEN; -STAT_DEBUG_1 <= (others => '0'); -STAT_DEBUG_2 <= (others => '0'); +--STAT_DEBUG_1 <= STAT_MPLEX; +STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16); +STAT_DEBUG_2(7 downto 4) <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16); +STAT_DEBUG_2(8) <= apl_to_buf_REPLY_DATAREADY(3); +STAT_DEBUG_2(11 downto 9) <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3); +STAT_DEBUG_2(15 downto 12) <= (others => '0'); +STAT_DEBUG_2(31 downto 16) <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32); end architecture; diff --git a/trb_net16_med_16_CC.vhd b/trb_net16_med_16_CC.vhd index e843839..fe009bf 100644 --- a/trb_net16_med_16_CC.vhd +++ b/trb_net16_med_16_CC.vhd @@ -60,7 +60,6 @@ architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is signal reg_DATA_CTRL_IN : std_logic; signal last_DATA_CTRL_IN : std_logic; - signal link_running_counter : unsigned(3 downto 0); signal link_running : std_logic; signal buf_DATA_VALID_OUT : std_logic; @@ -74,7 +73,6 @@ architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is signal rx_led : std_logic; signal resync : std_logic; signal resync_counter : unsigned(4 downto 0); - signal rx_mismatch : std_logic; signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_MED_READ_OUT : std_logic; @@ -82,6 +80,15 @@ architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal trbnet_reset : std_logic; + signal resync_needed: std_logic; + type link_state_t is (STARTUP, WAITING, WORKING, RESYNCING, RESYNC_WAIT); + signal link_state : link_state_t; + signal med_error : std_logic_vector(2 downto 0); + signal pattern_counter : unsigned(3 downto 0); + signal pattern_detected : std_logic; + signal state_bits : std_logic_vector(2 downto 0); + begin ----------------------- @@ -108,7 +115,7 @@ begin PROC_RX_COUNTER : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then + if RESET = '1' or resync = '1' then rx_counter <= c_H0; elsif buf_MED_DATAREADY_OUT = '1' and CLK_EN = '1' then if rx_counter = c_max_word_number then @@ -130,9 +137,15 @@ begin PROC_REG_MED_OUT : process(CLK) begin if rising_edge(CLK) then - MED_DATA_OUT <= buf_MED_DATA_OUT; - MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; - MED_PACKET_NUM_OUT<= buf_MED_PACKET_NUM_OUT; + if RESET = '1' then + MED_DATA_OUT <= buf_MED_DATA_OUT; + MED_DATAREADY_OUT <= '0'; + MED_PACKET_NUM_OUT<= buf_MED_PACKET_NUM_OUT; + else + MED_DATA_OUT <= buf_MED_DATA_OUT; + MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; + MED_PACKET_NUM_OUT<= buf_MED_PACKET_NUM_OUT; + end if; end if; end process; @@ -141,77 +154,21 @@ begin --Link detection & Status & Control signals ----------------------- ---during idle phases, the ctrl signal changes every clock cycle ---if no change is seen within 2 cycles, the link is broken ---if it changes for 16 cycles, the link is running - PROC_DETECT_SIGNAL : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - link_running_counter <= to_unsigned(0,4); - link_running <= '0'; - else - if link_running_counter = x"F" and rx_mismatch = '0' then - link_running <= '1'; - else - link_running <= '0'; - end if; - if reg_DATA_VALID_IN = '0' then - last_DATA_CTRL_IN <= reg_DATA_CTRL_IN; - if last_DATA_CTRL_IN /= reg_DATA_CTRL_IN and link_running_counter /= x"F" then - link_running_counter <= link_running_counter + to_unsigned(1,1); - elsif last_DATA_CTRL_IN = reg_DATA_CTRL_IN and link_running_counter /= 0 then - link_running_counter <= link_running_counter - to_unsigned(1,1); - end if; - end if; - end if; - end if; - end process; - - PROC_CHECK_RX_COUNTER : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' or CTRL_OP(15) = '1' then - rx_mismatch <= '0'; - elsif link_running = '1' then - if (reg_DATA_CTRL_IN = '1' and reg_DATA_VALID_IN = '1' and rx_counter /= c_H0) - or (reg_DATA_CTRL_IN = '0' and reg_DATA_VALID_IN = '1' and rx_counter = c_H0) - or (buf_MED_DATAREADY_OUT = '1' and MED_READ_IN = '0') then - rx_mismatch <= '1'; - end if; - end if; - end if; - end process; - + STAT_OP(2 downto 0) <= med_error; STAT_OP(8 downto 3) <= (others => '0'); STAT_OP(9) <= link_led; STAT_OP(10) <= rx_led; STAT_OP(11) <= tx_led; STAT_OP(12) <= '0'; STAT_OP(13) <= '0'; - STAT_OP(14) <= '1' when link_running_counter > x"1" and link_running_counter < x"A" else '0'; - STAT_OP(15) <= rx_mismatch; + STAT_OP(14) <= trbnet_reset; + STAT_OP(15) <= resync_needed; - PROC_ERROR : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - STAT_OP(2 downto 0) <= ERROR_NC; - else - if link_running = '1' then - STAT_OP(2 downto 0) <= ERROR_OK; - else - STAT_OP(2 downto 0) <= ERROR_NC; - end if; - end if; - end if; - end process; - PROC_LED : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then + if RESET = '1' or trbnet_reset = '1' then led_counter <= (others => '0'); rx_led <= '0'; tx_led <= '0'; @@ -234,24 +191,106 @@ begin end if; end process; - PROC_GEN_RESYNC : process(CLK) + + PROC_SIGNAL_DETECT_PREPARE : process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - resync_counter <= (others => '0'); - resync <= '0'; + last_DATA_CTRL_IN <= '0'; + pattern_detected <= '0'; + elsif reg_DATA_VALID_IN = '0' then + last_DATA_CTRL_IN <= reg_DATA_CTRL_IN; + pattern_detected <= last_DATA_CTRL_IN xor reg_DATA_CTRL_IN; + end if; + end if; + end process; + + PROC_FSM : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + link_state <= STARTUP; + link_running <= '0'; + resync_needed <= '0'; + trbnet_reset <= '1'; + resync <= '0'; else - if CTRL_OP(15) = '1' or resync_counter /= 0 then - resync_counter <= resync_counter + 1; - resync <= '1'; - else - resync_counter <= (others => '0'); - resync <= '0'; - end if; + case link_state is + when STARTUP => + med_error <= ERROR_NC; + link_running <= '0'; + trbnet_reset <= '1'; + resync_needed <= '0'; + if pattern_detected = '1' then + trbnet_reset <= '0'; + link_state <= WAITING; + pattern_counter <= x"4"; + end if; + + when WAITING => + med_error <= ERROR_WAIT; + if pattern_detected = '1' and reg_DATA_VALID_IN = '0' then + pattern_counter <= pattern_counter + "1"; + elsif pattern_detected = '0' then + pattern_counter <= pattern_counter - x"4"; + end if; + if pattern_counter < x"4" then + link_state <= STARTUP; + elsif pattern_counter = x"F" then + link_state <= WORKING; + end if; + + when WORKING => + med_error <= ERROR_OK; + link_running <= '1'; + if CTRL_OP(15) = '1' then + link_state <= RESYNCING; + resync_counter <= (others => '0'); + link_running <= '0'; + end if; + if (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '1' and rx_counter /= c_H0) + or (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '0' and rx_counter = c_H0) then + resync_needed <= '1'; + else + resync_needed <= '0'; + end if; + if pattern_detected = '0' then + link_running <= '0'; + link_state <= STARTUP; + end if; + + when RESYNCING => + med_error <= ERROR_WAIT; + resync <= '1'; + resync_counter <= resync_counter + "1"; + if resync_counter = x"F" then + resync <= '0'; + link_state <= RESYNC_WAIT; + end if; + + when RESYNC_WAIT => + med_error <= ERROR_WAIT; + if reg_DATA_VALID_IN = '0' and reg_DATA_IN = x"AAAA" then + link_state <= WAITING; + pattern_counter <= x"4"; + elsif pattern_detected = '0' then + link_state <= STARTUP; + end if; + + when others => + link_state <= STARTUP; + end case; end if; end if; end process; + state_bits <= "000" when link_state = STARTUP else + "001" when link_state = WAITING else + "010" when link_state = RESYNCING else + "011" when link_state = RESYNC_WAIT else + "100" when link_state = WORKING else "111"; + + ----------------------- --Sender ----------------------- @@ -299,7 +338,6 @@ begin - ----------------------- --Debug ----------------------- @@ -307,11 +345,11 @@ begin STAT_DEBUG(15 downto 0) <= reg_DATA_IN; STAT_DEBUG(16) <= reg_DATA_VALID_IN; STAT_DEBUG(17) <= reg_DATA_CTRL_IN; -STAT_DEBUG(18) <= rx_mismatch; -STAT_DEBUG(22 downto 19)<= link_running_counter(3 downto 0); +STAT_DEBUG(18) <= resync_needed; +STAT_DEBUG(22 downto 19)<= std_logic_vector(pattern_counter(3 downto 0)); STAT_DEBUG(23) <= resync; +STAT_DEBUG(26 downto 24)<= state_bits; - -STAT_DEBUG(63 downto 24) <= (others => '0'); +STAT_DEBUG(63 downto 27) <= (others => '0'); end architecture; \ No newline at end of file diff --git a/trb_net_CRC.vhd b/trb_net_CRC.vhd index e80a60f..7bf2d5c 100644 --- a/trb_net_CRC.vhd +++ b/trb_net_CRC.vhd @@ -22,7 +22,7 @@ end entity; architecture trb_net_CRC_arch of trb_net_CRC is -signal D,C, next_CRC_OUT, CRC : std_logic_vector(15 downto 0); +signal D,C, next_CRC_OUT, CRC : std_logic_vector(15 downto 0) := x"0000"; begin D <= DATA_IN; @@ -31,14 +31,14 @@ begin CRC_match <= not or_all(CRC); next_CRC_OUT(0) <= D(15) xor D(13) xor D(12) xor D(11) xor D(10) xor D(9) xor - D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor - D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor - C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor + D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor + D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor + C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor C(9) xor C(10) xor C(11) xor C(12) xor C(13) xor C(15); next_CRC_OUT(1) <= D(14) xor D(13) xor D(12) xor D(11) xor D(10) xor D(9) xor - D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor - D(2) xor D(1) xor C(1) xor C(2) xor C(3) xor C(4) xor - C(5) xor C(6) xor C(7) xor C(8) xor C(9) xor C(10) xor + D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor + D(2) xor D(1) xor C(1) xor C(2) xor C(3) xor C(4) xor + C(5) xor C(6) xor C(7) xor C(8) xor C(9) xor C(10) xor C(11) xor C(12) xor C(13) xor C(14); next_CRC_OUT(2) <= D(14) xor D(1) xor D(0) xor C(0) xor C(1) xor C(14); next_CRC_OUT(3) <= D(15) xor D(2) xor D(1) xor C(1) xor C(2) xor C(15); @@ -54,9 +54,9 @@ begin next_CRC_OUT(13) <= D(12) xor D(11) xor C(11) xor C(12); next_CRC_OUT(14) <= D(13) xor D(12) xor C(12) xor C(13); next_CRC_OUT(15) <= D(15) xor D(14) xor D(12) xor D(11) xor D(10) xor D(9) xor - D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor - D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor - C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor + D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor + D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor + C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor C(9) xor C(10) xor C(11) xor C(12) xor C(14) xor C(15); process(CLK) -- 2.43.0