From 03af03137dc795ad52abd6c28023d0908ab472c1 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 29 Aug 2013 11:53:17 +0200 Subject: [PATCH] added variable SPI mode --- trb3/DacProgramming.tex | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/trb3/DacProgramming.tex b/trb3/DacProgramming.tex index 19a9a3d..b607f39 100644 --- a/trb3/DacProgramming.tex +++ b/trb3/DacProgramming.tex @@ -12,6 +12,10 @@ Programming the DAC for threshold generation is simple: A standard SPI interface \item Register 0xd412 contains the read-back of data from SPI. Content depends on slave chip. \end{itemize*} +\paragraph*{VHDL Configuration} +The number of bits per word can be set with a generic in the VHDL component instantiation. If a value below 32 is chosen, the upper bits in all registers are ignored. +The number of waitcycles between two edges on SCK can be selected as well. The default for LTC2600 and Padiwa is 7 wait cycles, I.e. 6.25 MHz. + \paragraph*{Configuration File} The software takes a text file as input and generates the correct SPI sequence to load and activate the DAC. The ASCII format is shown below, the commands can be found in table~\ref{ltc2600cmd}. -- 2.43.0