From 03dfca99da876970182541b91d9278d8905ef9ae Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 29 Apr 2022 10:47:39 +0200 Subject: [PATCH] check in latest version of code --- code/HitBuffer.vhd | 44 ++++++++++++++++++++++++++--------------- code/ReadoutHandler.vhd | 6 +++++- code/TDC_FF.vhd | 7 +++++-- sim/clocked_tdc.mpf | 18 ++++++++--------- testbench/testbench.vhd | 1 + 5 files changed, 48 insertions(+), 28 deletions(-) diff --git a/code/HitBuffer.vhd b/code/HitBuffer.vhd index 767a41d..8a5e66d 100644 --- a/code/HitBuffer.vhd +++ b/code/HitBuffer.vhd @@ -16,6 +16,7 @@ entity HitBuffer is HIT_VALID : in std_logic; COARSE_TIME_IN : in std_logic_vector(8 downto 0); + THROWAWAY_TIME : in std_logic_vector(8 downto 0); READOUT_ACTIVE : in std_logic; SPIKE_SETTING : in unsigned(3 downto 0); @@ -34,9 +35,12 @@ architecture arch of HitBuffer is attribute HGROUP: string; attribute HGROUP of arch : architecture is "HitBuffer"; + attribute syn_hier : string; + attribute syn_hier of arch : architecture is "firm,hard"; + signal reg_hit, cdc_data : std_logic_vector(17 downto 0); -signal reg_hit_valid : std_logic; - +signal reg_hit_valid : std_logic; +signal count_spike_en : std_logic; signal cdc_empty, cdc_nextvalid, cdc_valid, cdc_read : std_logic; signal edge_rising : std_logic_vector(15 downto 0); @@ -57,7 +61,7 @@ signal spike_timer : unsigned(3 downto 0) := (others => '0'); signal hit_store : std_logic_vector(35 downto 0); alias hit_store_coarse : std_logic_vector(8 downto 0) is hit_store(25 downto 17); -signal count_fallingedges, count_risingedges : unsigned(23 downto 0); +signal count_edges2, count_edges1 : unsigned(23 downto 0); type buffer_state_t is (EMPTY,WAIT_HIT,WAIT_HIT2,GOT_HIT,HAS_HIT,DO_READOUT,WAIT_READOUT); signal buffer_state : buffer_state_t; @@ -98,6 +102,7 @@ cdc_valid <= reg_hit_valid; PROC_BUILD_HIT : process begin wait until rising_edge(CLK_TDC); hit_buffer_write <= '0'; + count_spike_en <= '0'; full_hit <= (others => '0'); if spike_timer /= x"0" then spike_timer <= spike_timer - 1; @@ -106,7 +111,6 @@ PROC_BUILD_HIT : process begin if cdc_valid = '1' and cdc_data(5) = '1' then edge_rising <= '1' & cdc_data(4) & '0' & cdc_data(14 downto 6) & cdc_data(3 downto 0); --- count_risingedges <= count_risingedges + 1; spike_timer <= SPIKE_SETTING; end if; @@ -115,16 +119,24 @@ PROC_BUILD_HIT : process begin edge_rising_valid <= '0'; if READOUT_ACTIVE = '0' and spike_timer = x"0" then hit_buffer_write <= '1'; - count_fallingedges <= count_fallingedges + 1; + elsif spike_timer /= x"0" then + count_spike_en <= '1'; end if; --- count_fallingedges <= count_fallingedges + 1; end if; + --if RESET_IN = '1' then + --count_edges1 <= (others => '0'); + --end if; + +end process; + +process begin + wait until rising_edge(CLK_TDC); if RESET_IN = '1' then --- count_risingedges <= (others => '0'); - count_fallingedges <= (others => '0'); + count_edges2 <= (others => '0'); + elsif count_spike_en = '1' then + count_edges2 <= count_edges2 + 1; end if; - end process; ---------------------------------------------------------------------- @@ -160,9 +172,9 @@ PROC_BUF : process begin hit_buffer_reset <= '0'; DATA_EMPTY <= '0'; - if hit_buffer_read = '1' then - count_risingedges <= count_risingedges + 1; - end if; +-- if hit_buffer_read = '1' then +-- count_edges1 <= count_edges1 + 1; +-- end if; case buffer_state is when EMPTY => @@ -202,7 +214,7 @@ PROC_BUF : process begin if hit_buffer_full = '1' then hit_buffer_read <= '1'; buffer_state <= WAIT_HIT; - elsif hit_store_coarse = COARSE_TIME_IN then --too old + elsif hit_store_coarse = THROWAWAY_TIME then --too old hit_buffer_read <= '1'; buffer_state <= WAIT_HIT; end if; @@ -233,7 +245,7 @@ PROC_BUF : process begin if RESET_IN = '1' then buffer_state <= EMPTY; hit_buffer_reset <= '1'; - count_risingedges <= (others => '0'); +-- count_edges1 <= (others => '0'); end if; end process; @@ -242,8 +254,8 @@ DATA_OUT <= hit_store(27 downto 0); ---------------------------------------------------------------------- -- Statistics ---------------------------------------------------------------------- -STATUS_OUT(31 downto 0) <= x"00" & std_logic_vector(count_risingedges) when rising_edge(CLK_SYS); -STATUS_OUT(63 downto 32) <= x"00" & std_logic_vector(count_fallingedges) when rising_edge(CLK_SYS); +STATUS_OUT(31 downto 0) <= x"00" & std_logic_vector(count_edges1) when rising_edge(CLK_SYS); +STATUS_OUT(63 downto 32) <= x"00" & std_logic_vector(count_edges2) when rising_edge(CLK_SYS); STATUS_OUT(71 downto 64) <= "00" & hit_buffer_level when rising_edge(CLK_SYS); STATUS_OUT(75 downto 72) <= std_logic_vector(spike_timer) when rising_edge(CLK_SYS); diff --git a/code/ReadoutHandler.vhd b/code/ReadoutHandler.vhd index c4d24e5..64dc4a0 100644 --- a/code/ReadoutHandler.vhd +++ b/code/ReadoutHandler.vhd @@ -37,6 +37,10 @@ end entity; architecture arch of ReadoutHandler is + attribute syn_hier : string; + attribute syn_hier of arch : architecture is "firm,hard"; + + signal timer, timer_d : unsigned(7 downto 0); type state_rdo_t is (IDLE,CALIB,WAIT_WINDOW, COLLECT, FINISH); @@ -128,7 +132,7 @@ end process; -- TDC Data Collector & Processor ---------------------------------------------------------------------- PROC_RDO_TDC : process - variable channel : integer range 0 to 16 := 0; + variable channel : integer range 0 to 15 := 0; begin wait until rising_edge(CLK_TDC); collect_finish_tdc <= '0'; diff --git a/code/TDC_FF.vhd b/code/TDC_FF.vhd index ebc5ad9..f1bc77d 100644 --- a/code/TDC_FF.vhd +++ b/code/TDC_FF.vhd @@ -46,7 +46,7 @@ signal calibration_pulse, calibration_pulse_i : std_logic_vector(1 downto 0); signal tdc_data : tdc_data_t(NUM_CHANNELS-1 downto 0); -signal coarse_time : unsigned(8 downto 0) := (others => '0'); +signal coarse_time, throwaway_time : unsigned(8 downto 0) := (others => '0'); type status_t is array(0 to 31) of std_logic_vector(95 downto 0); signal hitbuffer_status : status_t; @@ -55,6 +55,7 @@ signal CONF_enable : std_logic_vector(31 downto 0) := (others => '1'); signal CONF_configure : std_logic_vector(31 downto 0) := x"00000300"; alias CONF_externalcalibration : std_logic is CONF_configure(0); alias CONF_SPIKE : std_logic_vector(3 downto 0) is CONF_configure(11 downto 8); +alias CONF_window : std_logic_vector(8 downto 0) is CONF_configure(24 downto 16); signal status_rdo_handler : std_logic_vector(63 downto 0); begin @@ -62,6 +63,7 @@ begin -- Infrastructure ---------------------------------------------------------------------- coarse_time <= coarse_time + 1 when rising_edge(CLK_FAST); +throwaway_time <= coarse_time - unsigned(CONF_window) when rising_edge(CLK_FAST); THE_PLL : entity work.PLL_TDC port map( @@ -122,6 +124,7 @@ gen_CHANNELS : for i in 0 to NUM_CHANNELS-1 generate HIT_VALID => tdc_valid(i), COARSE_TIME_IN => std_logic_vector(coarse_time), + THROWAWAY_TIME => std_logic_vector(throwaway_time), READOUT_ACTIVE => readout_active_i(i/16), SPIKE_SETTING => unsigned(CONF_SPIKE), @@ -219,7 +222,7 @@ begin BUS_TX.data <= CONF_configure; elsif BUS_RX.addr = x"0010" then BUS_TX.data <= status_rdo_handler(31 downto 0); - elsif BUS_RX.addr = x"0002" then + elsif BUS_RX.addr = x"0011" then BUS_TX.data <= status_rdo_handler(63 downto 32); elsif BUS_RX.addr(15 downto 5) = x"01" & "000" then BUS_TX.data <= hitbuffer_status(addr)(31 downto 0); diff --git a/sim/clocked_tdc.mpf b/sim/clocked_tdc.mpf index 772c5b5..811a3e6 100644 --- a/sim/clocked_tdc.mpf +++ b/sim/clocked_tdc.mpf @@ -1741,19 +1741,19 @@ Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 17 Project_File_0 = /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.vhd -Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1626881862 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628673529 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_1 = /d/jspc22/trb/git/clocked_tdc/code/InpLut.vhd Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1627477869 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_2 = /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628070191 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628673529 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_3 = /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1625843383 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628673529 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_4 = /d/jspc22/trb/git/clocked_tdc/testbench/testbench.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628072872 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628764738 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_5 = /d/jspc22/trb/git/clocked_tdc/code/TDC_FF.vhd -Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628078173 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2008 +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628599732 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2008 Project_File_6 = /d/jspc22/trb/git/trbnet/trb_net_std.vhd -Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1598871123 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628673508 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_7 = /d/jspc22/trb/git/trbnet/basics/pulse_sync.vhd Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1597067255 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_8 = /d/jspc22/trb/git/clocked_tdc/code/clocked_tdc_pkg.vhd @@ -1761,11 +1761,11 @@ Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v Project_File_9 = /d/jspc22/trb/git/mdcupgrade/cores/PLL_TDC/PLL_TDC.vhd Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1625398169 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_10 = /d/jspc22/trb/git/clocked_tdc/code/ReadoutHandler.vhd -Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628071053 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 2008 +Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628165770 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2008 Project_File_11 = /d/jspc22/trb/git/clocked_tdc/code/ChannelRegs.vhd Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1627484301 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_12 = /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1626771221 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628673529 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_13 = /d/jspc22/trb/git/clocked_tdc/code/FFregs.vhd Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1625577598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_14 = /d/jspc22/trb/git/clocked_tdc/code/Decoder.vhd @@ -1773,7 +1773,7 @@ Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 Project_File_15 = /d/jspc22/trb/git/clocked_tdc/code/FFregs2.vhd Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1627559635 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_16 = /d/jspc22/trb/git/clocked_tdc/code/HitBuffer.vhd -Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628078306 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2008 +Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1628597170 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2008 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 1 diff --git a/testbench/testbench.vhd b/testbench/testbench.vhd index 62536a1..325298e 100644 --- a/testbench/testbench.vhd +++ b/testbench/testbench.vhd @@ -78,6 +78,7 @@ process begin RDO_RX.invalid_trg <= '0'; RDO_RX.valid_notiming_trg <= '0'; RDO_RX.valid_timing_trg <= '0'; + wait for 100 us; wait for 0.7 us; trigger <= '1'; wait for 100 ns; -- 2.43.0