From 04111913f2091d51fce57a5f8afe9d4625ce745a Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 2 Oct 2007 12:30:46 +0000 Subject: [PATCH] first 16bit simulation done, Jan --- trb_net16_active_apimbuf.vhd | 521 ++++++++++++++++++++++++++++++++++ trb_net16_base_api.vhd | 62 ++-- trb_net16_ibuf.vhd | 3 +- trb_net16_io_multiplexer.vhd | 37 ++- trb_net16_obuf.vhd | 56 ++-- trb_net16_sbuf.vhd | 2 +- trb_net16_term.vhd | 531 ++++++++++++++++++++--------------- trb_net_dummy_fifo.vhd | 3 - 8 files changed, 925 insertions(+), 290 deletions(-) create mode 100644 trb_net16_active_apimbuf.vhd diff --git a/trb_net16_active_apimbuf.vhd b/trb_net16_active_apimbuf.vhd new file mode 100644 index 0000000..794d73b --- /dev/null +++ b/trb_net16_active_apimbuf.vhd @@ -0,0 +1,521 @@ +-- an active api together with an iobuf + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +use work.trb_net_std.all; + +--Entity decalaration for clock generator +entity trb_net16_active_apimbuf is + + generic (INIT_DEPTH : integer := 1; -- Depth of the FIFO, 2^(n+1), if + -- the initibuf + REPLY_DEPTH : integer := 1; -- or the replyibuf + FIFO_TO_INT_DEPTH : integer := 1; -- Depth of the FIFO, 2^(n+1), + -- for the direction to + -- internal world + FIFO_TO_APL_DEPTH : integer := 1; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of + -- the master path, if set to 0 + -- no buffer is used at all + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_READ_IN: in std_logic; -- Media is reading + + MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_READ_OUT: out std_logic; -- buffer reads a word from media + MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + + -- APL Transmitter port + APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in std_logic; -- + APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out + APL_READ_IN: in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT: out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + + -- Status and control port => just coming from the iobuf for debugging + STAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + STAT_api_control_signals: out std_logic_vector(31 downto 0); + STAT_MPLEX: out std_logic_vector(31 downto 0); + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); + MPLEX_CTRL: in std_logic_vector (31 downto 0); + API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); +end entity; + +architecture trb_net16_active_apimbuf_arch of trb_net16_active_apimbuf is + +component trb_net16_iobuf is + + generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if + -- the initibuf + REPLY_DEPTH : integer := 3); -- or the replyibuf + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_INIT_READ_IN: in std_logic; -- Media is reading + + MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media + MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_REPLY_READ_IN: in std_logic; -- Media is reading + + MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media + MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + + -- Internal direction port + + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_READ_IN: in std_logic; + + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_READ_OUT: out std_logic; + + INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_READ_IN: in std_logic; + + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); -- General Status + STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) + ); +end component; + +component trb_net16_active_api is + + generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), + -- for the direction to + -- internal world + FIFO_TO_APL_DEPTH : integer := 3; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of + -- the master path, if set to 0 + -- no buffer is used at all + + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in std_logic; -- + APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in std_logic; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out + APL_READ_IN: in std_logic; -- Read data word + + -- APL Control port + APL_RUN_OUT: out std_logic; -- Data transfer is running + APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out std_logic_vector (7 downto 0); + + -- Internal direction port + -- This is just a clone from trb_net_iobuf + + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_READ_IN: in std_logic; + + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_READ_OUT: out std_logic; + + + INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_READ_IN: in std_logic; + + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); +end component; + +component trb_net16_io_multiplexer is + + generic (BUS_WIDTH : integer := 16; + MULT_WIDTH : integer := 1); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (BUS_WIDTH-1 downto 0); + -- highest bits are mult. + MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_READ_OUT: out std_logic; + + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (BUS_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_READ_IN: in std_logic; + + -- Internal direction port + INT_DATAREADY_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0); + INT_DATA_OUT: out std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0); + INT_READ_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0); + + INT_DATAREADY_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0); + INT_DATA_IN: in std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0); + INT_READ_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0); + + -- Status and control port + CTRL: in std_logic_vector (31 downto 0); + STAT: out std_logic_vector (31 downto 0) + ); +end component; + +signal apl_to_buf_INIT_DATAREADY: std_logic; +signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0); +signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0); +signal apl_to_buf_INIT_READ : std_logic; + +signal buf_to_apl_INIT_DATAREADY: std_logic; +signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0); +signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0); +signal buf_to_apl_INIT_READ : std_logic; + +signal apl_to_buf_REPLY_DATAREADY: std_logic; +signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0); +signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); +signal apl_to_buf_REPLY_READ : std_logic; + +signal buf_to_apl_REPLY_DATAREADY: std_logic; +signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0); +signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); +signal buf_to_apl_REPLY_READ : std_logic; + +-- for the connection to the multiplexer +signal MED_INIT_DATAREADY_OUT : std_logic; +signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0); +signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0); +signal MED_INIT_READ_IN : std_logic; + +signal MED_INIT_DATAREADY_IN : std_logic; +signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0); +signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0); +signal MED_INIT_READ_OUT : std_logic; + +signal MED_REPLY_DATAREADY_OUT : std_logic; +signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0); +signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0); +signal MED_REPLY_READ_IN : std_logic; + +signal MED_REPLY_DATAREADY_IN : std_logic; +signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0); +signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0); +signal MED_REPLY_READ_OUT : std_logic; + +signal m_DATAREADY_OUT : std_logic_vector (1 downto 0); +signal m_DATA_OUT : std_logic_vector (31 downto 0); +signal m_PACKET_NUM_OUT: std_logic_vector (3 downto 0); +signal m_READ_IN : std_logic_vector (1 downto 0); + +signal m_DATAREADY_IN : std_logic_vector (1 downto 0); +signal m_DATA_IN : std_logic_vector (31 downto 0); +signal m_PACKET_NUM_IN : std_logic_vector (3 downto 0); +signal m_READ_OUT : std_logic_vector (1 downto 0); + +begin + + m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT; + m_DATA_OUT(15 downto 0) <= MED_INIT_DATA_OUT; + m_DATA_OUT(31 downto 16) <= MED_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(1 downto 0) <= MED_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(3 downto 2) <= MED_REPLY_PACKET_NUM_OUT; + MED_INIT_READ_IN <= m_READ_IN(0); + MED_REPLY_READ_IN <= m_READ_IN(1); + + MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0); + MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1); + MED_INIT_DATA_IN <= m_DATA_IN(15 downto 0); + MED_REPLY_DATA_IN <= m_DATA_IN(31 downto 16); + MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(1 downto 0); + MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(3 downto 2); + m_READ_OUT(0) <= MED_INIT_READ_OUT; + m_READ_OUT(1) <= MED_REPLY_READ_OUT; + + + ACTIVE_API: trb_net16_active_api + + generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, + FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH) + + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN, + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, + APL_WRITE_IN => APL_WRITE_IN, + APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, + APL_DTYPE_IN => APL_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, + APL_SEND_IN => APL_SEND_IN, + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, + + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT, + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, + APL_TYP_OUT => APL_TYP_OUT, + APL_DATAREADY_OUT => APL_DATAREADY_OUT, + APL_READ_IN => APL_READ_IN, + + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT, + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT, + + -- Internal direction port + -- connect via private signals + + INT_INIT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, + INT_INIT_DATA_OUT => apl_to_buf_INIT_DATA, + INT_INIT_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM, + INT_INIT_READ_IN => apl_to_buf_INIT_READ, + + INT_INIT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, + INT_INIT_DATA_IN => buf_to_apl_INIT_DATA, + INT_INIT_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM, + INT_INIT_READ_OUT => buf_to_apl_INIT_READ, + + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, + INT_REPLY_DATA_OUT => apl_to_buf_REPLY_DATA, + INT_REPLY_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM, + INT_REPLY_READ_IN => apl_to_buf_REPLY_READ, + + INT_REPLY_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, + INT_REPLY_DATA_IN => buf_to_apl_REPLY_DATA, + INT_REPLY_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM, + INT_REPLY_READ_OUT => buf_to_apl_REPLY_READ, + + -- Status and control port + STAT_FIFO_TO_INT => api_stat_fifo_to_int, + STAT_FIFO_TO_APL => api_stat_fifo_to_apl + ); + +STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0); +STAT_api_control_signals(3) <= APL_WRITE_IN; +STAT_api_control_signals(4) <= APL_SEND_IN; +STAT_api_control_signals(7 downto 5) <= (others => '0'); +STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0); +STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY; +STAT_api_control_signals(12) <= apl_to_buf_INIT_READ; +STAT_api_control_signals(31 downto 13) <= (others => '0'); + + + +IOBUF: trb_net16_iobuf + + generic map (INIT_DEPTH => INIT_DEPTH, + REPLY_DEPTH => REPLY_DEPTH) + + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, + MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, + MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT, + MED_INIT_READ_IN => MED_INIT_READ_IN, + + MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, + MED_INIT_DATA_IN => MED_INIT_DATA_IN, + MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN, + MED_INIT_READ_OUT => MED_INIT_READ_OUT, + MED_INIT_ERROR_IN => (others => '0'), + + MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, + MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, + MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT, + MED_REPLY_READ_IN => MED_REPLY_READ_IN, + + MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, + MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, + MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN, + MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, + MED_REPLY_ERROR_IN => (others => '0'), + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA, + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM, + INT_INIT_READ_IN => buf_to_apl_INIT_READ, + + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY, + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA, + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM, + INT_INIT_READ_OUT => apl_to_buf_INIT_READ, + + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY, + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA, + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM, + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ, + + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY, + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA, + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM, + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ, + + -- Status and control port + STAT_GEN => STAT_GEN, + STAT_LOCKED => STAT_LOCKED, + STAT_INIT_BUFFER => STAT_INIT_BUFFER, + STAT_REPLY_BUFFER => STAT_REPLY_BUFFER, + CTRL_GEN => CTRL_GEN, + CTRL_LOCKED => CTRL_LOCKED, + STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER, + STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER + ); + + MPLEX: trb_net16_io_multiplexer + generic map (BUS_WIDTH => 16, + MULT_WIDTH => 1) + port map ( + CLK => CLK, + RESET => RESET , + CLK_EN => CLK_EN, + + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + + INT_DATAREADY_OUT => m_DATAREADY_IN, + INT_DATA_OUT =>m_DATA_IN, + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, + INT_READ_IN =>m_READ_OUT, + + INT_DATAREADY_IN =>m_DATAREADY_OUT, + INT_DATA_IN =>m_DATA_OUT, + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, + INT_READ_OUT =>m_READ_IN, + + CTRL => MPLEX_CTRL + + ); + +end architecture; + diff --git a/trb_net16_base_api.vhd b/trb_net16_base_api.vhd index 6cff6aa..20f0a54 100644 --- a/trb_net16_base_api.vhd +++ b/trb_net16_base_api.vhd @@ -234,7 +234,7 @@ architecture trb_net16_base_api_arch of trb_net16_base_api is signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); - signal out_select: OUTPUT_SELECT; + signal out_select, last_out_select: OUTPUT_SELECT; signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); signal combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0); signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0); @@ -242,7 +242,6 @@ architecture trb_net16_base_api_arch of trb_net16_base_api is signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0); signal update_registered_trailer: std_logic; - signal master_counter : std_logic_vector(1 downto 0); begin @@ -436,9 +435,9 @@ begin -- select data for int direction --------------------------------------- process (out_select, combined_header_F1, combined_header_F2, - combined_header_F3, registered_trailer_F1, registered_trailer_F2, - registered_trailer_F3, fifo_to_int_data_out, combined_trailer_F1, - combined_trailer_F2, combined_trailer_F3, master_counter) + combined_header_F3, registered_trailer_F1, registered_trailer_F2, + registered_trailer_F3, fifo_to_int_data_out, combined_trailer_F1, + combined_trailer_F2, combined_trailer_F3, master_counter) begin if out_select = HDR then if master_counter = "00" then @@ -503,11 +502,11 @@ begin STATE_COMB: process(current_state, APL_SEND_IN, slave_running, sequence_counter, APL_SHORT_TRANSFER_IN, APL_WRITE_IN, fifo_to_int_empty, - sbuf_free, master_counter, fifo_to_apl_full, - reg_APL_DATAREADY_OUT, reg_INT_SLAVE_READ_OUT, - INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, APL_READ_IN, - fifo_to_apl_packet_num_out, reg_APL_TYP_OUT, - reg_APL_PACKET_NUM_OUT) + sbuf_free, master_counter, fifo_to_apl_full, + reg_APL_DATAREADY_OUT, reg_INT_SLAVE_READ_OUT, + INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, APL_READ_IN, + fifo_to_apl_packet_num_out, reg_APL_TYP_OUT, + reg_APL_PACKET_NUM_OUT, last_out_select) begin next_state <= MY_ERROR; next_INT_MASTER_DATAREADY_OUT <= '0'; @@ -541,20 +540,22 @@ begin ------------------------------------------------------------------------------- elsif current_state = SEND_SHORT then next_state <= SEND_SHORT; + out_select <= TRM; if APL_SEND_IN = '0' then -- terminate the transfer next_state <= SEND_TRAILER; next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= TRM; end if; ------------------------------------------------------------------------------- -- SEND_HEADER ------------------------------------------------------------------------------- elsif current_state = SEND_HEADER then + out_select <= HDR; if sbuf_free = '1' then next_INT_MASTER_DATAREADY_OUT <= '1'; end if; - if master_counter = "11" then + if master_counter = "00" then next_state <= RUNNING; + next_INT_MASTER_DATAREADY_OUT <= '0'; else next_state <= SEND_HEADER; end if; @@ -564,9 +565,9 @@ begin elsif current_state = RUNNING then if APL_SEND_IN = '0' then -- terminate the transfer if fifo_to_int_empty = '1' then -- immediate stop - update_registered_trailer <= '1'; next_INT_MASTER_DATAREADY_OUT <= '1'; if master_counter = "11" then + update_registered_trailer <= '1'; next_state <= SEND_TRAILER; out_select <= TRM_COMB; end if; @@ -583,10 +584,11 @@ begin end if; else -- APL_SEND_IN: still running next_state <= RUNNING; + out_select <= DAT; if fifo_to_int_empty = '0' and sbuf_free = '1' then -- data words have to be prepared next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= DAT; + if master_counter /= "00" then fifo_to_int_read <= '1'; end if; @@ -597,25 +599,29 @@ begin ------------------------------------------------------------------------------- elsif current_state = SHUTDOWN then next_state <= SHUTDOWN; - if fifo_to_int_empty = '0' and sbuf_free = '1' then - -- data words have to be prepared - next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= DAT; - if master_counter /= "00" then - fifo_to_int_read <= '1'; + if sbuf_free = '1' then + if fifo_to_int_empty = '0' then + -- data words have to be prepared + next_INT_MASTER_DATAREADY_OUT <= '1'; + out_select <= DAT; + if master_counter /= "00" then + fifo_to_int_read <= '1'; + end if; + else + -- we are done + --implicit: fill with padding words + if master_counter = "00" then + next_state <= SEND_TRAILER; + out_select <= TRM; end if; - elsif sbuf_free = '1' then - -- we are done - if master_counter = "11" then - next_state <= SEND_TRAILER; - out_select <= TRM; + next_INT_MASTER_DATAREADY_OUT <= '1'; end if; - next_INT_MASTER_DATAREADY_OUT <= '1'; end if; ------------------------------------------------------------------------------- -- SEND_TRAILER ------------------------------------------------------------------------------- elsif current_state = SEND_TRAILER then + out_select <= TRM; if sbuf_free = '1' then next_INT_MASTER_DATAREADY_OUT <= '1'; end if; @@ -669,19 +675,19 @@ begin if RESET = '1' then sequence_counter <= (others => '0'); reg_INT_SLAVE_READ_OUT <= '0'; + last_out_select <= DAT; if API_TYPE = 1 then current_state <= IDLE; else current_state <= WAITING; end if; slave_running <= '0'; - tb_current_state <= IDLE; elsif CLK_EN = '1' then sequence_counter <= next_sequence_counter; + last_out_select <= out_select; reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT; current_state <= next_state; slave_running <= next_slave_running; - tb_current_state <= tb_next_state; end if; end if; end process; diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index de1b05a..0e8a68a 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -243,7 +243,8 @@ begin -- this process controls what will be forwarded to the internal point DATA_OUT : process (INT_HEADER_IN, fifo_data_out, current_last_header, INT_READ_IN, - release_locked, is_locked, sbuf_free, fifo_empty) + release_locked, is_locked, sbuf_free, fifo_empty, + fifo_packet_num_out, current_fifo_packet_type) begin tmp_INT_DATA_OUT <= fifo_data_out; tmp_INT_PACKET_NUM_OUT <= fifo_packet_num_out; diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index 845a7a2..c38f2c9 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -104,7 +104,9 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal endpoint_locked, next_endpoint_locked: std_logic; signal demux_sbuf_data_in : std_logic_vector((BUS_WIDTH+2)-1 downto 0); signal demux_sbuf_data_out: std_logic_vector((BUS_WIDTH+2)*(2**MULT_WIDTH)-1 downto 0); -begin + signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0); + signal current_mux_packet_number : std_logic_vector (1 downto 0); + begin ------------------------------------------------------------------------------- -- DEMUX ------------------------------------------------------------------------------ @@ -134,7 +136,8 @@ begin MED_READ_OUT <= current_MED_READ_OUT; comb_demux : process (next_demux_dr_tmp, demux_next_READ, INT_READ_IN, - MED_DATAREADY_IN, current_MED_READ_OUT) + MED_DATAREADY_IN, current_MED_READ_OUT, + MED_PACKET_NUM_IN, demux_dr_tmp) begin next_demux_dr <= (others => '0'); current_demux_READ <= (others => '0'); @@ -214,9 +217,9 @@ ARBITER: trb_net_priority_arbiter process(current_mux_buffer, mux_read, endpoint_locked) begin next_endpoint_locked <= endpoint_locked; - if current_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) = "11" and mux_read = '1' then + if current_mux_packet_number = "11" and mux_read = '1' then next_endpoint_locked <= '0'; - elsif current_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) = "00" and mux_read = '1' then + elsif current_mux_packet_number = "00" and mux_read = '1' then next_endpoint_locked <= '1'; end if; end process; @@ -232,6 +235,11 @@ ARBITER: trb_net_priority_arbiter end if; end process; + current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0' + else final_INT_READ_OUT; + + STAT(17 downto 16) <= current_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) xor current_mux_packet_number; + process(CLK) begin if rising_edge(CLK) then @@ -243,10 +251,19 @@ ARBITER: trb_net_priority_arbiter end if; end process; - INT_READ_OUT <= final_INT_READ_OUT; - + INT_READ_OUT <= current_INT_READ_OUT; + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_mux_packet_number <= "00"; + elsif mux_read = '1' then + current_mux_packet_number <= current_mux_packet_number + 1; + end if; + end if; + end process; MUX_SBUF: trb_net_sbuf @@ -284,19 +301,19 @@ MED_PACKET_NUM_OUT <= MUX_SBUF_data_out(BUS_WIDTH+1 downto BUS_WIDTH); -- end loop; -- end process; - process (tmp_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN) + process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN) variable var_mux_buffer : STD_LOGIC_VECTOR (BUS_WIDTH+2-1 downto 0); begin var_mux_buffer := (others => '0'); for i in 0 to 2**MULT_WIDTH-1 loop - if tmp_INT_READ_OUT(i) = '1' then + if current_INT_READ_OUT(i) = '1' then var_mux_buffer(BUS_WIDTH-1 downto 0) := var_mux_buffer(BUS_WIDTH-1 downto 0) or INT_DATA_IN((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)); var_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) := var_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) or INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i); if INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i) = "00" then var_mux_buffer(3+MULT_WIDTH-1 downto 3) - := var_mux_buffer(3+MULT_WIDTH-1 downto 3) or conv_std_logic_vector(i, MULT_WIDTH); + := conv_std_logic_vector(i, MULT_WIDTH); end if; end if; end loop; @@ -305,6 +322,6 @@ MED_PACKET_NUM_OUT <= MUX_SBUF_data_out(BUS_WIDTH+1 downto BUS_WIDTH); mux_enable <= (mux_next_READ); -- or MED_READ_IN - mux_read <= or_all(final_INT_READ_OUT and INT_DATAREADY_IN); + mux_read <= or_all(current_INT_READ_OUT and INT_DATAREADY_IN); end architecture; \ No newline at end of file diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index ef7410a..2c94fa7 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -129,7 +129,8 @@ begin -- buffer registers STAT_BUFFER(1 downto 0) <= TRANSMITTED_BUFFERS; STAT_BUFFER(15 downto 2) <= (others => '0'); - STAT_BUFFER(31 downto 16) <= CURRENT_DATA_COUNT; + STAT_BUFFER(20 downto 16) <= CURRENT_DATA_COUNT; + STAT_BUFFER(31 downto 21) <= (others => '0'); SEND_BUFFER_SIZE_IN <= CTRL_BUFFER(3 downto 0); REC_BUFFER_SIZE_IN <= CTRL_BUFFER(7 downto 4); SEND_ACK_IN <= CTRL_BUFFER(8); @@ -137,7 +138,7 @@ begin - GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN) + GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, INT_DATA_IN) begin current_NOP_word <= (others => '0'); current_ACK_word <= (others => '0'); @@ -180,7 +181,10 @@ begin --full buffers (despite the sbuf) can only occur on the last packet. COMB_NEXT_TRANSFER : process(transfer_state, comb_dataready, transfer_counter, current_NOP_word, CURRENT_DATA_COUNT, reg_SEND_ACK_IN, INT_DATAREADY_IN, INT_DATA_IN, - reg_INT_READ_OUT, reg_SEND_ACK_IN, saved_packet_type ) + reg_INT_READ_OUT, reg_SEND_ACK_IN, saved_packet_type, + current_DATA_word, send_ACK, send_EOB, sbuf_free, + current_ACK_word, current_EOB_word, send_DATA, + max_DATA_COUNT_minus_two, next_TRANSMITTED_BUFFERS) begin if transfer_counter = "11" and comb_dataready = '1' then next_transfer_state <= IDLE; @@ -201,11 +205,13 @@ begin next_transfer_state <= SENDING_DATA; current_output_data_buffer <= current_DATA_word; comb_dataready <= '1'; --I hope sbuf can store - if saved_packet_type = TYPE_TRM and transfer_counter = "11" then --TRM means EOB - next_DATA_COUNT <= (others => '0'); - increase_TRANSMITTED_BUFFERS <= '1'; - else - next_DATA_COUNT <= CURRENT_DATA_COUNT +1; + if transfer_counter = "11" then + if saved_packet_type = TYPE_TRM then --TRM means EOB + next_DATA_COUNT <= (others => '0'); + increase_TRANSMITTED_BUFFERS <= '1'; + else + next_DATA_COUNT <= CURRENT_DATA_COUNT +1; + end if; end if; if (send_ACK = '1' or send_EOB = '1' ) then if transfer_counter = "11" then --finish running packet, then stop. @@ -241,7 +247,7 @@ begin end if; if send_data = '0' or --block reading if two buffers have been sent or current buffer runs full ((current_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = (max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0))) - and reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1' ) --and INT_DATA_IN(TYPE_POSITION) = TYPE_TRM + and reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1' and transfer_counter = "11") --long version of (next_count = max_count-1) or (next_TRANSMITTED_BUFFERS(1) = '1') or sbuf_free = '0' then @@ -267,17 +273,27 @@ begin end if; end process; - - next_max_DATA_COUNT_minus_one <= "0000000000000011" when REC_BUFFER_SIZE_IN="0001" else - "0000000000000111" when REC_BUFFER_SIZE_IN="0010" else - "0000000000001111" when REC_BUFFER_SIZE_IN="0011" else - "0000000000011111" when REC_BUFFER_SIZE_IN="0100" else - "0000000000000001"; - next_max_DATA_COUNT_minus_two <= "0000000000000010" when REC_BUFFER_SIZE_IN="0001" else - "0000000000000110" when REC_BUFFER_SIZE_IN="0010" else - "0000000000001110" when REC_BUFFER_SIZE_IN="0011" else - "0000000000011110" when REC_BUFFER_SIZE_IN="0100" else - "0000000000000000"; + next_max_DATA_COUNT_minus_one <= "00011" when REC_BUFFER_SIZE_IN="0001" else + "00111" when REC_BUFFER_SIZE_IN="0010" else + "01111" when REC_BUFFER_SIZE_IN="0011" else + "11111" when REC_BUFFER_SIZE_IN="0100" else + "00001"; + next_max_DATA_COUNT_minus_two <= "00010" when REC_BUFFER_SIZE_IN="0001" else + "00110" when REC_BUFFER_SIZE_IN="0010" else + "01110" when REC_BUFFER_SIZE_IN="0011" else + "11110" when REC_BUFFER_SIZE_IN="0100" else + "00000"; + +-- next_max_DATA_COUNT_minus_one <= "0000000000000011" when REC_BUFFER_SIZE_IN="0001" else +-- "0000000000000111" when REC_BUFFER_SIZE_IN="0010" else +-- "0000000000001111" when REC_BUFFER_SIZE_IN="0011" else +-- "0000000000011111" when REC_BUFFER_SIZE_IN="0100" else +-- "0000000000000001"; +-- next_max_DATA_COUNT_minus_two <= "0000000000000010" when REC_BUFFER_SIZE_IN="0001" else +-- "0000000000000110" when REC_BUFFER_SIZE_IN="0010" else +-- "0000000000001110" when REC_BUFFER_SIZE_IN="0011" else +-- "0000000000011110" when REC_BUFFER_SIZE_IN="0100" else +-- "0000000000000000"; reg_max_DATA_COUNT : process(CLK) begin diff --git a/trb_net16_sbuf.vhd b/trb_net16_sbuf.vhd index 7f4d52b..b265e18 100644 --- a/trb_net16_sbuf.vhd +++ b/trb_net16_sbuf.vhd @@ -53,7 +53,7 @@ architecture trb_net16_sbuf_arch of trb_net16_sbuf is component trb_net_sbuf is generic (DATA_WIDTH : integer := DATA_WIDTH + NUM_WIDTH; - VERSION: integer := 1); + VERSION: integer := VERSION); port( -- Misc CLK : in std_logic; diff --git a/trb_net16_term.vhd b/trb_net16_term.vhd index bb16db1..a0fa40f 100644 --- a/trb_net16_term.vhd +++ b/trb_net16_term.vhd @@ -12,9 +12,10 @@ use work.trb_net_std.all; entity trb_net16_term is generic ( - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of + FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of -- the master path, if set to 0 -- no buffer is used at all + SEND_DATA_BACK : integer := 0 --answer with data or only a short transfer? ); port( -- Misc @@ -118,258 +119,334 @@ architecture trb_net16_term_arch of trb_net16_term is signal reg_F2, next_F2 : std_logic_vector(15 downto 0); signal reg_F3, next_F3 : std_logic_vector(15 downto 0); signal transfer_counter : std_logic_vector(1 downto 0); + signal send_trm, next_send_trm : std_logic; + signal buf_INT_DATAREADY_OUT : std_logic; begin - CHECK_BUFFER1: if FIFO_TERM_BUFFER_DEPTH >0 generate - FIFO_TERM_BUFFER1: trb_net16_fifo - generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2, - DEPTH => FIFO_TERM_BUFFER_DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_term_buffer_data_in, - PACKET_NUM_IN => fifo_term_buffer_packet_num_in, - WRITE_ENABLE_IN => fifo_term_buffer_write, - DATA_OUT => fifo_term_buffer_data_out, - PACKET_NUM_OUT => fifo_term_buffer_packet_num_out, - READ_ENABLE_IN => fifo_term_buffer_read, - FULL_OUT => fifo_term_buffer_full, - EMPTY_OUT => fifo_term_buffer_empty - ); - end generate CHECK_BUFFER1; - - CHECK_BUFFER2: if FIFO_TERM_BUFFER_DEPTH =0 generate - FIFO_TERM_BUFFER0: trb_net16_dummy_fifo - generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_term_buffer_data_in, - PACKET_NUM_IN => fifo_term_buffer_packet_num_in, - WRITE_ENABLE_IN => fifo_term_buffer_write, - DATA_OUT => fifo_term_buffer_data_out, - PACKET_NUM_OUT => fifo_term_buffer_packet_num_out, - READ_ENABLE_IN => fifo_term_buffer_read, - FULL_OUT => fifo_term_buffer_full, - EMPTY_OUT => fifo_term_buffer_empty - ); - - end generate CHECK_BUFFER2; - - APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; - APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; - APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; - APL_GOT_TRM <= reg_APL_GOT_TRM; - --count packets - REG_TRANSFER_COUNTER : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - transfer_counter <= (others => '0'); - elsif fifo_term_buffer_write = '1' then - transfer_counter <= transfer_counter + 1; - end if; - end if; - end process; - - --this holds the current packet type - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - saved_packet_type <= "111"; - elsif INT_PACKET_NUM_IN = "00" then - saved_packet_type <= INT_DATA_IN(2 downto 0); - end if; - end if; - end process; - - --create comb. real packet type - current_packet_type <= INT_DATA_IN(2 downto 0) when (INT_PACKET_NUM_IN = "00" and RESET = '0') - else saved_packet_type; - - FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_DATA_IN, - INT_DATAREADY_IN, - fifo_term_buffer_empty, fifo_term_buffer_data_out, - INT_READ_IN, tb_registered_target, - reg_APL_DTYPE_OUT, reg_APL_ERROR_PATTERN_OUT, - reg_APL_SEQNR_OUT, reg_APL_GOT_TRM,APL_MY_ADDRESS_IN, - APL_HOLD_TRM, APL_DTYPE_IN, APL_ERROR_PATTERN_IN, reg_F1, - reg_F2, reg_F3, current_packet_type, fifo_term_buffer_full, - INT_PACKET_NUM_IN, transfer_counter, - reg_APL_ERROR_PATTERN_IN, reg_APL_DTYPE_IN, - fifo_term_buffer_packet_num_out) - begin -- process - INT_READ_OUT <= '0'; - fifo_term_buffer_write <= '0'; - tb_next_state <= MY_ERROR; - tb_next_registered_target <= tb_registered_target; - fifo_term_buffer_read <= '0'; - INT_DATAREADY_OUT <= '0'; - next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; - next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; - next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; - next_APL_GOT_TRM <= reg_APL_GOT_TRM; - next_F1 <= reg_F1; - next_F2 <= reg_F2; - next_F3 <= reg_F3; - fifo_term_buffer_data_in <= (others => '0'); ------------------------------------------------------------------------ --- IDLE ------------------------------------------------------------------------ - if tb_current_state = IDLE then - INT_READ_OUT <= '1'; - tb_next_state <= IDLE; - - if current_packet_type = TYPE_HDR and INT_DATAREADY_IN = '1' then - --header is sent back with exchanged target and source address - tb_next_state <= SENDING_HEADER; - - elsif current_packet_type = TYPE_DAT and INT_DATAREADY_IN = '1' then - --data can be directly sent back - fifo_term_buffer_data_in <= INT_DATA_IN; - if fifo_term_buffer_full = '0' and (tb_registered_target = APL_MY_ADDRESS_IN - or tb_registered_target = BROADCAST_ADRESS) then - fifo_term_buffer_write <= '1'; - else - fifo_term_buffer_write <= '0'; - end if; - - elsif current_packet_type = TYPE_TRM and INT_DATAREADY_IN = '1' then - --TRM is given to APL +-- GEN_ONLYTRM: if SEND_DATA_BACK = 0 generate + APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; + APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; + APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; + APL_GOT_TRM <= reg_APL_GOT_TRM; + INT_READ_OUT <= not send_trm and not reg_APL_GOT_TRM; + + process(RESET, reg_APL_ERROR_PATTERN_OUT, reg_APL_DTYPE_OUT, reg_APL_SEQNR_OUT, reg_APL_GOT_TRM, current_packet_type, + INT_PACKET_NUM_IN, INT_DATA_IN, APL_HOLD_TRM, send_trm, reg_APL_ERROR_PATTERN_OUT, reg_APL_DTYPE_IN, + transfer_counter) + begin + next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; + next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; + next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; + next_APL_GOT_TRM <= reg_APL_GOT_TRM; + next_send_trm <= '0'; + buf_INT_DATAREADY_OUT <= '0'; + INT_DATA_OUT <= (others => '0'); + if current_packet_type = TYPE_TRM then if INT_PACKET_NUM_IN = "01" then next_APL_ERROR_PATTERN_OUT(31 downto 16) <= INT_DATA_IN; elsif INT_PACKET_NUM_IN = "10" then next_APL_ERROR_PATTERN_OUT(15 downto 0) <= INT_DATA_IN; elsif INT_PACKET_NUM_IN = "11" then - next_APL_DTYPE_OUT <= INT_DATA_IN(DTYPE_POSITION); - next_APL_SEQNR_OUT <= INT_DATA_IN(SEQNR_POSITION); + next_APL_DTYPE_OUT <= INT_DATA_IN(3 downto 0); + next_APL_SEQNR_OUT <= INT_DATA_IN(11 downto 4); next_APL_GOT_TRM <= '1'; end if; - tb_next_state <= RUNNING; end if; ------------------------------------------------------------------------ --- SENDING & RECEIVING HEADER ------------------------------------------------------------------------ - --this state is needed to exchange source and target address - elsif tb_current_state = SENDING_HEADER then - INT_READ_OUT <= '1'; - if INT_DATAREADY_IN = '1' then - fifo_term_buffer_write <= '1'; - if INT_PACKET_NUM_IN = "01" then - next_F2 <= INT_DATA_IN; - fifo_term_buffer_data_in <= (others => '0'); - fifo_term_buffer_data_in(2 downto 0) <= TYPE_HDR; - elsif INT_PACKET_NUM_IN = "10" then - next_F1 <= INT_DATA_IN; - tb_next_registered_target <= INT_DATA_IN; - fifo_term_buffer_data_in <= INT_DATA_IN; - elsif INT_PACKET_NUM_IN = "11" then - next_F3 <= INT_DATA_IN; - fifo_term_buffer_data_in <= reg_F2; + if (reg_APL_GOT_TRM = '1' and APL_HOLD_TRM = '0') or send_trm = '1' then + next_APL_GOT_TRM <= '0'; + if transfer_counter = "11" and INT_READ_IN = '1' then + next_send_trm <= '0'; + else + next_send_trm <= '1'; + end if; + buf_INT_DATAREADY_OUT <= '1'; + if transfer_counter = "00" then + INT_DATA_OUT <= (others => '0'); + INT_DATA_OUT(2 downto 0) <= TYPE_TRM; + elsif transfer_counter = "01" then + INT_DATA_OUT <= reg_APL_ERROR_PATTERN_OUT(31 downto 16); + elsif transfer_counter = "10" then + INT_DATA_OUT <= reg_APL_ERROR_PATTERN_OUT(15 downto 0); + else + INT_DATA_OUT(15 downto 12)<= (others => '0'); + INT_DATA_OUT(11 downto 4) <= reg_APL_SEQNR_OUT; + INT_DATA_OUT(3 downto 0) <= reg_APL_DTYPE_IN; end if; end if; - if transfer_counter = "11" then - INT_READ_OUT <= '0'; - fifo_term_buffer_data_in <= reg_F3; - fifo_term_buffer_write <= '1'; - tb_next_state <= IDLE; - end if; ------------------------------------------------------------------------ --- RUNNING ------------------------------------------------------------------------ - elsif tb_current_state = RUNNING then - if APL_HOLD_TRM = '1' then - tb_next_state <= RUNNING; - else - tb_next_state <= SEND_TRAILER; - end if; ------------------------------------------------------------------------ --- TRAILER ------------------------------------------------------------------------ - elsif tb_current_state = SEND_TRAILER then - tb_next_state <= SEND_TRAILER ; - fifo_term_buffer_write <= '1'; - if transfer_counter = "00" then - fifo_term_buffer_data_in <= (others => '0'); - fifo_term_buffer_data_in(2 downto 0) <= TYPE_TRM; - elsif transfer_counter = "01" then - fifo_term_buffer_data_in <= reg_APL_ERROR_PATTERN_IN(31 downto 16); - elsif transfer_counter = "10" then - fifo_term_buffer_data_in <= reg_APL_ERROR_PATTERN_IN(15 downto 0); - else - fifo_term_buffer_data_in(15 downto 12)<= (others => '0'); - fifo_term_buffer_data_in(11 downto 4) <= reg_APL_SEQNR_OUT; - fifo_term_buffer_data_in(3 downto 0) <= reg_APL_DTYPE_IN; + end process; + + --save data from api while sending trailer + CLK_REG2: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + reg_APL_DTYPE_IN <= (others => '0'); + reg_APL_ERROR_PATTERN_IN <= (others => '0'); + elsif APL_HOLD_TRM = '0' and send_trm = '0' then + reg_APL_DTYPE_IN <= APL_DTYPE_IN; + reg_APL_ERROR_PATTERN_IN <= APL_ERROR_PATTERN_IN; + end if; end if; - if transfer_counter = "11" then - tb_next_state <= IDLE; - tb_next_registered_target <= ILLEGAL_ADRESS; - next_APL_GOT_TRM <= '0'; + end process; + + --count packets + REG_TRANSFER_COUNTER : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + transfer_counter <= (others => '0'); + elsif buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then + transfer_counter <= transfer_counter + 1; + end if; end if; - end if; ------------------------------------------------------------------------ --- WRITE FIFO TO INT ------------------------------------------------------------------------ - INT_DATA_OUT <= fifo_term_buffer_data_out; - INT_PACKET_NUM_OUT <= fifo_term_buffer_packet_num_out; - if fifo_term_buffer_empty = '0' then - INT_DATAREADY_OUT <= '1'; - if (INT_READ_IN = '1') then - fifo_term_buffer_read <= '1'; + end process; + + INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; + INT_PACKET_NUM_OUT <= transfer_counter; +-- end generate; + + + +-- GEN_ALSODATA: if SEND_DATA_BACK = 1 generate +-- FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_DATA_IN, +-- INT_DATAREADY_IN, +-- fifo_term_buffer_empty, fifo_term_buffer_data_out, +-- INT_READ_IN, tb_registered_target, +-- reg_APL_DTYPE_OUT, reg_APL_ERROR_PATTERN_OUT, +-- reg_APL_SEQNR_OUT, reg_APL_GOT_TRM,APL_MY_ADDRESS_IN, +-- APL_HOLD_TRM, APL_DTYPE_IN, APL_ERROR_PATTERN_IN, reg_F1, +-- reg_F2, reg_F3, current_packet_type, fifo_term_buffer_full, +-- INT_PACKET_NUM_IN, transfer_counter, +-- reg_APL_ERROR_PATTERN_IN, reg_APL_DTYPE_IN, +-- fifo_term_buffer_packet_num_out) +-- begin -- process +-- INT_READ_OUT <= '1'; +-- fifo_term_buffer_write <= '0'; +-- tb_next_state <= MY_ERROR; +-- tb_next_registered_target <= tb_registered_target; +-- fifo_term_buffer_read <= '0'; +-- INT_DATAREADY_OUT <= '0'; +-- next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; +-- next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; +-- next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; +-- next_APL_GOT_TRM <= reg_APL_GOT_TRM; +-- next_F1 <= reg_F1; +-- next_F2 <= reg_F2; +-- next_F3 <= reg_F3; +-- fifo_term_buffer_data_in <= (others => '0'); +-- ----------------------------------------------------------------------- +-- -- IDLE +-- ----------------------------------------------------------------------- +-- if tb_current_state = IDLE then +-- INT_READ_OUT <= '1'; +-- tb_next_state <= IDLE; +-- if INT_DATAREADY_IN = '1' then +-- if current_packet_type = TYPE_HDR then +-- --header is sent back with exchanged target and source address +-- tb_next_state <= SENDING_HEADER; +-- elsif current_packet_type = TYPE_DAT then +-- --data can be directly sent back +-- fifo_term_buffer_data_in <= INT_DATA_IN; +-- if fifo_term_buffer_full = '0' and (tb_registered_target = APL_MY_ADDRESS_IN +-- or tb_registered_target = BROADCAST_ADRESS) then +-- fifo_term_buffer_write <= '1'; +-- else +-- fifo_term_buffer_write <= '0'; +-- end if; +-- +-- elsif current_packet_type = TYPE_TRM then +-- --TRM is given to APL +-- if INT_PACKET_NUM_IN = "01" then +-- next_APL_ERROR_PATTERN_OUT(31 downto 16) <= INT_DATA_IN; +-- elsif INT_PACKET_NUM_IN = "10" then +-- next_APL_ERROR_PATTERN_OUT(15 downto 0) <= INT_DATA_IN; +-- elsif INT_PACKET_NUM_IN = "11" then +-- next_APL_DTYPE_OUT <= INT_DATA_IN(DTYPE_POSITION); +-- next_APL_SEQNR_OUT <= INT_DATA_IN(SEQNR_POSITION); +-- next_APL_GOT_TRM <= '1'; +-- tb_next_state <= RUNNING; +-- end if; +-- +-- end if; +-- end if; +-- ----------------------------------------------------------------------- +-- -- SENDING & RECEIVING HEADER +-- ----------------------------------------------------------------------- +-- --this state is needed to exchange source and target address +-- elsif tb_current_state = SENDING_HEADER then +-- INT_READ_OUT <= '1'; +-- if INT_DATAREADY_IN = '1' then +-- fifo_term_buffer_write <= '1'; +-- if INT_PACKET_NUM_IN = "01" then +-- next_F2 <= INT_DATA_IN; +-- fifo_term_buffer_data_in <= (others => '0'); +-- fifo_term_buffer_data_in(2 downto 0) <= TYPE_HDR; +-- elsif INT_PACKET_NUM_IN = "10" then +-- next_F1 <= INT_DATA_IN; +-- tb_next_registered_target <= INT_DATA_IN; +-- fifo_term_buffer_data_in <= INT_DATA_IN; +-- elsif INT_PACKET_NUM_IN = "11" then +-- next_F3 <= INT_DATA_IN; +-- fifo_term_buffer_data_in <= reg_F2; +-- end if; +-- end if; +-- if transfer_counter = "11" then +-- INT_READ_OUT <= '0'; +-- fifo_term_buffer_data_in <= reg_F3; +-- fifo_term_buffer_write <= '1'; +-- tb_next_state <= IDLE; +-- end if; +-- ----------------------------------------------------------------------- +-- -- RUNNING +-- ----------------------------------------------------------------------- +-- elsif tb_current_state = RUNNING then +-- INT_READ_OUT <= '0'; +-- if APL_HOLD_TRM = '1' then +-- tb_next_state <= RUNNING; +-- else +-- tb_next_state <= SEND_TRAILER; +-- end if; +-- ----------------------------------------------------------------------- +-- -- TRAILER +-- ----------------------------------------------------------------------- +-- elsif tb_current_state = SEND_TRAILER then +-- INT_READ_OUT <= '0'; +-- tb_next_state <= SEND_TRAILER ; +-- fifo_term_buffer_write <= '1'; +-- if transfer_counter = "00" then +-- fifo_term_buffer_data_in <= (others => '0'); +-- fifo_term_buffer_data_in(2 downto 0) <= TYPE_TRM; +-- elsif transfer_counter = "01" then +-- fifo_term_buffer_data_in <= reg_APL_ERROR_PATTERN_IN(31 downto 16); +-- elsif transfer_counter = "10" then +-- fifo_term_buffer_data_in <= reg_APL_ERROR_PATTERN_IN(15 downto 0); +-- else +-- fifo_term_buffer_data_in(15 downto 12)<= (others => '0'); +-- fifo_term_buffer_data_in(11 downto 4) <= reg_APL_SEQNR_OUT; +-- fifo_term_buffer_data_in(3 downto 0) <= reg_APL_DTYPE_IN; +-- end if; +-- if transfer_counter = "11" then +-- tb_next_state <= IDLE; +-- tb_next_registered_target <= ILLEGAL_ADRESS; +-- next_APL_GOT_TRM <= '0'; +-- end if; +-- end if; +-- ----------------------------------------------------------------------- +-- -- WRITE FIFO TO INT +-- ----------------------------------------------------------------------- +-- INT_DATA_OUT <= fifo_term_buffer_data_out; +-- INT_PACKET_NUM_OUT <= fifo_term_buffer_packet_num_out; +-- if fifo_term_buffer_empty = '0' then +-- INT_DATAREADY_OUT <= '1'; +-- if (INT_READ_IN = '1') then +-- fifo_term_buffer_read <= '1'; +-- end if; +-- end if; +-- end process; +-- +-- fifo_term_buffer_packet_num_in <= transfer_counter; +-- + +-- end generate; + + + +-- CHECK_BUFFER1: if FIFO_TERM_BUFFER_DEPTH >0 generate +-- FIFO_TERM_BUFFER1: trb_net16_fifo +-- generic map ( +-- DATA_WIDTH => 16, +-- NUM_WIDTH => 2, +-- DEPTH => FIFO_TERM_BUFFER_DEPTH) +-- port map ( +-- CLK => CLK, +-- RESET => RESET, +-- CLK_EN => CLK_EN, +-- DATA_IN => fifo_term_buffer_data_in, +-- PACKET_NUM_IN => fifo_term_buffer_packet_num_in, +-- WRITE_ENABLE_IN => fifo_term_buffer_write, +-- DATA_OUT => fifo_term_buffer_data_out, +-- PACKET_NUM_OUT => fifo_term_buffer_packet_num_out, +-- READ_ENABLE_IN => fifo_term_buffer_read, +-- FULL_OUT => fifo_term_buffer_full, +-- EMPTY_OUT => fifo_term_buffer_empty +-- ); +-- end generate CHECK_BUFFER1; +-- +-- CHECK_BUFFER2: if FIFO_TERM_BUFFER_DEPTH =0 generate +-- FIFO_TERM_BUFFER0: trb_net16_dummy_fifo +-- generic map ( +-- DATA_WIDTH => 16, +-- NUM_WIDTH => 2) +-- port map ( +-- CLK => CLK, +-- RESET => RESET, +-- CLK_EN => CLK_EN, +-- DATA_IN => fifo_term_buffer_data_in, +-- PACKET_NUM_IN => fifo_term_buffer_packet_num_in, +-- WRITE_ENABLE_IN => fifo_term_buffer_write, +-- DATA_OUT => fifo_term_buffer_data_out, +-- PACKET_NUM_OUT => fifo_term_buffer_packet_num_out, +-- READ_ENABLE_IN => fifo_term_buffer_read, +-- FULL_OUT => fifo_term_buffer_full, +-- EMPTY_OUT => fifo_term_buffer_empty +-- ); +-- +-- end generate CHECK_BUFFER2; + +-- APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; +-- APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; +-- APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; +-- APL_GOT_TRM <= reg_APL_GOT_TRM; + + + + --this holds the current packet type + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or (INT_PACKET_NUM_IN = "11" and INT_DATAREADY_IN = '1') then + saved_packet_type <= "111"; + elsif INT_PACKET_NUM_IN = "00" and INT_DATAREADY_IN = '1' then + saved_packet_type <= INT_DATA_IN(2 downto 0); end if; end if; end process; - fifo_term_buffer_packet_num_in <= transfer_counter; + --create comb. real packet type + current_packet_type <= INT_DATA_IN(2 downto 0) when (INT_PACKET_NUM_IN = "00" and INT_DATAREADY_IN = '1' and RESET = '0') + else saved_packet_type; - CLK_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - tb_current_state <= IDLE; - tb_registered_target <= ILLEGAL_ADRESS; - reg_F1 <= ILLEGAL_ADRESS; - reg_F2 <= ILLEGAL_ADRESS; - reg_F3 <= (others => '0'); - reg_APL_GOT_TRM <= '0'; - reg_APL_DTYPE_OUT <= (others => '0'); - reg_APL_ERROR_PATTERN_OUT <= (others => '0'); - reg_APL_SEQNR_OUT <= (others => '0'); - else - tb_current_state <= tb_next_state; - tb_registered_target <= tb_next_registered_target; - reg_F1 <= next_F1; - reg_F2 <= next_F2; - reg_F3 <= next_F3; - reg_APL_GOT_TRM <= next_APL_GOT_TRM; - reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT; - reg_APL_ERROR_PATTERN_OUT <= next_APL_ERROR_PATTERN_OUT; - reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT; - end if; - end if; - end process; - --save data from api while sending trailer - CLK_REG2: process(CLK) - begin + CLK_REG: process(CLK) + begin if rising_edge(CLK) then if RESET = '1' then - reg_APL_DTYPE_IN <= (others => '0'); - reg_APL_ERROR_PATTERN_IN <= (others => '0'); - elsif APL_HOLD_TRM = '0' and tb_current_state /= SEND_TRAILER then - reg_APL_DTYPE_IN <= APL_DTYPE_IN; - reg_APL_ERROR_PATTERN_IN <= APL_ERROR_PATTERN_IN; + tb_current_state <= IDLE; + tb_registered_target <= ILLEGAL_ADRESS; + reg_F1 <= ILLEGAL_ADRESS; + reg_F2 <= ILLEGAL_ADRESS; + reg_F3 <= (others => '0'); + reg_APL_GOT_TRM <= '0'; + reg_APL_DTYPE_OUT <= (others => '0'); + reg_APL_ERROR_PATTERN_OUT <= (others => '0'); + reg_APL_SEQNR_OUT <= (others => '0'); + send_trm <= '0'; + else + tb_current_state <= tb_next_state; + tb_registered_target <= tb_next_registered_target; + reg_F1 <= next_F1; + reg_F2 <= next_F2; + reg_F3 <= next_F3; + reg_APL_GOT_TRM <= next_APL_GOT_TRM; + reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT; + reg_APL_ERROR_PATTERN_OUT <= next_APL_ERROR_PATTERN_OUT; + reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT; + send_trm <= next_send_trm; end if; end if; end process; + end architecture; diff --git a/trb_net_dummy_fifo.vhd b/trb_net_dummy_fifo.vhd index 8ac1438..22bac51 100644 --- a/trb_net_dummy_fifo.vhd +++ b/trb_net_dummy_fifo.vhd @@ -69,9 +69,6 @@ architecture arch_trb_net_dummy_fifo of trb_net_dummy_fifo is elsif CLK_EN = '1' then current_EMPTY <= next_EMPTY; current_FULL <= next_FULL; - else - current_EMPTY <= current_EMPTY; - current_FULL <= current_FULL; end if; end if; end process; -- 2.43.0