From 042d8b5db302d9bb4ffbebf8cf7cd7c9329a2d7f Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 31 Jan 2022 15:08:23 +0100 Subject: [PATCH] new link reset by faked SLAVE_ACTIVE_IN in CTS --- cts/trb3sc_cts.vhd | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 10f2519..23e7001 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -261,6 +261,9 @@ architecture trb3sc_arch of trb3sc_cts is signal coarse_counter : unsigned(15 downto 0); signal coarse_delay : std_logic_vector(15 downto 0); + signal slv_act_cnt : unsigned(7 downto 0); + signal slave_active_fake : std_logic; + -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; -- attribute syn_keep of tx_dlm_i : signal is true; @@ -321,6 +324,21 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- BUG: for some reasons, some TRB3sc refuse to work with this reset. Links are not destroyed reliably, -- and strange things happen with WAP. + THE_SLAVE_ACTIVE_FAKE_PROC: process( clk_sys ) + begin + if( rising_edge(clk_sys) ) then + if ( make_reset_by_gbe = '1' ) then + slv_act_cnt <= (others => '0'); + elsif( slave_active_fake = '0' ) then + if( timer.tick_ms = '1' ) then + slv_act_cnt <= slv_act_cnt + 1; + end if; + end if; + end if; + end process THE_SLAVE_ACTIVE_FAKE_PROC; + + slave_active_fake <= std_logic(slv_act_cnt(7)); + pll_calibration : entity work.pll_in125_out33 port map ( CLK => CLK_SUPPL_PCLK, @@ -380,7 +398,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate QUAD_RST_IN => '0', -- check GLOBAL_RESET_OUT => open, SLAVE_ACTIVE_OUT => open, - SLAVE_ACTIVE_IN => '1', + SLAVE_ACTIVE_IN => slave_active_fake, --'1', TX_PLL_LOL_IN => tx_pll_lol_all_i, TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, TX_CLK_AVAIL_OUT => tx_clk_avail_i, -- 2.43.0