From 045b36092f2bbef6f9a808d02c85b0021240b761 Mon Sep 17 00:00:00 2001 From: Cahit Date: Tue, 26 Jan 2016 09:29:59 +0100 Subject: [PATCH] updated release note information --- releases/ReleaseNotes.org | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/releases/ReleaseNotes.org b/releases/ReleaseNotes.org index d31a2ce..d8fd7b3 100644 --- a/releases/ReleaseNotes.org +++ b/releases/ReleaseNotes.org @@ -12,19 +12,22 @@ | tdc_v2.3 | 08.12.2015 | Trailer word is introduced to mark some error bits. | | | | Temperature value is added to the data stream for status trigger (0xE). | | | | Some bugs are fixed for physics and status trigger mixture. | +| | | Compile time vlaue is added to the data stream for status trigger (0xE). | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v2.2 | 07.10.2015 | The delay line size is decreased to 288 from 304. | | | | The trigger window end and coarse counter reset signals are distributed via SECONDARY clock nets | -| | | A bug in the semi-asynchronous stretcher (combinatoral reset signal caused blockage) is removed. | +| | | A bug in the semi-asynchronous stretcher (combinatorial reset signal caused blockage) is removed. | +|------------+----------------+----------------------------------------------------------------------------------| +| tdc_v2.1.6 | 06.08.2015 | Updated the codes with record based bus lines. | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v2.1.5 | 22.06.2015 | Extra coarse counter reset register for higher frequency. | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v2.1.4 | 17.06.2015 | Several bug fixes for the stretcher option. | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v2.1.2 | 28.01.2015 | In case of a missing reference time a header error bit is set and DAQ keeps running. | -| | | Grass hits in ToT with calbration trigger is removed. The ToT mean value - 10ns gives the stretching offset of the channel. | +| | | Grass hits in ToT with calibration trigger is removed. The ToT mean value - 10ns gives the stretching offset of the channel. | | | | Channel invert bits are implemented. | -| | | Trigger window bugfix. | +| | | Trigger window bug-fix. | | | | Resource usages in Channel_200 and Channel entity are decreased. | | | | Hit detection is increased to 2 bits. | | | | Coarse counter number is increased to channel number for better timing. | @@ -34,13 +37,13 @@ | tdc_v2.1.1 | 28.01.2015 | The dead time of the TDC is decreased to 20ns. | | | | Small bug with "Light Mode" is removed. | | | | "Data Limit" parameter is removed, as it is not needed due to the dynamic buffer size. | -| | | Coarse/Epoch counter misallignment bug is fixed. | +| | | Coarse/Epoch counter misalignment bug is fixed. | | | | Channel input is blocked until the falling edge information is written in the ring buffer to avoid data mismatch. | | | | Ring buffer overwrite bit is implemented. | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v2.1.0 | 15.12.2014 | The ring buffer almost full threshold is made dynamic in order to "mimic" a adjustable ring buffer size. | |------------+----------------+----------------------------------------------------------------------------------| -| tdc_v2.0.1 | 05.12.2014 | Calibration-physik trigger switching problem is fixed. | +| tdc_v2.0.1 | 05.12.2014 | Calibration-physic trigger switching problem is fixed. | | | | With the calibration trigger 50ns pulses are sent to the channels in order to calibrate the ToT measurements in the channels. There are some grass hits around the main peak. | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v2.0 | 01.12.2014 | Double edge detection in a single channel is implemented. | @@ -50,7 +53,7 @@ | tdc_v1.7.1 | 29.07.2014 | Feature Bit support. | | | | Tidy up the entities. | |------------+----------------+----------------------------------------------------------------------------------| -| tdc_v1.7 | 24.06.2014 | Paralel working Readouts are implemented. | +| tdc_v1.7 | 24.06.2014 | Parallel working Readouts are implemented. | | | | Trigger time calculation is done in the trigger handler. | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v1.6.3 | 24.06.2014 | Bug fix in the hit rate counters (syncronisation problem). | @@ -67,25 +70,25 @@ |------------+----------------+----------------------------------------------------------------------------------| | tdc_v1.6 | 20.01.2014 | Epoch counter bug fix (data word - epoch word place swap). | | | | Trigger window bug fix (epoch counter more than 24 bit had integer conversion problem. Trigger window right side control is enabled). | -| | | Readout algorith change (the channel fifos are readout to intermediate buffer, so the later channels in the readout order are kept as the trigger arrival time). | +| | | Readout algorithm change (the channel FIFOs are readout to intermediate buffer, so the later channels in the readout order are kept as the trigger arrival time). | | | | Trigger on TDC channel (the feature for triggering on TDC channel is implemented) Reference channel hit rate counter implemented. | | | | The channels (incl. ch0) can be calibrated with the internal oscillator with different frequencies (see manual slow control registers). | | | | The coarse counter can be set to reset via slow control. The action will take place when the first valid trigger arrives. | | | | | |------------+----------------+----------------------------------------------------------------------------------| -| tdc_v1.5.1 | 20.06.2013 | Efficiency bug fix (epoch counter update - hit at the same time). Hit level bit bug fix for the web server. Reference Channel coarse counter alignmet fix. | +| tdc_v1.5.1 | 20.06.2013 | Efficiency bug fix (epoch counter update - hit at the same time). Hit level bit bug fix for the web server. Reference Channel coarse counter alignment fix. | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v1.5 | 03.05.2013 | TDC calibration trigger is implemented in order to shoot every channel with sufficient # of hits for proper calibration. Also the TDC is adapted for short pulses. | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v1.4 | 18.04.2013 | Limiting data transfer functionality is added. Use 0xc804 register to define the # of word per channel to be read-out. | |------------+----------------+----------------------------------------------------------------------------------| -| tdc_v1.3 | 05.03.2013 | Encoder efficiency is increased to 100%. Extra bits are encoded in the data (low resolution and no successfull binary conversion, see the manual). | +| tdc_v1.3 | 05.03.2013 | Encoder efficiency is increased to 100%. Extra bits are encoded in the data (low resolution and no successful binary conversion, see the manual). | | | | Channel block during the readout is removed. Only the relevant hits per trigger are readout. | | | | Control registers are moved to 0xc800. | |------------+----------------+----------------------------------------------------------------------------------| -| tdc_v1.2 | 12.11.2012 | First strecher prototype is successfully implemented. Some bugs are fixed. | +| tdc_v1.2 | 12.11.2012 | First stecher prototype is successfully implemented. Some bugs are fixed. | |------------+----------------+----------------------------------------------------------------------------------| -| tdc_v1.1.1 | 07.11.2012 | The status registers are moved to the bus address 0xc100. Also debug registers (encoder start, fifo write, lost hits) are included in the bus - 0xc200 0xc300 0xc400 | +| tdc_v1.1.1 | 07.11.2012 | The status registers are moved to the bus address 0xc100. Also debug registers (encoder start, FIFO write, lost hits) are included in the bus - 0xc200 0xc300 0xc400 | |------------+----------------+----------------------------------------------------------------------------------| | tdc_v1.1 | 26.10.2012 | Readout process is collected in an individual entity. | |------------+----------------+----------------------------------------------------------------------------------| -- 2.43.0